AMDGPUAsmPrinter.cpp revision 360784 
1//===-- AMDGPUAsmPrinter.cpp - AMDGPU assembly printer --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9/// \file
10///
11/// The AMDGPUAsmPrinter is used to print both assembly string and also binary
12/// code.  When passed an MCAsmStreamer it prints assembly and when passed
13/// an MCObjectStreamer it outputs binary code.
14//
15//===----------------------------------------------------------------------===//
16//
17
18#include "AMDGPUAsmPrinter.h"
19#include "AMDGPU.h"
20#include "AMDGPUSubtarget.h"
21#include "AMDGPUTargetMachine.h"
22#include "MCTargetDesc/AMDGPUInstPrinter.h"
23#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
24#include "MCTargetDesc/AMDGPUTargetStreamer.h"
25#include "R600AsmPrinter.h"
26#include "R600Defines.h"
27#include "R600MachineFunctionInfo.h"
28#include "R600RegisterInfo.h"
29#include "SIDefines.h"
30#include "SIInstrInfo.h"
31#include "SIMachineFunctionInfo.h"
32#include "SIRegisterInfo.h"
33#include "TargetInfo/AMDGPUTargetInfo.h"
34#include "Utils/AMDGPUBaseInfo.h"
35#include "llvm/BinaryFormat/ELF.h"
36#include "llvm/CodeGen/MachineFrameInfo.h"
37#include "llvm/IR/DiagnosticInfo.h"
38#include "llvm/MC/MCAssembler.h"
39#include "llvm/MC/MCContext.h"
40#include "llvm/MC/MCSectionELF.h"
41#include "llvm/MC/MCStreamer.h"
42#include "llvm/Support/AMDGPUMetadata.h"
43#include "llvm/Support/MathExtras.h"
44#include "llvm/Support/TargetParser.h"
45#include "llvm/Support/TargetRegistry.h"
46#include "llvm/Target/TargetLoweringObjectFile.h"
47
48using namespace llvm;
49using namespace llvm::AMDGPU;
50using namespace llvm::AMDGPU::HSAMD;
51
52// TODO: This should get the default rounding mode from the kernel. We just set
53// the default here, but this could change if the OpenCL rounding mode pragmas
54// are used.
55//
56// The denormal mode here should match what is reported by the OpenCL runtime
57// for the CL_FP_DENORM bit from CL_DEVICE_{HALF|SINGLE|DOUBLE}_FP_CONFIG, but
58// can also be override to flush with the -cl-denorms-are-zero compiler flag.
59//
60// AMD OpenCL only sets flush none and reports CL_FP_DENORM for double
61// precision, and leaves single precision to flush all and does not report
62// CL_FP_DENORM for CL_DEVICE_SINGLE_FP_CONFIG. Mesa's OpenCL currently reports
63// CL_FP_DENORM for both.
64//
65// FIXME: It seems some instructions do not support single precision denormals
66// regardless of the mode (exp_*_f32, rcp_*_f32, rsq_*_f32, rsq_*f32, sqrt_f32,
67// and sin_f32, cos_f32 on most parts).
68
69// We want to use these instructions, and using fp32 denormals also causes
70// instructions to run at the double precision rate for the device so it's
71// probably best to just report no single precision denormals.
72static uint32_t getFPMode(AMDGPU::SIModeRegisterDefaults Mode) {
73
74  // TODO: Is there any real use for the flush in only / flush out only modes?
75  uint32_t FP32Denormals =
76    Mode.FP32Denormals ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
77
78  uint32_t FP64Denormals =
79    Mode.FP64FP16Denormals ? FP_DENORM_FLUSH_NONE : FP_DENORM_FLUSH_IN_FLUSH_OUT;
80
81  return FP_ROUND_MODE_SP(FP_ROUND_ROUND_TO_NEAREST) |
82         FP_ROUND_MODE_DP(FP_ROUND_ROUND_TO_NEAREST) |
83         FP_DENORM_MODE_SP(FP32Denormals) |
84         FP_DENORM_MODE_DP(FP64Denormals);
85}
86
87static AsmPrinter *
88createAMDGPUAsmPrinterPass(TargetMachine &tm,
89                           std::unique_ptr<MCStreamer> &&Streamer) {
90  return new AMDGPUAsmPrinter(tm, std::move(Streamer));
91}
92
93extern "C" void LLVM_EXTERNAL_VISIBILITY LLVMInitializeAMDGPUAsmPrinter() {
94  TargetRegistry::RegisterAsmPrinter(getTheAMDGPUTarget(),
95                                     llvm::createR600AsmPrinterPass);
96  TargetRegistry::RegisterAsmPrinter(getTheGCNTarget(),
97                                     createAMDGPUAsmPrinterPass);
98}
99
100AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM,
101                                   std::unique_ptr<MCStreamer> Streamer)
102  : AsmPrinter(TM, std::move(Streamer)) {
103    if (IsaInfo::hasCodeObjectV3(getGlobalSTI()))
104      HSAMetadataStream.reset(new MetadataStreamerV3());
105    else
106      HSAMetadataStream.reset(new MetadataStreamerV2());
107}
108
109StringRef AMDGPUAsmPrinter::getPassName() const {
110  return "AMDGPU Assembly Printer";
111}
112
113const MCSubtargetInfo *AMDGPUAsmPrinter::getGlobalSTI() const {
114  return TM.getMCSubtargetInfo();
115}
116
117AMDGPUTargetStreamer* AMDGPUAsmPrinter::getTargetStreamer() const {
118  if (!OutStreamer)
119    return nullptr;
120  return static_cast<AMDGPUTargetStreamer*>(OutStreamer->getTargetStreamer());
121}
122
123void AMDGPUAsmPrinter::EmitStartOfAsmFile(Module &M) {
124  if (IsaInfo::hasCodeObjectV3(getGlobalSTI())) {
125    std::string ExpectedTarget;
126    raw_string_ostream ExpectedTargetOS(ExpectedTarget);
127    IsaInfo::streamIsaVersion(getGlobalSTI(), ExpectedTargetOS);
128
129    getTargetStreamer()->EmitDirectiveAMDGCNTarget(ExpectedTarget);
130  }
131
132  if (TM.getTargetTriple().getOS() != Triple::AMDHSA &&
133      TM.getTargetTriple().getOS() != Triple::AMDPAL)
134    return;
135
136  if (TM.getTargetTriple().getOS() == Triple::AMDHSA)
137    HSAMetadataStream->begin(M);
138
139  if (TM.getTargetTriple().getOS() == Triple::AMDPAL)
140    getTargetStreamer()->getPALMetadata()->readFromIR(M);
141
142  if (IsaInfo::hasCodeObjectV3(getGlobalSTI()))
143    return;
144
145  // HSA emits NT_AMDGPU_HSA_CODE_OBJECT_VERSION for code objects v2.
146  if (TM.getTargetTriple().getOS() == Triple::AMDHSA)
147    getTargetStreamer()->EmitDirectiveHSACodeObjectVersion(2, 1);
148
149  // HSA and PAL emit NT_AMDGPU_HSA_ISA for code objects v2.
150  IsaVersion Version = getIsaVersion(getGlobalSTI()->getCPU());
151  getTargetStreamer()->EmitDirectiveHSACodeObjectISA(
152      Version.Major, Version.Minor, Version.Stepping, "AMD", "AMDGPU");
153}
154
155void AMDGPUAsmPrinter::EmitEndOfAsmFile(Module &M) {
156  // Following code requires TargetStreamer to be present.
157  if (!getTargetStreamer())
158    return;
159
160  if (!IsaInfo::hasCodeObjectV3(getGlobalSTI())) {
161    // Emit ISA Version (NT_AMD_AMDGPU_ISA).
162    std::string ISAVersionString;
163    raw_string_ostream ISAVersionStream(ISAVersionString);
164    IsaInfo::streamIsaVersion(getGlobalSTI(), ISAVersionStream);
165    getTargetStreamer()->EmitISAVersion(ISAVersionStream.str());
166  }
167
168  // Emit HSA Metadata (NT_AMD_AMDGPU_HSA_METADATA).
169  if (TM.getTargetTriple().getOS() == Triple::AMDHSA) {
170    HSAMetadataStream->end();
171    bool Success = HSAMetadataStream->emitTo(*getTargetStreamer());
172    (void)Success;
173    assert(Success && "Malformed HSA Metadata");
174  }
175}
176
177bool AMDGPUAsmPrinter::isBlockOnlyReachableByFallthrough(
178  const MachineBasicBlock *MBB) const {
179  if (!AsmPrinter::isBlockOnlyReachableByFallthrough(MBB))
180    return false;
181
182  if (MBB->empty())
183    return true;
184
185  // If this is a block implementing a long branch, an expression relative to
186  // the start of the block is needed.  to the start of the block.
187  // XXX - Is there a smarter way to check this?
188  return (MBB->back().getOpcode() != AMDGPU::S_SETPC_B64);
189}
190
191void AMDGPUAsmPrinter::EmitFunctionBodyStart() {
192  const SIMachineFunctionInfo &MFI = *MF->getInfo<SIMachineFunctionInfo>();
193  if (!MFI.isEntryFunction())
194    return;
195
196  const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
197  const Function &F = MF->getFunction();
198  if (!STM.hasCodeObjectV3() && STM.isAmdHsaOrMesa(F) &&
199      (F.getCallingConv() == CallingConv::AMDGPU_KERNEL ||
200       F.getCallingConv() == CallingConv::SPIR_KERNEL)) {
201    amd_kernel_code_t KernelCode;
202    getAmdKernelCode(KernelCode, CurrentProgramInfo, *MF);
203    getTargetStreamer()->EmitAMDKernelCodeT(KernelCode);
204  }
205
206  if (STM.isAmdHsaOS())
207    HSAMetadataStream->emitKernel(*MF, CurrentProgramInfo);
208}
209
210void AMDGPUAsmPrinter::EmitFunctionBodyEnd() {
211  const SIMachineFunctionInfo &MFI = *MF->getInfo<SIMachineFunctionInfo>();
212  if (!MFI.isEntryFunction())
213    return;
214
215  if (!IsaInfo::hasCodeObjectV3(getGlobalSTI()) ||
216      TM.getTargetTriple().getOS() != Triple::AMDHSA)
217    return;
218
219  auto &Streamer = getTargetStreamer()->getStreamer();
220  auto &Context = Streamer.getContext();
221  auto &ObjectFileInfo = *Context.getObjectFileInfo();
222  auto &ReadOnlySection = *ObjectFileInfo.getReadOnlySection();
223
224  Streamer.PushSection();
225  Streamer.SwitchSection(&ReadOnlySection);
226
227  // CP microcode requires the kernel descriptor to be allocated on 64 byte
228  // alignment.
229  Streamer.EmitValueToAlignment(64, 0, 1, 0);
230  if (ReadOnlySection.getAlignment() < 64)
231    ReadOnlySection.setAlignment(Align(64));
232
233  const MCSubtargetInfo &STI = MF->getSubtarget();
234
235  SmallString<128> KernelName;
236  getNameWithPrefix(KernelName, &MF->getFunction());
237  getTargetStreamer()->EmitAmdhsaKernelDescriptor(
238      STI, KernelName, getAmdhsaKernelDescriptor(*MF, CurrentProgramInfo),
239      CurrentProgramInfo.NumVGPRsForWavesPerEU,
240      CurrentProgramInfo.NumSGPRsForWavesPerEU -
241          IsaInfo::getNumExtraSGPRs(&STI,
242                                    CurrentProgramInfo.VCCUsed,
243                                    CurrentProgramInfo.FlatUsed),
244      CurrentProgramInfo.VCCUsed, CurrentProgramInfo.FlatUsed,
245      hasXNACK(STI));
246
247  Streamer.PopSection();
248}
249
250void AMDGPUAsmPrinter::EmitFunctionEntryLabel() {
251  if (IsaInfo::hasCodeObjectV3(getGlobalSTI()) &&
252      TM.getTargetTriple().getOS() == Triple::AMDHSA) {
253    AsmPrinter::EmitFunctionEntryLabel();
254    return;
255  }
256
257  const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
258  const GCNSubtarget &STM = MF->getSubtarget<GCNSubtarget>();
259  if (MFI->isEntryFunction() && STM.isAmdHsaOrMesa(MF->getFunction())) {
260    SmallString<128> SymbolName;
261    getNameWithPrefix(SymbolName, &MF->getFunction()),
262    getTargetStreamer()->EmitAMDGPUSymbolType(
263        SymbolName, ELF::STT_AMDGPU_HSA_KERNEL);
264  }
265  if (DumpCodeInstEmitter) {
266    // Disassemble function name label to text.
267    DisasmLines.push_back(MF->getName().str() + ":");
268    DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLines.back().size());
269    HexLines.push_back("");
270  }
271
272  AsmPrinter::EmitFunctionEntryLabel();
273}
274
275void AMDGPUAsmPrinter::EmitBasicBlockStart(const MachineBasicBlock &MBB) {
276  if (DumpCodeInstEmitter && !isBlockOnlyReachableByFallthrough(&MBB)) {
277    // Write a line for the basic block label if it is not only fallthrough.
278    DisasmLines.push_back(
279        (Twine("BB") + Twine(getFunctionNumber())
280         + "_" + Twine(MBB.getNumber()) + ":").str());
281    DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLines.back().size());
282    HexLines.push_back("");
283  }
284  AsmPrinter::EmitBasicBlockStart(MBB);
285}
286
287void AMDGPUAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {
288  if (GV->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS) {
289    if (GV->hasInitializer() && !isa<UndefValue>(GV->getInitializer())) {
290      OutContext.reportError({},
291                             Twine(GV->getName()) +
292                                 ": unsupported initializer for address space");
293      return;
294    }
295
296    // LDS variables aren't emitted in HSA or PAL yet.
297    const Triple::OSType OS = TM.getTargetTriple().getOS();
298    if (OS == Triple::AMDHSA || OS == Triple::AMDPAL)
299      return;
300
301    MCSymbol *GVSym = getSymbol(GV);
302
303    GVSym->redefineIfPossible();
304    if (GVSym->isDefined() || GVSym->isVariable())
305      report_fatal_error("symbol '" + Twine(GVSym->getName()) +
306                         "' is already defined");
307
308    const DataLayout &DL = GV->getParent()->getDataLayout();
309    uint64_t Size = DL.getTypeAllocSize(GV->getValueType());
310    unsigned Align = GV->getAlignment();
311    if (!Align)
312      Align = 4;
313
314    EmitVisibility(GVSym, GV->getVisibility(), !GV->isDeclaration());
315    EmitLinkage(GV, GVSym);
316    if (auto TS = getTargetStreamer())
317      TS->emitAMDGPULDS(GVSym, Size, Align);
318    return;
319  }
320
321  AsmPrinter::EmitGlobalVariable(GV);
322}
323
324bool AMDGPUAsmPrinter::doFinalization(Module &M) {
325  CallGraphResourceInfo.clear();
326
327  // Pad with s_code_end to help tools and guard against instruction prefetch
328  // causing stale data in caches. Arguably this should be done by the linker,
329  // which is why this isn't done for Mesa.
330  const MCSubtargetInfo &STI = *getGlobalSTI();
331  if (AMDGPU::isGFX10(STI) &&
332      (STI.getTargetTriple().getOS() == Triple::AMDHSA ||
333       STI.getTargetTriple().getOS() == Triple::AMDPAL)) {
334    OutStreamer->SwitchSection(getObjFileLowering().getTextSection());
335    getTargetStreamer()->EmitCodeEnd();
336  }
337
338  return AsmPrinter::doFinalization(M);
339}
340
341// Print comments that apply to both callable functions and entry points.
342void AMDGPUAsmPrinter::emitCommonFunctionComments(
343  uint32_t NumVGPR,
344  Optional<uint32_t> NumAGPR,
345  uint32_t TotalNumVGPR,
346  uint32_t NumSGPR,
347  uint64_t ScratchSize,
348  uint64_t CodeSize,
349  const AMDGPUMachineFunction *MFI) {
350  OutStreamer->emitRawComment(" codeLenInByte = " + Twine(CodeSize), false);
351  OutStreamer->emitRawComment(" NumSgprs: " + Twine(NumSGPR), false);
352  OutStreamer->emitRawComment(" NumVgprs: " + Twine(NumVGPR), false);
353  if (NumAGPR) {
354    OutStreamer->emitRawComment(" NumAgprs: " + Twine(*NumAGPR), false);
355    OutStreamer->emitRawComment(" TotalNumVgprs: " + Twine(TotalNumVGPR),
356                                false);
357  }
358  OutStreamer->emitRawComment(" ScratchSize: " + Twine(ScratchSize), false);
359  OutStreamer->emitRawComment(" MemoryBound: " + Twine(MFI->isMemoryBound()),
360                              false);
361}
362
363uint16_t AMDGPUAsmPrinter::getAmdhsaKernelCodeProperties(
364    const MachineFunction &MF) const {
365  const SIMachineFunctionInfo &MFI = *MF.getInfo<SIMachineFunctionInfo>();
366  uint16_t KernelCodeProperties = 0;
367
368  if (MFI.hasPrivateSegmentBuffer()) {
369    KernelCodeProperties |=
370        amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
371  }
372  if (MFI.hasDispatchPtr()) {
373    KernelCodeProperties |=
374        amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
375  }
376  if (MFI.hasQueuePtr()) {
377    KernelCodeProperties |=
378        amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
379  }
380  if (MFI.hasKernargSegmentPtr()) {
381    KernelCodeProperties |=
382        amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
383  }
384  if (MFI.hasDispatchID()) {
385    KernelCodeProperties |=
386        amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
387  }
388  if (MFI.hasFlatScratchInit()) {
389    KernelCodeProperties |=
390        amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
391  }
392  if (MF.getSubtarget<GCNSubtarget>().isWave32()) {
393    KernelCodeProperties |=
394        amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32;
395  }
396
397  return KernelCodeProperties;
398}
399
400amdhsa::kernel_descriptor_t AMDGPUAsmPrinter::getAmdhsaKernelDescriptor(
401    const MachineFunction &MF,
402    const SIProgramInfo &PI) const {
403  amdhsa::kernel_descriptor_t KernelDescriptor;
404  memset(&KernelDescriptor, 0x0, sizeof(KernelDescriptor));
405
406  assert(isUInt<32>(PI.ScratchSize));
407  assert(isUInt<32>(PI.ComputePGMRSrc1));
408  assert(isUInt<32>(PI.ComputePGMRSrc2));
409
410  KernelDescriptor.group_segment_fixed_size = PI.LDSSize;
411  KernelDescriptor.private_segment_fixed_size = PI.ScratchSize;
412  KernelDescriptor.compute_pgm_rsrc1 = PI.ComputePGMRSrc1;
413  KernelDescriptor.compute_pgm_rsrc2 = PI.ComputePGMRSrc2;
414  KernelDescriptor.kernel_code_properties = getAmdhsaKernelCodeProperties(MF);
415
416  return KernelDescriptor;
417}
418
419bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
420  CurrentProgramInfo = SIProgramInfo();
421
422  const AMDGPUMachineFunction *MFI = MF.getInfo<AMDGPUMachineFunction>();
423
424  // The starting address of all shader programs must be 256 bytes aligned.
425  // Regular functions just need the basic required instruction alignment.
426  MF.setAlignment(MFI->isEntryFunction() ? Align(256) : Align(4));
427
428  SetupMachineFunction(MF);
429
430  const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
431  MCContext &Context = getObjFileLowering().getContext();
432  // FIXME: This should be an explicit check for Mesa.
433  if (!STM.isAmdHsaOS() && !STM.isAmdPalOS()) {
434    MCSectionELF *ConfigSection =
435        Context.getELFSection(".AMDGPU.config", ELF::SHT_PROGBITS, 0);
436    OutStreamer->SwitchSection(ConfigSection);
437  }
438
439  if (MFI->isEntryFunction()) {
440    getSIProgramInfo(CurrentProgramInfo, MF);
441  } else {
442    auto I = CallGraphResourceInfo.insert(
443      std::make_pair(&MF.getFunction(), SIFunctionResourceInfo()));
444    SIFunctionResourceInfo &Info = I.first->second;
445    assert(I.second && "should only be called once per function");
446    Info = analyzeResourceUsage(MF);
447  }
448
449  if (STM.isAmdPalOS())
450    EmitPALMetadata(MF, CurrentProgramInfo);
451  else if (!STM.isAmdHsaOS()) {
452    EmitProgramInfoSI(MF, CurrentProgramInfo);
453  }
454
455  DumpCodeInstEmitter = nullptr;
456  if (STM.dumpCode()) {
457    // For -dumpcode, get the assembler out of the streamer, even if it does
458    // not really want to let us have it. This only works with -filetype=obj.
459    bool SaveFlag = OutStreamer->getUseAssemblerInfoForParsing();
460    OutStreamer->setUseAssemblerInfoForParsing(true);
461    MCAssembler *Assembler = OutStreamer->getAssemblerPtr();
462    OutStreamer->setUseAssemblerInfoForParsing(SaveFlag);
463    if (Assembler)
464      DumpCodeInstEmitter = Assembler->getEmitterPtr();
465  }
466
467  DisasmLines.clear();
468  HexLines.clear();
469  DisasmLineMaxLen = 0;
470
471  EmitFunctionBody();
472
473  if (isVerbose()) {
474    MCSectionELF *CommentSection =
475        Context.getELFSection(".AMDGPU.csdata", ELF::SHT_PROGBITS, 0);
476    OutStreamer->SwitchSection(CommentSection);
477
478    if (!MFI->isEntryFunction()) {
479      OutStreamer->emitRawComment(" Function info:", false);
480      SIFunctionResourceInfo &Info = CallGraphResourceInfo[&MF.getFunction()];
481      emitCommonFunctionComments(
482        Info.NumVGPR,
483        STM.hasMAIInsts() ? Info.NumAGPR : Optional<uint32_t>(),
484        Info.getTotalNumVGPRs(STM),
485        Info.getTotalNumSGPRs(MF.getSubtarget<GCNSubtarget>()),
486        Info.PrivateSegmentSize,
487        getFunctionCodeSize(MF), MFI);
488      return false;
489    }
490
491    OutStreamer->emitRawComment(" Kernel info:", false);
492    emitCommonFunctionComments(CurrentProgramInfo.NumArchVGPR,
493                               STM.hasMAIInsts()
494                                 ? CurrentProgramInfo.NumAccVGPR
495                                 : Optional<uint32_t>(),
496                               CurrentProgramInfo.NumVGPR,
497                               CurrentProgramInfo.NumSGPR,
498                               CurrentProgramInfo.ScratchSize,
499                               getFunctionCodeSize(MF), MFI);
500
501    OutStreamer->emitRawComment(
502      " FloatMode: " + Twine(CurrentProgramInfo.FloatMode), false);
503    OutStreamer->emitRawComment(
504      " IeeeMode: " + Twine(CurrentProgramInfo.IEEEMode), false);
505    OutStreamer->emitRawComment(
506      " LDSByteSize: " + Twine(CurrentProgramInfo.LDSSize) +
507      " bytes/workgroup (compile time only)", false);
508
509    OutStreamer->emitRawComment(
510      " SGPRBlocks: " + Twine(CurrentProgramInfo.SGPRBlocks), false);
511    OutStreamer->emitRawComment(
512      " VGPRBlocks: " + Twine(CurrentProgramInfo.VGPRBlocks), false);
513
514    OutStreamer->emitRawComment(
515      " NumSGPRsForWavesPerEU: " +
516      Twine(CurrentProgramInfo.NumSGPRsForWavesPerEU), false);
517    OutStreamer->emitRawComment(
518      " NumVGPRsForWavesPerEU: " +
519      Twine(CurrentProgramInfo.NumVGPRsForWavesPerEU), false);
520
521    OutStreamer->emitRawComment(
522      " Occupancy: " +
523      Twine(CurrentProgramInfo.Occupancy), false);
524
525    OutStreamer->emitRawComment(
526      " WaveLimiterHint : " + Twine(MFI->needsWaveLimiter()), false);
527
528    OutStreamer->emitRawComment(
529      " COMPUTE_PGM_RSRC2:USER_SGPR: " +
530      Twine(G_00B84C_USER_SGPR(CurrentProgramInfo.ComputePGMRSrc2)), false);
531    OutStreamer->emitRawComment(
532      " COMPUTE_PGM_RSRC2:TRAP_HANDLER: " +
533      Twine(G_00B84C_TRAP_HANDLER(CurrentProgramInfo.ComputePGMRSrc2)), false);
534    OutStreamer->emitRawComment(
535      " COMPUTE_PGM_RSRC2:TGID_X_EN: " +
536      Twine(G_00B84C_TGID_X_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
537    OutStreamer->emitRawComment(
538      " COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
539      Twine(G_00B84C_TGID_Y_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
540    OutStreamer->emitRawComment(
541      " COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
542      Twine(G_00B84C_TGID_Z_EN(CurrentProgramInfo.ComputePGMRSrc2)), false);
543    OutStreamer->emitRawComment(
544      " COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
545      Twine(G_00B84C_TIDIG_COMP_CNT(CurrentProgramInfo.ComputePGMRSrc2)),
546      false);
547  }
548
549  if (DumpCodeInstEmitter) {
550
551    OutStreamer->SwitchSection(
552        Context.getELFSection(".AMDGPU.disasm", ELF::SHT_NOTE, 0));
553
554    for (size_t i = 0; i < DisasmLines.size(); ++i) {
555      std::string Comment = "\n";
556      if (!HexLines[i].empty()) {
557        Comment = std::string(DisasmLineMaxLen - DisasmLines[i].size(), ' ');
558        Comment += " ; " + HexLines[i] + "\n";
559      }
560
561      OutStreamer->EmitBytes(StringRef(DisasmLines[i]));
562      OutStreamer->EmitBytes(StringRef(Comment));
563    }
564  }
565
566  return false;
567}
568
569uint64_t AMDGPUAsmPrinter::getFunctionCodeSize(const MachineFunction &MF) const {
570  const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
571  const SIInstrInfo *TII = STM.getInstrInfo();
572
573  uint64_t CodeSize = 0;
574
575  for (const MachineBasicBlock &MBB : MF) {
576    for (const MachineInstr &MI : MBB) {
577      // TODO: CodeSize should account for multiple functions.
578
579      // TODO: Should we count size of debug info?
580      if (MI.isDebugInstr())
581        continue;
582
583      CodeSize += TII->getInstSizeInBytes(MI);
584    }
585  }
586
587  return CodeSize;
588}
589
590static bool hasAnyNonFlatUseOfReg(const MachineRegisterInfo &MRI,
591                                  const SIInstrInfo &TII,
592                                  unsigned Reg) {
593  for (const MachineOperand &UseOp : MRI.reg_operands(Reg)) {
594    if (!UseOp.isImplicit() || !TII.isFLAT(*UseOp.getParent()))
595      return true;
596  }
597
598  return false;
599}
600
601int32_t AMDGPUAsmPrinter::SIFunctionResourceInfo::getTotalNumSGPRs(
602  const GCNSubtarget &ST) const {
603  return NumExplicitSGPR + IsaInfo::getNumExtraSGPRs(&ST,
604                                                     UsesVCC, UsesFlatScratch);
605}
606
607int32_t AMDGPUAsmPrinter::SIFunctionResourceInfo::getTotalNumVGPRs(
608  const GCNSubtarget &ST) const {
609  return std::max(NumVGPR, NumAGPR);
610}
611
612AMDGPUAsmPrinter::SIFunctionResourceInfo AMDGPUAsmPrinter::analyzeResourceUsage(
613  const MachineFunction &MF) const {
614  SIFunctionResourceInfo Info;
615
616  const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
617  const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
618  const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
619  const MachineRegisterInfo &MRI = MF.getRegInfo();
620  const SIInstrInfo *TII = ST.getInstrInfo();
621  const SIRegisterInfo &TRI = TII->getRegisterInfo();
622
623  Info.UsesFlatScratch = MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_LO) ||
624                         MRI.isPhysRegUsed(AMDGPU::FLAT_SCR_HI);
625
626  // Even if FLAT_SCRATCH is implicitly used, it has no effect if flat
627  // instructions aren't used to access the scratch buffer. Inline assembly may
628  // need it though.
629  //
630  // If we only have implicit uses of flat_scr on flat instructions, it is not
631  // really needed.
632  if (Info.UsesFlatScratch && !MFI->hasFlatScratchInit() &&
633      (!hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR) &&
634       !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_LO) &&
635       !hasAnyNonFlatUseOfReg(MRI, *TII, AMDGPU::FLAT_SCR_HI))) {
636    Info.UsesFlatScratch = false;
637  }
638
639  Info.HasDynamicallySizedStack = FrameInfo.hasVarSizedObjects();
640  Info.PrivateSegmentSize = FrameInfo.getStackSize();
641  if (MFI->isStackRealigned())
642    Info.PrivateSegmentSize += FrameInfo.getMaxAlignment();
643
644
645  Info.UsesVCC = MRI.isPhysRegUsed(AMDGPU::VCC_LO) ||
646                 MRI.isPhysRegUsed(AMDGPU::VCC_HI);
647
648  // If there are no calls, MachineRegisterInfo can tell us the used register
649  // count easily.
650  // A tail call isn't considered a call for MachineFrameInfo's purposes.
651  if (!FrameInfo.hasCalls() && !FrameInfo.hasTailCall()) {
652    MCPhysReg HighestVGPRReg = AMDGPU::NoRegister;
653    for (MCPhysReg Reg : reverse(AMDGPU::VGPR_32RegClass.getRegisters())) {
654      if (MRI.isPhysRegUsed(Reg)) {
655        HighestVGPRReg = Reg;
656        break;
657      }
658    }
659
660    if (ST.hasMAIInsts()) {
661      MCPhysReg HighestAGPRReg = AMDGPU::NoRegister;
662      for (MCPhysReg Reg : reverse(AMDGPU::AGPR_32RegClass.getRegisters())) {
663        if (MRI.isPhysRegUsed(Reg)) {
664          HighestAGPRReg = Reg;
665          break;
666        }
667      }
668      Info.NumAGPR = HighestAGPRReg == AMDGPU::NoRegister ? 0 :
669        TRI.getHWRegIndex(HighestAGPRReg) + 1;
670    }
671
672    MCPhysReg HighestSGPRReg = AMDGPU::NoRegister;
673    for (MCPhysReg Reg : reverse(AMDGPU::SGPR_32RegClass.getRegisters())) {
674      if (MRI.isPhysRegUsed(Reg)) {
675        HighestSGPRReg = Reg;
676        break;
677      }
678    }
679
680    // We found the maximum register index. They start at 0, so add one to get the
681    // number of registers.
682    Info.NumVGPR = HighestVGPRReg == AMDGPU::NoRegister ? 0 :
683      TRI.getHWRegIndex(HighestVGPRReg) + 1;
684    Info.NumExplicitSGPR = HighestSGPRReg == AMDGPU::NoRegister ? 0 :
685      TRI.getHWRegIndex(HighestSGPRReg) + 1;
686
687    return Info;
688  }
689
690  int32_t MaxVGPR = -1;
691  int32_t MaxAGPR = -1;
692  int32_t MaxSGPR = -1;
693  uint64_t CalleeFrameSize = 0;
694
695  for (const MachineBasicBlock &MBB : MF) {
696    for (const MachineInstr &MI : MBB) {
697      // TODO: Check regmasks? Do they occur anywhere except calls?
698      for (const MachineOperand &MO : MI.operands()) {
699        unsigned Width = 0;
700        bool IsSGPR = false;
701        bool IsAGPR = false;
702
703        if (!MO.isReg())
704          continue;
705
706        Register Reg = MO.getReg();
707        switch (Reg) {
708        case AMDGPU::EXEC:
709        case AMDGPU::EXEC_LO:
710        case AMDGPU::EXEC_HI:
711        case AMDGPU::SCC:
712        case AMDGPU::M0:
713        case AMDGPU::SRC_SHARED_BASE:
714        case AMDGPU::SRC_SHARED_LIMIT:
715        case AMDGPU::SRC_PRIVATE_BASE:
716        case AMDGPU::SRC_PRIVATE_LIMIT:
717        case AMDGPU::SGPR_NULL:
718          continue;
719
720        case AMDGPU::SRC_POPS_EXITING_WAVE_ID:
721          llvm_unreachable("src_pops_exiting_wave_id should not be used");
722
723        case AMDGPU::NoRegister:
724          assert(MI.isDebugInstr());
725          continue;
726
727        case AMDGPU::VCC:
728        case AMDGPU::VCC_LO:
729        case AMDGPU::VCC_HI:
730          Info.UsesVCC = true;
731          continue;
732
733        case AMDGPU::FLAT_SCR:
734        case AMDGPU::FLAT_SCR_LO:
735        case AMDGPU::FLAT_SCR_HI:
736          continue;
737
738        case AMDGPU::XNACK_MASK:
739        case AMDGPU::XNACK_MASK_LO:
740        case AMDGPU::XNACK_MASK_HI:
741          llvm_unreachable("xnack_mask registers should not be used");
742
743        case AMDGPU::LDS_DIRECT:
744          llvm_unreachable("lds_direct register should not be used");
745
746        case AMDGPU::TBA:
747        case AMDGPU::TBA_LO:
748        case AMDGPU::TBA_HI:
749        case AMDGPU::TMA:
750        case AMDGPU::TMA_LO:
751        case AMDGPU::TMA_HI:
752          llvm_unreachable("trap handler registers should not be used");
753
754        case AMDGPU::SRC_VCCZ:
755          llvm_unreachable("src_vccz register should not be used");
756
757        case AMDGPU::SRC_EXECZ:
758          llvm_unreachable("src_execz register should not be used");
759
760        case AMDGPU::SRC_SCC:
761          llvm_unreachable("src_scc register should not be used");
762
763        default:
764          break;
765        }
766
767        if (AMDGPU::SReg_32RegClass.contains(Reg)) {
768          assert(!AMDGPU::TTMP_32RegClass.contains(Reg) &&
769                 "trap handler registers should not be used");
770          IsSGPR = true;
771          Width = 1;
772        } else if (AMDGPU::VGPR_32RegClass.contains(Reg)) {
773          IsSGPR = false;
774          Width = 1;
775        } else if (AMDGPU::AGPR_32RegClass.contains(Reg)) {
776          IsSGPR = false;
777          IsAGPR = true;
778          Width = 1;
779        } else if (AMDGPU::SReg_64RegClass.contains(Reg)) {
780          assert(!AMDGPU::TTMP_64RegClass.contains(Reg) &&
781                 "trap handler registers should not be used");
782          IsSGPR = true;
783          Width = 2;
784        } else if (AMDGPU::VReg_64RegClass.contains(Reg)) {
785          IsSGPR = false;
786          Width = 2;
787        } else if (AMDGPU::AReg_64RegClass.contains(Reg)) {
788          IsSGPR = false;
789          IsAGPR = true;
790          Width = 2;
791        } else if (AMDGPU::VReg_96RegClass.contains(Reg)) {
792          IsSGPR = false;
793          Width = 3;
794        } else if (AMDGPU::SReg_96RegClass.contains(Reg)) {
795          IsSGPR = true;
796          Width = 3;
797        } else if (AMDGPU::SReg_128RegClass.contains(Reg)) {
798          assert(!AMDGPU::TTMP_128RegClass.contains(Reg) &&
799            "trap handler registers should not be used");
800          IsSGPR = true;
801          Width = 4;
802        } else if (AMDGPU::VReg_128RegClass.contains(Reg)) {
803          IsSGPR = false;
804          Width = 4;
805        } else if (AMDGPU::AReg_128RegClass.contains(Reg)) {
806          IsSGPR = false;
807          IsAGPR = true;
808          Width = 4;
809        } else if (AMDGPU::VReg_160RegClass.contains(Reg)) {
810          IsSGPR = false;
811          Width = 5;
812        } else if (AMDGPU::SReg_160RegClass.contains(Reg)) {
813          IsSGPR = true;
814          Width = 5;
815        } else if (AMDGPU::SReg_256RegClass.contains(Reg)) {
816          assert(!AMDGPU::TTMP_256RegClass.contains(Reg) &&
817            "trap handler registers should not be used");
818          IsSGPR = true;
819          Width = 8;
820        } else if (AMDGPU::VReg_256RegClass.contains(Reg)) {
821          IsSGPR = false;
822          Width = 8;
823        } else if (AMDGPU::SReg_512RegClass.contains(Reg)) {
824          assert(!AMDGPU::TTMP_512RegClass.contains(Reg) &&
825            "trap handler registers should not be used");
826          IsSGPR = true;
827          Width = 16;
828        } else if (AMDGPU::VReg_512RegClass.contains(Reg)) {
829          IsSGPR = false;
830          Width = 16;
831        } else if (AMDGPU::AReg_512RegClass.contains(Reg)) {
832          IsSGPR = false;
833          IsAGPR = true;
834          Width = 16;
835        } else if (AMDGPU::SReg_1024RegClass.contains(Reg)) {
836          IsSGPR = true;
837          Width = 32;
838        } else if (AMDGPU::VReg_1024RegClass.contains(Reg)) {
839          IsSGPR = false;
840          Width = 32;
841        } else if (AMDGPU::AReg_1024RegClass.contains(Reg)) {
842          IsSGPR = false;
843          IsAGPR = true;
844          Width = 32;
845        } else {
846          llvm_unreachable("Unknown register class");
847        }
848        unsigned HWReg = TRI.getHWRegIndex(Reg);
849        int MaxUsed = HWReg + Width - 1;
850        if (IsSGPR) {
851          MaxSGPR = MaxUsed > MaxSGPR ? MaxUsed : MaxSGPR;
852        } else if (IsAGPR) {
853          MaxAGPR = MaxUsed > MaxAGPR ? MaxUsed : MaxAGPR;
854        } else {
855          MaxVGPR = MaxUsed > MaxVGPR ? MaxUsed : MaxVGPR;
856        }
857      }
858
859      if (MI.isCall()) {
860        // Pseudo used just to encode the underlying global. Is there a better
861        // way to track this?
862
863        const MachineOperand *CalleeOp
864          = TII->getNamedOperand(MI, AMDGPU::OpName::callee);
865        const Function *Callee = cast<Function>(CalleeOp->getGlobal());
866        if (Callee->isDeclaration()) {
867          // If this is a call to an external function, we can't do much. Make
868          // conservative guesses.
869
870          // 48 SGPRs - vcc, - flat_scr, -xnack
871          int MaxSGPRGuess =
872            47 - IsaInfo::getNumExtraSGPRs(&ST, true, ST.hasFlatAddressSpace());
873          MaxSGPR = std::max(MaxSGPR, MaxSGPRGuess);
874          MaxVGPR = std::max(MaxVGPR, 23);
875          MaxAGPR = std::max(MaxAGPR, 23);
876
877          CalleeFrameSize = std::max(CalleeFrameSize, UINT64_C(16384));
878          Info.UsesVCC = true;
879          Info.UsesFlatScratch = ST.hasFlatAddressSpace();
880          Info.HasDynamicallySizedStack = true;
881        } else {
882          // We force CodeGen to run in SCC order, so the callee's register
883          // usage etc. should be the cumulative usage of all callees.
884
885          auto I = CallGraphResourceInfo.find(Callee);
886          if (I == CallGraphResourceInfo.end()) {
887            // Avoid crashing on undefined behavior with an illegal call to a
888            // kernel. If a callsite's calling convention doesn't match the
889            // function's, it's undefined behavior. If the callsite calling
890            // convention does match, that would have errored earlier.
891            // FIXME: The verifier shouldn't allow this.
892            if (AMDGPU::isEntryFunctionCC(Callee->getCallingConv()))
893              report_fatal_error("invalid call to entry function");
894
895            llvm_unreachable("callee should have been handled before caller");
896          }
897
898          MaxSGPR = std::max(I->second.NumExplicitSGPR - 1, MaxSGPR);
899          MaxVGPR = std::max(I->second.NumVGPR - 1, MaxVGPR);
900          MaxAGPR = std::max(I->second.NumAGPR - 1, MaxAGPR);
901          CalleeFrameSize
902            = std::max(I->second.PrivateSegmentSize, CalleeFrameSize);
903          Info.UsesVCC |= I->second.UsesVCC;
904          Info.UsesFlatScratch |= I->second.UsesFlatScratch;
905          Info.HasDynamicallySizedStack |= I->second.HasDynamicallySizedStack;
906          Info.HasRecursion |= I->second.HasRecursion;
907        }
908
909        if (!Callee->doesNotRecurse())
910          Info.HasRecursion = true;
911      }
912    }
913  }
914
915  Info.NumExplicitSGPR = MaxSGPR + 1;
916  Info.NumVGPR = MaxVGPR + 1;
917  Info.NumAGPR = MaxAGPR + 1;
918  Info.PrivateSegmentSize += CalleeFrameSize;
919
920  return Info;
921}
922
923void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
924                                        const MachineFunction &MF) {
925  SIFunctionResourceInfo Info = analyzeResourceUsage(MF);
926  const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
927
928  ProgInfo.NumArchVGPR = Info.NumVGPR;
929  ProgInfo.NumAccVGPR = Info.NumAGPR;
930  ProgInfo.NumVGPR = Info.getTotalNumVGPRs(STM);
931  ProgInfo.NumSGPR = Info.NumExplicitSGPR;
932  ProgInfo.ScratchSize = Info.PrivateSegmentSize;
933  ProgInfo.VCCUsed = Info.UsesVCC;
934  ProgInfo.FlatUsed = Info.UsesFlatScratch;
935  ProgInfo.DynamicCallStack = Info.HasDynamicallySizedStack || Info.HasRecursion;
936
937  if (!isUInt<32>(ProgInfo.ScratchSize)) {
938    DiagnosticInfoStackSize DiagStackSize(MF.getFunction(),
939                                          ProgInfo.ScratchSize, DS_Error);
940    MF.getFunction().getContext().diagnose(DiagStackSize);
941  }
942
943  const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
944
945  // TODO(scott.linder): The calculations related to SGPR/VGPR blocks are
946  // duplicated in part in AMDGPUAsmParser::calculateGPRBlocks, and could be
947  // unified.
948  unsigned ExtraSGPRs = IsaInfo::getNumExtraSGPRs(
949      &STM, ProgInfo.VCCUsed, ProgInfo.FlatUsed);
950
951  // Check the addressable register limit before we add ExtraSGPRs.
952  if (STM.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS &&
953      !STM.hasSGPRInitBug()) {
954    unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
955    if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
956      // This can happen due to a compiler bug or when using inline asm.
957      LLVMContext &Ctx = MF.getFunction().getContext();
958      DiagnosticInfoResourceLimit Diag(MF.getFunction(),
959                                       "addressable scalar registers",
960                                       ProgInfo.NumSGPR, DS_Error,
961                                       DK_ResourceLimit,
962                                       MaxAddressableNumSGPRs);
963      Ctx.diagnose(Diag);
964      ProgInfo.NumSGPR = MaxAddressableNumSGPRs - 1;
965    }
966  }
967
968  // Account for extra SGPRs and VGPRs reserved for debugger use.
969  ProgInfo.NumSGPR += ExtraSGPRs;
970
971  // Ensure there are enough SGPRs and VGPRs for wave dispatch, where wave
972  // dispatch registers are function args.
973  unsigned WaveDispatchNumSGPR = 0, WaveDispatchNumVGPR = 0;
974  for (auto &Arg : MF.getFunction().args()) {
975    unsigned NumRegs = (Arg.getType()->getPrimitiveSizeInBits() + 31) / 32;
976    if (Arg.hasAttribute(Attribute::InReg))
977      WaveDispatchNumSGPR += NumRegs;
978    else
979      WaveDispatchNumVGPR += NumRegs;
980  }
981  ProgInfo.NumSGPR = std::max(ProgInfo.NumSGPR, WaveDispatchNumSGPR);
982  ProgInfo.NumVGPR = std::max(ProgInfo.NumVGPR, WaveDispatchNumVGPR);
983
984  // Adjust number of registers used to meet default/requested minimum/maximum
985  // number of waves per execution unit request.
986  ProgInfo.NumSGPRsForWavesPerEU = std::max(
987    std::max(ProgInfo.NumSGPR, 1u), STM.getMinNumSGPRs(MFI->getMaxWavesPerEU()));
988  ProgInfo.NumVGPRsForWavesPerEU = std::max(
989    std::max(ProgInfo.NumVGPR, 1u), STM.getMinNumVGPRs(MFI->getMaxWavesPerEU()));
990
991  if (STM.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS ||
992      STM.hasSGPRInitBug()) {
993    unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
994    if (ProgInfo.NumSGPR > MaxAddressableNumSGPRs) {
995      // This can happen due to a compiler bug or when using inline asm to use
996      // the registers which are usually reserved for vcc etc.
997      LLVMContext &Ctx = MF.getFunction().getContext();
998      DiagnosticInfoResourceLimit Diag(MF.getFunction(),
999                                       "scalar registers",
1000                                       ProgInfo.NumSGPR, DS_Error,
1001                                       DK_ResourceLimit,
1002                                       MaxAddressableNumSGPRs);
1003      Ctx.diagnose(Diag);
1004      ProgInfo.NumSGPR = MaxAddressableNumSGPRs;
1005      ProgInfo.NumSGPRsForWavesPerEU = MaxAddressableNumSGPRs;
1006    }
1007  }
1008
1009  if (STM.hasSGPRInitBug()) {
1010    ProgInfo.NumSGPR =
1011        AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
1012    ProgInfo.NumSGPRsForWavesPerEU =
1013        AMDGPU::IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
1014  }
1015
1016  if (MFI->getNumUserSGPRs() > STM.getMaxNumUserSGPRs()) {
1017    LLVMContext &Ctx = MF.getFunction().getContext();
1018    DiagnosticInfoResourceLimit Diag(MF.getFunction(), "user SGPRs",
1019                                     MFI->getNumUserSGPRs(), DS_Error);
1020    Ctx.diagnose(Diag);
1021  }
1022
1023  if (MFI->getLDSSize() > static_cast<unsigned>(STM.getLocalMemorySize())) {
1024    LLVMContext &Ctx = MF.getFunction().getContext();
1025    DiagnosticInfoResourceLimit Diag(MF.getFunction(), "local memory",
1026                                     MFI->getLDSSize(), DS_Error);
1027    Ctx.diagnose(Diag);
1028  }
1029
1030  ProgInfo.SGPRBlocks = IsaInfo::getNumSGPRBlocks(
1031      &STM, ProgInfo.NumSGPRsForWavesPerEU);
1032  ProgInfo.VGPRBlocks = IsaInfo::getNumVGPRBlocks(
1033      &STM, ProgInfo.NumVGPRsForWavesPerEU);
1034
1035  const SIModeRegisterDefaults Mode = MFI->getMode();
1036
1037  // Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
1038  // register.
1039  ProgInfo.FloatMode = getFPMode(Mode);
1040
1041  ProgInfo.IEEEMode = Mode.IEEE;
1042
1043  // Make clamp modifier on NaN input returns 0.
1044  ProgInfo.DX10Clamp = Mode.DX10Clamp;
1045
1046  unsigned LDSAlignShift;
1047  if (STM.getGeneration() < AMDGPUSubtarget::SEA_ISLANDS) {
1048    // LDS is allocated in 64 dword blocks.
1049    LDSAlignShift = 8;
1050  } else {
1051    // LDS is allocated in 128 dword blocks.
1052    LDSAlignShift = 9;
1053  }
1054
1055  unsigned LDSSpillSize =
1056    MFI->getLDSWaveSpillSize() * MFI->getMaxFlatWorkGroupSize();
1057
1058  ProgInfo.LDSSize = MFI->getLDSSize() + LDSSpillSize;
1059  ProgInfo.LDSBlocks =
1060      alignTo(ProgInfo.LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift;
1061
1062  // Scratch is allocated in 256 dword blocks.
1063  unsigned ScratchAlignShift = 10;
1064  // We need to program the hardware with the amount of scratch memory that
1065  // is used by the entire wave.  ProgInfo.ScratchSize is the amount of
1066  // scratch memory used per thread.
1067  ProgInfo.ScratchBlocks =
1068      alignTo(ProgInfo.ScratchSize * STM.getWavefrontSize(),
1069              1ULL << ScratchAlignShift) >>
1070      ScratchAlignShift;
1071
1072  if (getIsaVersion(getGlobalSTI()->getCPU()).Major >= 10) {
1073    ProgInfo.WgpMode = STM.isCuModeEnabled() ? 0 : 1;
1074    ProgInfo.MemOrdered = 1;
1075  }
1076
1077  ProgInfo.ComputePGMRSrc1 =
1078      S_00B848_VGPRS(ProgInfo.VGPRBlocks) |
1079      S_00B848_SGPRS(ProgInfo.SGPRBlocks) |
1080      S_00B848_PRIORITY(ProgInfo.Priority) |
1081      S_00B848_FLOAT_MODE(ProgInfo.FloatMode) |
1082      S_00B848_PRIV(ProgInfo.Priv) |
1083      S_00B848_DX10_CLAMP(ProgInfo.DX10Clamp) |
1084      S_00B848_DEBUG_MODE(ProgInfo.DebugMode) |
1085      S_00B848_IEEE_MODE(ProgInfo.IEEEMode) |
1086      S_00B848_WGP_MODE(ProgInfo.WgpMode) |
1087      S_00B848_MEM_ORDERED(ProgInfo.MemOrdered);
1088
1089  // 0 = X, 1 = XY, 2 = XYZ
1090  unsigned TIDIGCompCnt = 0;
1091  if (MFI->hasWorkItemIDZ())
1092    TIDIGCompCnt = 2;
1093  else if (MFI->hasWorkItemIDY())
1094    TIDIGCompCnt = 1;
1095
1096  ProgInfo.ComputePGMRSrc2 =
1097      S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
1098      S_00B84C_USER_SGPR(MFI->getNumUserSGPRs()) |
1099      // For AMDHSA, TRAP_HANDLER must be zero, as it is populated by the CP.
1100      S_00B84C_TRAP_HANDLER(STM.isAmdHsaOS() ? 0 : STM.isTrapHandlerEnabled()) |
1101      S_00B84C_TGID_X_EN(MFI->hasWorkGroupIDX()) |
1102      S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) |
1103      S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) |
1104      S_00B84C_TG_SIZE_EN(MFI->hasWorkGroupInfo()) |
1105      S_00B84C_TIDIG_COMP_CNT(TIDIGCompCnt) |
1106      S_00B84C_EXCP_EN_MSB(0) |
1107      // For AMDHSA, LDS_SIZE must be zero, as it is populated by the CP.
1108      S_00B84C_LDS_SIZE(STM.isAmdHsaOS() ? 0 : ProgInfo.LDSBlocks) |
1109      S_00B84C_EXCP_EN(0);
1110
1111  ProgInfo.Occupancy = STM.computeOccupancy(MF, ProgInfo.LDSSize,
1112                                            ProgInfo.NumSGPRsForWavesPerEU,
1113                                            ProgInfo.NumVGPRsForWavesPerEU);
1114}
1115
1116static unsigned getRsrcReg(CallingConv::ID CallConv) {
1117  switch (CallConv) {
1118  default: LLVM_FALLTHROUGH;
1119  case CallingConv::AMDGPU_CS: return R_00B848_COMPUTE_PGM_RSRC1;
1120  case CallingConv::AMDGPU_LS: return R_00B528_SPI_SHADER_PGM_RSRC1_LS;
1121  case CallingConv::AMDGPU_HS: return R_00B428_SPI_SHADER_PGM_RSRC1_HS;
1122  case CallingConv::AMDGPU_ES: return R_00B328_SPI_SHADER_PGM_RSRC1_ES;
1123  case CallingConv::AMDGPU_GS: return R_00B228_SPI_SHADER_PGM_RSRC1_GS;
1124  case CallingConv::AMDGPU_VS: return R_00B128_SPI_SHADER_PGM_RSRC1_VS;
1125  case CallingConv::AMDGPU_PS: return R_00B028_SPI_SHADER_PGM_RSRC1_PS;
1126  }
1127}
1128
1129void AMDGPUAsmPrinter::EmitProgramInfoSI(const MachineFunction &MF,
1130                                         const SIProgramInfo &CurrentProgramInfo) {
1131  const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1132  unsigned RsrcReg = getRsrcReg(MF.getFunction().getCallingConv());
1133
1134  if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) {
1135    OutStreamer->EmitIntValue(R_00B848_COMPUTE_PGM_RSRC1, 4);
1136
1137    OutStreamer->EmitIntValue(CurrentProgramInfo.ComputePGMRSrc1, 4);
1138
1139    OutStreamer->EmitIntValue(R_00B84C_COMPUTE_PGM_RSRC2, 4);
1140    OutStreamer->EmitIntValue(CurrentProgramInfo.ComputePGMRSrc2, 4);
1141
1142    OutStreamer->EmitIntValue(R_00B860_COMPUTE_TMPRING_SIZE, 4);
1143    OutStreamer->EmitIntValue(S_00B860_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
1144
1145    // TODO: Should probably note flat usage somewhere. SC emits a "FlatPtr32 =
1146    // 0" comment but I don't see a corresponding field in the register spec.
1147  } else {
1148    OutStreamer->EmitIntValue(RsrcReg, 4);
1149    OutStreamer->EmitIntValue(S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
1150                              S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks), 4);
1151    OutStreamer->EmitIntValue(R_0286E8_SPI_TMPRING_SIZE, 4);
1152    OutStreamer->EmitIntValue(
1153        S_0286E8_WAVESIZE(CurrentProgramInfo.ScratchBlocks), 4);
1154  }
1155
1156  if (MF.getFunction().getCallingConv() == CallingConv::AMDGPU_PS) {
1157    OutStreamer->EmitIntValue(R_00B02C_SPI_SHADER_PGM_RSRC2_PS, 4);
1158    OutStreamer->EmitIntValue(S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks), 4);
1159    OutStreamer->EmitIntValue(R_0286CC_SPI_PS_INPUT_ENA, 4);
1160    OutStreamer->EmitIntValue(MFI->getPSInputEnable(), 4);
1161    OutStreamer->EmitIntValue(R_0286D0_SPI_PS_INPUT_ADDR, 4);
1162    OutStreamer->EmitIntValue(MFI->getPSInputAddr(), 4);
1163  }
1164
1165  OutStreamer->EmitIntValue(R_SPILLED_SGPRS, 4);
1166  OutStreamer->EmitIntValue(MFI->getNumSpilledSGPRs(), 4);
1167  OutStreamer->EmitIntValue(R_SPILLED_VGPRS, 4);
1168  OutStreamer->EmitIntValue(MFI->getNumSpilledVGPRs(), 4);
1169}
1170
1171// This is the equivalent of EmitProgramInfoSI above, but for when the OS type
1172// is AMDPAL.  It stores each compute/SPI register setting and other PAL
1173// metadata items into the PALMD::Metadata, combining with any provided by the
1174// frontend as LLVM metadata. Once all functions are written, the PAL metadata
1175// is then written as a single block in the .note section.
1176void AMDGPUAsmPrinter::EmitPALMetadata(const MachineFunction &MF,
1177       const SIProgramInfo &CurrentProgramInfo) {
1178  const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1179  auto CC = MF.getFunction().getCallingConv();
1180  auto MD = getTargetStreamer()->getPALMetadata();
1181
1182  MD->setEntryPoint(CC, MF.getFunction().getName());
1183  MD->setNumUsedVgprs(CC, CurrentProgramInfo.NumVGPRsForWavesPerEU);
1184  MD->setNumUsedSgprs(CC, CurrentProgramInfo.NumSGPRsForWavesPerEU);
1185  if (AMDGPU::isCompute(MF.getFunction().getCallingConv())) {
1186    MD->setRsrc1(CC, CurrentProgramInfo.ComputePGMRSrc1);
1187    MD->setRsrc2(CC, CurrentProgramInfo.ComputePGMRSrc2);
1188  } else {
1189    MD->setRsrc1(CC, S_00B028_VGPRS(CurrentProgramInfo.VGPRBlocks) |
1190        S_00B028_SGPRS(CurrentProgramInfo.SGPRBlocks));
1191    if (CurrentProgramInfo.ScratchBlocks > 0)
1192      MD->setRsrc2(CC, S_00B84C_SCRATCH_EN(1));
1193  }
1194  // ScratchSize is in bytes, 16 aligned.
1195  MD->setScratchSize(CC, alignTo(CurrentProgramInfo.ScratchSize, 16));
1196  if (MF.getFunction().getCallingConv() == CallingConv::AMDGPU_PS) {
1197    MD->setRsrc2(CC, S_00B02C_EXTRA_LDS_SIZE(CurrentProgramInfo.LDSBlocks));
1198    MD->setSpiPsInputEna(MFI->getPSInputEnable());
1199    MD->setSpiPsInputAddr(MFI->getPSInputAddr());
1200  }
1201
1202  const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
1203  if (STM.isWave32())
1204    MD->setWave32(MF.getFunction().getCallingConv());
1205}
1206
1207// This is supposed to be log2(Size)
1208static amd_element_byte_size_t getElementByteSizeValue(unsigned Size) {
1209  switch (Size) {
1210  case 4:
1211    return AMD_ELEMENT_4_BYTES;
1212  case 8:
1213    return AMD_ELEMENT_8_BYTES;
1214  case 16:
1215    return AMD_ELEMENT_16_BYTES;
1216  default:
1217    llvm_unreachable("invalid private_element_size");
1218  }
1219}
1220
1221void AMDGPUAsmPrinter::getAmdKernelCode(amd_kernel_code_t &Out,
1222                                        const SIProgramInfo &CurrentProgramInfo,
1223                                        const MachineFunction &MF) const {
1224  const Function &F = MF.getFunction();
1225  assert(F.getCallingConv() == CallingConv::AMDGPU_KERNEL ||
1226         F.getCallingConv() == CallingConv::SPIR_KERNEL);
1227
1228  const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1229  const GCNSubtarget &STM = MF.getSubtarget<GCNSubtarget>();
1230
1231  AMDGPU::initDefaultAMDKernelCodeT(Out, &STM);
1232
1233  Out.compute_pgm_resource_registers =
1234      CurrentProgramInfo.ComputePGMRSrc1 |
1235      (CurrentProgramInfo.ComputePGMRSrc2 << 32);
1236  Out.code_properties |= AMD_CODE_PROPERTY_IS_PTR64;
1237
1238  if (CurrentProgramInfo.DynamicCallStack)
1239    Out.code_properties |= AMD_CODE_PROPERTY_IS_DYNAMIC_CALLSTACK;
1240
1241  AMD_HSA_BITS_SET(Out.code_properties,
1242                   AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE,
1243                   getElementByteSizeValue(STM.getMaxPrivateElementSize()));
1244
1245  if (MFI->hasPrivateSegmentBuffer()) {
1246    Out.code_properties |=
1247      AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
1248  }
1249
1250  if (MFI->hasDispatchPtr())
1251    Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
1252
1253  if (MFI->hasQueuePtr())
1254    Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
1255
1256  if (MFI->hasKernargSegmentPtr())
1257    Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
1258
1259  if (MFI->hasDispatchID())
1260    Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
1261
1262  if (MFI->hasFlatScratchInit())
1263    Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
1264
1265  if (MFI->hasDispatchPtr())
1266    Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
1267
1268  if (STM.isXNACKEnabled())
1269    Out.code_properties |= AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED;
1270
1271  Align MaxKernArgAlign;
1272  Out.kernarg_segment_byte_size = STM.getKernArgSegmentSize(F, MaxKernArgAlign);
1273  Out.wavefront_sgpr_count = CurrentProgramInfo.NumSGPR;
1274  Out.workitem_vgpr_count = CurrentProgramInfo.NumVGPR;
1275  Out.workitem_private_segment_byte_size = CurrentProgramInfo.ScratchSize;
1276  Out.workgroup_group_segment_byte_size = CurrentProgramInfo.LDSSize;
1277
1278  // kernarg_segment_alignment is specified as log of the alignment.
1279  // The minimum alignment is 16.
1280  Out.kernarg_segment_alignment = Log2(std::max(Align(16), MaxKernArgAlign));
1281}
1282
1283bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
1284                                       const char *ExtraCode, raw_ostream &O) {
1285  // First try the generic code, which knows about modifiers like 'c' and 'n'.
1286  if (!AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, O))
1287    return false;
1288
1289  if (ExtraCode && ExtraCode[0]) {
1290    if (ExtraCode[1] != 0)
1291      return true; // Unknown modifier.
1292
1293    switch (ExtraCode[0]) {
1294    case 'r':
1295      break;
1296    default:
1297      return true;
1298    }
1299  }
1300
1301  // TODO: Should be able to support other operand types like globals.
1302  const MachineOperand &MO = MI->getOperand(OpNo);
1303  if (MO.isReg()) {
1304    AMDGPUInstPrinter::printRegOperand(MO.getReg(), O,
1305                                       *MF->getSubtarget().getRegisterInfo());
1306    return false;
1307  }
1308
1309  return true;
1310}
1311