AArch64SchedExynosM3.td revision 360784
1//=- AArch64SchedExynosM3.td - Samsung Exynos M3 Sched Defs --*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for the Samsung Exynos M3 to support 10// instruction scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// The Exynos-M3 is an advanced superscalar microprocessor with a 6-wide 16// in-order stage for decode and dispatch and a wider issue stage. 17// The execution units and loads and stores are out-of-order. 18 19def ExynosM3Model : SchedMachineModel { 20 let IssueWidth = 6; // Up to 6 uops per cycle. 21 let MicroOpBufferSize = 228; // ROB size. 22 let LoopMicroOpBufferSize = 40; // Based on the instruction queue size. 23 let LoadLatency = 4; // Optimistic load cases. 24 let MispredictPenalty = 16; // Minimum branch misprediction penalty. 25 let CompleteModel = 1; // Use the default model otherwise. 26 27 list<Predicate> UnsupportedFeatures = SVEUnsupported.F; 28} 29 30//===----------------------------------------------------------------------===// 31// Define each kind of processor resource and number available on the Exynos-M3, 32// which has 12 pipelines, each with its own queue with out-of-order dispatch. 33 34let SchedModel = ExynosM3Model in { 35 36def M3UnitA : ProcResource<2>; // Simple integer 37def M3UnitC : ProcResource<2>; // Simple and complex integer 38def M3UnitD : ProcResource<1>; // Integer division (inside C0, serialized) 39def M3UnitB : ProcResource<2>; // Branch 40def M3UnitL : ProcResource<2>; // Load 41def M3UnitS : ProcResource<1>; // Store 42def M3PipeF0 : ProcResource<1>; // FP #0 43let Super = M3PipeF0 in { 44 def M3UnitFMAC0 : ProcResource<1>; // FP multiplication 45 def M3UnitFADD0 : ProcResource<1>; // Simple FP 46 def M3UnitFCVT0 : ProcResource<1>; // FP conversion 47 def M3UnitFSQR : ProcResource<2>; // FP square root (serialized) 48 def M3UnitNALU0 : ProcResource<1>; // Simple vector 49 def M3UnitNMSC : ProcResource<1>; // FP and vector miscellanea 50 def M3UnitNSHT0 : ProcResource<1>; // Vector shifting 51 def M3UnitNSHF0 : ProcResource<1>; // Vector shuffling 52} 53def M3PipeF1 : ProcResource<1>; // FP #1 54let Super = M3PipeF1 in { 55 def M3UnitFMAC1 : ProcResource<1>; // FP multiplication 56 def M3UnitFADD1 : ProcResource<1>; // Simple FP 57 def M3UnitFDIV0 : ProcResource<2>; // FP division (serialized) 58 def M3UnitFCVT1 : ProcResource<1>; // FP conversion 59 def M3UnitFST0 : ProcResource<1>; // FP store 60 def M3UnitNALU1 : ProcResource<1>; // Simple vector 61 def M3UnitNCRY0 : ProcResource<1>; // Cryptographic 62 def M3UnitNMUL : ProcResource<1>; // Vector multiplication 63 def M3UnitNSHT1 : ProcResource<1>; // Vector shifting 64 def M3UnitNSHF1 : ProcResource<1>; // Vector shuffling 65} 66def M3PipeF2 : ProcResource<1>; // FP #2 67let Super = M3PipeF2 in { 68 def M3UnitFMAC2 : ProcResource<1>; // FP multiplication 69 def M3UnitFADD2 : ProcResource<1>; // Simple FP 70 def M3UnitFDIV1 : ProcResource<2>; // FP division (serialized) 71 def M3UnitFST1 : ProcResource<1>; // FP store 72 def M3UnitNALU2 : ProcResource<1>; // Simple vector 73 def M3UnitNCRY1 : ProcResource<1>; // Cryptographic 74 def M3UnitNSHT2 : ProcResource<1>; // Vector shifting 75 def M3UnitNSHF2 : ProcResource<1>; // Vector shuffling 76} 77 78 79def M3UnitALU : ProcResGroup<[M3UnitA, 80 M3UnitC]>; 81def M3UnitFMAC : ProcResGroup<[M3UnitFMAC0, 82 M3UnitFMAC1, 83 M3UnitFMAC2]>; 84def M3UnitFADD : ProcResGroup<[M3UnitFADD0, 85 M3UnitFADD1, 86 M3UnitFADD2]>; 87def M3UnitFDIV : ProcResGroup<[M3UnitFDIV0, 88 M3UnitFDIV1]>; 89def M3UnitFCVT : ProcResGroup<[M3UnitFCVT0, 90 M3UnitFCVT1]>; 91def M3UnitFST : ProcResGroup<[M3UnitFST0, 92 M3UnitFST1]>; 93def M3UnitNALU : ProcResGroup<[M3UnitNALU0, 94 M3UnitNALU1, 95 M3UnitNALU2]>; 96def M3UnitNCRY : ProcResGroup<[M3UnitNCRY0, 97 M3UnitNCRY1]>; 98def M3UnitNSHT : ProcResGroup<[M3UnitNSHT0, 99 M3UnitNSHT1, 100 M3UnitNSHT2]>; 101def M3UnitNSHF : ProcResGroup<[M3UnitNSHF0, 102 M3UnitNSHF1, 103 M3UnitNSHF2]>; 104 105//===----------------------------------------------------------------------===// 106// Coarse scheduling model. 107 108def M3WriteZ0 : SchedWriteRes<[]> { let Latency = 0; 109 let NumMicroOps = 1; } 110def M3WriteZ1 : SchedWriteRes<[]> { let Latency = 1; 111 let NumMicroOps = 0; } 112 113def M3WriteA1 : SchedWriteRes<[M3UnitALU]> { let Latency = 1; } 114def M3WriteAA : SchedWriteRes<[M3UnitALU]> { let Latency = 2; 115 let ResourceCycles = [2]; } 116def M3WriteAB : SchedWriteRes<[M3UnitALU, 117 M3UnitC]> { let Latency = 1; 118 let NumMicroOps = 2; } 119def M3WriteAC : SchedWriteRes<[M3UnitALU, 120 M3UnitALU, 121 M3UnitC]> { let Latency = 2; 122 let NumMicroOps = 3; } 123def M3WriteAD : SchedWriteRes<[M3UnitALU, 124 M3UnitC]> { let Latency = 2; 125 let NumMicroOps = 2; } 126def M3WriteC1 : SchedWriteRes<[M3UnitC]> { let Latency = 1; } 127def M3WriteC2 : SchedWriteRes<[M3UnitC]> { let Latency = 2; } 128def M3WriteAU : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M3WriteZ0]>, 129 SchedVar<ExynosArithPred, [M3WriteA1]>, 130 SchedVar<ExynosLogicPred, [M3WriteA1]>, 131 SchedVar<NoSchedPred, [M3WriteAA]>]>; 132def M3WriteAV : SchedWriteVariant<[SchedVar<IsCopyIdiomPred, [M3WriteZ0]>, 133 SchedVar<ExynosArithPred, [M3WriteA1]>, 134 SchedVar<NoSchedPred, [M3WriteAA]>]>; 135def M3WriteAW : SchedWriteVariant<[SchedVar<IsZeroIdiomPred, [M3WriteZ0]>, 136 SchedVar<ExynosLogicPred, [M3WriteA1]>, 137 SchedVar<NoSchedPred, [M3WriteAA]>]>; 138def M3WriteAX : SchedWriteVariant<[SchedVar<ExynosArithPred, [M3WriteA1]>, 139 SchedVar<ExynosLogicPred, [M3WriteA1]>, 140 SchedVar<NoSchedPred, [M3WriteAA]>]>; 141def M3WriteAY : SchedWriteVariant<[SchedVar<ExynosRotateRightImmPred, [M3WriteA1]>, 142 SchedVar<NoSchedPred, [M3WriteAA]>]>; 143 144def M3WriteB1 : SchedWriteRes<[M3UnitB]> { let Latency = 1; } 145def M3WriteBX : SchedWriteVariant<[SchedVar<ExynosBranchLinkLRPred, [M3WriteAC]>, 146 SchedVar<NoSchedPred, [M3WriteAB]>]>; 147 148def M3WriteL4 : SchedWriteRes<[M3UnitL]> { let Latency = 4; } 149def M3WriteL5 : SchedWriteRes<[M3UnitL]> { let Latency = 5; } 150def M3WriteLA : SchedWriteRes<[M3UnitL, 151 M3UnitL]> { let Latency = 5; 152 let NumMicroOps = 1; } 153def M3WriteLB : SchedWriteRes<[M3UnitA, 154 M3UnitL]> { let Latency = 5; 155 let NumMicroOps = 2; } 156def M3WriteLC : SchedWriteRes<[M3UnitA, 157 M3UnitL, 158 M3UnitL]> { let Latency = 5; 159 let NumMicroOps = 2; } 160def M3WriteLD : SchedWriteRes<[M3UnitA, 161 M3UnitL]> { let Latency = 4; 162 let NumMicroOps = 2; } 163def M3WriteLE : SchedWriteRes<[M3UnitA, 164 M3UnitL]> { let Latency = 6; 165 let NumMicroOps = 2; } 166def M3WriteLH : SchedWriteRes<[]> { let Latency = 5; 167 let NumMicroOps = 0; } 168def M3WriteLX : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M3WriteL5]>, 169 SchedVar<NoSchedPred, [M3WriteL4]>]>; 170def M3WriteLY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M3WriteLE]>, 171 SchedVar<NoSchedPred, [M3WriteL5]>]>; 172 173def M3WriteS1 : SchedWriteRes<[M3UnitS]> { let Latency = 1; } 174def M3WriteSA : SchedWriteRes<[M3UnitA, 175 M3UnitS, 176 M3UnitFST]> { let Latency = 3; 177 let NumMicroOps = 2; } 178def M3WriteSB : SchedWriteRes<[M3UnitA, 179 M3UnitS]> { let Latency = 2; 180 let NumMicroOps = 2; } 181def M3WriteSC : SchedWriteRes<[M3UnitA, 182 M3UnitS, 183 M3UnitFST]> { let Latency = 1; 184 let NumMicroOps = 2; } 185def M3WriteSY : SchedWriteVariant<[SchedVar<ExynosScaledIdxPred, [M3WriteSA]>, 186 SchedVar<NoSchedPred, [WriteVST]>]>; 187 188def M3ReadAdrBase : SchedReadVariant<[SchedVar<ExynosScaledIdxPred, [ReadDefault]>, 189 SchedVar<NoSchedPred, [ReadDefault]>]>; 190 191// Branch instructions. 192def : SchedAlias<WriteBr, M3WriteZ0>; 193def : SchedAlias<WriteBrReg, M3WriteC1>; 194 195// Arithmetic and logical integer instructions. 196def : SchedAlias<WriteI, M3WriteA1>; 197def : SchedAlias<WriteISReg, M3WriteA1>; 198def : SchedAlias<WriteIEReg, M3WriteA1>; 199def : SchedAlias<WriteIS, M3WriteA1>; 200 201// Move instructions. 202def : SchedAlias<WriteImm, M3WriteA1>; 203 204// Divide and multiply instructions. 205def : WriteRes<WriteID32, [M3UnitC, 206 M3UnitD]> { let Latency = 12; 207 let ResourceCycles = [1, 12]; } 208def : WriteRes<WriteID64, [M3UnitC, 209 M3UnitD]> { let Latency = 21; 210 let ResourceCycles = [1, 21]; } 211def : WriteRes<WriteIM32, [M3UnitC]> { let Latency = 3; } 212def : WriteRes<WriteIM64, [M3UnitC]> { let Latency = 4; 213 let ResourceCycles = [2]; } 214 215// Miscellaneous instructions. 216def : SchedAlias<WriteExtr, M3WriteAY>; 217 218// Addressing modes. 219def : SchedAlias<WriteAdr, M3WriteZ1>; 220def : SchedAlias<ReadAdrBase, M3ReadAdrBase>; 221 222// Load instructions. 223def : SchedAlias<WriteLD, M3WriteL4>; 224def : WriteRes<WriteLDHi, []> { let Latency = 4; 225 let NumMicroOps = 0; } 226def : SchedAlias<WriteLDIdx, M3WriteLB>; 227 228// Store instructions. 229def : SchedAlias<WriteST, M3WriteS1>; 230def : SchedAlias<WriteSTP, M3WriteS1>; 231def : SchedAlias<WriteSTX, M3WriteS1>; 232def : SchedAlias<WriteSTIdx, M3WriteSB>; 233 234// FP data instructions. 235def : WriteRes<WriteF, [M3UnitFADD]> { let Latency = 2; } 236def : WriteRes<WriteFCmp, [M3UnitNMSC]> { let Latency = 2; } 237def : WriteRes<WriteFDiv, [M3UnitFDIV]> { let Latency = 12; 238 let ResourceCycles = [12]; } 239def : WriteRes<WriteFMul, [M3UnitFMAC]> { let Latency = 4; } 240 241// FP miscellaneous instructions. 242def : WriteRes<WriteFCvt, [M3UnitFCVT]> { let Latency = 3; } 243def : WriteRes<WriteFImm, [M3UnitNALU]> { let Latency = 1; } 244def : WriteRes<WriteFCopy, [M3UnitNALU]> { let Latency = 1; } 245 246// FP load instructions. 247def : SchedAlias<WriteVLD, M3WriteL5>; 248 249// FP store instructions. 250def : WriteRes<WriteVST, [M3UnitS, 251 M3UnitFST]> { let Latency = 1; 252 let NumMicroOps = 1; } 253 254// ASIMD FP instructions. 255def : WriteRes<WriteV, [M3UnitNALU]> { let Latency = 3; } 256 257// Other miscellaneous instructions. 258def : WriteRes<WriteAtomic, []> { let Unsupported = 1; } 259def : WriteRes<WriteBarrier, []> { let Latency = 1; } 260def : WriteRes<WriteHint, []> { let Latency = 1; } 261def : WriteRes<WriteSys, []> { let Latency = 1; } 262 263//===----------------------------------------------------------------------===// 264// Generic fast forwarding. 265 266// TODO: Add FP register forwarding rules. 267 268def : ReadAdvance<ReadI, 0>; 269def : ReadAdvance<ReadISReg, 0>; 270def : ReadAdvance<ReadIEReg, 0>; 271def : ReadAdvance<ReadIM, 0>; 272// TODO: The forwarding for 32 bits actually saves 2 cycles. 273def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>; 274def : ReadAdvance<ReadID, 0>; 275def : ReadAdvance<ReadExtrHi, 0>; 276def : ReadAdvance<ReadAdrBase, 0>; 277def : ReadAdvance<ReadVLD, 0>; 278 279//===----------------------------------------------------------------------===// 280// Finer scheduling model. 281 282def M3WriteNEONA : SchedWriteRes<[M3UnitNSHF, 283 M3UnitFADD]> { let Latency = 3; 284 let NumMicroOps = 2; } 285def M3WriteNEONB : SchedWriteRes<[M3UnitNALU, 286 M3UnitFST]> { let Latency = 10; 287 let NumMicroOps = 2; } 288def M3WriteNEOND : SchedWriteRes<[M3UnitNSHF, 289 M3UnitFST]> { let Latency = 6; 290 let NumMicroOps = 2; } 291def M3WriteNEONH : SchedWriteRes<[M3UnitNALU, 292 M3UnitS]> { let Latency = 5; 293 let NumMicroOps = 2; } 294def M3WriteNEONI : SchedWriteRes<[M3UnitNSHF, 295 M3UnitS]> { let Latency = 5; 296 let NumMicroOps = 2; } 297def M3WriteNEONV : SchedWriteRes<[M3UnitFDIV0, 298 M3UnitFDIV1]> { let Latency = 7; 299 let NumMicroOps = 2; 300 let ResourceCycles = [8, 8]; } 301def M3WriteNEONW : SchedWriteRes<[M3UnitFDIV0, 302 M3UnitFDIV1]> { let Latency = 12; 303 let NumMicroOps = 2; 304 let ResourceCycles = [13, 13]; } 305def M3WriteNEONX : SchedWriteRes<[M3UnitFSQR, 306 M3UnitFSQR]> { let Latency = 18; 307 let NumMicroOps = 2; 308 let ResourceCycles = [19, 19]; } 309def M3WriteNEONY : SchedWriteRes<[M3UnitFSQR, 310 M3UnitFSQR]> { let Latency = 25; 311 let NumMicroOps = 2; 312 let ResourceCycles = [26, 26]; } 313def M3WriteNEONZ : SchedWriteRes<[M3UnitNMSC, 314 M3UnitNMSC]> { let Latency = 5; 315 let NumMicroOps = 2; } 316def M3WriteFADD2 : SchedWriteRes<[M3UnitFADD]> { let Latency = 2; } 317def M3WriteFCVT2 : SchedWriteRes<[M3UnitFCVT]> { let Latency = 2; } 318def M3WriteFCVT3 : SchedWriteRes<[M3UnitFCVT]> { let Latency = 3; } 319def M3WriteFCVT3A : SchedWriteRes<[M3UnitFCVT0]> { let Latency = 3; } 320def M3WriteFCVT4A : SchedWriteRes<[M3UnitFCVT0]> { let Latency = 4; } 321def M3WriteFCVT4 : SchedWriteRes<[M3UnitFCVT]> { let Latency = 4; } 322def M3WriteFDIV10 : SchedWriteRes<[M3UnitFDIV]> { let Latency = 7; 323 let ResourceCycles = [8]; } 324def M3WriteFDIV12 : SchedWriteRes<[M3UnitFDIV]> { let Latency = 12; 325 let ResourceCycles = [13]; } 326def M3WriteFMAC3 : SchedWriteRes<[M3UnitFMAC]> { let Latency = 3; } 327def M3WriteFMAC4 : SchedWriteRes<[M3UnitFMAC]> { let Latency = 4; } 328def M3WriteFMAC5 : SchedWriteRes<[M3UnitFMAC]> { let Latency = 5; } 329def M3WriteFSQR17 : SchedWriteRes<[M3UnitFSQR]> { let Latency = 18; 330 let ResourceCycles = [19]; } 331def M3WriteFSQR25 : SchedWriteRes<[M3UnitFSQR]> { let Latency = 25; 332 let ResourceCycles = [26]; } 333def M3WriteNALU1 : SchedWriteRes<[M3UnitNALU]> { let Latency = 1; } 334def M3WriteNCRY1A : SchedWriteRes<[M3UnitNCRY0]> { let Latency = 1; } 335def M3WriteNCRY3A : SchedWriteRes<[M3UnitNCRY0]> { let Latency = 3; } 336def M3WriteNCRY5A : SchedWriteRes<[M3UnitNCRY]> { let Latency = 5; } 337def M3WriteNMSC1 : SchedWriteRes<[M3UnitNMSC]> { let Latency = 1; } 338def M3WriteNMSC2 : SchedWriteRes<[M3UnitNMSC]> { let Latency = 2; } 339def M3WriteNMSC3 : SchedWriteRes<[M3UnitNMSC]> { let Latency = 3; } 340def M3WriteNMUL3 : SchedWriteRes<[M3UnitNMUL]> { let Latency = 3; } 341def M3WriteNSHF1 : SchedWriteRes<[M3UnitNSHF]> { let Latency = 1; } 342def M3WriteNSHF3 : SchedWriteRes<[M3UnitNSHF]> { let Latency = 3; } 343def M3WriteNSHT1 : SchedWriteRes<[M3UnitNSHT]> { let Latency = 1; } 344def M3WriteNSHT2 : SchedWriteRes<[M3UnitNSHT]> { let Latency = 2; } 345def M3WriteNSHT3 : SchedWriteRes<[M3UnitNSHT]> { let Latency = 3; } 346def M3WriteVLDA : SchedWriteRes<[M3UnitL, 347 M3UnitL]> { let Latency = 5; 348 let NumMicroOps = 2; } 349def M3WriteVLDB : SchedWriteRes<[M3UnitL, 350 M3UnitL, 351 M3UnitL]> { let Latency = 6; 352 let NumMicroOps = 3; } 353def M3WriteVLDC : SchedWriteRes<[M3UnitL, 354 M3UnitL, 355 M3UnitL, 356 M3UnitL]> { let Latency = 6; 357 let NumMicroOps = 4; } 358def M3WriteVLDD : SchedWriteRes<[M3UnitL, 359 M3UnitNALU]> { let Latency = 7; 360 let NumMicroOps = 2; 361 let ResourceCycles = [2, 1]; } 362def M3WriteVLDE : SchedWriteRes<[M3UnitL, 363 M3UnitNALU]> { let Latency = 6; 364 let NumMicroOps = 2; 365 let ResourceCycles = [2, 1]; } 366def M3WriteVLDF : SchedWriteRes<[M3UnitL, 367 M3UnitL]> { let Latency = 10; 368 let NumMicroOps = 2; 369 let ResourceCycles = [5, 5]; } 370def M3WriteVLDG : SchedWriteRes<[M3UnitL, 371 M3UnitNALU, 372 M3UnitNALU]> { let Latency = 7; 373 let NumMicroOps = 3; 374 let ResourceCycles = [2, 1, 1]; } 375def M3WriteVLDH : SchedWriteRes<[M3UnitL, 376 M3UnitNALU, 377 M3UnitNALU]> { let Latency = 6; 378 let NumMicroOps = 3; 379 let ResourceCycles = [2, 1, 1]; } 380def M3WriteVLDI : SchedWriteRes<[M3UnitL, 381 M3UnitL, 382 M3UnitL]> { let Latency = 12; 383 let NumMicroOps = 3; 384 let ResourceCycles = [6, 6, 6]; } 385def M3WriteVLDJ : SchedWriteRes<[M3UnitL, 386 M3UnitNALU, 387 M3UnitNALU, 388 M3UnitNALU]> { let Latency = 7; 389 let NumMicroOps = 4; 390 let ResourceCycles = [2, 1, 1, 1]; } 391def M3WriteVLDK : SchedWriteRes<[M3UnitL, 392 M3UnitNALU, 393 M3UnitNALU, 394 M3UnitNALU, 395 M3UnitNALU]> { let Latency = 9; 396 let NumMicroOps = 5; 397 let ResourceCycles = [4, 1, 1, 1, 1]; } 398def M3WriteVLDL : SchedWriteRes<[M3UnitL, 399 M3UnitNALU, 400 M3UnitNALU, 401 M3UnitL, 402 M3UnitNALU]> { let Latency = 6; 403 let NumMicroOps = 5; 404 let ResourceCycles = [6, 1, 1, 6, 1]; } 405def M3WriteVLDM : SchedWriteRes<[M3UnitL, 406 M3UnitNALU, 407 M3UnitNALU, 408 M3UnitL, 409 M3UnitNALU, 410 M3UnitNALU]> { let Latency = 7; 411 let NumMicroOps = 6; 412 let ResourceCycles = [6, 1, 1, 6, 1, 1]; } 413def M3WriteVLDN : SchedWriteRes<[M3UnitL, 414 M3UnitL, 415 M3UnitL, 416 M3UnitL]> { let Latency = 14; 417 let NumMicroOps = 4; 418 let ResourceCycles = [6, 6, 6, 6]; } 419def M3WriteVSTA : WriteSequence<[WriteVST], 2>; 420def M3WriteVSTB : WriteSequence<[WriteVST], 3>; 421def M3WriteVSTC : WriteSequence<[WriteVST], 4>; 422def M3WriteVSTD : SchedWriteRes<[M3UnitS, 423 M3UnitFST, 424 M3UnitS, 425 M3UnitFST]> { let Latency = 7; 426 let NumMicroOps = 4; 427 let ResourceCycles = [1, 3, 1, 3]; } 428def M3WriteVSTE : SchedWriteRes<[M3UnitS, 429 M3UnitFST, 430 M3UnitS, 431 M3UnitFST, 432 M3UnitS, 433 M3UnitFST]> { let Latency = 8; 434 let NumMicroOps = 6; 435 let ResourceCycles = [1, 3, 1, 3, 1, 3]; } 436def M3WriteVSTF : SchedWriteRes<[M3UnitNALU, 437 M3UnitFST, 438 M3UnitFST, 439 M3UnitS, 440 M3UnitFST, 441 M3UnitS, 442 M3UnitFST]> { let Latency = 15; 443 let NumMicroOps = 7; 444 let ResourceCycles = [1, 3, 3, 1, 3, 1, 3]; } 445def M3WriteVSTG : SchedWriteRes<[M3UnitNALU, 446 M3UnitFST, 447 M3UnitFST, 448 M3UnitS, 449 M3UnitFST, 450 M3UnitS, 451 M3UnitFST, 452 M3UnitS, 453 M3UnitFST]> { let Latency = 16; 454 let NumMicroOps = 9; 455 let ResourceCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; } 456def M3WriteVSTH : SchedWriteRes<[M3UnitNALU, 457 M3UnitFST, 458 M3UnitFST, 459 M3UnitS, 460 M3UnitFST]> { let Latency = 14; 461 let NumMicroOps = 5; 462 let ResourceCycles = [1, 3, 3, 1, 3]; } 463def M3WriteVSTI : SchedWriteRes<[M3UnitNALU, 464 M3UnitFST, 465 M3UnitFST, 466 M3UnitS, 467 M3UnitFST, 468 M3UnitS, 469 M3UnitFST, 470 M3UnitS, 471 M3UnitFST]> { let Latency = 17; 472 let NumMicroOps = 9; 473 let ResourceCycles = [1, 3, 3, 1, 3, 1, 3, 1, 3]; } 474 475// Special cases. 476def M3WriteAES : SchedWriteRes<[M3UnitNCRY]> { let Latency = 1; } 477def M3WriteCOPY : SchedWriteVariant<[SchedVar<ExynosFPPred, [M3WriteNALU1]>, 478 SchedVar<NoSchedPred, [M3WriteZ0]>]>; 479def M3WriteMOVI : SchedWriteVariant<[SchedVar<IsZeroFPIdiomPred, [M3WriteZ0]>, 480 SchedVar<NoSchedPred, [M3WriteNALU1]>]>; 481 482// Fast forwarding. 483def M3ReadAES : SchedReadAdvance<1, [M3WriteAES]>; 484def M3ReadFMAC : SchedReadAdvance<1, [M3WriteFMAC4, 485 M3WriteFMAC5]>; 486def M3ReadNMUL : SchedReadAdvance<1, [M3WriteNMUL3]>; 487 488// Branch instructions 489def : InstRW<[M3WriteB1], (instrs Bcc)>; 490def : InstRW<[M3WriteA1], (instrs BL)>; 491def : InstRW<[M3WriteBX], (instrs BLR)>; 492def : InstRW<[M3WriteC1], (instregex "^CBN?Z[WX]")>; 493def : InstRW<[M3WriteAD], (instregex "^TBN?Z[WX]")>; 494 495// Arithmetic and logical integer instructions. 496def : InstRW<[M3WriteAX], (instregex "^(ADD|AND|BIC|EON|EOR|ORN|SUB)[WX]rs$")>; 497def : InstRW<[M3WriteAU], (instrs ORRWrs, ORRXrs)>; 498def : InstRW<[M3WriteAX], (instregex "^(ADD|SUB)S?[WX]rx(64)?$")>; 499def : InstRW<[M3WriteAX], (instregex "^(ADD|AND|BIC|SUB)S[WX]rs$")>; 500def : InstRW<[M3WriteAV], (instrs ADDWri, ADDXri)>; 501def : InstRW<[M3WriteAW], (instrs ORRWri, ORRXri)>; 502 503// Move instructions. 504def : InstRW<[M3WriteCOPY], (instrs COPY)>; 505def : InstRW<[M3WriteZ0], (instrs ADR, ADRP)>; 506def : InstRW<[M3WriteZ0], (instregex "^MOV[NZ][WX]i")>; 507 508// Divide and multiply instructions. 509 510// Miscellaneous instructions. 511 512// Load instructions. 513def : InstRW<[M3WriteLD, 514 WriteLDHi, 515 WriteAdr], (instregex "^LDP(SW|W|X)(post|pre)")>; 516def : InstRW<[M3WriteLB, 517 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roW")>; 518def : InstRW<[M3WriteLX, 519 ReadAdrBase], (instregex "^LDR(BB|SBW|SBX|HH|SHW|SHX|SW|W|X)roX")>; 520def : InstRW<[M3WriteLB, 521 ReadAdrBase], (instrs PRFMroW)>; 522def : InstRW<[M3WriteLX, 523 ReadAdrBase], (instrs PRFMroX)>; 524 525// Store instructions. 526def : InstRW<[M3WriteSB, 527 ReadAdrBase], (instregex "^STR(BB|HH|W|X)roW")>; 528def : InstRW<[WriteST, 529 ReadAdrBase], (instregex "^STR(BB|HH|W|X)roX")>; 530 531// FP data instructions. 532def : InstRW<[M3WriteNSHF1], (instregex "^FABS[DS]r")>; 533def : InstRW<[M3WriteFADD2], (instregex "^F(ADD|SUB)[DS]rr")>; 534def : InstRW<[M3WriteFDIV10], (instrs FDIVSrr)>; 535def : InstRW<[M3WriteFDIV12], (instrs FDIVDrr)>; 536def : InstRW<[M3WriteNMSC1], (instregex "^F(MAX|MIN).+rr")>; 537def : InstRW<[M3WriteFMAC3], (instregex "^FN?MUL[DS]rr")>; 538def : InstRW<[M3WriteFMAC4, 539 M3ReadFMAC], (instregex "^FN?M(ADD|SUB)[DS]rrr")>; 540def : InstRW<[M3WriteNALU1], (instregex "^FNEG[DS]r")>; 541def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT.+r")>; 542def : InstRW<[M3WriteNEONH], (instregex "^FCSEL[DS]rrr")>; 543def : InstRW<[M3WriteFSQR17], (instrs FSQRTSr)>; 544def : InstRW<[M3WriteFSQR25], (instrs FSQRTDr)>; 545 546// FP miscellaneous instructions. 547def : InstRW<[M3WriteFCVT3], (instregex "^FCVT[DHS][DHS]r")>; 548def : InstRW<[M3WriteFCVT4A], (instregex "^[SU]CVTF[SU][XW][DHS]ri")>; 549def : InstRW<[M3WriteFCVT3A], (instregex "^FCVT[AMNPZ][SU]U[XW][DHS]r")>; 550def : InstRW<[M3WriteFCVT3A], (instregex "^FCVTZ[SU][dhs]")>; 551def : InstRW<[M3WriteNALU1], (instregex "^FMOV[DS][ir]")>; 552def : InstRW<[M3WriteFCVT4], (instregex "^[FU](RECP|RSQRT)Ev1")>; 553def : InstRW<[M3WriteNMSC1], (instregex "^FRECPXv1")>; 554def : InstRW<[M3WriteFMAC4, 555 M3ReadFMAC], (instregex "^F(RECP|RSQRT)S(16|32|64)")>; 556def : InstRW<[M3WriteNALU1], (instregex "^FMOV[WX][DS]r")>; 557def : InstRW<[M3WriteNALU1], (instregex "^FMOV[DS][WX]r")>; 558def : InstRW<[M3WriteNEONI], (instregex "^FMOV(DX|XD)Highr")>; 559 560// FP load instructions. 561def : InstRW<[WriteVLD], (instregex "^LDR[DSQ]l")>; 562def : InstRW<[WriteVLD], (instregex "^LDUR[BDHSQ]i")>; 563def : InstRW<[WriteVLD, 564 WriteAdr], (instregex "^LDR[BDHSQ](post|pre)")>; 565def : InstRW<[WriteVLD], (instregex "^LDR[BDHSQ]ui")>; 566def : InstRW<[M3WriteLE, 567 ReadAdrBase], (instregex "^LDR[BDHS]roW")>; 568def : InstRW<[WriteVLD, 569 ReadAdrBase], (instregex "^LDR[BDHS]roX")>; 570def : InstRW<[M3WriteLY, 571 ReadAdrBase], (instregex "^LDRQro[WX]")>; 572def : InstRW<[WriteVLD, 573 M3WriteLH], (instregex "^LDN?P[DS]i")>; 574def : InstRW<[M3WriteLA, 575 M3WriteLH], (instregex "^LDN?PQi")>; 576def : InstRW<[M3WriteLB, 577 M3WriteLH, 578 WriteAdr], (instregex "^LDP[DS](post|pre)")>; 579def : InstRW<[M3WriteLC, 580 M3WriteLH, 581 WriteAdr], (instregex "^LDPQ(post|pre)")>; 582 583// FP store instructions. 584def : InstRW<[WriteVST], (instregex "^STUR[BDHSQ]i")>; 585def : InstRW<[WriteVST, 586 WriteAdr], (instregex "^STR[BDHSQ](post|pre)")>; 587def : InstRW<[WriteVST], (instregex "^STR[BDHSQ]ui")>; 588def : InstRW<[M3WriteSA, 589 ReadAdrBase], (instregex "^STR[BDHS]roW")>; 590def : InstRW<[M3WriteSA, 591 ReadAdrBase], (instregex "^STRQroW")>; 592def : InstRW<[WriteVST, 593 ReadAdrBase], (instregex "^STR[BDHS]roX")>; 594def : InstRW<[M3WriteSY, 595 ReadAdrBase], (instregex "^STRQroX")>; 596def : InstRW<[WriteVST], (instregex "^STN?P[DSQ]i")>; 597def : InstRW<[WriteVST, 598 WriteAdr], (instregex "^STP[DS](post|pre)")>; 599def : InstRW<[M3WriteSC, 600 WriteAdr], (instregex "^STPQ(post|pre)")>; 601 602// ASIMD instructions. 603def : InstRW<[M3WriteNMSC3], (instregex "^[SU]ABAL?v")>; 604def : InstRW<[M3WriteNMSC1], (instregex "^[SU]ABDL?v")>; 605def : InstRW<[M3WriteNMSC1], (instregex "^((SQ)?ABS|SQNEG)v")>; 606def : InstRW<[M3WriteNALU1], (instregex "^(ADD|NEG|SUB)v")>; 607def : InstRW<[M3WriteNMSC3], (instregex "^[SU]?ADDL?Pv")>; 608def : InstRW<[M3WriteNMSC3], (instregex "^[SU]H(ADD|SUB)v")>; 609def : InstRW<[M3WriteNMSC3], (instregex "^[SU](ADD|SUB)[LW]V?v")>; 610def : InstRW<[M3WriteNMSC3], (instregex "^R?(ADD|SUB)HN2?v")>; 611def : InstRW<[M3WriteNMSC3], (instregex "^[SU]Q(ADD|SUB)v")>; 612def : InstRW<[M3WriteNMSC3], (instregex "^(SU|US)QADDv")>; 613def : InstRW<[M3WriteNMSC3], (instregex "^[SU]RHADDv")>; 614def : InstRW<[M3WriteNMSC1], (instregex "^CM(EQ|GE|GT|HI|HS|LE|LT)v")>; 615def : InstRW<[M3WriteNALU1], (instregex "^CMTSTv")>; 616def : InstRW<[M3WriteNALU1], (instregex "^(AND|BIC|EOR|MVNI|NOT|ORN|ORR)v")>; 617def : InstRW<[M3WriteNMSC1], (instregex "^[SU](MIN|MAX)v")>; 618def : InstRW<[M3WriteNMSC2], (instregex "^[SU](MIN|MAX)Pv")>; 619def : InstRW<[M3WriteNMSC3], (instregex "^[SU](MIN|MAX)Vv")>; 620def : InstRW<[M3WriteNMUL3], (instregex "^(MUL|SQR?DMULH)v")>; 621def : InstRW<[M3WriteNMUL3, 622 M3ReadNMUL], (instregex "^ML[AS]v")>; 623def : InstRW<[M3WriteNMUL3], (instregex "^[SU]ML[AS]Lv")>; 624def : InstRW<[M3WriteNMUL3], (instregex "^SQDML[AS]L")>; 625def : InstRW<[M3WriteNMUL3], (instregex "^(S|U|SQD)MULLv")>; 626def : InstRW<[M3WriteNMSC3], (instregex "^[SU]ADALPv")>; 627def : InstRW<[M3WriteNSHT3], (instregex "^[SU]R?SRAv")>; 628def : InstRW<[M3WriteNSHT1], (instregex "^SHL[dv]")>; 629def : InstRW<[M3WriteNSHT1], (instregex "^[SU]SH[LR][dv]")>; 630def : InstRW<[M3WriteNSHT1], (instregex "^S[RS]I[dv]")>; 631def : InstRW<[M3WriteNSHT2], (instregex "^[SU]?SHLLv")>; 632def : InstRW<[M3WriteNSHT3], (instregex "^(([SU]Q)?R)?SHRU?N[bhsv]")>; 633def : InstRW<[M3WriteNSHT3], (instregex "^[SU]RSH[LR][dv]")>; 634def : InstRW<[M3WriteNSHT3], (instregex "^[SU]QR?SHLU?[bdhsv]")>; 635 636// ASIMD FP instructions. 637def : InstRW<[M3WriteNSHF1], (instregex "^FABSv")>; 638def : InstRW<[M3WriteFADD2], (instregex "^F(ABD|ADD|SUB)v")>; 639def : InstRW<[M3WriteNEONA], (instregex "^FADDP")>; 640def : InstRW<[M3WriteNMSC1], (instregex "^F(AC|CM)(EQ|GE|GT|LE|LT)v[^1]")>; 641def : InstRW<[M3WriteFCVT3], (instregex "^FCVT(L|N|XN)v")>; 642def : InstRW<[M3WriteFCVT2], (instregex "^FCVT[AMNPZ][SU]v")>; 643def : InstRW<[M3WriteFCVT2], (instregex "^[SU]CVTFv")>; 644def : InstRW<[M3WriteFDIV10], (instrs FDIVv2f32)>; 645def : InstRW<[M3WriteNEONV], (instrs FDIVv4f32)>; 646def : InstRW<[M3WriteNEONW], (instrs FDIVv2f64)>; 647def : InstRW<[M3WriteNMSC1], (instregex "^F(MAX|MIN)(NM)?v")>; 648def : InstRW<[M3WriteNMSC2], (instregex "^F(MAX|MIN)(NM)?Pv")>; 649def : InstRW<[M3WriteNEONZ], (instregex "^F(MAX|MIN)(NM)?Vv")>; 650def : InstRW<[M3WriteFMAC3], (instregex "^FMULX?v.[fi]")>; 651def : InstRW<[M3WriteFMAC4, 652 M3ReadFMAC], (instregex "^FML[AS]v.f")>; 653def : InstRW<[M3WriteFMAC5, 654 M3ReadFMAC], (instregex "^FML[AS]v.i")>; 655def : InstRW<[M3WriteNALU1], (instregex "^FNEGv")>; 656def : InstRW<[M3WriteFCVT3A], (instregex "^FRINT[AIMNPXZ]v")>; 657def : InstRW<[M3WriteFSQR17], (instrs FSQRTv2f32)>; 658def : InstRW<[M3WriteNEONX], (instrs FSQRTv4f32)>; 659def : InstRW<[M3WriteNEONY], (instrs FSQRTv2f64)>; 660 661// ASIMD miscellaneous instructions. 662def : InstRW<[M3WriteNALU1], (instregex "^RBITv")>; 663def : InstRW<[M3WriteNALU1], (instregex "^(BIF|BIT|BSL)v")>; 664def : InstRW<[M3WriteNEONB], (instregex "^DUPv.+gpr")>; 665def : InstRW<[M3WriteNSHF1], (instregex "^DUPv.+lane")>; 666def : InstRW<[M3WriteNSHF1], (instregex "^EXTv")>; 667def : InstRW<[M3WriteNSHF1], (instregex "^[SU]?Q?XTU?Nv")>; 668def : InstRW<[M3WriteNSHF1], (instregex "^CPY")>; 669def : InstRW<[M3WriteNSHF1], (instregex "^INSv.+lane")>; 670def : InstRW<[M3WriteMOVI], (instregex "^MOVI")>; 671def : InstRW<[M3WriteNALU1], (instregex "^FMOVv")>; 672def : InstRW<[M3WriteFCVT4], (instregex "^[FU](RECP|RSQRT)Ev[248]")>; 673def : InstRW<[M3WriteFMAC4, 674 M3ReadFMAC], (instregex "^F(RECP|RSQRT)Sv")>; 675def : InstRW<[M3WriteNSHF1], (instregex "^REV(16|32|64)v")>; 676def : InstRW<[M3WriteNSHF1], (instregex "^TB[LX]v")>; 677def : InstRW<[M3WriteNEOND], (instregex "^[SU]MOVv")>; 678def : InstRW<[M3WriteNSHF3], (instregex "^INSv.+gpr")>; 679def : InstRW<[M3WriteNSHF1], (instregex "^(TRN|UZP|ZIP)[12]v")>; 680 681// ASIMD load instructions. 682def : InstRW<[M3WriteL5], (instregex "LD1Onev(8b|4h|2s|1d)$")>; 683def : InstRW<[M3WriteL5, 684 M3WriteA1], (instregex "LD1Onev(8b|4h|2s|1d)_POST")>; 685def : InstRW<[M3WriteL5], (instregex "LD1Onev(16b|8h|4s|2d)$")>; 686def : InstRW<[M3WriteL5, 687 M3WriteA1], (instregex "LD1Onev(16b|8h|4s|2d)_POST")>; 688 689def : InstRW<[M3WriteVLDA], (instregex "LD1Twov(8b|4h|2s|1d)$")>; 690def : InstRW<[M3WriteVLDA, 691 M3WriteA1], (instregex "LD1Twov(8b|4h|2s|1d)_POST")>; 692def : InstRW<[M3WriteVLDA], (instregex "LD1Twov(16b|8h|4s|2d)$")>; 693def : InstRW<[M3WriteVLDA, 694 M3WriteA1], (instregex "LD1Twov(16b|8h|4s|2d)_POST")>; 695 696def : InstRW<[M3WriteVLDB], (instregex "LD1Threev(8b|4h|2s|1d)$")>; 697def : InstRW<[M3WriteVLDB, 698 M3WriteA1], (instregex "LD1Threev(8b|4h|2s|1d)_POST")>; 699def : InstRW<[M3WriteVLDB], (instregex "LD1Threev(16b|8h|4s|2d)$")>; 700def : InstRW<[M3WriteVLDB, 701 M3WriteA1], (instregex "LD1Threev(16b|8h|4s|2d)_POST")>; 702 703def : InstRW<[M3WriteVLDC], (instregex "LD1Fourv(8b|4h|2s|1d)$")>; 704def : InstRW<[M3WriteVLDC, 705 M3WriteA1], (instregex "LD1Fourv(8b|4h|2s|1d)_POST")>; 706def : InstRW<[M3WriteVLDC], (instregex "LD1Fourv(16b|8h|4s|2d)$")>; 707def : InstRW<[M3WriteVLDC, 708 M3WriteA1], (instregex "LD1Fourv(16b|8h|4s|2d)_POST")>; 709 710def : InstRW<[M3WriteVLDD], (instregex "LD1i(8|16|32)$")>; 711def : InstRW<[M3WriteVLDD, 712 M3WriteA1], (instregex "LD1i(8|16|32)_POST")>; 713def : InstRW<[M3WriteVLDE], (instregex "LD1i(64)$")>; 714def : InstRW<[M3WriteVLDE, 715 M3WriteA1], (instregex "LD1i(64)_POST")>; 716 717def : InstRW<[M3WriteL5], (instregex "LD1Rv(8b|4h|2s|1d)$")>; 718def : InstRW<[M3WriteL5, 719 M3WriteA1], (instregex "LD1Rv(8b|4h|2s|1d)_POST")>; 720def : InstRW<[M3WriteL5], (instregex "LD1Rv(16b|8h|4s|2d)$")>; 721def : InstRW<[M3WriteL5, 722 M3WriteA1], (instregex "LD1Rv(16b|8h|4s|2d)_POST")>; 723 724def : InstRW<[M3WriteVLDF], (instregex "LD2Twov(8b|4h|2s)$")>; 725def : InstRW<[M3WriteVLDF, 726 M3WriteA1], (instregex "LD2Twov(8b|4h|2s)_POST")>; 727def : InstRW<[M3WriteVLDF], (instregex "LD2Twov(16b|8h|4s|2d)$")>; 728def : InstRW<[M3WriteVLDF, 729 M3WriteA1], (instregex "LD2Twov(16b|8h|4s|2d)_POST")>; 730 731def : InstRW<[M3WriteVLDG], (instregex "LD2i(8|16|32)$")>; 732def : InstRW<[M3WriteVLDG, 733 M3WriteA1], (instregex "LD2i(8|16|32)_POST")>; 734def : InstRW<[M3WriteVLDH], (instregex "LD2i(64)$")>; 735def : InstRW<[M3WriteVLDH, 736 M3WriteA1], (instregex "LD2i(64)_POST")>; 737 738def : InstRW<[M3WriteVLDA], (instregex "LD2Rv(8b|4h|2s|1d)$")>; 739def : InstRW<[M3WriteVLDA, 740 M3WriteA1], (instregex "LD2Rv(8b|4h|2s|1d)_POST")>; 741def : InstRW<[M3WriteVLDA], (instregex "LD2Rv(16b|8h|4s|2d)$")>; 742def : InstRW<[M3WriteVLDA, 743 M3WriteA1], (instregex "LD2Rv(16b|8h|4s|2d)_POST")>; 744 745def : InstRW<[M3WriteVLDI], (instregex "LD3Threev(8b|4h|2s)$")>; 746def : InstRW<[M3WriteVLDI, 747 M3WriteA1], (instregex "LD3Threev(8b|4h|2s)_POST")>; 748def : InstRW<[M3WriteVLDI], (instregex "LD3Threev(16b|8h|4s|2d)$")>; 749def : InstRW<[M3WriteVLDI, 750 M3WriteA1], (instregex "LD3Threev(16b|8h|4s|2d)_POST")>; 751 752def : InstRW<[M3WriteVLDJ], (instregex "LD3i(8|16|32)$")>; 753def : InstRW<[M3WriteVLDJ, 754 M3WriteA1], (instregex "LD3i(8|16|32)_POST")>; 755def : InstRW<[M3WriteVLDL], (instregex "LD3i(64)$")>; 756def : InstRW<[M3WriteVLDL, 757 M3WriteA1], (instregex "LD3i(64)_POST")>; 758 759def : InstRW<[M3WriteVLDB], (instregex "LD3Rv(8b|4h|2s|1d)$")>; 760def : InstRW<[M3WriteVLDB, 761 M3WriteA1], (instregex "LD3Rv(8b|4h|2s|1d)_POST")>; 762def : InstRW<[M3WriteVLDB], (instregex "LD3Rv(16b|8h|4s|2d)$")>; 763def : InstRW<[M3WriteVLDB, 764 M3WriteA1], (instregex "LD3Rv(16b|8h|4s|2d)_POST")>; 765 766def : InstRW<[M3WriteVLDN], (instregex "LD4Fourv(8b|4h|2s)$")>; 767def : InstRW<[M3WriteVLDN, 768 M3WriteA1], (instregex "LD4Fourv(8b|4h|2s)_POST")>; 769def : InstRW<[M3WriteVLDN], (instregex "LD4Fourv(16b|8h|4s|2d)$")>; 770def : InstRW<[M3WriteVLDN, 771 M3WriteA1], (instregex "LD4Fourv(16b|8h|4s|2d)_POST")>; 772 773def : InstRW<[M3WriteVLDK], (instregex "LD4i(8|16|32)$")>; 774def : InstRW<[M3WriteVLDK, 775 M3WriteA1], (instregex "LD4i(8|16|32)_POST")>; 776def : InstRW<[M3WriteVLDM], (instregex "LD4i(64)$")>; 777def : InstRW<[M3WriteVLDM, 778 M3WriteA1], (instregex "LD4i(64)_POST")>; 779 780def : InstRW<[M3WriteVLDC], (instregex "LD4Rv(8b|4h|2s|1d)$")>; 781def : InstRW<[M3WriteVLDC, 782 M3WriteA1], (instregex "LD4Rv(8b|4h|2s|1d)_POST")>; 783def : InstRW<[M3WriteVLDC], (instregex "LD4Rv(16b|8h|4s|2d)$")>; 784def : InstRW<[M3WriteVLDC, 785 M3WriteA1], (instregex "LD4Rv(16b|8h|4s|2d)_POST")>; 786 787// ASIMD store instructions. 788def : InstRW<[WriteVST], (instregex "ST1Onev(8b|4h|2s|1d)$")>; 789def : InstRW<[WriteVST, 790 WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d)_POST")>; 791def : InstRW<[WriteVST], (instregex "ST1Onev(16b|8h|4s|2d)$")>; 792def : InstRW<[WriteVST, 793 WriteAdr], (instregex "ST1Onev(16b|8h|4s|2d)_POST")>; 794 795def : InstRW<[M3WriteVSTA], (instregex "ST1Twov(8b|4h|2s|1d)$")>; 796def : InstRW<[M3WriteVSTA, 797 WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d)_POST")>; 798def : InstRW<[M3WriteVSTA], (instregex "ST1Twov(16b|8h|4s|2d)$")>; 799def : InstRW<[M3WriteVSTA, 800 WriteAdr], (instregex "ST1Twov(16b|8h|4s|2d)_POST")>; 801 802def : InstRW<[M3WriteVSTB], (instregex "ST1Threev(8b|4h|2s|1d)$")>; 803def : InstRW<[M3WriteVSTB, 804 WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d)_POST")>; 805def : InstRW<[M3WriteVSTB], (instregex "ST1Threev(16b|8h|4s|2d)$")>; 806def : InstRW<[M3WriteVSTB, 807 WriteAdr], (instregex "ST1Threev(16b|8h|4s|2d)_POST")>; 808 809def : InstRW<[M3WriteVSTC], (instregex "ST1Fourv(8b|4h|2s|1d)$")>; 810def : InstRW<[M3WriteVSTC, 811 WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d)_POST")>; 812def : InstRW<[M3WriteVSTC], (instregex "ST1Fourv(16b|8h|4s|2d)$")>; 813def : InstRW<[M3WriteVSTC, 814 WriteAdr], (instregex "ST1Fourv(16b|8h|4s|2d)_POST")>; 815 816def : InstRW<[M3WriteVSTD], (instregex "ST1i(8|16|32|64)$")>; 817def : InstRW<[M3WriteVSTD, 818 WriteAdr], (instregex "ST1i(8|16|32|64)_POST")>; 819 820def : InstRW<[M3WriteVSTD], (instregex "ST2Twov(8b|4h|2s)$")>; 821def : InstRW<[M3WriteVSTD, 822 WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST")>; 823def : InstRW<[M3WriteVSTE], (instregex "ST2Twov(16b|8h|4s|2d)$")>; 824def : InstRW<[M3WriteVSTE, 825 WriteAdr], (instregex "ST2Twov(16b|8h|4s|2d)_POST")>; 826 827def : InstRW<[M3WriteVSTD], (instregex "ST2i(8|16|32)$")>; 828def : InstRW<[M3WriteVSTD, 829 WriteAdr], (instregex "ST2i(8|16|32)_POST")>; 830def : InstRW<[M3WriteVSTD], (instregex "ST2i(64)$")>; 831def : InstRW<[M3WriteVSTD, 832 WriteAdr], (instregex "ST2i(64)_POST")>; 833 834def : InstRW<[M3WriteVSTF], (instregex "ST3Threev(8b|4h|2s)$")>; 835def : InstRW<[M3WriteVSTF, 836 WriteAdr], (instregex "ST3Threev(8b|4h|2s)_POST")>; 837def : InstRW<[M3WriteVSTG], (instregex "ST3Threev(16b|8h|4s|2d)$")>; 838def : InstRW<[M3WriteVSTG, 839 WriteAdr], (instregex "ST3Threev(16b|8h|4s|2d)_POST")>; 840 841def : InstRW<[M3WriteVSTH], (instregex "ST3i(8|16|32)$")>; 842def : InstRW<[M3WriteVSTH, 843 WriteAdr], (instregex "ST3i(8|16|32)_POST")>; 844def : InstRW<[M3WriteVSTF], (instregex "ST3i(64)$")>; 845def : InstRW<[M3WriteVSTF, 846 WriteAdr], (instregex "ST3i(64)_POST")>; 847 848def : InstRW<[M3WriteVSTF], (instregex "ST4Fourv(8b|4h|2s)$")>; 849def : InstRW<[M3WriteVSTF, 850 WriteAdr], (instregex "ST4Fourv(8b|4h|2s)_POST")>; 851def : InstRW<[M3WriteVSTI], (instregex "ST4Fourv(16b|8h|4s|2d)$")>; 852def : InstRW<[M3WriteVSTI, 853 WriteAdr], (instregex "ST4Fourv(16b|8h|4s|2d)_POST")>; 854 855def : InstRW<[M3WriteVSTF], (instregex "ST4i(8|16|32|64)$")>; 856def : InstRW<[M3WriteVSTF, 857 WriteAdr], (instregex "ST4i(8|16|32|64)_POST")>; 858 859// Cryptography instructions. 860def : InstRW<[M3WriteAES], (instregex "^AES[DE]")>; 861def : InstRW<[M3WriteAES, 862 M3ReadAES], (instregex "^AESI?MC")>; 863 864def : InstRW<[M3WriteNCRY3A], (instregex "^PMULL?v")>; 865 866def : InstRW<[M3WriteNCRY1A], (instregex "^SHA1([CHMP]|SU[01])")>; 867def : InstRW<[M3WriteNCRY1A], (instregex "^SHA256SU0")>; 868def : InstRW<[M3WriteNCRY5A], (instregex "^SHA256(H2?|SU1)")>; 869 870// CRC instructions. 871def : InstRW<[M3WriteC2], (instregex "^CRC32")>; 872 873} // SchedModel = ExynosM3Model 874