RetireControlUnit.cpp revision 360784 
1//===---------------------- RetireControlUnit.cpp ---------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8/// \file
9///
10/// This file simulates the hardware responsible for retiring instructions.
11///
12//===----------------------------------------------------------------------===//
13
14#include "llvm/MCA/HardwareUnits/RetireControlUnit.h"
15#include "llvm/Support/Debug.h"
16
17#define DEBUG_TYPE "llvm-mca"
18
19namespace llvm {
20namespace mca {
21
22RetireControlUnit::RetireControlUnit(const MCSchedModel &SM)
23    : NextAvailableSlotIdx(0), CurrentInstructionSlotIdx(0),
24      NumROBEntries(SM.MicroOpBufferSize),
25      AvailableEntries(SM.MicroOpBufferSize), MaxRetirePerCycle(0) {
26  // Check if the scheduling model provides extra information about the machine
27  // processor. If so, then use that information to set the reorder buffer size
28  // and the maximum number of instructions retired per cycle.
29  if (SM.hasExtraProcessorInfo()) {
30    const MCExtraProcessorInfo &EPI = SM.getExtraProcessorInfo();
31    if (EPI.ReorderBufferSize)
32      AvailableEntries = EPI.ReorderBufferSize;
33    MaxRetirePerCycle = EPI.MaxRetirePerCycle;
34  }
35  NumROBEntries = AvailableEntries;
36  assert(NumROBEntries && "Invalid reorder buffer size!");
37  Queue.resize(2 * NumROBEntries);
38}
39
40// Reserves a number of slots, and returns a new token.
41unsigned RetireControlUnit::dispatch(const InstRef &IR) {
42  const Instruction &Inst = *IR.getInstruction();
43  unsigned Entries = normalizeQuantity(Inst.getNumMicroOps());
44  assert((AvailableEntries >= Entries) && "Reorder Buffer unavailable!");
45
46  unsigned TokenID = NextAvailableSlotIdx;
47  Queue[NextAvailableSlotIdx] = {IR, Entries, false};
48  NextAvailableSlotIdx += std::max(1U, Entries);
49  NextAvailableSlotIdx %= Queue.size();
50
51  AvailableEntries -= Entries;
52  return TokenID;
53}
54
55const RetireControlUnit::RUToken &RetireControlUnit::getCurrentToken() const {
56  const RetireControlUnit::RUToken &Current = Queue[CurrentInstructionSlotIdx];
57#ifndef NDEBUG
58  const Instruction *Inst = Current.IR.getInstruction();
59  assert(Inst && "Invalid RUToken in the RCU queue.");
60#endif
61  return Current;
62}
63
64unsigned RetireControlUnit::computeNextSlotIdx() const {
65  const RetireControlUnit::RUToken &Current = getCurrentToken();
66  unsigned NextSlotIdx = CurrentInstructionSlotIdx + std::max(1U, Current.NumSlots);
67  return NextSlotIdx % Queue.size();
68}
69
70const RetireControlUnit::RUToken &RetireControlUnit::peekNextToken() const {
71  return Queue[computeNextSlotIdx()];
72}
73
74void RetireControlUnit::consumeCurrentToken() {
75  RetireControlUnit::RUToken &Current = Queue[CurrentInstructionSlotIdx];
76  Current.IR.getInstruction()->retire();
77
78  // Update the slot index to be the next item in the circular queue.
79  CurrentInstructionSlotIdx += std::max(1U, Current.NumSlots);
80  CurrentInstructionSlotIdx %= Queue.size();
81  AvailableEntries += Current.NumSlots;
82  Current = { InstRef(), 0U, false };
83}
84
85void RetireControlUnit::onInstructionExecuted(unsigned TokenID) {
86  assert(Queue.size() > TokenID);
87  assert(Queue[TokenID].IR.getInstruction() && "Instruction was not dispatched!");
88  assert(Queue[TokenID].Executed == false && "Instruction already executed!");
89  Queue[TokenID].Executed = true;
90}
91
92#ifndef NDEBUG
93void RetireControlUnit::dump() const {
94  dbgs() << "Retire Unit: { Total ROB Entries =" << NumROBEntries
95         << ", Available ROB entries=" << AvailableEntries << " }\n";
96}
97#endif
98
99} // namespace mca
100} // namespace llvm
101