libunwind.h revision 360784 
1//===---------------------------- libunwind.h -----------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//
8// Compatible with libunwind API documented at:
9//   http://www.nongnu.org/libunwind/man/libunwind(3).html
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef __LIBUNWIND__
14#define __LIBUNWIND__
15
16#include <__libunwind_config.h>
17
18#include <stdint.h>
19#include <stddef.h>
20
21#ifdef __APPLE__
22  #if __clang__
23    #if __has_include(<Availability.h>)
24      #include <Availability.h>
25    #endif
26  #elif __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ >= 1050
27    #include <Availability.h>
28  #endif
29
30  #ifdef __arm__
31     #define LIBUNWIND_AVAIL __attribute__((unavailable))
32  #elif defined(__OSX_AVAILABLE_STARTING)
33    #define LIBUNWIND_AVAIL __OSX_AVAILABLE_STARTING(__MAC_10_6, __IPHONE_5_0)
34  #else
35    #include <AvailabilityMacros.h>
36    #ifdef AVAILABLE_MAC_OS_X_VERSION_10_6_AND_LATER
37      #define LIBUNWIND_AVAIL AVAILABLE_MAC_OS_X_VERSION_10_6_AND_LATER
38    #else
39      #define LIBUNWIND_AVAIL __attribute__((unavailable))
40    #endif
41  #endif
42#else
43  #define LIBUNWIND_AVAIL
44#endif
45
46/* error codes */
47enum {
48  UNW_ESUCCESS      = 0,     /* no error */
49  UNW_EUNSPEC       = -6540, /* unspecified (general) error */
50  UNW_ENOMEM        = -6541, /* out of memory */
51  UNW_EBADREG       = -6542, /* bad register number */
52  UNW_EREADONLYREG  = -6543, /* attempt to write read-only register */
53  UNW_ESTOPUNWIND   = -6544, /* stop unwinding */
54  UNW_EINVALIDIP    = -6545, /* invalid IP */
55  UNW_EBADFRAME     = -6546, /* bad frame */
56  UNW_EINVAL        = -6547, /* unsupported operation or bad value */
57  UNW_EBADVERSION   = -6548, /* unwind info has unsupported version */
58  UNW_ENOINFO       = -6549  /* no unwind info found */
59#if defined(_LIBUNWIND_TARGET_AARCH64) && !defined(_LIBUNWIND_IS_NATIVE_ONLY)
60  , UNW_ECROSSRASIGNING = -6550 /* cross unwind with return address signing */
61#endif
62};
63
64struct unw_context_t {
65  uint64_t data[_LIBUNWIND_CONTEXT_SIZE];
66};
67typedef struct unw_context_t unw_context_t;
68
69struct unw_cursor_t {
70  uint64_t data[_LIBUNWIND_CURSOR_SIZE];
71};
72typedef struct unw_cursor_t unw_cursor_t;
73
74typedef struct unw_addr_space *unw_addr_space_t;
75
76typedef int unw_regnum_t;
77typedef uintptr_t unw_word_t;
78#if defined(__arm__) && !defined(__ARM_DWARF_EH__)
79typedef uint64_t unw_fpreg_t;
80#else
81typedef double unw_fpreg_t;
82#endif
83
84struct unw_proc_info_t {
85  unw_word_t  start_ip;         /* start address of function */
86  unw_word_t  end_ip;           /* address after end of function */
87  unw_word_t  lsda;             /* address of language specific data area, */
88                                /*  or zero if not used */
89  unw_word_t  handler;          /* personality routine, or zero if not used */
90  unw_word_t  gp;               /* not used */
91  unw_word_t  flags;            /* not used */
92  uint32_t    format;           /* compact unwind encoding, or zero if none */
93  uint32_t    unwind_info_size; /* size of DWARF unwind info, or zero if none */
94  unw_word_t  unwind_info;      /* address of DWARF unwind info, or zero */
95  unw_word_t  extra;            /* mach_header of mach-o image containing func */
96};
97typedef struct unw_proc_info_t unw_proc_info_t;
98
99#ifdef __cplusplus
100extern "C" {
101#endif
102
103extern int unw_getcontext(unw_context_t *) LIBUNWIND_AVAIL;
104extern int unw_init_local(unw_cursor_t *, unw_context_t *) LIBUNWIND_AVAIL;
105extern int unw_step(unw_cursor_t *) LIBUNWIND_AVAIL;
106extern int unw_get_reg(unw_cursor_t *, unw_regnum_t, unw_word_t *) LIBUNWIND_AVAIL;
107extern int unw_get_fpreg(unw_cursor_t *, unw_regnum_t, unw_fpreg_t *) LIBUNWIND_AVAIL;
108extern int unw_set_reg(unw_cursor_t *, unw_regnum_t, unw_word_t) LIBUNWIND_AVAIL;
109extern int unw_set_fpreg(unw_cursor_t *, unw_regnum_t, unw_fpreg_t)  LIBUNWIND_AVAIL;
110extern int unw_resume(unw_cursor_t *) LIBUNWIND_AVAIL;
111
112#ifdef __arm__
113/* Save VFP registers in FSTMX format (instead of FSTMD). */
114extern void unw_save_vfp_as_X(unw_cursor_t *) LIBUNWIND_AVAIL;
115#endif
116
117
118extern const char *unw_regname(unw_cursor_t *, unw_regnum_t) LIBUNWIND_AVAIL;
119extern int unw_get_proc_info(unw_cursor_t *, unw_proc_info_t *) LIBUNWIND_AVAIL;
120extern int unw_is_fpreg(unw_cursor_t *, unw_regnum_t) LIBUNWIND_AVAIL;
121extern int unw_is_signal_frame(unw_cursor_t *) LIBUNWIND_AVAIL;
122extern int unw_get_proc_name(unw_cursor_t *, char *, size_t, unw_word_t *) LIBUNWIND_AVAIL;
123//extern int       unw_get_save_loc(unw_cursor_t*, int, unw_save_loc_t*);
124
125extern unw_addr_space_t unw_local_addr_space;
126
127#ifdef __cplusplus
128}
129#endif
130
131// architecture independent register numbers
132enum {
133  UNW_REG_IP = -1, // instruction pointer
134  UNW_REG_SP = -2, // stack pointer
135};
136
137// 32-bit x86 registers
138enum {
139  UNW_X86_EAX = 0,
140  UNW_X86_ECX = 1,
141  UNW_X86_EDX = 2,
142  UNW_X86_EBX = 3,
143  UNW_X86_EBP = 4,
144  UNW_X86_ESP = 5,
145  UNW_X86_ESI = 6,
146  UNW_X86_EDI = 7
147};
148
149// 64-bit x86_64 registers
150enum {
151  UNW_X86_64_RAX = 0,
152  UNW_X86_64_RDX = 1,
153  UNW_X86_64_RCX = 2,
154  UNW_X86_64_RBX = 3,
155  UNW_X86_64_RSI = 4,
156  UNW_X86_64_RDI = 5,
157  UNW_X86_64_RBP = 6,
158  UNW_X86_64_RSP = 7,
159  UNW_X86_64_R8  = 8,
160  UNW_X86_64_R9  = 9,
161  UNW_X86_64_R10 = 10,
162  UNW_X86_64_R11 = 11,
163  UNW_X86_64_R12 = 12,
164  UNW_X86_64_R13 = 13,
165  UNW_X86_64_R14 = 14,
166  UNW_X86_64_R15 = 15,
167  UNW_X86_64_RIP = 16,
168  UNW_X86_64_XMM0 = 17,
169  UNW_X86_64_XMM1 = 18,
170  UNW_X86_64_XMM2 = 19,
171  UNW_X86_64_XMM3 = 20,
172  UNW_X86_64_XMM4 = 21,
173  UNW_X86_64_XMM5 = 22,
174  UNW_X86_64_XMM6 = 23,
175  UNW_X86_64_XMM7 = 24,
176  UNW_X86_64_XMM8 = 25,
177  UNW_X86_64_XMM9 = 26,
178  UNW_X86_64_XMM10 = 27,
179  UNW_X86_64_XMM11 = 28,
180  UNW_X86_64_XMM12 = 29,
181  UNW_X86_64_XMM13 = 30,
182  UNW_X86_64_XMM14 = 31,
183  UNW_X86_64_XMM15 = 32,
184};
185
186
187// 32-bit ppc register numbers
188enum {
189  UNW_PPC_R0  = 0,
190  UNW_PPC_R1  = 1,
191  UNW_PPC_R2  = 2,
192  UNW_PPC_R3  = 3,
193  UNW_PPC_R4  = 4,
194  UNW_PPC_R5  = 5,
195  UNW_PPC_R6  = 6,
196  UNW_PPC_R7  = 7,
197  UNW_PPC_R8  = 8,
198  UNW_PPC_R9  = 9,
199  UNW_PPC_R10 = 10,
200  UNW_PPC_R11 = 11,
201  UNW_PPC_R12 = 12,
202  UNW_PPC_R13 = 13,
203  UNW_PPC_R14 = 14,
204  UNW_PPC_R15 = 15,
205  UNW_PPC_R16 = 16,
206  UNW_PPC_R17 = 17,
207  UNW_PPC_R18 = 18,
208  UNW_PPC_R19 = 19,
209  UNW_PPC_R20 = 20,
210  UNW_PPC_R21 = 21,
211  UNW_PPC_R22 = 22,
212  UNW_PPC_R23 = 23,
213  UNW_PPC_R24 = 24,
214  UNW_PPC_R25 = 25,
215  UNW_PPC_R26 = 26,
216  UNW_PPC_R27 = 27,
217  UNW_PPC_R28 = 28,
218  UNW_PPC_R29 = 29,
219  UNW_PPC_R30 = 30,
220  UNW_PPC_R31 = 31,
221  UNW_PPC_F0  = 32,
222  UNW_PPC_F1  = 33,
223  UNW_PPC_F2  = 34,
224  UNW_PPC_F3  = 35,
225  UNW_PPC_F4  = 36,
226  UNW_PPC_F5  = 37,
227  UNW_PPC_F6  = 38,
228  UNW_PPC_F7  = 39,
229  UNW_PPC_F8  = 40,
230  UNW_PPC_F9  = 41,
231  UNW_PPC_F10 = 42,
232  UNW_PPC_F11 = 43,
233  UNW_PPC_F12 = 44,
234  UNW_PPC_F13 = 45,
235  UNW_PPC_F14 = 46,
236  UNW_PPC_F15 = 47,
237  UNW_PPC_F16 = 48,
238  UNW_PPC_F17 = 49,
239  UNW_PPC_F18 = 50,
240  UNW_PPC_F19 = 51,
241  UNW_PPC_F20 = 52,
242  UNW_PPC_F21 = 53,
243  UNW_PPC_F22 = 54,
244  UNW_PPC_F23 = 55,
245  UNW_PPC_F24 = 56,
246  UNW_PPC_F25 = 57,
247  UNW_PPC_F26 = 58,
248  UNW_PPC_F27 = 59,
249  UNW_PPC_F28 = 60,
250  UNW_PPC_F29 = 61,
251  UNW_PPC_F30 = 62,
252  UNW_PPC_F31 = 63,
253  UNW_PPC_MQ  = 64,
254  UNW_PPC_LR  = 65,
255  UNW_PPC_CTR = 66,
256  UNW_PPC_AP  = 67,
257  UNW_PPC_CR0 = 68,
258  UNW_PPC_CR1 = 69,
259  UNW_PPC_CR2 = 70,
260  UNW_PPC_CR3 = 71,
261  UNW_PPC_CR4 = 72,
262  UNW_PPC_CR5 = 73,
263  UNW_PPC_CR6 = 74,
264  UNW_PPC_CR7 = 75,
265  UNW_PPC_XER = 76,
266  UNW_PPC_V0  = 77,
267  UNW_PPC_V1  = 78,
268  UNW_PPC_V2  = 79,
269  UNW_PPC_V3  = 80,
270  UNW_PPC_V4  = 81,
271  UNW_PPC_V5  = 82,
272  UNW_PPC_V6  = 83,
273  UNW_PPC_V7  = 84,
274  UNW_PPC_V8  = 85,
275  UNW_PPC_V9  = 86,
276  UNW_PPC_V10 = 87,
277  UNW_PPC_V11 = 88,
278  UNW_PPC_V12 = 89,
279  UNW_PPC_V13 = 90,
280  UNW_PPC_V14 = 91,
281  UNW_PPC_V15 = 92,
282  UNW_PPC_V16 = 93,
283  UNW_PPC_V17 = 94,
284  UNW_PPC_V18 = 95,
285  UNW_PPC_V19 = 96,
286  UNW_PPC_V20 = 97,
287  UNW_PPC_V21 = 98,
288  UNW_PPC_V22 = 99,
289  UNW_PPC_V23 = 100,
290  UNW_PPC_V24 = 101,
291  UNW_PPC_V25 = 102,
292  UNW_PPC_V26 = 103,
293  UNW_PPC_V27 = 104,
294  UNW_PPC_V28 = 105,
295  UNW_PPC_V29 = 106,
296  UNW_PPC_V30 = 107,
297  UNW_PPC_V31 = 108,
298  UNW_PPC_VRSAVE  = 109,
299  UNW_PPC_VSCR    = 110,
300  UNW_PPC_SPE_ACC = 111,
301  UNW_PPC_SPEFSCR = 112
302};
303
304// 64-bit ppc register numbers
305enum {
306  UNW_PPC64_R0      = 0,
307  UNW_PPC64_R1      = 1,
308  UNW_PPC64_R2      = 2,
309  UNW_PPC64_R3      = 3,
310  UNW_PPC64_R4      = 4,
311  UNW_PPC64_R5      = 5,
312  UNW_PPC64_R6      = 6,
313  UNW_PPC64_R7      = 7,
314  UNW_PPC64_R8      = 8,
315  UNW_PPC64_R9      = 9,
316  UNW_PPC64_R10     = 10,
317  UNW_PPC64_R11     = 11,
318  UNW_PPC64_R12     = 12,
319  UNW_PPC64_R13     = 13,
320  UNW_PPC64_R14     = 14,
321  UNW_PPC64_R15     = 15,
322  UNW_PPC64_R16     = 16,
323  UNW_PPC64_R17     = 17,
324  UNW_PPC64_R18     = 18,
325  UNW_PPC64_R19     = 19,
326  UNW_PPC64_R20     = 20,
327  UNW_PPC64_R21     = 21,
328  UNW_PPC64_R22     = 22,
329  UNW_PPC64_R23     = 23,
330  UNW_PPC64_R24     = 24,
331  UNW_PPC64_R25     = 25,
332  UNW_PPC64_R26     = 26,
333  UNW_PPC64_R27     = 27,
334  UNW_PPC64_R28     = 28,
335  UNW_PPC64_R29     = 29,
336  UNW_PPC64_R30     = 30,
337  UNW_PPC64_R31     = 31,
338  UNW_PPC64_F0      = 32,
339  UNW_PPC64_F1      = 33,
340  UNW_PPC64_F2      = 34,
341  UNW_PPC64_F3      = 35,
342  UNW_PPC64_F4      = 36,
343  UNW_PPC64_F5      = 37,
344  UNW_PPC64_F6      = 38,
345  UNW_PPC64_F7      = 39,
346  UNW_PPC64_F8      = 40,
347  UNW_PPC64_F9      = 41,
348  UNW_PPC64_F10     = 42,
349  UNW_PPC64_F11     = 43,
350  UNW_PPC64_F12     = 44,
351  UNW_PPC64_F13     = 45,
352  UNW_PPC64_F14     = 46,
353  UNW_PPC64_F15     = 47,
354  UNW_PPC64_F16     = 48,
355  UNW_PPC64_F17     = 49,
356  UNW_PPC64_F18     = 50,
357  UNW_PPC64_F19     = 51,
358  UNW_PPC64_F20     = 52,
359  UNW_PPC64_F21     = 53,
360  UNW_PPC64_F22     = 54,
361  UNW_PPC64_F23     = 55,
362  UNW_PPC64_F24     = 56,
363  UNW_PPC64_F25     = 57,
364  UNW_PPC64_F26     = 58,
365  UNW_PPC64_F27     = 59,
366  UNW_PPC64_F28     = 60,
367  UNW_PPC64_F29     = 61,
368  UNW_PPC64_F30     = 62,
369  UNW_PPC64_F31     = 63,
370  // 64: reserved
371  UNW_PPC64_LR      = 65,
372  UNW_PPC64_CTR     = 66,
373  // 67: reserved
374  UNW_PPC64_CR0     = 68,
375  UNW_PPC64_CR1     = 69,
376  UNW_PPC64_CR2     = 70,
377  UNW_PPC64_CR3     = 71,
378  UNW_PPC64_CR4     = 72,
379  UNW_PPC64_CR5     = 73,
380  UNW_PPC64_CR6     = 74,
381  UNW_PPC64_CR7     = 75,
382  UNW_PPC64_XER     = 76,
383  UNW_PPC64_V0      = 77,
384  UNW_PPC64_V1      = 78,
385  UNW_PPC64_V2      = 79,
386  UNW_PPC64_V3      = 80,
387  UNW_PPC64_V4      = 81,
388  UNW_PPC64_V5      = 82,
389  UNW_PPC64_V6      = 83,
390  UNW_PPC64_V7      = 84,
391  UNW_PPC64_V8      = 85,
392  UNW_PPC64_V9      = 86,
393  UNW_PPC64_V10     = 87,
394  UNW_PPC64_V11     = 88,
395  UNW_PPC64_V12     = 89,
396  UNW_PPC64_V13     = 90,
397  UNW_PPC64_V14     = 91,
398  UNW_PPC64_V15     = 92,
399  UNW_PPC64_V16     = 93,
400  UNW_PPC64_V17     = 94,
401  UNW_PPC64_V18     = 95,
402  UNW_PPC64_V19     = 96,
403  UNW_PPC64_V20     = 97,
404  UNW_PPC64_V21     = 98,
405  UNW_PPC64_V22     = 99,
406  UNW_PPC64_V23     = 100,
407  UNW_PPC64_V24     = 101,
408  UNW_PPC64_V25     = 102,
409  UNW_PPC64_V26     = 103,
410  UNW_PPC64_V27     = 104,
411  UNW_PPC64_V28     = 105,
412  UNW_PPC64_V29     = 106,
413  UNW_PPC64_V30     = 107,
414  UNW_PPC64_V31     = 108,
415  // 109, 111-113: OpenPOWER ELF V2 ABI: reserved
416  // Borrowing VRSAVE number from PPC32.
417  UNW_PPC64_VRSAVE  = 109,
418  UNW_PPC64_VSCR    = 110,
419  UNW_PPC64_TFHAR   = 114,
420  UNW_PPC64_TFIAR   = 115,
421  UNW_PPC64_TEXASR  = 116,
422  UNW_PPC64_VS0     = UNW_PPC64_F0,
423  UNW_PPC64_VS1     = UNW_PPC64_F1,
424  UNW_PPC64_VS2     = UNW_PPC64_F2,
425  UNW_PPC64_VS3     = UNW_PPC64_F3,
426  UNW_PPC64_VS4     = UNW_PPC64_F4,
427  UNW_PPC64_VS5     = UNW_PPC64_F5,
428  UNW_PPC64_VS6     = UNW_PPC64_F6,
429  UNW_PPC64_VS7     = UNW_PPC64_F7,
430  UNW_PPC64_VS8     = UNW_PPC64_F8,
431  UNW_PPC64_VS9     = UNW_PPC64_F9,
432  UNW_PPC64_VS10    = UNW_PPC64_F10,
433  UNW_PPC64_VS11    = UNW_PPC64_F11,
434  UNW_PPC64_VS12    = UNW_PPC64_F12,
435  UNW_PPC64_VS13    = UNW_PPC64_F13,
436  UNW_PPC64_VS14    = UNW_PPC64_F14,
437  UNW_PPC64_VS15    = UNW_PPC64_F15,
438  UNW_PPC64_VS16    = UNW_PPC64_F16,
439  UNW_PPC64_VS17    = UNW_PPC64_F17,
440  UNW_PPC64_VS18    = UNW_PPC64_F18,
441  UNW_PPC64_VS19    = UNW_PPC64_F19,
442  UNW_PPC64_VS20    = UNW_PPC64_F20,
443  UNW_PPC64_VS21    = UNW_PPC64_F21,
444  UNW_PPC64_VS22    = UNW_PPC64_F22,
445  UNW_PPC64_VS23    = UNW_PPC64_F23,
446  UNW_PPC64_VS24    = UNW_PPC64_F24,
447  UNW_PPC64_VS25    = UNW_PPC64_F25,
448  UNW_PPC64_VS26    = UNW_PPC64_F26,
449  UNW_PPC64_VS27    = UNW_PPC64_F27,
450  UNW_PPC64_VS28    = UNW_PPC64_F28,
451  UNW_PPC64_VS29    = UNW_PPC64_F29,
452  UNW_PPC64_VS30    = UNW_PPC64_F30,
453  UNW_PPC64_VS31    = UNW_PPC64_F31,
454  UNW_PPC64_VS32    = UNW_PPC64_V0,
455  UNW_PPC64_VS33    = UNW_PPC64_V1,
456  UNW_PPC64_VS34    = UNW_PPC64_V2,
457  UNW_PPC64_VS35    = UNW_PPC64_V3,
458  UNW_PPC64_VS36    = UNW_PPC64_V4,
459  UNW_PPC64_VS37    = UNW_PPC64_V5,
460  UNW_PPC64_VS38    = UNW_PPC64_V6,
461  UNW_PPC64_VS39    = UNW_PPC64_V7,
462  UNW_PPC64_VS40    = UNW_PPC64_V8,
463  UNW_PPC64_VS41    = UNW_PPC64_V9,
464  UNW_PPC64_VS42    = UNW_PPC64_V10,
465  UNW_PPC64_VS43    = UNW_PPC64_V11,
466  UNW_PPC64_VS44    = UNW_PPC64_V12,
467  UNW_PPC64_VS45    = UNW_PPC64_V13,
468  UNW_PPC64_VS46    = UNW_PPC64_V14,
469  UNW_PPC64_VS47    = UNW_PPC64_V15,
470  UNW_PPC64_VS48    = UNW_PPC64_V16,
471  UNW_PPC64_VS49    = UNW_PPC64_V17,
472  UNW_PPC64_VS50    = UNW_PPC64_V18,
473  UNW_PPC64_VS51    = UNW_PPC64_V19,
474  UNW_PPC64_VS52    = UNW_PPC64_V20,
475  UNW_PPC64_VS53    = UNW_PPC64_V21,
476  UNW_PPC64_VS54    = UNW_PPC64_V22,
477  UNW_PPC64_VS55    = UNW_PPC64_V23,
478  UNW_PPC64_VS56    = UNW_PPC64_V24,
479  UNW_PPC64_VS57    = UNW_PPC64_V25,
480  UNW_PPC64_VS58    = UNW_PPC64_V26,
481  UNW_PPC64_VS59    = UNW_PPC64_V27,
482  UNW_PPC64_VS60    = UNW_PPC64_V28,
483  UNW_PPC64_VS61    = UNW_PPC64_V29,
484  UNW_PPC64_VS62    = UNW_PPC64_V30,
485  UNW_PPC64_VS63    = UNW_PPC64_V31
486};
487
488// 64-bit ARM64 registers
489enum {
490  UNW_ARM64_X0  = 0,
491  UNW_ARM64_X1  = 1,
492  UNW_ARM64_X2  = 2,
493  UNW_ARM64_X3  = 3,
494  UNW_ARM64_X4  = 4,
495  UNW_ARM64_X5  = 5,
496  UNW_ARM64_X6  = 6,
497  UNW_ARM64_X7  = 7,
498  UNW_ARM64_X8  = 8,
499  UNW_ARM64_X9  = 9,
500  UNW_ARM64_X10 = 10,
501  UNW_ARM64_X11 = 11,
502  UNW_ARM64_X12 = 12,
503  UNW_ARM64_X13 = 13,
504  UNW_ARM64_X14 = 14,
505  UNW_ARM64_X15 = 15,
506  UNW_ARM64_X16 = 16,
507  UNW_ARM64_X17 = 17,
508  UNW_ARM64_X18 = 18,
509  UNW_ARM64_X19 = 19,
510  UNW_ARM64_X20 = 20,
511  UNW_ARM64_X21 = 21,
512  UNW_ARM64_X22 = 22,
513  UNW_ARM64_X23 = 23,
514  UNW_ARM64_X24 = 24,
515  UNW_ARM64_X25 = 25,
516  UNW_ARM64_X26 = 26,
517  UNW_ARM64_X27 = 27,
518  UNW_ARM64_X28 = 28,
519  UNW_ARM64_X29 = 29,
520  UNW_ARM64_FP  = 29,
521  UNW_ARM64_X30 = 30,
522  UNW_ARM64_LR  = 30,
523  UNW_ARM64_X31 = 31,
524  UNW_ARM64_SP  = 31,
525  // reserved block
526  UNW_ARM64_RA_SIGN_STATE = 34,
527  // reserved block
528  UNW_ARM64_D0  = 64,
529  UNW_ARM64_D1  = 65,
530  UNW_ARM64_D2  = 66,
531  UNW_ARM64_D3  = 67,
532  UNW_ARM64_D4  = 68,
533  UNW_ARM64_D5  = 69,
534  UNW_ARM64_D6  = 70,
535  UNW_ARM64_D7  = 71,
536  UNW_ARM64_D8  = 72,
537  UNW_ARM64_D9  = 73,
538  UNW_ARM64_D10 = 74,
539  UNW_ARM64_D11 = 75,
540  UNW_ARM64_D12 = 76,
541  UNW_ARM64_D13 = 77,
542  UNW_ARM64_D14 = 78,
543  UNW_ARM64_D15 = 79,
544  UNW_ARM64_D16 = 80,
545  UNW_ARM64_D17 = 81,
546  UNW_ARM64_D18 = 82,
547  UNW_ARM64_D19 = 83,
548  UNW_ARM64_D20 = 84,
549  UNW_ARM64_D21 = 85,
550  UNW_ARM64_D22 = 86,
551  UNW_ARM64_D23 = 87,
552  UNW_ARM64_D24 = 88,
553  UNW_ARM64_D25 = 89,
554  UNW_ARM64_D26 = 90,
555  UNW_ARM64_D27 = 91,
556  UNW_ARM64_D28 = 92,
557  UNW_ARM64_D29 = 93,
558  UNW_ARM64_D30 = 94,
559  UNW_ARM64_D31 = 95,
560};
561
562// 32-bit ARM registers. Numbers match DWARF for ARM spec #3.1 Table 1.
563// Naming scheme uses recommendations given in Note 4 for VFP-v2 and VFP-v3.
564// In this scheme, even though the 64-bit floating point registers D0-D31
565// overlap physically with the 32-bit floating pointer registers S0-S31,
566// they are given a non-overlapping range of register numbers.
567//
568// Commented out ranges are not preserved during unwinding.
569enum {
570  UNW_ARM_R0  = 0,
571  UNW_ARM_R1  = 1,
572  UNW_ARM_R2  = 2,
573  UNW_ARM_R3  = 3,
574  UNW_ARM_R4  = 4,
575  UNW_ARM_R5  = 5,
576  UNW_ARM_R6  = 6,
577  UNW_ARM_R7  = 7,
578  UNW_ARM_R8  = 8,
579  UNW_ARM_R9  = 9,
580  UNW_ARM_R10 = 10,
581  UNW_ARM_R11 = 11,
582  UNW_ARM_R12 = 12,
583  UNW_ARM_SP  = 13,  // Logical alias for UNW_REG_SP
584  UNW_ARM_R13 = 13,
585  UNW_ARM_LR  = 14,
586  UNW_ARM_R14 = 14,
587  UNW_ARM_IP  = 15,  // Logical alias for UNW_REG_IP
588  UNW_ARM_R15 = 15,
589  // 16-63 -- OBSOLETE. Used in VFP1 to represent both S0-S31 and D0-D31.
590  UNW_ARM_S0  = 64,
591  UNW_ARM_S1  = 65,
592  UNW_ARM_S2  = 66,
593  UNW_ARM_S3  = 67,
594  UNW_ARM_S4  = 68,
595  UNW_ARM_S5  = 69,
596  UNW_ARM_S6  = 70,
597  UNW_ARM_S7  = 71,
598  UNW_ARM_S8  = 72,
599  UNW_ARM_S9  = 73,
600  UNW_ARM_S10 = 74,
601  UNW_ARM_S11 = 75,
602  UNW_ARM_S12 = 76,
603  UNW_ARM_S13 = 77,
604  UNW_ARM_S14 = 78,
605  UNW_ARM_S15 = 79,
606  UNW_ARM_S16 = 80,
607  UNW_ARM_S17 = 81,
608  UNW_ARM_S18 = 82,
609  UNW_ARM_S19 = 83,
610  UNW_ARM_S20 = 84,
611  UNW_ARM_S21 = 85,
612  UNW_ARM_S22 = 86,
613  UNW_ARM_S23 = 87,
614  UNW_ARM_S24 = 88,
615  UNW_ARM_S25 = 89,
616  UNW_ARM_S26 = 90,
617  UNW_ARM_S27 = 91,
618  UNW_ARM_S28 = 92,
619  UNW_ARM_S29 = 93,
620  UNW_ARM_S30 = 94,
621  UNW_ARM_S31 = 95,
622  //  96-103 -- OBSOLETE. F0-F7. Used by the FPA system. Superseded by VFP.
623  // 104-111 -- wCGR0-wCGR7, ACC0-ACC7 (Intel wireless MMX)
624  UNW_ARM_WR0 = 112,
625  UNW_ARM_WR1 = 113,
626  UNW_ARM_WR2 = 114,
627  UNW_ARM_WR3 = 115,
628  UNW_ARM_WR4 = 116,
629  UNW_ARM_WR5 = 117,
630  UNW_ARM_WR6 = 118,
631  UNW_ARM_WR7 = 119,
632  UNW_ARM_WR8 = 120,
633  UNW_ARM_WR9 = 121,
634  UNW_ARM_WR10 = 122,
635  UNW_ARM_WR11 = 123,
636  UNW_ARM_WR12 = 124,
637  UNW_ARM_WR13 = 125,
638  UNW_ARM_WR14 = 126,
639  UNW_ARM_WR15 = 127,
640  // 128-133 -- SPSR, SPSR_{FIQ|IRQ|ABT|UND|SVC}
641  // 134-143 -- Reserved
642  // 144-150 -- R8_USR-R14_USR
643  // 151-157 -- R8_FIQ-R14_FIQ
644  // 158-159 -- R13_IRQ-R14_IRQ
645  // 160-161 -- R13_ABT-R14_ABT
646  // 162-163 -- R13_UND-R14_UND
647  // 164-165 -- R13_SVC-R14_SVC
648  // 166-191 -- Reserved
649  UNW_ARM_WC0 = 192,
650  UNW_ARM_WC1 = 193,
651  UNW_ARM_WC2 = 194,
652  UNW_ARM_WC3 = 195,
653  // 196-199 -- wC4-wC7 (Intel wireless MMX control)
654  // 200-255 -- Reserved
655  UNW_ARM_D0  = 256,
656  UNW_ARM_D1  = 257,
657  UNW_ARM_D2  = 258,
658  UNW_ARM_D3  = 259,
659  UNW_ARM_D4  = 260,
660  UNW_ARM_D5  = 261,
661  UNW_ARM_D6  = 262,
662  UNW_ARM_D7  = 263,
663  UNW_ARM_D8  = 264,
664  UNW_ARM_D9  = 265,
665  UNW_ARM_D10 = 266,
666  UNW_ARM_D11 = 267,
667  UNW_ARM_D12 = 268,
668  UNW_ARM_D13 = 269,
669  UNW_ARM_D14 = 270,
670  UNW_ARM_D15 = 271,
671  UNW_ARM_D16 = 272,
672  UNW_ARM_D17 = 273,
673  UNW_ARM_D18 = 274,
674  UNW_ARM_D19 = 275,
675  UNW_ARM_D20 = 276,
676  UNW_ARM_D21 = 277,
677  UNW_ARM_D22 = 278,
678  UNW_ARM_D23 = 279,
679  UNW_ARM_D24 = 280,
680  UNW_ARM_D25 = 281,
681  UNW_ARM_D26 = 282,
682  UNW_ARM_D27 = 283,
683  UNW_ARM_D28 = 284,
684  UNW_ARM_D29 = 285,
685  UNW_ARM_D30 = 286,
686  UNW_ARM_D31 = 287,
687  // 288-319 -- Reserved for VFP/Neon
688  // 320-8191 -- Reserved
689  // 8192-16383 -- Unspecified vendor co-processor register.
690};
691
692// OpenRISC1000 register numbers
693enum {
694  UNW_OR1K_R0  = 0,
695  UNW_OR1K_R1  = 1,
696  UNW_OR1K_R2  = 2,
697  UNW_OR1K_R3  = 3,
698  UNW_OR1K_R4  = 4,
699  UNW_OR1K_R5  = 5,
700  UNW_OR1K_R6  = 6,
701  UNW_OR1K_R7  = 7,
702  UNW_OR1K_R8  = 8,
703  UNW_OR1K_R9  = 9,
704  UNW_OR1K_R10 = 10,
705  UNW_OR1K_R11 = 11,
706  UNW_OR1K_R12 = 12,
707  UNW_OR1K_R13 = 13,
708  UNW_OR1K_R14 = 14,
709  UNW_OR1K_R15 = 15,
710  UNW_OR1K_R16 = 16,
711  UNW_OR1K_R17 = 17,
712  UNW_OR1K_R18 = 18,
713  UNW_OR1K_R19 = 19,
714  UNW_OR1K_R20 = 20,
715  UNW_OR1K_R21 = 21,
716  UNW_OR1K_R22 = 22,
717  UNW_OR1K_R23 = 23,
718  UNW_OR1K_R24 = 24,
719  UNW_OR1K_R25 = 25,
720  UNW_OR1K_R26 = 26,
721  UNW_OR1K_R27 = 27,
722  UNW_OR1K_R28 = 28,
723  UNW_OR1K_R29 = 29,
724  UNW_OR1K_R30 = 30,
725  UNW_OR1K_R31 = 31,
726  UNW_OR1K_EPCR = 32,
727};
728
729// MIPS registers
730enum {
731  UNW_MIPS_R0  = 0,
732  UNW_MIPS_R1  = 1,
733  UNW_MIPS_R2  = 2,
734  UNW_MIPS_R3  = 3,
735  UNW_MIPS_R4  = 4,
736  UNW_MIPS_R5  = 5,
737  UNW_MIPS_R6  = 6,
738  UNW_MIPS_R7  = 7,
739  UNW_MIPS_R8  = 8,
740  UNW_MIPS_R9  = 9,
741  UNW_MIPS_R10 = 10,
742  UNW_MIPS_R11 = 11,
743  UNW_MIPS_R12 = 12,
744  UNW_MIPS_R13 = 13,
745  UNW_MIPS_R14 = 14,
746  UNW_MIPS_R15 = 15,
747  UNW_MIPS_R16 = 16,
748  UNW_MIPS_R17 = 17,
749  UNW_MIPS_R18 = 18,
750  UNW_MIPS_R19 = 19,
751  UNW_MIPS_R20 = 20,
752  UNW_MIPS_R21 = 21,
753  UNW_MIPS_R22 = 22,
754  UNW_MIPS_R23 = 23,
755  UNW_MIPS_R24 = 24,
756  UNW_MIPS_R25 = 25,
757  UNW_MIPS_R26 = 26,
758  UNW_MIPS_R27 = 27,
759  UNW_MIPS_R28 = 28,
760  UNW_MIPS_R29 = 29,
761  UNW_MIPS_R30 = 30,
762  UNW_MIPS_R31 = 31,
763  UNW_MIPS_F0  = 32,
764  UNW_MIPS_F1  = 33,
765  UNW_MIPS_F2  = 34,
766  UNW_MIPS_F3  = 35,
767  UNW_MIPS_F4  = 36,
768  UNW_MIPS_F5  = 37,
769  UNW_MIPS_F6  = 38,
770  UNW_MIPS_F7  = 39,
771  UNW_MIPS_F8  = 40,
772  UNW_MIPS_F9  = 41,
773  UNW_MIPS_F10 = 42,
774  UNW_MIPS_F11 = 43,
775  UNW_MIPS_F12 = 44,
776  UNW_MIPS_F13 = 45,
777  UNW_MIPS_F14 = 46,
778  UNW_MIPS_F15 = 47,
779  UNW_MIPS_F16 = 48,
780  UNW_MIPS_F17 = 49,
781  UNW_MIPS_F18 = 50,
782  UNW_MIPS_F19 = 51,
783  UNW_MIPS_F20 = 52,
784  UNW_MIPS_F21 = 53,
785  UNW_MIPS_F22 = 54,
786  UNW_MIPS_F23 = 55,
787  UNW_MIPS_F24 = 56,
788  UNW_MIPS_F25 = 57,
789  UNW_MIPS_F26 = 58,
790  UNW_MIPS_F27 = 59,
791  UNW_MIPS_F28 = 60,
792  UNW_MIPS_F29 = 61,
793  UNW_MIPS_F30 = 62,
794  UNW_MIPS_F31 = 63,
795  UNW_MIPS_HI = 64,
796  UNW_MIPS_LO = 65,
797};
798
799// SPARC registers
800enum {
801  UNW_SPARC_G0 = 0,
802  UNW_SPARC_G1 = 1,
803  UNW_SPARC_G2 = 2,
804  UNW_SPARC_G3 = 3,
805  UNW_SPARC_G4 = 4,
806  UNW_SPARC_G5 = 5,
807  UNW_SPARC_G6 = 6,
808  UNW_SPARC_G7 = 7,
809  UNW_SPARC_O0 = 8,
810  UNW_SPARC_O1 = 9,
811  UNW_SPARC_O2 = 10,
812  UNW_SPARC_O3 = 11,
813  UNW_SPARC_O4 = 12,
814  UNW_SPARC_O5 = 13,
815  UNW_SPARC_O6 = 14,
816  UNW_SPARC_O7 = 15,
817  UNW_SPARC_L0 = 16,
818  UNW_SPARC_L1 = 17,
819  UNW_SPARC_L2 = 18,
820  UNW_SPARC_L3 = 19,
821  UNW_SPARC_L4 = 20,
822  UNW_SPARC_L5 = 21,
823  UNW_SPARC_L6 = 22,
824  UNW_SPARC_L7 = 23,
825  UNW_SPARC_I0 = 24,
826  UNW_SPARC_I1 = 25,
827  UNW_SPARC_I2 = 26,
828  UNW_SPARC_I3 = 27,
829  UNW_SPARC_I4 = 28,
830  UNW_SPARC_I5 = 29,
831  UNW_SPARC_I6 = 30,
832  UNW_SPARC_I7 = 31,
833};
834
835// RISC-V registers. These match the DWARF register numbers defined by section
836// 4 of the RISC-V ELF psABI specification, which can be found at:
837//
838// https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md
839enum {
840  UNW_RISCV_X0  = 0,
841  UNW_RISCV_X1  = 1,
842  UNW_RISCV_X2  = 2,
843  UNW_RISCV_X3  = 3,
844  UNW_RISCV_X4  = 4,
845  UNW_RISCV_X5  = 5,
846  UNW_RISCV_X6  = 6,
847  UNW_RISCV_X7  = 7,
848  UNW_RISCV_X8  = 8,
849  UNW_RISCV_X9  = 9,
850  UNW_RISCV_X10 = 10,
851  UNW_RISCV_X11 = 11,
852  UNW_RISCV_X12 = 12,
853  UNW_RISCV_X13 = 13,
854  UNW_RISCV_X14 = 14,
855  UNW_RISCV_X15 = 15,
856  UNW_RISCV_X16 = 16,
857  UNW_RISCV_X17 = 17,
858  UNW_RISCV_X18 = 18,
859  UNW_RISCV_X19 = 19,
860  UNW_RISCV_X20 = 20,
861  UNW_RISCV_X21 = 21,
862  UNW_RISCV_X22 = 22,
863  UNW_RISCV_X23 = 23,
864  UNW_RISCV_X24 = 24,
865  UNW_RISCV_X25 = 25,
866  UNW_RISCV_X26 = 26,
867  UNW_RISCV_X27 = 27,
868  UNW_RISCV_X28 = 28,
869  UNW_RISCV_X29 = 29,
870  UNW_RISCV_X30 = 30,
871  UNW_RISCV_X31 = 31,
872  UNW_RISCV_F0  = 32,
873  UNW_RISCV_F1  = 33,
874  UNW_RISCV_F2  = 34,
875  UNW_RISCV_F3  = 35,
876  UNW_RISCV_F4  = 36,
877  UNW_RISCV_F5  = 37,
878  UNW_RISCV_F6  = 38,
879  UNW_RISCV_F7  = 39,
880  UNW_RISCV_F8  = 40,
881  UNW_RISCV_F9  = 41,
882  UNW_RISCV_F10 = 42,
883  UNW_RISCV_F11 = 43,
884  UNW_RISCV_F12 = 44,
885  UNW_RISCV_F13 = 45,
886  UNW_RISCV_F14 = 46,
887  UNW_RISCV_F15 = 47,
888  UNW_RISCV_F16 = 48,
889  UNW_RISCV_F17 = 49,
890  UNW_RISCV_F18 = 50,
891  UNW_RISCV_F19 = 51,
892  UNW_RISCV_F20 = 52,
893  UNW_RISCV_F21 = 53,
894  UNW_RISCV_F22 = 54,
895  UNW_RISCV_F23 = 55,
896  UNW_RISCV_F24 = 56,
897  UNW_RISCV_F25 = 57,
898  UNW_RISCV_F26 = 58,
899  UNW_RISCV_F27 = 59,
900  UNW_RISCV_F28 = 60,
901  UNW_RISCV_F29 = 61,
902  UNW_RISCV_F30 = 62,
903  UNW_RISCV_F31 = 63,
904};
905
906#endif
907