arm_neon.td revision 360784
150479Speter//===--- arm_neon.td - ARM NEON compiler interface ------------------------===// 227008Sbrian// 327008Sbrian// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 474816Sru// See https://llvm.org/LICENSE.txt for license information. 527008Sbrian// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6201390Sed// 7201390Sed//===----------------------------------------------------------------------===// 8125270Smarcel// 9125232Sdeischen// This file defines the TableGen definitions from which the ARM NEON header 1080029Sobrien// file will be generated. See ARM document DUI0348B. 1127008Sbrian// 12//===----------------------------------------------------------------------===// 13 14include "arm_neon_incl.td" 15 16def OP_ADD : Op<(op "+", $p0, $p1)>; 17def OP_ADDL : Op<(op "+", (call "vmovl", $p0), (call "vmovl", $p1))>; 18def OP_ADDLHi : Op<(op "+", (call "vmovl_high", $p0), 19 (call "vmovl_high", $p1))>; 20def OP_ADDW : Op<(op "+", $p0, (call "vmovl", $p1))>; 21def OP_ADDWHi : Op<(op "+", $p0, (call "vmovl_high", $p1))>; 22def OP_SUB : Op<(op "-", $p0, $p1)>; 23def OP_SUBL : Op<(op "-", (call "vmovl", $p0), (call "vmovl", $p1))>; 24def OP_SUBLHi : Op<(op "-", (call "vmovl_high", $p0), 25 (call "vmovl_high", $p1))>; 26def OP_SUBW : Op<(op "-", $p0, (call "vmovl", $p1))>; 27def OP_SUBWHi : Op<(op "-", $p0, (call "vmovl_high", $p1))>; 28def OP_MUL : Op<(op "*", $p0, $p1)>; 29def OP_MLA : Op<(op "+", $p0, (op "*", $p1, $p2))>; 30def OP_MLAL : Op<(op "+", $p0, (call "vmull", $p1, $p2))>; 31def OP_MULLHi : Op<(call "vmull", (call "vget_high", $p0), 32 (call "vget_high", $p1))>; 33def OP_MULLHi_P64 : Op<(call "vmull", 34 (cast "poly64_t", (call "vget_high", $p0)), 35 (cast "poly64_t", (call "vget_high", $p1)))>; 36def OP_MULLHi_N : Op<(call "vmull_n", (call "vget_high", $p0), $p1)>; 37def OP_MLALHi : Op<(call "vmlal", $p0, (call "vget_high", $p1), 38 (call "vget_high", $p2))>; 39def OP_MLALHi_N : Op<(call "vmlal_n", $p0, (call "vget_high", $p1), $p2)>; 40def OP_MLS : Op<(op "-", $p0, (op "*", $p1, $p2))>; 41def OP_FMLS : Op<(call "vfma", $p0, (op "-", $p1), $p2)>; 42def OP_MLSL : Op<(op "-", $p0, (call "vmull", $p1, $p2))>; 43def OP_MLSLHi : Op<(call "vmlsl", $p0, (call "vget_high", $p1), 44 (call "vget_high", $p2))>; 45def OP_MLSLHi_N : Op<(call "vmlsl_n", $p0, (call "vget_high", $p1), $p2)>; 46def OP_MUL_N : Op<(op "*", $p0, (dup $p1))>; 47def OP_MULX_N : Op<(call "vmulx", $p0, (dup $p1))>; 48def OP_MLA_N : Op<(op "+", $p0, (op "*", $p1, (dup $p2)))>; 49def OP_MLS_N : Op<(op "-", $p0, (op "*", $p1, (dup $p2)))>; 50def OP_FMLA_N : Op<(call "vfma", $p0, $p1, (dup $p2))>; 51def OP_FMLS_N : Op<(call "vfma", $p0, (op "-", $p1), (dup $p2))>; 52def OP_MLAL_N : Op<(op "+", $p0, (call "vmull", $p1, (dup $p2)))>; 53def OP_MLSL_N : Op<(op "-", $p0, (call "vmull", $p1, (dup $p2)))>; 54def OP_MUL_LN : Op<(op "*", $p0, (splat $p1, $p2))>; 55def OP_MULX_LN : Op<(call "vmulx", $p0, (splat $p1, $p2))>; 56def OP_MULL_N : Op<(call "vmull", $p0, (dup $p1))>; 57def OP_MULL_LN : Op<(call "vmull", $p0, (splat $p1, $p2))>; 58def OP_MULLHi_LN: Op<(call "vmull", (call "vget_high", $p0), (splat $p1, $p2))>; 59def OP_MLA_LN : Op<(op "+", $p0, (op "*", $p1, (splat $p2, $p3)))>; 60def OP_MLS_LN : Op<(op "-", $p0, (op "*", $p1, (splat $p2, $p3)))>; 61def OP_MLAL_LN : Op<(op "+", $p0, (call "vmull", $p1, (splat $p2, $p3)))>; 62def OP_MLALHi_LN: Op<(op "+", $p0, (call "vmull", (call "vget_high", $p1), 63 (splat $p2, $p3)))>; 64def OP_MLSL_LN : Op<(op "-", $p0, (call "vmull", $p1, (splat $p2, $p3)))>; 65def OP_MLSLHi_LN : Op<(op "-", $p0, (call "vmull", (call "vget_high", $p1), 66 (splat $p2, $p3)))>; 67def OP_QDMULL_N : Op<(call "vqdmull", $p0, (dup $p1))>; 68def OP_QDMULL_LN : Op<(call "vqdmull", $p0, (splat $p1, $p2))>; 69def OP_QDMULLHi_LN : Op<(call "vqdmull", (call "vget_high", $p0), 70 (splat $p1, $p2))>; 71def OP_QDMLAL_N : Op<(call "vqdmlal", $p0, $p1, (dup $p2))>; 72def OP_QDMLAL_LN : Op<(call "vqdmlal", $p0, $p1, (splat $p2, $p3))>; 73def OP_QDMLALHi_LN : Op<(call "vqdmlal", $p0, (call "vget_high", $p1), 74 (splat $p2, $p3))>; 75def OP_QDMLSL_N : Op<(call "vqdmlsl", $p0, $p1, (dup $p2))>; 76def OP_QDMLSL_LN : Op<(call "vqdmlsl", $p0, $p1, (splat $p2, $p3))>; 77def OP_QDMLSLHi_LN : Op<(call "vqdmlsl", $p0, (call "vget_high", $p1), 78 (splat $p2, $p3))>; 79def OP_QDMULH_N : Op<(call "vqdmulh", $p0, (dup $p1))>; 80def OP_QDMULH_LN : Op<(call "vqdmulh", $p0, (splat $p1, $p2))>; 81def OP_QRDMULH_LN : Op<(call "vqrdmulh", $p0, (splat $p1, $p2))>; 82def OP_QRDMULH_N : Op<(call "vqrdmulh", $p0, (dup $p1))>; 83def OP_QRDMLAH : Op<(call "vqadd", $p0, (call "vqrdmulh", $p1, $p2))>; 84def OP_QRDMLSH : Op<(call "vqsub", $p0, (call "vqrdmulh", $p1, $p2))>; 85def OP_QRDMLAH_LN : Op<(call "vqadd", $p0, (call "vqrdmulh", $p1, (splat $p2, $p3)))>; 86def OP_QRDMLSH_LN : Op<(call "vqsub", $p0, (call "vqrdmulh", $p1, (splat $p2, $p3)))>; 87def OP_FMS_LN : Op<(call "vfma_lane", $p0, (op "-", $p1), $p2, $p3)>; 88def OP_FMS_LNQ : Op<(call "vfma_laneq", $p0, (op "-", $p1), $p2, $p3)>; 89def OP_TRN1 : Op<(shuffle $p0, $p1, (interleave (decimate mask0, 2), 90 (decimate mask1, 2)))>; 91def OP_ZIP1 : Op<(shuffle $p0, $p1, (lowhalf (interleave mask0, mask1)))>; 92def OP_UZP1 : Op<(shuffle $p0, $p1, (add (decimate mask0, 2), 93 (decimate mask1, 2)))>; 94def OP_TRN2 : Op<(shuffle $p0, $p1, (interleave 95 (decimate (rotl mask0, 1), 2), 96 (decimate (rotl mask1, 1), 2)))>; 97def OP_ZIP2 : Op<(shuffle $p0, $p1, (highhalf (interleave mask0, mask1)))>; 98def OP_UZP2 : Op<(shuffle $p0, $p1, (add (decimate (rotl mask0, 1), 2), 99 (decimate (rotl mask1, 1), 2)))>; 100def OP_EQ : Op<(cast "R", (op "==", $p0, $p1))>; 101def OP_GE : Op<(cast "R", (op ">=", $p0, $p1))>; 102def OP_LE : Op<(cast "R", (op "<=", $p0, $p1))>; 103def OP_GT : Op<(cast "R", (op ">", $p0, $p1))>; 104def OP_LT : Op<(cast "R", (op "<", $p0, $p1))>; 105def OP_NEG : Op<(op "-", $p0)>; 106def OP_NOT : Op<(op "~", $p0)>; 107def OP_AND : Op<(op "&", $p0, $p1)>; 108def OP_OR : Op<(op "|", $p0, $p1)>; 109def OP_XOR : Op<(op "^", $p0, $p1)>; 110def OP_ANDN : Op<(op "&", $p0, (op "~", $p1))>; 111def OP_ORN : Op<(op "|", $p0, (op "~", $p1))>; 112def OP_CAST : LOp<[(save_temp $promote, $p0), 113 (cast "R", $promote)]>; 114def OP_HI : Op<(shuffle $p0, $p0, (highhalf mask0))>; 115def OP_LO : Op<(shuffle $p0, $p0, (lowhalf mask0))>; 116def OP_CONC : Op<(shuffle $p0, $p1, (add mask0, mask1))>; 117def OP_DUP : Op<(dup $p0)>; 118def OP_DUP_LN : Op<(splat $p0, $p1)>; 119def OP_SEL : Op<(cast "R", (op "|", 120 (op "&", $p0, (cast $p0, $p1)), 121 (op "&", (op "~", $p0), (cast $p0, $p2))))>; 122def OP_REV16 : Op<(shuffle $p0, $p0, (rev 16, mask0))>; 123def OP_REV32 : Op<(shuffle $p0, $p0, (rev 32, mask0))>; 124def OP_REV64 : Op<(shuffle $p0, $p0, (rev 64, mask0))>; 125def OP_XTN : Op<(call "vcombine", $p0, (call "vmovn", $p1))>; 126def OP_SQXTUN : Op<(call "vcombine", (cast $p0, "U", $p0), 127 (call "vqmovun", $p1))>; 128def OP_QXTN : Op<(call "vcombine", $p0, (call "vqmovn", $p1))>; 129def OP_VCVT_NA_HI_F16 : Op<(call "vcombine", $p0, (call "vcvt_f16_f32", $p1))>; 130def OP_VCVT_NA_HI_F32 : Op<(call "vcombine", $p0, (call "vcvt_f32_f64", $p1))>; 131def OP_VCVT_EX_HI_F32 : Op<(call "vcvt_f32_f16", (call "vget_high", $p0))>; 132def OP_VCVT_EX_HI_F64 : Op<(call "vcvt_f64_f32", (call "vget_high", $p0))>; 133def OP_VCVTX_HI : Op<(call "vcombine", $p0, (call "vcvtx_f32", $p1))>; 134def OP_REINT : Op<(cast "R", $p0)>; 135def OP_ADDHNHi : Op<(call "vcombine", $p0, (call "vaddhn", $p1, $p2))>; 136def OP_RADDHNHi : Op<(call "vcombine", $p0, (call "vraddhn", $p1, $p2))>; 137def OP_SUBHNHi : Op<(call "vcombine", $p0, (call "vsubhn", $p1, $p2))>; 138def OP_RSUBHNHi : Op<(call "vcombine", $p0, (call "vrsubhn", $p1, $p2))>; 139def OP_ABDL : Op<(cast "R", (call "vmovl", (cast $p0, "U", 140 (call "vabd", $p0, $p1))))>; 141def OP_ABDLHi : Op<(call "vabdl", (call "vget_high", $p0), 142 (call "vget_high", $p1))>; 143def OP_ABA : Op<(op "+", $p0, (call "vabd", $p1, $p2))>; 144def OP_ABAL : Op<(op "+", $p0, (call "vabdl", $p1, $p2))>; 145def OP_ABALHi : Op<(call "vabal", $p0, (call "vget_high", $p1), 146 (call "vget_high", $p2))>; 147def OP_QDMULLHi : Op<(call "vqdmull", (call "vget_high", $p0), 148 (call "vget_high", $p1))>; 149def OP_QDMULLHi_N : Op<(call "vqdmull_n", (call "vget_high", $p0), $p1)>; 150def OP_QDMLALHi : Op<(call "vqdmlal", $p0, (call "vget_high", $p1), 151 (call "vget_high", $p2))>; 152def OP_QDMLALHi_N : Op<(call "vqdmlal_n", $p0, (call "vget_high", $p1), $p2)>; 153def OP_QDMLSLHi : Op<(call "vqdmlsl", $p0, (call "vget_high", $p1), 154 (call "vget_high", $p2))>; 155def OP_QDMLSLHi_N : Op<(call "vqdmlsl_n", $p0, (call "vget_high", $p1), $p2)>; 156def OP_DIV : Op<(op "/", $p0, $p1)>; 157def OP_LONG_HI : Op<(cast "R", (call (name_replace "_high_", "_"), 158 (call "vget_high", $p0), $p1))>; 159def OP_NARROW_HI : Op<(cast "R", (call "vcombine", 160 (cast "R", "H", $p0), 161 (cast "R", "H", 162 (call (name_replace "_high_", "_"), 163 $p1, $p2))))>; 164def OP_MOVL_HI : LOp<[(save_temp $a1, (call "vget_high", $p0)), 165 (cast "R", 166 (call "vshll_n", $a1, (literal "int32_t", "0")))]>; 167def OP_COPY_LN : Op<(call "vset_lane", (call "vget_lane", $p2, $p3), $p0, $p1)>; 168def OP_SCALAR_MUL_LN : Op<(op "*", $p0, (call "vget_lane", $p1, $p2))>; 169def OP_SCALAR_MULX_LN : Op<(call "vmulx", $p0, (call "vget_lane", $p1, $p2))>; 170def OP_SCALAR_VMULX_LN : LOp<[(save_temp $x, (call "vget_lane", $p0, 171 (literal "int32_t", "0"))), 172 (save_temp $y, (call "vget_lane", $p1, $p2)), 173 (save_temp $z, (call "vmulx", $x, $y)), 174 (call "vset_lane", $z, $p0, $p2)]>; 175def OP_SCALAR_VMULX_LNQ : LOp<[(save_temp $x, (call "vget_lane", $p0, 176 (literal "int32_t", "0"))), 177 (save_temp $y, (call "vget_lane", $p1, $p2)), 178 (save_temp $z, (call "vmulx", $x, $y)), 179 (call "vset_lane", $z, $p0, (literal "int32_t", 180 "0"))]>; 181class ScalarMulOp<string opname> : 182 Op<(call opname, $p0, (call "vget_lane", $p1, $p2))>; 183 184def OP_SCALAR_QDMULL_LN : ScalarMulOp<"vqdmull">; 185def OP_SCALAR_QDMULH_LN : ScalarMulOp<"vqdmulh">; 186def OP_SCALAR_QRDMULH_LN : ScalarMulOp<"vqrdmulh">; 187 188def OP_SCALAR_QRDMLAH_LN : Op<(call "vqadd", $p0, (call "vqrdmulh", $p1, 189 (call "vget_lane", $p2, $p3)))>; 190def OP_SCALAR_QRDMLSH_LN : Op<(call "vqsub", $p0, (call "vqrdmulh", $p1, 191 (call "vget_lane", $p2, $p3)))>; 192 193def OP_SCALAR_HALF_GET_LN : Op<(bitcast "float16_t", 194 (call "vget_lane", 195 (bitcast "int16x4_t", $p0), $p1))>; 196def OP_SCALAR_HALF_GET_LNQ : Op<(bitcast "float16_t", 197 (call "vget_lane", 198 (bitcast "int16x8_t", $p0), $p1))>; 199def OP_SCALAR_HALF_SET_LN : Op<(bitcast "float16x4_t", 200 (call "vset_lane", 201 (bitcast "int16_t", $p0), 202 (bitcast "int16x4_t", $p1), $p2))>; 203def OP_SCALAR_HALF_SET_LNQ : Op<(bitcast "float16x8_t", 204 (call "vset_lane", 205 (bitcast "int16_t", $p0), 206 (bitcast "int16x8_t", $p1), $p2))>; 207 208def OP_DOT_LN 209 : Op<(call "vdot", $p0, $p1, 210 (bitcast $p1, (splat(bitcast "uint32x2_t", $p2), $p3)))>; 211def OP_DOT_LNQ 212 : Op<(call "vdot", $p0, $p1, 213 (bitcast $p1, (splat(bitcast "uint32x4_t", $p2), $p3)))>; 214 215def OP_FMLAL_LN : Op<(call "vfmlal_low", $p0, $p1, 216 (dup_typed $p1, (call "vget_lane", $p2, $p3)))>; 217def OP_FMLSL_LN : Op<(call "vfmlsl_low", $p0, $p1, 218 (dup_typed $p1, (call "vget_lane", $p2, $p3)))>; 219def OP_FMLAL_LN_Hi : Op<(call "vfmlal_high", $p0, $p1, 220 (dup_typed $p1, (call "vget_lane", $p2, $p3)))>; 221def OP_FMLSL_LN_Hi : Op<(call "vfmlsl_high", $p0, $p1, 222 (dup_typed $p1, (call "vget_lane", $p2, $p3)))>; 223 224//===----------------------------------------------------------------------===// 225// Instructions 226//===----------------------------------------------------------------------===// 227 228//////////////////////////////////////////////////////////////////////////////// 229// E.3.1 Addition 230def VADD : IOpInst<"vadd", "...", 231 "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_ADD>; 232def VADDL : SOpInst<"vaddl", "(>Q)..", "csiUcUsUi", OP_ADDL>; 233def VADDW : SOpInst<"vaddw", "(>Q)(>Q).", "csiUcUsUi", OP_ADDW>; 234def VHADD : SInst<"vhadd", "...", "csiUcUsUiQcQsQiQUcQUsQUi">; 235def VRHADD : SInst<"vrhadd", "...", "csiUcUsUiQcQsQiQUcQUsQUi">; 236def VQADD : SInst<"vqadd", "...", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 237def VADDHN : IInst<"vaddhn", "<QQ", "silUsUiUl">; 238def VRADDHN : IInst<"vraddhn", "<QQ", "silUsUiUl">; 239 240//////////////////////////////////////////////////////////////////////////////// 241// E.3.2 Multiplication 242def VMUL : IOpInst<"vmul", "...", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MUL>; 243def VMULP : SInst<"vmul", "...", "PcQPc">; 244def VMLA : IOpInst<"vmla", "....", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLA>; 245def VMLAL : SOpInst<"vmlal", "(>Q)(>Q)..", "csiUcUsUi", OP_MLAL>; 246def VMLS : IOpInst<"vmls", "....", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_MLS>; 247def VMLSL : SOpInst<"vmlsl", "(>Q)(>Q)..", "csiUcUsUi", OP_MLSL>; 248def VQDMULH : SInst<"vqdmulh", "...", "siQsQi">; 249def VQRDMULH : SInst<"vqrdmulh", "...", "siQsQi">; 250 251let ArchGuard = "defined(__ARM_FEATURE_QRDMX)" in { 252def VQRDMLAH : SOpInst<"vqrdmlah", "....", "siQsQi", OP_QRDMLAH>; 253def VQRDMLSH : SOpInst<"vqrdmlsh", "....", "siQsQi", OP_QRDMLSH>; 254} 255 256def VQDMLAL : SInst<"vqdmlal", "(>Q)(>Q)..", "si">; 257def VQDMLSL : SInst<"vqdmlsl", "(>Q)(>Q)..", "si">; 258def VMULL : SInst<"vmull", "(>Q)..", "csiUcUsUiPc">; 259def VQDMULL : SInst<"vqdmull", "(>Q)..", "si">; 260 261//////////////////////////////////////////////////////////////////////////////// 262// E.3.3 Subtraction 263def VSUB : IOpInst<"vsub", "...", 264 "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUl", OP_SUB>; 265def VSUBL : SOpInst<"vsubl", "(>Q)..", "csiUcUsUi", OP_SUBL>; 266def VSUBW : SOpInst<"vsubw", "(>Q)(>Q).", "csiUcUsUi", OP_SUBW>; 267def VQSUB : SInst<"vqsub", "...", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 268def VHSUB : SInst<"vhsub", "...", "csiUcUsUiQcQsQiQUcQUsQUi">; 269def VSUBHN : IInst<"vsubhn", "<QQ", "silUsUiUl">; 270def VRSUBHN : IInst<"vrsubhn", "<QQ", "silUsUiUl">; 271 272//////////////////////////////////////////////////////////////////////////////// 273// E.3.4 Comparison 274def VCEQ : IOpInst<"vceq", "U..", "csifUcUsUiPcQcQsQiQfQUcQUsQUiQPc", OP_EQ>; 275def VCGE : SOpInst<"vcge", "U..", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GE>; 276let InstName = "vcge" in 277def VCLE : SOpInst<"vcle", "U..", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LE>; 278def VCGT : SOpInst<"vcgt", "U..", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_GT>; 279let InstName = "vcgt" in 280def VCLT : SOpInst<"vclt", "U..", "csifUcUsUiQcQsQiQfQUcQUsQUi", OP_LT>; 281let InstName = "vacge" in { 282def VCAGE : IInst<"vcage", "U..", "fQf">; 283def VCALE : IInst<"vcale", "U..", "fQf">; 284} 285let InstName = "vacgt" in { 286def VCAGT : IInst<"vcagt", "U..", "fQf">; 287def VCALT : IInst<"vcalt", "U..", "fQf">; 288} 289def VTST : WInst<"vtst", "U..", "csiUcUsUiPcPsQcQsQiQUcQUsQUiQPcQPs">; 290 291//////////////////////////////////////////////////////////////////////////////// 292// E.3.5 Absolute Difference 293def VABD : SInst<"vabd", "...", "csiUcUsUifQcQsQiQUcQUsQUiQf">; 294def VABDL : SOpInst<"vabdl", "(>Q)..", "csiUcUsUi", OP_ABDL>; 295def VABA : SOpInst<"vaba", "....", "csiUcUsUiQcQsQiQUcQUsQUi", OP_ABA>; 296def VABAL : SOpInst<"vabal", "(>Q)(>Q)..", "csiUcUsUi", OP_ABAL>; 297 298//////////////////////////////////////////////////////////////////////////////// 299// E.3.6 Max/Min 300def VMAX : SInst<"vmax", "...", "csiUcUsUifQcQsQiQUcQUsQUiQf">; 301def VMIN : SInst<"vmin", "...", "csiUcUsUifQcQsQiQUcQUsQUiQf">; 302 303//////////////////////////////////////////////////////////////////////////////// 304// E.3.7 Pairwise Addition 305def VPADD : IInst<"vpadd", "...", "csiUcUsUif">; 306def VPADDL : SInst<"vpaddl", ">.", "csiUcUsUiQcQsQiQUcQUsQUi">; 307def VPADAL : SInst<"vpadal", ">>.", "csiUcUsUiQcQsQiQUcQUsQUi">; 308 309//////////////////////////////////////////////////////////////////////////////// 310// E.3.8-9 Folding Max/Min 311def VPMAX : SInst<"vpmax", "...", "csiUcUsUif">; 312def VPMIN : SInst<"vpmin", "...", "csiUcUsUif">; 313 314//////////////////////////////////////////////////////////////////////////////// 315// E.3.10 Reciprocal/Sqrt 316def VRECPS : IInst<"vrecps", "...", "fQf">; 317def VRSQRTS : IInst<"vrsqrts", "...", "fQf">; 318 319//////////////////////////////////////////////////////////////////////////////// 320// E.3.11 Shifts by signed variable 321def VSHL : SInst<"vshl", "..S", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 322def VQSHL : SInst<"vqshl", "..S", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 323def VRSHL : SInst<"vrshl", "..S", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 324def VQRSHL : SInst<"vqrshl", "..S", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 325 326//////////////////////////////////////////////////////////////////////////////// 327// E.3.12 Shifts by constant 328let isShift = 1 in { 329def VSHR_N : SInst<"vshr_n", "..I", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 330def VSHL_N : IInst<"vshl_n", "..I", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 331def VRSHR_N : SInst<"vrshr_n", "..I", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 332def VSRA_N : SInst<"vsra_n", "...I", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 333def VRSRA_N : SInst<"vrsra_n", "...I", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 334def VQSHL_N : SInst<"vqshl_n", "..I", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl">; 335def VQSHLU_N : SInst<"vqshlu_n", "U.I", "csilQcQsQiQl">; 336def VSHRN_N : IInst<"vshrn_n", "<QI", "silUsUiUl">; 337def VQSHRUN_N : SInst<"vqshrun_n", "(<U)QI", "sil">; 338def VQRSHRUN_N : SInst<"vqrshrun_n", "(<U)QI", "sil">; 339def VQSHRN_N : SInst<"vqshrn_n", "<QI", "silUsUiUl">; 340def VRSHRN_N : IInst<"vrshrn_n", "<QI", "silUsUiUl">; 341def VQRSHRN_N : SInst<"vqrshrn_n", "<QI", "silUsUiUl">; 342def VSHLL_N : SInst<"vshll_n", "(>Q).I", "csiUcUsUi">; 343 344//////////////////////////////////////////////////////////////////////////////// 345// E.3.13 Shifts with insert 346def VSRI_N : WInst<"vsri_n", "...I", 347 "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">; 348def VSLI_N : WInst<"vsli_n", "...I", 349 "csilUcUsUiUlPcPsQcQsQiQlQUcQUsQUiQUlQPcQPs">; 350} 351 352//////////////////////////////////////////////////////////////////////////////// 353// E.3.14 Loads and stores of a single vector 354def VLD1 : WInst<"vld1", ".(c*!)", 355 "QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">; 356def VLD1_X2 : WInst<"vld1_x2", "2(c*!)", 357 "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">; 358def VLD1_X3 : WInst<"vld1_x3", "3(c*!)", 359 "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">; 360def VLD1_X4 : WInst<"vld1_x4", "4(c*!)", 361 "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">; 362def VLD1_LANE : WInst<"vld1_lane", ".(c*!).I", 363 "QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">; 364def VLD1_DUP : WInst<"vld1_dup", ".(c*!)", 365 "QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">; 366def VST1 : WInst<"vst1", "v*(.!)", 367 "QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">; 368def VST1_X2 : WInst<"vst1_x2", "v*(2!)", 369 "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">; 370def VST1_X3 : WInst<"vst1_x3", "v*(3!)", 371 "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">; 372def VST1_X4 : WInst<"vst1_x4", "v*(4!)", 373 "cfilsUcUiUlUsQcQfQiQlQsQUcQUiQUlQUsPcPsQPcQPs">; 374def VST1_LANE : WInst<"vst1_lane", "v*(.!)I", 375 "QUcQUsQUiQUlQcQsQiQlQfQPcQPsUcUsUiUlcsilfPcPs">; 376let ArchGuard = "(__ARM_FP & 2)" in { 377def VLD1_F16 : WInst<"vld1", ".(c*!)", "hQh">; 378def VLD1_X2_F16 : WInst<"vld1_x2", "2(c*!)", "hQh">; 379def VLD1_X3_F16 : WInst<"vld1_x3", "3(c*!)", "hQh">; 380def VLD1_X4_F16 : WInst<"vld1_x4", "4(c*!)", "hQh">; 381def VLD1_LANE_F16 : WInst<"vld1_lane", ".(c*!).I", "hQh">; 382def VLD1_DUP_F16 : WInst<"vld1_dup", ".(c*!)", "hQh">; 383def VST1_F16 : WInst<"vst1", "v*(.!)", "hQh">; 384def VST1_X2_F16 : WInst<"vst1_x2", "v*(2!)", "hQh">; 385def VST1_X3_F16 : WInst<"vst1_x3", "v*(3!)", "hQh">; 386def VST1_X4_F16 : WInst<"vst1_x4", "v*(4!)", "hQh">; 387def VST1_LANE_F16 : WInst<"vst1_lane", "v*(.!)I", "hQh">; 388} 389 390//////////////////////////////////////////////////////////////////////////////// 391// E.3.15 Loads and stores of an N-element structure 392def VLD2 : WInst<"vld2", "2(c*!)", "QUcQUsQUiQcQsQiQfQPcQPsUcUsUiUlcsilfPcPs">; 393def VLD3 : WInst<"vld3", "3(c*!)", "QUcQUsQUiQcQsQiQfQPcQPsUcUsUiUlcsilfPcPs">; 394def VLD4 : WInst<"vld4", "4(c*!)", "QUcQUsQUiQcQsQiQfQPcQPsUcUsUiUlcsilfPcPs">; 395def VLD2_DUP : WInst<"vld2_dup", "2(c*!)", 396 "UcUsUiUlcsilfPcPsQcQfQiQlQsQPcQPsQUcQUiQUlQUs">; 397def VLD3_DUP : WInst<"vld3_dup", "3(c*!)", 398 "UcUsUiUlcsilfPcPsQcQfQiQlQsQPcQPsQUcQUiQUlQUs">; 399def VLD4_DUP : WInst<"vld4_dup", "4(c*!)", 400 "UcUsUiUlcsilfPcPsQcQfQiQlQsQPcQPsQUcQUiQUlQUs">; 401def VLD2_LANE : WInst<"vld2_lane", "2(c*!)2I", "QUsQUiQsQiQfQPsUcUsUicsifPcPs">; 402def VLD3_LANE : WInst<"vld3_lane", "3(c*!)3I", "QUsQUiQsQiQfQPsUcUsUicsifPcPs">; 403def VLD4_LANE : WInst<"vld4_lane", "4(c*!)4I", "QUsQUiQsQiQfQPsUcUsUicsifPcPs">; 404def VST2 : WInst<"vst2", "v*(2!)", "QUcQUsQUiQcQsQiQfQPcQPsUcUsUiUlcsilfPcPs">; 405def VST3 : WInst<"vst3", "v*(3!)", "QUcQUsQUiQcQsQiQfQPcQPsUcUsUiUlcsilfPcPs">; 406def VST4 : WInst<"vst4", "v*(4!)", "QUcQUsQUiQcQsQiQfQPcQPsUcUsUiUlcsilfPcPs">; 407def VST2_LANE : WInst<"vst2_lane", "v*(2!)I", "QUsQUiQsQiQfQPsUcUsUicsifPcPs">; 408def VST3_LANE : WInst<"vst3_lane", "v*(3!)I", "QUsQUiQsQiQfQPsUcUsUicsifPcPs">; 409def VST4_LANE : WInst<"vst4_lane", "v*(4!)I", "QUsQUiQsQiQfQPsUcUsUicsifPcPs">; 410let ArchGuard = "(__ARM_FP & 2)" in { 411def VLD2_F16 : WInst<"vld2", "2(c*!)", "hQh">; 412def VLD3_F16 : WInst<"vld3", "3(c*!)", "hQh">; 413def VLD4_F16 : WInst<"vld4", "4(c*!)", "hQh">; 414def VLD2_DUP_F16 : WInst<"vld2_dup", "2(c*!)", "hQh">; 415def VLD3_DUP_F16 : WInst<"vld3_dup", "3(c*!)", "hQh">; 416def VLD4_DUP_F16 : WInst<"vld4_dup", "4(c*!)", "hQh">; 417def VLD2_LANE_F16 : WInst<"vld2_lane", "2(c*!)2I", "hQh">; 418def VLD3_LANE_F16 : WInst<"vld3_lane", "3(c*!)3I", "hQh">; 419def VLD4_LANE_F16 : WInst<"vld4_lane", "4(c*!)4I", "hQh">; 420def VST2_F16 : WInst<"vst2", "v*(2!)", "hQh">; 421def VST3_F16 : WInst<"vst3", "v*(3!)", "hQh">; 422def VST4_F16 : WInst<"vst4", "v*(4!)", "hQh">; 423def VST2_LANE_F16 : WInst<"vst2_lane", "v*(2!)I", "hQh">; 424def VST3_LANE_F16 : WInst<"vst3_lane", "v*(3!)I", "hQh">; 425def VST4_LANE_F16 : WInst<"vst4_lane", "v*(4!)I", "hQh">; 426} 427 428//////////////////////////////////////////////////////////////////////////////// 429// E.3.16 Extract lanes from a vector 430let InstName = "vmov" in 431def VGET_LANE : IInst<"vget_lane", "1.I", 432 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">; 433 434//////////////////////////////////////////////////////////////////////////////// 435// E.3.17 Set lanes within a vector 436let InstName = "vmov" in 437def VSET_LANE : IInst<"vset_lane", ".1.I", 438 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl">; 439 440//////////////////////////////////////////////////////////////////////////////// 441// E.3.18 Initialize a vector from bit pattern 442def VCREATE : NoTestOpInst<"vcreate", ".(IU>)", "csihfUcUsUiUlPcPsl", OP_CAST> { 443 let BigEndianSafe = 1; 444} 445 446//////////////////////////////////////////////////////////////////////////////// 447// E.3.19 Set all lanes to same value 448let InstName = "vmov" in { 449def VDUP_N : WOpInst<"vdup_n", ".1", 450 "UcUsUicsiPcPshfQUcQUsQUiQcQsQiQPcQPsQhQflUlQlQUl", 451 OP_DUP>; 452def VMOV_N : WOpInst<"vmov_n", ".1", 453 "UcUsUicsiPcPshfQUcQUsQUiQcQsQiQPcQPsQhQflUlQlQUl", 454 OP_DUP>; 455} 456let InstName = "" in 457def VDUP_LANE: WOpInst<"vdup_lane", ".qI", 458 "UcUsUicsiPcPsfQUcQUsQUiQcQsQiQPcQPsQflUlQlQUl", 459 OP_DUP_LN>; 460 461//////////////////////////////////////////////////////////////////////////////// 462// E.3.20 Combining vectors 463def VCOMBINE : NoTestOpInst<"vcombine", "Q..", "csilhfUcUsUiUlPcPs", OP_CONC>; 464 465//////////////////////////////////////////////////////////////////////////////// 466// E.3.21 Splitting vectors 467// Note that the ARM NEON Reference 2.0 mistakenly document the vget_high_f16() 468// and vget_low_f16() intrinsics as AArch64-only. We (and GCC) support all 469// versions of these intrinsics in both AArch32 and AArch64 architectures. See 470// D45668 for more details. 471let InstName = "vmov" in { 472def VGET_HIGH : NoTestOpInst<"vget_high", ".Q", "csilhfUcUsUiUlPcPs", OP_HI>; 473def VGET_LOW : NoTestOpInst<"vget_low", ".Q", "csilhfUcUsUiUlPcPs", OP_LO>; 474} 475 476//////////////////////////////////////////////////////////////////////////////// 477// E.3.22 Converting vectors 478 479let ArchGuard = "(__ARM_FP & 2)" in { 480 def VCVT_F16_F32 : SInst<"vcvt_f16_f32", "(<q)(.!)", "Hf">; 481 def VCVT_F32_F16 : SInst<"vcvt_f32_f16", "(>Q)(.!)", "h">; 482} 483 484def VCVT_S32 : SInst<"vcvt_s32", "S.", "fQf">; 485def VCVT_U32 : SInst<"vcvt_u32", "U.", "fQf">; 486def VCVT_F32 : SInst<"vcvt_f32", "F(.!)", "iUiQiQUi">; 487let isVCVT_N = 1 in { 488def VCVT_N_S32 : SInst<"vcvt_n_s32", "S.I", "fQf">; 489def VCVT_N_U32 : SInst<"vcvt_n_u32", "U.I", "fQf">; 490def VCVT_N_F32 : SInst<"vcvt_n_f32", "F(.!)I", "iUiQiQUi">; 491} 492 493def VMOVN : IInst<"vmovn", "<Q", "silUsUiUl">; 494def VMOVL : SInst<"vmovl", "(>Q).", "csiUcUsUi">; 495def VQMOVN : SInst<"vqmovn", "<Q", "silUsUiUl">; 496def VQMOVUN : SInst<"vqmovun", "(<U)Q", "sil">; 497 498//////////////////////////////////////////////////////////////////////////////// 499// E.3.23-24 Table lookup, Extended table lookup 500let InstName = "vtbl" in { 501def VTBL1 : WInst<"vtbl1", "..p", "UccPc">; 502def VTBL2 : WInst<"vtbl2", ".2p", "UccPc">; 503def VTBL3 : WInst<"vtbl3", ".3p", "UccPc">; 504def VTBL4 : WInst<"vtbl4", ".4p", "UccPc">; 505} 506let InstName = "vtbx" in { 507def VTBX1 : WInst<"vtbx1", "...p", "UccPc">; 508def VTBX2 : WInst<"vtbx2", "..2p", "UccPc">; 509def VTBX3 : WInst<"vtbx3", "..3p", "UccPc">; 510def VTBX4 : WInst<"vtbx4", "..4p", "UccPc">; 511} 512 513//////////////////////////////////////////////////////////////////////////////// 514// E.3.25 Operations with a scalar value 515def VMLA_LANE : IOpInst<"vmla_lane", "...qI", 516 "siUsUifQsQiQUsQUiQf", OP_MLA_LN>; 517def VMLAL_LANE : SOpInst<"vmlal_lane", "(>Q)(>Q)..I", "siUsUi", OP_MLAL_LN>; 518def VQDMLAL_LANE : SOpInst<"vqdmlal_lane", "(>Q)(>Q)..I", "si", OP_QDMLAL_LN>; 519def VMLS_LANE : IOpInst<"vmls_lane", "...qI", 520 "siUsUifQsQiQUsQUiQf", OP_MLS_LN>; 521def VMLSL_LANE : SOpInst<"vmlsl_lane", "(>Q)(>Q)..I", "siUsUi", OP_MLSL_LN>; 522def VQDMLSL_LANE : SOpInst<"vqdmlsl_lane", "(>Q)(>Q)..I", "si", OP_QDMLSL_LN>; 523def VMUL_N : IOpInst<"vmul_n", "..1", "sifUsUiQsQiQfQUsQUi", OP_MUL_N>; 524def VMUL_LANE : IOpInst<"vmul_lane", "..qI", 525 "sifUsUiQsQiQfQUsQUi", OP_MUL_LN>; 526def VMULL_N : SOpInst<"vmull_n", "(>Q).1", "siUsUi", OP_MULL_N>; 527def VMULL_LANE : SOpInst<"vmull_lane", "(>Q)..I", "siUsUi", OP_MULL_LN>; 528def VQDMULL_N : SOpInst<"vqdmull_n", "(>Q).1", "si", OP_QDMULL_N>; 529def VQDMULL_LANE : SOpInst<"vqdmull_lane", "(>Q)..I", "si", OP_QDMULL_LN>; 530def VQDMULH_N : SOpInst<"vqdmulh_n", "..1", "siQsQi", OP_QDMULH_N>; 531def VQDMULH_LANE : SOpInst<"vqdmulh_lane", "..qI", "siQsQi", OP_QDMULH_LN>; 532def VQRDMULH_N : SOpInst<"vqrdmulh_n", "..1", "siQsQi", OP_QRDMULH_N>; 533def VQRDMULH_LANE : SOpInst<"vqrdmulh_lane", "..qI", "siQsQi", OP_QRDMULH_LN>; 534 535let ArchGuard = "defined(__ARM_FEATURE_QRDMX)" in { 536def VQRDMLAH_LANE : SOpInst<"vqrdmlah_lane", "...qI", "siQsQi", OP_QRDMLAH_LN>; 537def VQRDMLSH_LANE : SOpInst<"vqrdmlsh_lane", "...qI", "siQsQi", OP_QRDMLSH_LN>; 538} 539 540def VMLA_N : IOpInst<"vmla_n", "...1", "siUsUifQsQiQUsQUiQf", OP_MLA_N>; 541def VMLAL_N : SOpInst<"vmlal_n", "(>Q)(>Q).1", "siUsUi", OP_MLAL_N>; 542def VQDMLAL_N : SOpInst<"vqdmlal_n", "(>Q)(>Q).1", "si", OP_QDMLAL_N>; 543def VMLS_N : IOpInst<"vmls_n", "...1", "siUsUifQsQiQUsQUiQf", OP_MLS_N>; 544def VMLSL_N : SOpInst<"vmlsl_n", "(>Q)(>Q).1", "siUsUi", OP_MLSL_N>; 545def VQDMLSL_N : SOpInst<"vqdmlsl_n", "(>Q)(>Q).1", "si", OP_QDMLSL_N>; 546 547//////////////////////////////////////////////////////////////////////////////// 548// E.3.26 Vector Extract 549def VEXT : WInst<"vext", "...I", 550 "cUcPcsUsPsiUilUlfQcQUcQPcQsQUsQPsQiQUiQlQUlQf">; 551 552//////////////////////////////////////////////////////////////////////////////// 553// E.3.27 Reverse vector elements 554def VREV64 : WOpInst<"vrev64", "..", "csiUcUsUiPcPsfQcQsQiQUcQUsQUiQPcQPsQf", 555 OP_REV64>; 556def VREV32 : WOpInst<"vrev32", "..", "csUcUsPcPsQcQsQUcQUsQPcQPs", OP_REV32>; 557def VREV16 : WOpInst<"vrev16", "..", "cUcPcQcQUcQPc", OP_REV16>; 558 559//////////////////////////////////////////////////////////////////////////////// 560// E.3.28 Other single operand arithmetic 561def VABS : SInst<"vabs", "..", "csifQcQsQiQf">; 562def VQABS : SInst<"vqabs", "..", "csiQcQsQi">; 563def VNEG : SOpInst<"vneg", "..", "csifQcQsQiQf", OP_NEG>; 564def VQNEG : SInst<"vqneg", "..", "csiQcQsQi">; 565def VCLS : SInst<"vcls", "..", "csiQcQsQi">; 566def VCLZ : IInst<"vclz", "..", "csiUcUsUiQcQsQiQUcQUsQUi">; 567def VCNT : WInst<"vcnt", "..", "UccPcQUcQcQPc">; 568def VRECPE : SInst<"vrecpe", "..", "fUiQfQUi">; 569def VRSQRTE : SInst<"vrsqrte", "..", "fUiQfQUi">; 570 571//////////////////////////////////////////////////////////////////////////////// 572// E.3.29 Logical operations 573def VMVN : LOpInst<"vmvn", "..", "csiUcUsUiPcQcQsQiQUcQUsQUiQPc", OP_NOT>; 574def VAND : LOpInst<"vand", "...", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_AND>; 575def VORR : LOpInst<"vorr", "...", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_OR>; 576def VEOR : LOpInst<"veor", "...", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_XOR>; 577def VBIC : LOpInst<"vbic", "...", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ANDN>; 578def VORN : LOpInst<"vorn", "...", "csilUcUsUiUlQcQsQiQlQUcQUsQUiQUl", OP_ORN>; 579let isHiddenLInst = 1 in 580def VBSL : SInst<"vbsl", ".U..", 581 "csilUcUsUiUlfPcPsQcQsQiQlQUcQUsQUiQUlQfQPcQPs">; 582 583//////////////////////////////////////////////////////////////////////////////// 584// E.3.30 Transposition operations 585def VTRN : WInst<"vtrn", "2..", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">; 586def VZIP : WInst<"vzip", "2..", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">; 587def VUZP : WInst<"vuzp", "2..", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">; 588 589//////////////////////////////////////////////////////////////////////////////// 590// E.3.31 Vector reinterpret cast operations 591def VREINTERPRET 592 : NoTestOpInst<"vreinterpret", "..", 593 "csilUcUsUiUlhfPcPsQcQsQiQlQUcQUsQUiQUlQhQfQPcQPs", OP_REINT> { 594 let CartesianProductOfTypes = 1; 595 let ArchGuard = "!defined(__aarch64__)"; 596 let BigEndianSafe = 1; 597} 598 599//////////////////////////////////////////////////////////////////////////////// 600// Vector fused multiply-add operations 601 602let ArchGuard = "defined(__ARM_FEATURE_FMA)" in { 603 def VFMA : SInst<"vfma", "....", "fQf">; 604 def VFMS : SOpInst<"vfms", "....", "fQf", OP_FMLS>; 605 def FMLA_N_F32 : SOpInst<"vfma_n", "...1", "fQf", OP_FMLA_N>; 606} 607 608//////////////////////////////////////////////////////////////////////////////// 609// fp16 vector operations 610def SCALAR_HALF_GET_LANE : IOpInst<"vget_lane", "1.I", "h", OP_SCALAR_HALF_GET_LN>; 611def SCALAR_HALF_SET_LANE : IOpInst<"vset_lane", ".1.I", "h", OP_SCALAR_HALF_SET_LN>; 612def SCALAR_HALF_GET_LANEQ : IOpInst<"vget_lane", "1.I", "Qh", OP_SCALAR_HALF_GET_LNQ>; 613def SCALAR_HALF_SET_LANEQ : IOpInst<"vset_lane", ".1.I", "Qh", OP_SCALAR_HALF_SET_LNQ>; 614 615//////////////////////////////////////////////////////////////////////////////// 616// AArch64 Intrinsics 617 618let ArchGuard = "defined(__aarch64__)" in { 619 620//////////////////////////////////////////////////////////////////////////////// 621// Load/Store 622def LD1 : WInst<"vld1", ".(c*!)", "dQdPlQPl">; 623def LD2 : WInst<"vld2", "2(c*!)", "QUlQldQdPlQPl">; 624def LD3 : WInst<"vld3", "3(c*!)", "QUlQldQdPlQPl">; 625def LD4 : WInst<"vld4", "4(c*!)", "QUlQldQdPlQPl">; 626def ST1 : WInst<"vst1", "v*(.!)", "dQdPlQPl">; 627def ST2 : WInst<"vst2", "v*(2!)", "QUlQldQdPlQPl">; 628def ST3 : WInst<"vst3", "v*(3!)", "QUlQldQdPlQPl">; 629def ST4 : WInst<"vst4", "v*(4!)", "QUlQldQdPlQPl">; 630 631def LD1_X2 : WInst<"vld1_x2", "2(c*!)", 632 "dQdPlQPl">; 633def LD1_X3 : WInst<"vld1_x3", "3(c*!)", 634 "dQdPlQPl">; 635def LD1_X4 : WInst<"vld1_x4", "4(c*!)", 636 "dQdPlQPl">; 637 638def ST1_X2 : WInst<"vst1_x2", "v*(2!)", "dQdPlQPl">; 639def ST1_X3 : WInst<"vst1_x3", "v*(3!)", "dQdPlQPl">; 640def ST1_X4 : WInst<"vst1_x4", "v*(4!)", "dQdPlQPl">; 641 642def LD1_LANE : WInst<"vld1_lane", ".(c*!).I", "dQdPlQPl">; 643def LD2_LANE : WInst<"vld2_lane", "2(c*!)2I", "lUlQcQUcQPcQlQUldQdPlQPl">; 644def LD3_LANE : WInst<"vld3_lane", "3(c*!)3I", "lUlQcQUcQPcQlQUldQdPlQPl">; 645def LD4_LANE : WInst<"vld4_lane", "4(c*!)4I", "lUlQcQUcQPcQlQUldQdPlQPl">; 646def ST1_LANE : WInst<"vst1_lane", "v*(.!)I", "dQdPlQPl">; 647def ST2_LANE : WInst<"vst2_lane", "v*(2!)I", "lUlQcQUcQPcQlQUldQdPlQPl">; 648def ST3_LANE : WInst<"vst3_lane", "v*(3!)I", "lUlQcQUcQPcQlQUldQdPlQPl">; 649def ST4_LANE : WInst<"vst4_lane", "v*(4!)I", "lUlQcQUcQPcQlQUldQdPlQPl">; 650 651def LD1_DUP : WInst<"vld1_dup", ".(c*!)", "dQdPlQPl">; 652def LD2_DUP : WInst<"vld2_dup", "2(c*!)", "dQdPlQPl">; 653def LD3_DUP : WInst<"vld3_dup", "3(c*!)", "dQdPlQPl">; 654def LD4_DUP : WInst<"vld4_dup", "4(c*!)", "dQdPlQPl">; 655 656def VLDRQ : WInst<"vldrq", "1(c*!)", "Pk">; 657def VSTRQ : WInst<"vstrq", "v*(1!)", "Pk">; 658 659//////////////////////////////////////////////////////////////////////////////// 660// Addition 661def ADD : IOpInst<"vadd", "...", "dQd", OP_ADD>; 662 663//////////////////////////////////////////////////////////////////////////////// 664// Subtraction 665def SUB : IOpInst<"vsub", "...", "dQd", OP_SUB>; 666 667//////////////////////////////////////////////////////////////////////////////// 668// Multiplication 669def MUL : IOpInst<"vmul", "...", "dQd", OP_MUL>; 670def MLA : IOpInst<"vmla", "....", "dQd", OP_MLA>; 671def MLS : IOpInst<"vmls", "....", "dQd", OP_MLS>; 672 673//////////////////////////////////////////////////////////////////////////////// 674// Multiplication Extended 675def MULX : SInst<"vmulx", "...", "fdQfQd">; 676 677//////////////////////////////////////////////////////////////////////////////// 678// Division 679def FDIV : IOpInst<"vdiv", "...", "fdQfQd", OP_DIV>; 680 681//////////////////////////////////////////////////////////////////////////////// 682// Vector fused multiply-add operations 683def FMLA : SInst<"vfma", "....", "dQd">; 684def FMLS : SOpInst<"vfms", "....", "dQd", OP_FMLS>; 685 686//////////////////////////////////////////////////////////////////////////////// 687// MUL, MLA, MLS, FMA, FMS definitions with scalar argument 688def VMUL_N_A64 : IOpInst<"vmul_n", "..1", "Qd", OP_MUL_N>; 689 690def FMLA_N : SOpInst<"vfma_n", "...1", "dQd", OP_FMLA_N>; 691def FMLS_N : SOpInst<"vfms_n", "...1", "fdQfQd", OP_FMLS_N>; 692 693def MLA_N : SOpInst<"vmla_n", "...1", "Qd", OP_MLA_N>; 694def MLS_N : SOpInst<"vmls_n", "...1", "Qd", OP_MLS_N>; 695 696//////////////////////////////////////////////////////////////////////////////// 697// Logical operations 698def BSL : SInst<"vbsl", ".U..", "dPlQdQPl">; 699 700//////////////////////////////////////////////////////////////////////////////// 701// Absolute Difference 702def ABD : SInst<"vabd", "...", "dQd">; 703 704//////////////////////////////////////////////////////////////////////////////// 705// saturating absolute/negate 706def ABS : SInst<"vabs", "..", "dQdlQl">; 707def QABS : SInst<"vqabs", "..", "lQl">; 708def NEG : SOpInst<"vneg", "..", "dlQdQl", OP_NEG>; 709def QNEG : SInst<"vqneg", "..", "lQl">; 710 711//////////////////////////////////////////////////////////////////////////////// 712// Signed Saturating Accumulated of Unsigned Value 713def SUQADD : SInst<"vuqadd", "..U", "csilQcQsQiQl">; 714 715//////////////////////////////////////////////////////////////////////////////// 716// Unsigned Saturating Accumulated of Signed Value 717def USQADD : SInst<"vsqadd", "..S", "UcUsUiUlQUcQUsQUiQUl">; 718 719//////////////////////////////////////////////////////////////////////////////// 720// Reciprocal/Sqrt 721def FRECPS : IInst<"vrecps", "...", "dQd">; 722def FRSQRTS : IInst<"vrsqrts", "...", "dQd">; 723def FRECPE : SInst<"vrecpe", "..", "dQd">; 724def FRSQRTE : SInst<"vrsqrte", "..", "dQd">; 725def FSQRT : SInst<"vsqrt", "..", "fdQfQd">; 726 727//////////////////////////////////////////////////////////////////////////////// 728// bitwise reverse 729def RBIT : IInst<"vrbit", "..", "cUcPcQcQUcQPc">; 730 731//////////////////////////////////////////////////////////////////////////////// 732// Integer extract and narrow to high 733def XTN2 : SOpInst<"vmovn_high", "(<Q)<Q", "silUsUiUl", OP_XTN>; 734 735//////////////////////////////////////////////////////////////////////////////// 736// Signed integer saturating extract and unsigned narrow to high 737def SQXTUN2 : SOpInst<"vqmovun_high", "(<U)(<q).", "HsHiHl", OP_SQXTUN>; 738 739//////////////////////////////////////////////////////////////////////////////// 740// Integer saturating extract and narrow to high 741def QXTN2 : SOpInst<"vqmovn_high", "(<Q)<Q", "silUsUiUl", OP_QXTN>; 742 743//////////////////////////////////////////////////////////////////////////////// 744// Converting vectors 745 746def VCVT_F32_F64 : SInst<"vcvt_f32_f64", "(<q).", "Qd">; 747def VCVT_F64_F32 : SInst<"vcvt_f64_f32", "(>Q).", "f">; 748 749def VCVT_S64 : SInst<"vcvt_s64", "S.", "dQd">; 750def VCVT_U64 : SInst<"vcvt_u64", "U.", "dQd">; 751def VCVT_F64 : SInst<"vcvt_f64", "F(.!)", "lUlQlQUl">; 752 753def VCVT_HIGH_F16_F32 : SOpInst<"vcvt_high_f16", "<(<q!)Q", "Hf", OP_VCVT_NA_HI_F16>; 754def VCVT_HIGH_F32_F16 : SOpInst<"vcvt_high_f32", "(>Q)(Q!)", "h", OP_VCVT_EX_HI_F32>; 755def VCVT_HIGH_F32_F64 : SOpInst<"vcvt_high_f32", "(<Q)(F<!)Q", "d", OP_VCVT_NA_HI_F32>; 756def VCVT_HIGH_F64_F32 : SOpInst<"vcvt_high_f64", "(>Q)(Q!)", "f", OP_VCVT_EX_HI_F64>; 757 758def VCVTX_F32_F64 : SInst<"vcvtx_f32", "(F<)(Q!)", "d">; 759def VCVTX_HIGH_F32_F64 : SOpInst<"vcvtx_high_f32", "(<Q)(F<!)Q", "d", OP_VCVTX_HI>; 760 761//////////////////////////////////////////////////////////////////////////////// 762// Comparison 763def FCAGE : IInst<"vcage", "U..", "dQd">; 764def FCAGT : IInst<"vcagt", "U..", "dQd">; 765def FCALE : IInst<"vcale", "U..", "dQd">; 766def FCALT : IInst<"vcalt", "U..", "dQd">; 767def CMTST : WInst<"vtst", "U..", "lUlPlQlQUlQPl">; 768def CFMEQ : SOpInst<"vceq", "U..", "lUldQdQlQUlPlQPl", OP_EQ>; 769def CFMGE : SOpInst<"vcge", "U..", "lUldQdQlQUl", OP_GE>; 770def CFMLE : SOpInst<"vcle", "U..", "lUldQdQlQUl", OP_LE>; 771def CFMGT : SOpInst<"vcgt", "U..", "lUldQdQlQUl", OP_GT>; 772def CFMLT : SOpInst<"vclt", "U..", "lUldQdQlQUl", OP_LT>; 773 774def CMEQ : SInst<"vceqz", "U.", 775 "csilfUcUsUiUlPcPsPlQcQsQiQlQfQUcQUsQUiQUlQPcQPsdQdQPl">; 776def CMGE : SInst<"vcgez", "U.", "csilfdQcQsQiQlQfQd">; 777def CMLE : SInst<"vclez", "U.", "csilfdQcQsQiQlQfQd">; 778def CMGT : SInst<"vcgtz", "U.", "csilfdQcQsQiQlQfQd">; 779def CMLT : SInst<"vcltz", "U.", "csilfdQcQsQiQlQfQd">; 780 781//////////////////////////////////////////////////////////////////////////////// 782// Max/Min Integer 783def MAX : SInst<"vmax", "...", "dQd">; 784def MIN : SInst<"vmin", "...", "dQd">; 785 786//////////////////////////////////////////////////////////////////////////////// 787// Pairwise Max/Min 788def MAXP : SInst<"vpmax", "...", "QcQsQiQUcQUsQUiQfQd">; 789def MINP : SInst<"vpmin", "...", "QcQsQiQUcQUsQUiQfQd">; 790 791//////////////////////////////////////////////////////////////////////////////// 792// Pairwise MaxNum/MinNum Floating Point 793def FMAXNMP : SInst<"vpmaxnm", "...", "fQfQd">; 794def FMINNMP : SInst<"vpminnm", "...", "fQfQd">; 795 796//////////////////////////////////////////////////////////////////////////////// 797// Pairwise Addition 798def ADDP : IInst<"vpadd", "...", "QcQsQiQlQUcQUsQUiQUlQfQd">; 799 800//////////////////////////////////////////////////////////////////////////////// 801// Shifts by constant 802let isShift = 1 in { 803// Left shift long high 804def SHLL_HIGH_N : SOpInst<"vshll_high_n", ">.I", "HcHsHiHUcHUsHUi", 805 OP_LONG_HI>; 806 807//////////////////////////////////////////////////////////////////////////////// 808def SRI_N : WInst<"vsri_n", "...I", "PlQPl">; 809def SLI_N : WInst<"vsli_n", "...I", "PlQPl">; 810 811// Right shift narrow high 812def SHRN_HIGH_N : IOpInst<"vshrn_high_n", "<(<q).I", 813 "HsHiHlHUsHUiHUl", OP_NARROW_HI>; 814def QSHRUN_HIGH_N : SOpInst<"vqshrun_high_n", "<(<q).I", 815 "HsHiHl", OP_NARROW_HI>; 816def RSHRN_HIGH_N : IOpInst<"vrshrn_high_n", "<(<q).I", 817 "HsHiHlHUsHUiHUl", OP_NARROW_HI>; 818def QRSHRUN_HIGH_N : SOpInst<"vqrshrun_high_n", "<(<q).I", 819 "HsHiHl", OP_NARROW_HI>; 820def QSHRN_HIGH_N : SOpInst<"vqshrn_high_n", "<(<q).I", 821 "HsHiHlHUsHUiHUl", OP_NARROW_HI>; 822def QRSHRN_HIGH_N : SOpInst<"vqrshrn_high_n", "<(<q).I", 823 "HsHiHlHUsHUiHUl", OP_NARROW_HI>; 824} 825 826//////////////////////////////////////////////////////////////////////////////// 827// Converting vectors 828def VMOVL_HIGH : SOpInst<"vmovl_high", ">.", "HcHsHiHUcHUsHUi", OP_MOVL_HI>; 829 830let isVCVT_N = 1 in { 831def CVTF_N_F64 : SInst<"vcvt_n_f64", "F(.!)I", "lUlQlQUl">; 832def FCVTZS_N_S64 : SInst<"vcvt_n_s64", "S.I", "dQd">; 833def FCVTZS_N_U64 : SInst<"vcvt_n_u64", "U.I", "dQd">; 834} 835 836//////////////////////////////////////////////////////////////////////////////// 837// 3VDiff class using high 64-bit in operands 838def VADDL_HIGH : SOpInst<"vaddl_high", "(>Q)QQ", "csiUcUsUi", OP_ADDLHi>; 839def VADDW_HIGH : SOpInst<"vaddw_high", "(>Q)(>Q)Q", "csiUcUsUi", OP_ADDWHi>; 840def VSUBL_HIGH : SOpInst<"vsubl_high", "(>Q)QQ", "csiUcUsUi", OP_SUBLHi>; 841def VSUBW_HIGH : SOpInst<"vsubw_high", "(>Q)(>Q)Q", "csiUcUsUi", OP_SUBWHi>; 842 843def VABDL_HIGH : SOpInst<"vabdl_high", "(>Q)QQ", "csiUcUsUi", OP_ABDLHi>; 844def VABAL_HIGH : SOpInst<"vabal_high", "(>Q)(>Q)QQ", "csiUcUsUi", OP_ABALHi>; 845 846def VMULL_HIGH : SOpInst<"vmull_high", "(>Q)QQ", "csiUcUsUiPc", OP_MULLHi>; 847def VMULL_HIGH_N : SOpInst<"vmull_high_n", "(>Q)Q1", "siUsUi", OP_MULLHi_N>; 848def VMLAL_HIGH : SOpInst<"vmlal_high", "(>Q)(>Q)QQ", "csiUcUsUi", OP_MLALHi>; 849def VMLAL_HIGH_N : SOpInst<"vmlal_high_n", "(>Q)(>Q)Q1", "siUsUi", OP_MLALHi_N>; 850def VMLSL_HIGH : SOpInst<"vmlsl_high", "(>Q)(>Q)QQ", "csiUcUsUi", OP_MLSLHi>; 851def VMLSL_HIGH_N : SOpInst<"vmlsl_high_n", "(>Q)(>Q)Q1", "siUsUi", OP_MLSLHi_N>; 852 853def VADDHN_HIGH : SOpInst<"vaddhn_high", "(<Q)<QQ", "silUsUiUl", OP_ADDHNHi>; 854def VRADDHN_HIGH : SOpInst<"vraddhn_high", "(<Q)<QQ", "silUsUiUl", OP_RADDHNHi>; 855def VSUBHN_HIGH : SOpInst<"vsubhn_high", "(<Q)<QQ", "silUsUiUl", OP_SUBHNHi>; 856def VRSUBHN_HIGH : SOpInst<"vrsubhn_high", "(<Q)<QQ", "silUsUiUl", OP_RSUBHNHi>; 857 858def VQDMULL_HIGH : SOpInst<"vqdmull_high", "(>Q)QQ", "si", OP_QDMULLHi>; 859def VQDMULL_HIGH_N : SOpInst<"vqdmull_high_n", "(>Q)Q1", "si", OP_QDMULLHi_N>; 860def VQDMLAL_HIGH : SOpInst<"vqdmlal_high", "(>Q)(>Q)QQ", "si", OP_QDMLALHi>; 861def VQDMLAL_HIGH_N : SOpInst<"vqdmlal_high_n", "(>Q)(>Q)Q1", "si", OP_QDMLALHi_N>; 862def VQDMLSL_HIGH : SOpInst<"vqdmlsl_high", "(>Q)(>Q)QQ", "si", OP_QDMLSLHi>; 863def VQDMLSL_HIGH_N : SOpInst<"vqdmlsl_high_n", "(>Q)(>Q)Q1", "si", OP_QDMLSLHi_N>; 864def VMULL_P64 : SInst<"vmull", "(1>)11", "Pl">; 865def VMULL_HIGH_P64 : SOpInst<"vmull_high", "(1>)..", "HPl", OP_MULLHi_P64>; 866 867 868//////////////////////////////////////////////////////////////////////////////// 869// Extract or insert element from vector 870def GET_LANE : IInst<"vget_lane", "1.I", "dQdPlQPl">; 871def SET_LANE : IInst<"vset_lane", ".1.I", "dQdPlQPl">; 872def COPY_LANE : IOpInst<"vcopy_lane", "..I.I", 873 "csilUcUsUiUlPcPsPlfd", OP_COPY_LN>; 874def COPYQ_LANE : IOpInst<"vcopy_lane", "..IqI", 875 "QcQsQiQlQUcQUsQUiQUlQPcQPsQfQdQPl", OP_COPY_LN>; 876def COPY_LANEQ : IOpInst<"vcopy_laneq", "..IQI", 877 "csilPcPsPlUcUsUiUlfd", OP_COPY_LN>; 878def COPYQ_LANEQ : IOpInst<"vcopy_laneq", "..I.I", 879 "QcQsQiQlQUcQUsQUiQUlQPcQPsQfQdQPl", OP_COPY_LN>; 880 881//////////////////////////////////////////////////////////////////////////////// 882// Set all lanes to same value 883def VDUP_LANE1: WOpInst<"vdup_lane", ".qI", "hdQhQdPlQPl", OP_DUP_LN>; 884def VDUP_LANE2: WOpInst<"vdup_laneq", ".QI", 885 "csilUcUsUiUlPcPshfdQcQsQiQlQPcQPsQUcQUsQUiQUlQhQfQdPlQPl", 886 OP_DUP_LN>; 887def DUP_N : WOpInst<"vdup_n", ".1", "dQdPlQPl", OP_DUP>; 888def MOV_N : WOpInst<"vmov_n", ".1", "dQdPlQPl", OP_DUP>; 889 890//////////////////////////////////////////////////////////////////////////////// 891def COMBINE : NoTestOpInst<"vcombine", "Q..", "dPl", OP_CONC>; 892 893//////////////////////////////////////////////////////////////////////////////// 894//Initialize a vector from bit pattern 895def CREATE : NoTestOpInst<"vcreate", ".(IU>)", "dPl", OP_CAST> { 896 let BigEndianSafe = 1; 897} 898 899//////////////////////////////////////////////////////////////////////////////// 900 901def VMLA_LANEQ : IOpInst<"vmla_laneq", "...QI", 902 "siUsUifQsQiQUsQUiQf", OP_MLA_LN>; 903def VMLS_LANEQ : IOpInst<"vmls_laneq", "...QI", 904 "siUsUifQsQiQUsQUiQf", OP_MLS_LN>; 905 906def VFMA_LANE : IInst<"vfma_lane", "...qI", "fdQfQd">; 907def VFMA_LANEQ : IInst<"vfma_laneq", "...QI", "fdQfQd"> { 908 let isLaneQ = 1; 909} 910def VFMS_LANE : IOpInst<"vfms_lane", "...qI", "fdQfQd", OP_FMS_LN>; 911def VFMS_LANEQ : IOpInst<"vfms_laneq", "...QI", "fdQfQd", OP_FMS_LNQ>; 912 913def VMLAL_LANEQ : SOpInst<"vmlal_laneq", "(>Q)(>Q).QI", "siUsUi", OP_MLAL_LN>; 914def VMLAL_HIGH_LANE : SOpInst<"vmlal_high_lane", "(>Q)(>Q)Q.I", "siUsUi", 915 OP_MLALHi_LN>; 916def VMLAL_HIGH_LANEQ : SOpInst<"vmlal_high_laneq", "(>Q)(>Q)QQI", "siUsUi", 917 OP_MLALHi_LN>; 918def VMLSL_LANEQ : SOpInst<"vmlsl_laneq", "(>Q)(>Q).QI", "siUsUi", OP_MLSL_LN>; 919def VMLSL_HIGH_LANE : SOpInst<"vmlsl_high_lane", "(>Q)(>Q)Q.I", "siUsUi", 920 OP_MLSLHi_LN>; 921def VMLSL_HIGH_LANEQ : SOpInst<"vmlsl_high_laneq", "(>Q)(>Q)QQI", "siUsUi", 922 OP_MLSLHi_LN>; 923 924def VQDMLAL_LANEQ : SOpInst<"vqdmlal_laneq", "(>Q)(>Q).QI", "si", OP_QDMLAL_LN>; 925def VQDMLAL_HIGH_LANE : SOpInst<"vqdmlal_high_lane", "(>Q)(>Q)Q.I", "si", 926 OP_QDMLALHi_LN>; 927def VQDMLAL_HIGH_LANEQ : SOpInst<"vqdmlal_high_laneq", "(>Q)(>Q)QQI", "si", 928 OP_QDMLALHi_LN>; 929def VQDMLSL_LANEQ : SOpInst<"vqdmlsl_laneq", "(>Q)(>Q).QI", "si", OP_QDMLSL_LN>; 930def VQDMLSL_HIGH_LANE : SOpInst<"vqdmlsl_high_lane", "(>Q)(>Q)Q.I", "si", 931 OP_QDMLSLHi_LN>; 932def VQDMLSL_HIGH_LANEQ : SOpInst<"vqdmlsl_high_laneq", "(>Q)(>Q)QQI", "si", 933 OP_QDMLSLHi_LN>; 934 935// Newly add double parameter for vmul_lane in aarch64 936// Note: d type is handled by SCALAR_VMUL_LANE 937def VMUL_LANE_A64 : IOpInst<"vmul_lane", "..qI", "Qd", OP_MUL_LN>; 938 939// Note: d type is handled by SCALAR_VMUL_LANEQ 940def VMUL_LANEQ : IOpInst<"vmul_laneq", "..QI", 941 "sifUsUiQsQiQUsQUiQfQd", OP_MUL_LN>; 942def VMULL_LANEQ : SOpInst<"vmull_laneq", "(>Q).QI", "siUsUi", OP_MULL_LN>; 943def VMULL_HIGH_LANE : SOpInst<"vmull_high_lane", "(>Q)Q.I", "siUsUi", 944 OP_MULLHi_LN>; 945def VMULL_HIGH_LANEQ : SOpInst<"vmull_high_laneq", "(>Q)QQI", "siUsUi", 946 OP_MULLHi_LN>; 947 948def VQDMULL_LANEQ : SOpInst<"vqdmull_laneq", "(>Q).QI", "si", OP_QDMULL_LN>; 949def VQDMULL_HIGH_LANE : SOpInst<"vqdmull_high_lane", "(>Q)Q.I", "si", 950 OP_QDMULLHi_LN>; 951def VQDMULL_HIGH_LANEQ : SOpInst<"vqdmull_high_laneq", "(>Q)QQI", "si", 952 OP_QDMULLHi_LN>; 953 954def VQDMULH_LANEQ : SOpInst<"vqdmulh_laneq", "..QI", "siQsQi", OP_QDMULH_LN>; 955def VQRDMULH_LANEQ : SOpInst<"vqrdmulh_laneq", "..QI", "siQsQi", OP_QRDMULH_LN>; 956 957let ArchGuard = "defined(__ARM_FEATURE_QRDMX) && defined(__aarch64__)" in { 958def VQRDMLAH_LANEQ : SOpInst<"vqrdmlah_laneq", "...QI", "siQsQi", OP_QRDMLAH_LN>; 959def VQRDMLSH_LANEQ : SOpInst<"vqrdmlsh_laneq", "...QI", "siQsQi", OP_QRDMLSH_LN>; 960} 961 962// Note: d type implemented by SCALAR_VMULX_LANE 963def VMULX_LANE : IOpInst<"vmulx_lane", "..qI", "fQfQd", OP_MULX_LN>; 964// Note: d type is implemented by SCALAR_VMULX_LANEQ 965def VMULX_LANEQ : IOpInst<"vmulx_laneq", "..QI", "fQfQd", OP_MULX_LN>; 966 967//////////////////////////////////////////////////////////////////////////////// 968// Across vectors class 969def VADDLV : SInst<"vaddlv", "(1>).", "csiUcUsUiQcQsQiQUcQUsQUi">; 970def VMAXV : SInst<"vmaxv", "1.", "csifUcUsUiQcQsQiQUcQUsQUiQfQd">; 971def VMINV : SInst<"vminv", "1.", "csifUcUsUiQcQsQiQUcQUsQUiQfQd">; 972def VADDV : SInst<"vaddv", "1.", "csifUcUsUiQcQsQiQUcQUsQUiQfQdQlQUl">; 973def FMAXNMV : SInst<"vmaxnmv", "1.", "fQfQd">; 974def FMINNMV : SInst<"vminnmv", "1.", "fQfQd">; 975 976//////////////////////////////////////////////////////////////////////////////// 977// Newly added Vector Extract for f64 978def VEXT_A64 : WInst<"vext", "...I", "dQdPlQPl">; 979 980//////////////////////////////////////////////////////////////////////////////// 981// Crypto 982let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_CRYPTO)" in { 983def AESE : SInst<"vaese", "...", "QUc">; 984def AESD : SInst<"vaesd", "...", "QUc">; 985def AESMC : SInst<"vaesmc", "..", "QUc">; 986def AESIMC : SInst<"vaesimc", "..", "QUc">; 987 988def SHA1H : SInst<"vsha1h", "11", "Ui">; 989def SHA1SU1 : SInst<"vsha1su1", "...", "QUi">; 990def SHA256SU0 : SInst<"vsha256su0", "...", "QUi">; 991 992def SHA1C : SInst<"vsha1c", "..1.", "QUi">; 993def SHA1P : SInst<"vsha1p", "..1.", "QUi">; 994def SHA1M : SInst<"vsha1m", "..1.", "QUi">; 995def SHA1SU0 : SInst<"vsha1su0", "....", "QUi">; 996def SHA256H : SInst<"vsha256h", "....", "QUi">; 997def SHA256H2 : SInst<"vsha256h2", "....", "QUi">; 998def SHA256SU1 : SInst<"vsha256su1", "....", "QUi">; 999} 1000 1001//////////////////////////////////////////////////////////////////////////////// 1002// Float -> Int conversions with explicit rounding mode 1003 1004let ArchGuard = "__ARM_ARCH >= 8" in { 1005def FCVTNS_S32 : SInst<"vcvtn_s32", "S.", "fQf">; 1006def FCVTNU_S32 : SInst<"vcvtn_u32", "U.", "fQf">; 1007def FCVTPS_S32 : SInst<"vcvtp_s32", "S.", "fQf">; 1008def FCVTPU_S32 : SInst<"vcvtp_u32", "U.", "fQf">; 1009def FCVTMS_S32 : SInst<"vcvtm_s32", "S.", "fQf">; 1010def FCVTMU_S32 : SInst<"vcvtm_u32", "U.", "fQf">; 1011def FCVTAS_S32 : SInst<"vcvta_s32", "S.", "fQf">; 1012def FCVTAU_S32 : SInst<"vcvta_u32", "U.", "fQf">; 1013} 1014 1015let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__)" in { 1016def FCVTNS_S64 : SInst<"vcvtn_s64", "S.", "dQd">; 1017def FCVTNU_S64 : SInst<"vcvtn_u64", "U.", "dQd">; 1018def FCVTPS_S64 : SInst<"vcvtp_s64", "S.", "dQd">; 1019def FCVTPU_S64 : SInst<"vcvtp_u64", "U.", "dQd">; 1020def FCVTMS_S64 : SInst<"vcvtm_s64", "S.", "dQd">; 1021def FCVTMU_S64 : SInst<"vcvtm_u64", "U.", "dQd">; 1022def FCVTAS_S64 : SInst<"vcvta_s64", "S.", "dQd">; 1023def FCVTAU_S64 : SInst<"vcvta_u64", "U.", "dQd">; 1024} 1025 1026//////////////////////////////////////////////////////////////////////////////// 1027// Round to Integral 1028 1029let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_DIRECTED_ROUNDING)" in { 1030def FRINTN_S32 : SInst<"vrndn", "..", "fQf">; 1031def FRINTA_S32 : SInst<"vrnda", "..", "fQf">; 1032def FRINTP_S32 : SInst<"vrndp", "..", "fQf">; 1033def FRINTM_S32 : SInst<"vrndm", "..", "fQf">; 1034def FRINTX_S32 : SInst<"vrndx", "..", "fQf">; 1035def FRINTZ_S32 : SInst<"vrnd", "..", "fQf">; 1036def FRINTI_S32 : SInst<"vrndi", "..", "fQf">; 1037} 1038 1039let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__) && defined(__ARM_FEATURE_DIRECTED_ROUNDING)" in { 1040def FRINTN_S64 : SInst<"vrndn", "..", "dQd">; 1041def FRINTA_S64 : SInst<"vrnda", "..", "dQd">; 1042def FRINTP_S64 : SInst<"vrndp", "..", "dQd">; 1043def FRINTM_S64 : SInst<"vrndm", "..", "dQd">; 1044def FRINTX_S64 : SInst<"vrndx", "..", "dQd">; 1045def FRINTZ_S64 : SInst<"vrnd", "..", "dQd">; 1046def FRINTI_S64 : SInst<"vrndi", "..", "dQd">; 1047} 1048 1049//////////////////////////////////////////////////////////////////////////////// 1050// MaxNum/MinNum Floating Point 1051 1052let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_NUMERIC_MAXMIN)" in { 1053def FMAXNM_S32 : SInst<"vmaxnm", "...", "fQf">; 1054def FMINNM_S32 : SInst<"vminnm", "...", "fQf">; 1055} 1056 1057let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__) && defined(__ARM_FEATURE_NUMERIC_MAXMIN)" in { 1058def FMAXNM_S64 : SInst<"vmaxnm", "...", "dQd">; 1059def FMINNM_S64 : SInst<"vminnm", "...", "dQd">; 1060} 1061 1062//////////////////////////////////////////////////////////////////////////////// 1063// Permutation 1064def VTRN1 : SOpInst<"vtrn1", "...", 1065 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_TRN1>; 1066def VZIP1 : SOpInst<"vzip1", "...", 1067 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_ZIP1>; 1068def VUZP1 : SOpInst<"vuzp1", "...", 1069 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_UZP1>; 1070def VTRN2 : SOpInst<"vtrn2", "...", 1071 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_TRN2>; 1072def VZIP2 : SOpInst<"vzip2", "...", 1073 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_ZIP2>; 1074def VUZP2 : SOpInst<"vuzp2", "...", 1075 "csiUcUsUifPcPsQcQsQiQlQUcQUsQUiQUlQfQdQPcQPsQPl", OP_UZP2>; 1076 1077//////////////////////////////////////////////////////////////////////////////// 1078// Table lookup 1079let InstName = "vtbl" in { 1080def VQTBL1_A64 : WInst<"vqtbl1", ".QU", "UccPcQUcQcQPc">; 1081def VQTBL2_A64 : WInst<"vqtbl2", ".(2Q)U", "UccPcQUcQcQPc">; 1082def VQTBL3_A64 : WInst<"vqtbl3", ".(3Q)U", "UccPcQUcQcQPc">; 1083def VQTBL4_A64 : WInst<"vqtbl4", ".(4Q)U", "UccPcQUcQcQPc">; 1084} 1085let InstName = "vtbx" in { 1086def VQTBX1_A64 : WInst<"vqtbx1", "..QU", "UccPcQUcQcQPc">; 1087def VQTBX2_A64 : WInst<"vqtbx2", "..(2Q)U", "UccPcQUcQcQPc">; 1088def VQTBX3_A64 : WInst<"vqtbx3", "..(3Q)U", "UccPcQUcQcQPc">; 1089def VQTBX4_A64 : WInst<"vqtbx4", "..(4Q)U", "UccPcQUcQcQPc">; 1090} 1091 1092//////////////////////////////////////////////////////////////////////////////// 1093// Vector reinterpret cast operations 1094 1095// NeonEmitter implicitly takes the cartesian product of the type string with 1096// itself during generation so, unlike all other intrinsics, this one should 1097// include *all* types, not just additional ones. 1098def VVREINTERPRET 1099 : NoTestOpInst<"vreinterpret", "..", 1100 "csilUcUsUiUlhfdPcPsPlQcQsQiQlQUcQUsQUiQUlQhQfQdQPcQPsQPlQPk", OP_REINT> { 1101 let CartesianProductOfTypes = 1; 1102 let BigEndianSafe = 1; 1103 let ArchGuard = "__ARM_ARCH >= 8 && defined(__aarch64__)"; 1104} 1105 1106//////////////////////////////////////////////////////////////////////////////// 1107// Scalar Intrinsics 1108// Scalar Arithmetic 1109 1110// Scalar Addition 1111def SCALAR_ADD : SInst<"vadd", "111", "SlSUl">; 1112// Scalar Saturating Add 1113def SCALAR_QADD : SInst<"vqadd", "111", "ScSsSiSlSUcSUsSUiSUl">; 1114 1115// Scalar Subtraction 1116def SCALAR_SUB : SInst<"vsub", "111", "SlSUl">; 1117// Scalar Saturating Sub 1118def SCALAR_QSUB : SInst<"vqsub", "111", "ScSsSiSlSUcSUsSUiSUl">; 1119 1120let InstName = "vmov" in { 1121def VGET_HIGH_A64 : NoTestOpInst<"vget_high", ".Q", "dPl", OP_HI>; 1122def VGET_LOW_A64 : NoTestOpInst<"vget_low", ".Q", "dPl", OP_LO>; 1123} 1124 1125//////////////////////////////////////////////////////////////////////////////// 1126// Scalar Shift 1127// Scalar Shift Left 1128def SCALAR_SHL: SInst<"vshl", "111", "SlSUl">; 1129// Scalar Saturating Shift Left 1130def SCALAR_QSHL: SInst<"vqshl", "111", "ScSsSiSlSUcSUsSUiSUl">; 1131// Scalar Saturating Rounding Shift Left 1132def SCALAR_QRSHL: SInst<"vqrshl", "111", "ScSsSiSlSUcSUsSUiSUl">; 1133// Scalar Shift Rounding Left 1134def SCALAR_RSHL: SInst<"vrshl", "111", "SlSUl">; 1135 1136//////////////////////////////////////////////////////////////////////////////// 1137// Scalar Shift (Immediate) 1138let isScalarShift = 1 in { 1139// Signed/Unsigned Shift Right (Immediate) 1140def SCALAR_SSHR_N: SInst<"vshr_n", "11I", "SlSUl">; 1141// Signed/Unsigned Rounding Shift Right (Immediate) 1142def SCALAR_SRSHR_N: SInst<"vrshr_n", "11I", "SlSUl">; 1143 1144// Signed/Unsigned Shift Right and Accumulate (Immediate) 1145def SCALAR_SSRA_N: SInst<"vsra_n", "111I", "SlSUl">; 1146// Signed/Unsigned Rounding Shift Right and Accumulate (Immediate) 1147def SCALAR_SRSRA_N: SInst<"vrsra_n", "111I", "SlSUl">; 1148 1149// Shift Left (Immediate) 1150def SCALAR_SHL_N: SInst<"vshl_n", "11I", "SlSUl">; 1151// Signed/Unsigned Saturating Shift Left (Immediate) 1152def SCALAR_SQSHL_N: SInst<"vqshl_n", "11I", "ScSsSiSlSUcSUsSUiSUl">; 1153// Signed Saturating Shift Left Unsigned (Immediate) 1154def SCALAR_SQSHLU_N: SInst<"vqshlu_n", "11I", "ScSsSiSl">; 1155 1156// Shift Right And Insert (Immediate) 1157def SCALAR_SRI_N: SInst<"vsri_n", "111I", "SlSUl">; 1158// Shift Left And Insert (Immediate) 1159def SCALAR_SLI_N: SInst<"vsli_n", "111I", "SlSUl">; 1160 1161let isScalarNarrowShift = 1 in { 1162 // Signed/Unsigned Saturating Shift Right Narrow (Immediate) 1163 def SCALAR_SQSHRN_N: SInst<"vqshrn_n", "(1<)1I", "SsSiSlSUsSUiSUl">; 1164 // Signed/Unsigned Saturating Rounded Shift Right Narrow (Immediate) 1165 def SCALAR_SQRSHRN_N: SInst<"vqrshrn_n", "(1<)1I", "SsSiSlSUsSUiSUl">; 1166 // Signed Saturating Shift Right Unsigned Narrow (Immediate) 1167 def SCALAR_SQSHRUN_N: SInst<"vqshrun_n", "(1<)1I", "SsSiSl">; 1168 // Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate) 1169 def SCALAR_SQRSHRUN_N: SInst<"vqrshrun_n", "(1<)1I", "SsSiSl">; 1170} 1171 1172//////////////////////////////////////////////////////////////////////////////// 1173// Scalar Signed/Unsigned Fixed-point Convert To Floating-Point (Immediate) 1174def SCALAR_SCVTF_N_F32: SInst<"vcvt_n_f32", "(1F)(1!)I", "SiSUi">; 1175def SCALAR_SCVTF_N_F64: SInst<"vcvt_n_f64", "(1F)(1!)I", "SlSUl">; 1176 1177//////////////////////////////////////////////////////////////////////////////// 1178// Scalar Floating-point Convert To Signed/Unsigned Fixed-point (Immediate) 1179def SCALAR_FCVTZS_N_S32 : SInst<"vcvt_n_s32", "(1S)1I", "Sf">; 1180def SCALAR_FCVTZU_N_U32 : SInst<"vcvt_n_u32", "(1U)1I", "Sf">; 1181def SCALAR_FCVTZS_N_S64 : SInst<"vcvt_n_s64", "(1S)1I", "Sd">; 1182def SCALAR_FCVTZU_N_U64 : SInst<"vcvt_n_u64", "(1U)1I", "Sd">; 1183} 1184 1185//////////////////////////////////////////////////////////////////////////////// 1186// Scalar Floating-point Round to Integral 1187let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_DIRECTED_ROUNDING)" in { 1188def SCALAR_FRINTN_S32 : SInst<"vrndn", "11", "Sf">; 1189} 1190 1191//////////////////////////////////////////////////////////////////////////////// 1192// Scalar Reduce Pairwise Addition (Scalar and Floating Point) 1193def SCALAR_ADDP : SInst<"vpadd", "1.", "SfSHlSHdSHUl">; 1194 1195//////////////////////////////////////////////////////////////////////////////// 1196// Scalar Reduce Floating Point Pairwise Max/Min 1197def SCALAR_FMAXP : SInst<"vpmax", "1.", "SfSQd">; 1198 1199def SCALAR_FMINP : SInst<"vpmin", "1.", "SfSQd">; 1200 1201//////////////////////////////////////////////////////////////////////////////// 1202// Scalar Reduce Floating Point Pairwise maxNum/minNum 1203def SCALAR_FMAXNMP : SInst<"vpmaxnm", "1.", "SfSQd">; 1204def SCALAR_FMINNMP : SInst<"vpminnm", "1.", "SfSQd">; 1205 1206//////////////////////////////////////////////////////////////////////////////// 1207// Scalar Integer Saturating Doubling Multiply Half High 1208def SCALAR_SQDMULH : SInst<"vqdmulh", "111", "SsSi">; 1209 1210//////////////////////////////////////////////////////////////////////////////// 1211// Scalar Integer Saturating Rounding Doubling Multiply Half High 1212def SCALAR_SQRDMULH : SInst<"vqrdmulh", "111", "SsSi">; 1213 1214let ArchGuard = "defined(__ARM_FEATURE_QRDMX) && defined(__aarch64__)" in { 1215//////////////////////////////////////////////////////////////////////////////// 1216// Signed Saturating Rounding Doubling Multiply Accumulate Returning High Half 1217def SCALAR_SQRDMLAH : SOpInst<"vqrdmlah", "1111", "SsSi", OP_QRDMLAH>; 1218 1219//////////////////////////////////////////////////////////////////////////////// 1220// Signed Saturating Rounding Doubling Multiply Subtract Returning High Half 1221def SCALAR_SQRDMLSH : SOpInst<"vqrdmlsh", "1111", "SsSi", OP_QRDMLSH>; 1222} 1223 1224//////////////////////////////////////////////////////////////////////////////// 1225// Scalar Floating-point Multiply Extended 1226def SCALAR_FMULX : IInst<"vmulx", "111", "SfSd">; 1227 1228//////////////////////////////////////////////////////////////////////////////// 1229// Scalar Floating-point Reciprocal Step 1230def SCALAR_FRECPS : IInst<"vrecps", "111", "SfSd">; 1231 1232//////////////////////////////////////////////////////////////////////////////// 1233// Scalar Floating-point Reciprocal Square Root Step 1234def SCALAR_FRSQRTS : IInst<"vrsqrts", "111", "SfSd">; 1235 1236//////////////////////////////////////////////////////////////////////////////// 1237// Scalar Signed Integer Convert To Floating-point 1238def SCALAR_SCVTFS : SInst<"vcvt_f32", "(1F)(1!)", "Si">; 1239def SCALAR_SCVTFD : SInst<"vcvt_f64", "(1F)(1!)", "Sl">; 1240 1241//////////////////////////////////////////////////////////////////////////////// 1242// Scalar Unsigned Integer Convert To Floating-point 1243def SCALAR_UCVTFS : SInst<"vcvt_f32", "(1F)(1!)", "SUi">; 1244def SCALAR_UCVTFD : SInst<"vcvt_f64", "(1F)(1!)", "SUl">; 1245 1246//////////////////////////////////////////////////////////////////////////////// 1247// Scalar Floating-point Converts 1248def SCALAR_FCVTXN : IInst<"vcvtx_f32", "(1F<)(1!)", "Sd">; 1249def SCALAR_FCVTNSS : SInst<"vcvtn_s32", "(1S)1", "Sf">; 1250def SCALAR_FCVTNUS : SInst<"vcvtn_u32", "(1U)1", "Sf">; 1251def SCALAR_FCVTNSD : SInst<"vcvtn_s64", "(1S)1", "Sd">; 1252def SCALAR_FCVTNUD : SInst<"vcvtn_u64", "(1U)1", "Sd">; 1253def SCALAR_FCVTMSS : SInst<"vcvtm_s32", "(1S)1", "Sf">; 1254def SCALAR_FCVTMUS : SInst<"vcvtm_u32", "(1U)1", "Sf">; 1255def SCALAR_FCVTMSD : SInst<"vcvtm_s64", "(1S)1", "Sd">; 1256def SCALAR_FCVTMUD : SInst<"vcvtm_u64", "(1U)1", "Sd">; 1257def SCALAR_FCVTASS : SInst<"vcvta_s32", "(1S)1", "Sf">; 1258def SCALAR_FCVTAUS : SInst<"vcvta_u32", "(1U)1", "Sf">; 1259def SCALAR_FCVTASD : SInst<"vcvta_s64", "(1S)1", "Sd">; 1260def SCALAR_FCVTAUD : SInst<"vcvta_u64", "(1U)1", "Sd">; 1261def SCALAR_FCVTPSS : SInst<"vcvtp_s32", "(1S)1", "Sf">; 1262def SCALAR_FCVTPUS : SInst<"vcvtp_u32", "(1U)1", "Sf">; 1263def SCALAR_FCVTPSD : SInst<"vcvtp_s64", "(1S)1", "Sd">; 1264def SCALAR_FCVTPUD : SInst<"vcvtp_u64", "(1U)1", "Sd">; 1265def SCALAR_FCVTZSS : SInst<"vcvt_s32", "(1S)1", "Sf">; 1266def SCALAR_FCVTZUS : SInst<"vcvt_u32", "(1U)1", "Sf">; 1267def SCALAR_FCVTZSD : SInst<"vcvt_s64", "(1S)1", "Sd">; 1268def SCALAR_FCVTZUD : SInst<"vcvt_u64", "(1U)1", "Sd">; 1269 1270//////////////////////////////////////////////////////////////////////////////// 1271// Scalar Floating-point Reciprocal Estimate 1272def SCALAR_FRECPE : IInst<"vrecpe", "11", "SfSd">; 1273 1274//////////////////////////////////////////////////////////////////////////////// 1275// Scalar Floating-point Reciprocal Exponent 1276def SCALAR_FRECPX : IInst<"vrecpx", "11", "SfSd">; 1277 1278//////////////////////////////////////////////////////////////////////////////// 1279// Scalar Floating-point Reciprocal Square Root Estimate 1280def SCALAR_FRSQRTE : IInst<"vrsqrte", "11", "SfSd">; 1281 1282//////////////////////////////////////////////////////////////////////////////// 1283// Scalar Integer Comparison 1284def SCALAR_CMEQ : SInst<"vceq", "111", "SlSUl">; 1285def SCALAR_CMEQZ : SInst<"vceqz", "11", "SlSUl">; 1286def SCALAR_CMGE : SInst<"vcge", "111", "Sl">; 1287def SCALAR_CMGEZ : SInst<"vcgez", "11", "Sl">; 1288def SCALAR_CMHS : SInst<"vcge", "111", "SUl">; 1289def SCALAR_CMLE : SInst<"vcle", "111", "SlSUl">; 1290def SCALAR_CMLEZ : SInst<"vclez", "11", "Sl">; 1291def SCALAR_CMLT : SInst<"vclt", "111", "SlSUl">; 1292def SCALAR_CMLTZ : SInst<"vcltz", "11", "Sl">; 1293def SCALAR_CMGT : SInst<"vcgt", "111", "Sl">; 1294def SCALAR_CMGTZ : SInst<"vcgtz", "11", "Sl">; 1295def SCALAR_CMHI : SInst<"vcgt", "111", "SUl">; 1296def SCALAR_CMTST : SInst<"vtst", "111", "SlSUl">; 1297 1298//////////////////////////////////////////////////////////////////////////////// 1299// Scalar Floating-point Comparison 1300def SCALAR_FCMEQ : IInst<"vceq", "(1U)11", "SfSd">; 1301def SCALAR_FCMEQZ : IInst<"vceqz", "(1U)1", "SfSd">; 1302def SCALAR_FCMGE : IInst<"vcge", "(1U)11", "SfSd">; 1303def SCALAR_FCMGEZ : IInst<"vcgez", "(1U)1", "SfSd">; 1304def SCALAR_FCMGT : IInst<"vcgt", "(1U)11", "SfSd">; 1305def SCALAR_FCMGTZ : IInst<"vcgtz", "(1U)1", "SfSd">; 1306def SCALAR_FCMLE : IInst<"vcle", "(1U)11", "SfSd">; 1307def SCALAR_FCMLEZ : IInst<"vclez", "(1U)1", "SfSd">; 1308def SCALAR_FCMLT : IInst<"vclt", "(1U)11", "SfSd">; 1309def SCALAR_FCMLTZ : IInst<"vcltz", "(1U)1", "SfSd">; 1310 1311//////////////////////////////////////////////////////////////////////////////// 1312// Scalar Floating-point Absolute Compare Mask Greater Than Or Equal 1313def SCALAR_FACGE : IInst<"vcage", "(1U)11", "SfSd">; 1314def SCALAR_FACLE : IInst<"vcale", "(1U)11", "SfSd">; 1315 1316//////////////////////////////////////////////////////////////////////////////// 1317// Scalar Floating-point Absolute Compare Mask Greater Than 1318def SCALAR_FACGT : IInst<"vcagt", "(1U)11", "SfSd">; 1319def SCALAR_FACLT : IInst<"vcalt", "(1U)11", "SfSd">; 1320 1321//////////////////////////////////////////////////////////////////////////////// 1322// Scalar Absolute Value 1323def SCALAR_ABS : SInst<"vabs", "11", "Sl">; 1324 1325//////////////////////////////////////////////////////////////////////////////// 1326// Scalar Absolute Difference 1327def SCALAR_ABD : IInst<"vabd", "111", "SfSd">; 1328 1329//////////////////////////////////////////////////////////////////////////////// 1330// Scalar Signed Saturating Absolute Value 1331def SCALAR_SQABS : SInst<"vqabs", "11", "ScSsSiSl">; 1332 1333//////////////////////////////////////////////////////////////////////////////// 1334// Scalar Negate 1335def SCALAR_NEG : SInst<"vneg", "11", "Sl">; 1336 1337//////////////////////////////////////////////////////////////////////////////// 1338// Scalar Signed Saturating Negate 1339def SCALAR_SQNEG : SInst<"vqneg", "11", "ScSsSiSl">; 1340 1341//////////////////////////////////////////////////////////////////////////////// 1342// Scalar Signed Saturating Accumulated of Unsigned Value 1343def SCALAR_SUQADD : SInst<"vuqadd", "11(1U)", "ScSsSiSl">; 1344 1345//////////////////////////////////////////////////////////////////////////////// 1346// Scalar Unsigned Saturating Accumulated of Signed Value 1347def SCALAR_USQADD : SInst<"vsqadd", "11(1S)", "SUcSUsSUiSUl">; 1348 1349//////////////////////////////////////////////////////////////////////////////// 1350// Signed Saturating Doubling Multiply-Add Long 1351def SCALAR_SQDMLAL : SInst<"vqdmlal", "(1>)(1>)11", "SsSi">; 1352 1353//////////////////////////////////////////////////////////////////////////////// 1354// Signed Saturating Doubling Multiply-Subtract Long 1355def SCALAR_SQDMLSL : SInst<"vqdmlsl", "(1>)(1>)11", "SsSi">; 1356 1357//////////////////////////////////////////////////////////////////////////////// 1358// Signed Saturating Doubling Multiply Long 1359def SCALAR_SQDMULL : SInst<"vqdmull", "(1>)11", "SsSi">; 1360 1361//////////////////////////////////////////////////////////////////////////////// 1362// Scalar Signed Saturating Extract Unsigned Narrow 1363def SCALAR_SQXTUN : SInst<"vqmovun", "(1<)1", "SsSiSl">; 1364 1365//////////////////////////////////////////////////////////////////////////////// 1366// Scalar Signed Saturating Extract Narrow 1367def SCALAR_SQXTN : SInst<"vqmovn", "(1<)1", "SsSiSl">; 1368 1369//////////////////////////////////////////////////////////////////////////////// 1370// Scalar Unsigned Saturating Extract Narrow 1371def SCALAR_UQXTN : SInst<"vqmovn", "(1<)1", "SUsSUiSUl">; 1372 1373// Scalar Floating Point multiply (scalar, by element) 1374def SCALAR_FMUL_LANE : IOpInst<"vmul_lane", "11.I", "SfSd", OP_SCALAR_MUL_LN>; 1375def SCALAR_FMUL_LANEQ : IOpInst<"vmul_laneq", "11QI", "SfSd", OP_SCALAR_MUL_LN>; 1376 1377// Scalar Floating Point multiply extended (scalar, by element) 1378def SCALAR_FMULX_LANE : IOpInst<"vmulx_lane", "11.I", "SfSd", OP_SCALAR_MULX_LN>; 1379def SCALAR_FMULX_LANEQ : IOpInst<"vmulx_laneq", "11QI", "SfSd", OP_SCALAR_MULX_LN>; 1380 1381def SCALAR_VMUL_N : IInst<"vmul_n", "..1", "d">; 1382 1383// VMUL_LANE_A64 d type implemented using scalar mul lane 1384def SCALAR_VMUL_LANE : IInst<"vmul_lane", "..qI", "d">; 1385 1386// VMUL_LANEQ d type implemented using scalar mul lane 1387def SCALAR_VMUL_LANEQ : IInst<"vmul_laneq", "..QI", "d"> { 1388 let isLaneQ = 1; 1389} 1390 1391// VMULX_LANE d type implemented using scalar vmulx_lane 1392def SCALAR_VMULX_LANE : IOpInst<"vmulx_lane", "..qI", "d", OP_SCALAR_VMULX_LN>; 1393 1394// VMULX_LANEQ d type implemented using scalar vmulx_laneq 1395def SCALAR_VMULX_LANEQ : IOpInst<"vmulx_laneq", "..QI", "d", OP_SCALAR_VMULX_LNQ>; 1396 1397// Scalar Floating Point fused multiply-add (scalar, by element) 1398def SCALAR_FMLA_LANE : IInst<"vfma_lane", "111.I", "SfSd">; 1399def SCALAR_FMLA_LANEQ : IInst<"vfma_laneq", "111QI", "SfSd">; 1400 1401// Scalar Floating Point fused multiply-subtract (scalar, by element) 1402def SCALAR_FMLS_LANE : IOpInst<"vfms_lane", "111.I", "SfSd", OP_FMS_LN>; 1403def SCALAR_FMLS_LANEQ : IOpInst<"vfms_laneq", "111QI", "SfSd", OP_FMS_LNQ>; 1404 1405// Signed Saturating Doubling Multiply Long (scalar by element) 1406def SCALAR_SQDMULL_LANE : SOpInst<"vqdmull_lane", "(1>)1.I", "SsSi", OP_SCALAR_QDMULL_LN>; 1407def SCALAR_SQDMULL_LANEQ : SOpInst<"vqdmull_laneq", "(1>)1QI", "SsSi", OP_SCALAR_QDMULL_LN>; 1408 1409// Signed Saturating Doubling Multiply-Add Long (scalar by element) 1410def SCALAR_SQDMLAL_LANE : SInst<"vqdmlal_lane", "(1>)(1>)1.I", "SsSi">; 1411def SCALAR_SQDMLAL_LANEQ : SInst<"vqdmlal_laneq", "(1>)(1>)1QI", "SsSi">; 1412 1413// Signed Saturating Doubling Multiply-Subtract Long (scalar by element) 1414def SCALAR_SQDMLS_LANE : SInst<"vqdmlsl_lane", "(1>)(1>)1.I", "SsSi">; 1415def SCALAR_SQDMLS_LANEQ : SInst<"vqdmlsl_laneq", "(1>)(1>)1QI", "SsSi">; 1416 1417// Scalar Integer Saturating Doubling Multiply Half High (scalar by element) 1418def SCALAR_SQDMULH_LANE : SOpInst<"vqdmulh_lane", "11.I", "SsSi", OP_SCALAR_QDMULH_LN>; 1419def SCALAR_SQDMULH_LANEQ : SOpInst<"vqdmulh_laneq", "11QI", "SsSi", OP_SCALAR_QDMULH_LN>; 1420 1421// Scalar Integer Saturating Rounding Doubling Multiply Half High 1422def SCALAR_SQRDMULH_LANE : SOpInst<"vqrdmulh_lane", "11.I", "SsSi", OP_SCALAR_QRDMULH_LN>; 1423def SCALAR_SQRDMULH_LANEQ : SOpInst<"vqrdmulh_laneq", "11QI", "SsSi", OP_SCALAR_QRDMULH_LN>; 1424 1425let ArchGuard = "defined(__ARM_FEATURE_QRDMX) && defined(__aarch64__)" in { 1426// Signed Saturating Rounding Doubling Multiply Accumulate Returning High Half 1427def SCALAR_SQRDMLAH_LANE : SOpInst<"vqrdmlah_lane", "111.I", "SsSi", OP_SCALAR_QRDMLAH_LN>; 1428def SCALAR_SQRDMLAH_LANEQ : SOpInst<"vqrdmlah_laneq", "111QI", "SsSi", OP_SCALAR_QRDMLAH_LN>; 1429 1430// Signed Saturating Rounding Doubling Multiply Subtract Returning High Half 1431def SCALAR_SQRDMLSH_LANE : SOpInst<"vqrdmlsh_lane", "111.I", "SsSi", OP_SCALAR_QRDMLSH_LN>; 1432def SCALAR_SQRDMLSH_LANEQ : SOpInst<"vqrdmlsh_laneq", "111QI", "SsSi", OP_SCALAR_QRDMLSH_LN>; 1433} 1434 1435def SCALAR_VDUP_LANE : IInst<"vdup_lane", "1.I", "ScSsSiSlSfSdSUcSUsSUiSUlSPcSPs">; 1436def SCALAR_VDUP_LANEQ : IInst<"vdup_laneq", "1QI", "ScSsSiSlSfSdSUcSUsSUiSUlSPcSPs">; 1437} 1438 1439// ARMv8.2-A FP16 vector intrinsics for A32/A64. 1440let ArchGuard = "defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)" in { 1441 1442 // ARMv8.2-A FP16 one-operand vector intrinsics. 1443 1444 // Comparison 1445 def CMEQH : SInst<"vceqz", "U.", "hQh">; 1446 def CMGEH : SInst<"vcgez", "U.", "hQh">; 1447 def CMGTH : SInst<"vcgtz", "U.", "hQh">; 1448 def CMLEH : SInst<"vclez", "U.", "hQh">; 1449 def CMLTH : SInst<"vcltz", "U.", "hQh">; 1450 1451 // Vector conversion 1452 def VCVT_F16 : SInst<"vcvt_f16", "F(.!)", "sUsQsQUs">; 1453 def VCVT_S16 : SInst<"vcvt_s16", "S.", "hQh">; 1454 def VCVT_U16 : SInst<"vcvt_u16", "U.", "hQh">; 1455 def VCVTA_S16 : SInst<"vcvta_s16", "S.", "hQh">; 1456 def VCVTA_U16 : SInst<"vcvta_u16", "U.", "hQh">; 1457 def VCVTM_S16 : SInst<"vcvtm_s16", "S.", "hQh">; 1458 def VCVTM_U16 : SInst<"vcvtm_u16", "U.", "hQh">; 1459 def VCVTN_S16 : SInst<"vcvtn_s16", "S.", "hQh">; 1460 def VCVTN_U16 : SInst<"vcvtn_u16", "U.", "hQh">; 1461 def VCVTP_S16 : SInst<"vcvtp_s16", "S.", "hQh">; 1462 def VCVTP_U16 : SInst<"vcvtp_u16", "U.", "hQh">; 1463 1464 // Vector rounding 1465 let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_DIRECTED_ROUNDING) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)" in { 1466 def FRINTZH : SInst<"vrnd", "..", "hQh">; 1467 def FRINTNH : SInst<"vrndn", "..", "hQh">; 1468 def FRINTAH : SInst<"vrnda", "..", "hQh">; 1469 def FRINTPH : SInst<"vrndp", "..", "hQh">; 1470 def FRINTMH : SInst<"vrndm", "..", "hQh">; 1471 def FRINTXH : SInst<"vrndx", "..", "hQh">; 1472 } 1473 1474 // Misc. 1475 def VABSH : SInst<"vabs", "..", "hQh">; 1476 def VNEGH : SOpInst<"vneg", "..", "hQh", OP_NEG>; 1477 def VRECPEH : SInst<"vrecpe", "..", "hQh">; 1478 def FRSQRTEH : SInst<"vrsqrte", "..", "hQh">; 1479 1480 // ARMv8.2-A FP16 two-operands vector intrinsics. 1481 1482 // Misc. 1483 def VADDH : SOpInst<"vadd", "...", "hQh", OP_ADD>; 1484 def VABDH : SInst<"vabd", "...", "hQh">; 1485 def VSUBH : SOpInst<"vsub", "...", "hQh", OP_SUB>; 1486 1487 // Comparison 1488 let InstName = "vacge" in { 1489 def VCAGEH : SInst<"vcage", "U..", "hQh">; 1490 def VCALEH : SInst<"vcale", "U..", "hQh">; 1491 } 1492 let InstName = "vacgt" in { 1493 def VCAGTH : SInst<"vcagt", "U..", "hQh">; 1494 def VCALTH : SInst<"vcalt", "U..", "hQh">; 1495 } 1496 def VCEQH : SOpInst<"vceq", "U..", "hQh", OP_EQ>; 1497 def VCGEH : SOpInst<"vcge", "U..", "hQh", OP_GE>; 1498 def VCGTH : SOpInst<"vcgt", "U..", "hQh", OP_GT>; 1499 let InstName = "vcge" in 1500 def VCLEH : SOpInst<"vcle", "U..", "hQh", OP_LE>; 1501 let InstName = "vcgt" in 1502 def VCLTH : SOpInst<"vclt", "U..", "hQh", OP_LT>; 1503 1504 // Vector conversion 1505 let isVCVT_N = 1 in { 1506 def VCVT_N_F16 : SInst<"vcvt_n_f16", "F(.!)I", "sUsQsQUs">; 1507 def VCVT_N_S16 : SInst<"vcvt_n_s16", "S.I", "hQh">; 1508 def VCVT_N_U16 : SInst<"vcvt_n_u16", "U.I", "hQh">; 1509 } 1510 1511 // Max/Min 1512 def VMAXH : SInst<"vmax", "...", "hQh">; 1513 def VMINH : SInst<"vmin", "...", "hQh">; 1514 let ArchGuard = "__ARM_ARCH >= 8 && defined(__ARM_FEATURE_NUMERIC_MAXMIN) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)" in { 1515 def FMAXNMH : SInst<"vmaxnm", "...", "hQh">; 1516 def FMINNMH : SInst<"vminnm", "...", "hQh">; 1517 } 1518 1519 // Multiplication/Division 1520 def VMULH : SOpInst<"vmul", "...", "hQh", OP_MUL>; 1521 1522 // Pairwise addition 1523 def VPADDH : SInst<"vpadd", "...", "h">; 1524 1525 // Pairwise Max/Min 1526 def VPMAXH : SInst<"vpmax", "...", "h">; 1527 def VPMINH : SInst<"vpmin", "...", "h">; 1528 1529 // Reciprocal/Sqrt 1530 def VRECPSH : SInst<"vrecps", "...", "hQh">; 1531 def VRSQRTSH : SInst<"vrsqrts", "...", "hQh">; 1532 1533 // ARMv8.2-A FP16 three-operands vector intrinsics. 1534 1535 // Vector fused multiply-add operations 1536 def VFMAH : SInst<"vfma", "....", "hQh">; 1537 def VFMSH : SOpInst<"vfms", "....", "hQh", OP_FMLS>; 1538 1539 // ARMv8.2-A FP16 lane vector intrinsics. 1540 1541 // Mul lane 1542 def VMUL_LANEH : IOpInst<"vmul_lane", "..qI", "hQh", OP_MUL_LN>; 1543 def VMUL_NH : IOpInst<"vmul_n", "..1", "hQh", OP_MUL_N>; 1544 1545 // Data processing intrinsics - section 5 1546 1547 // Logical operations 1548 let isHiddenLInst = 1 in 1549 def VBSLH : SInst<"vbsl", ".U..", "hQh">; 1550 1551 // Transposition operations 1552 def VZIPH : WInst<"vzip", "2..", "hQh">; 1553 def VUZPH : WInst<"vuzp", "2..", "hQh">; 1554 def VTRNH : WInst<"vtrn", "2..", "hQh">; 1555 1556 1557 let ArchGuard = "!defined(__aarch64__)" in { 1558 // Set all lanes to same value. 1559 // Already implemented prior to ARMv8.2-A. 1560 def VMOV_NH : WOpInst<"vmov_n", ".1", "hQh", OP_DUP>; 1561 def VDUP_NH : WOpInst<"vdup_n", ".1", "hQh", OP_DUP>; 1562 def VDUP_LANE1H : WOpInst<"vdup_lane", ".qI", "hQh", OP_DUP_LN>; 1563 } 1564 1565 // Vector Extract 1566 def VEXTH : WInst<"vext", "...I", "hQh">; 1567 1568 // Reverse vector elements 1569 def VREV64H : WOpInst<"vrev64", "..", "hQh", OP_REV64>; 1570} 1571 1572// ARMv8.2-A FP16 vector intrinsics for A64 only. 1573let ArchGuard = "defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(__aarch64__)" in { 1574 1575 // Vector rounding 1576 def FRINTIH : SInst<"vrndi", "..", "hQh">; 1577 1578 // Misc. 1579 def FSQRTH : SInst<"vsqrt", "..", "hQh">; 1580 1581 // Multiplication/Division 1582 def MULXH : SInst<"vmulx", "...", "hQh">; 1583 def FDIVH : IOpInst<"vdiv", "...", "hQh", OP_DIV>; 1584 1585 // Pairwise addition 1586 def VPADDH1 : SInst<"vpadd", "...", "Qh">; 1587 1588 // Pairwise Max/Min 1589 def VPMAXH1 : SInst<"vpmax", "...", "Qh">; 1590 def VPMINH1 : SInst<"vpmin", "...", "Qh">; 1591 1592 // Pairwise MaxNum/MinNum 1593 def FMAXNMPH : SInst<"vpmaxnm", "...", "hQh">; 1594 def FMINNMPH : SInst<"vpminnm", "...", "hQh">; 1595 1596 // ARMv8.2-A FP16 lane vector intrinsics. 1597 1598 // FMA lane 1599 def VFMA_LANEH : IInst<"vfma_lane", "...qI", "hQh">; 1600 def VFMA_LANEQH : IInst<"vfma_laneq", "...QI", "hQh">; 1601 1602 // FMA lane with scalar argument 1603 def FMLA_NH : SOpInst<"vfma_n", "...1", "hQh", OP_FMLA_N>; 1604 // Scalar floating point fused multiply-add (scalar, by element) 1605 def SCALAR_FMLA_LANEH : IInst<"vfma_lane", "111.I", "Sh">; 1606 def SCALAR_FMLA_LANEQH : IInst<"vfma_laneq", "111QI", "Sh">; 1607 1608 // FMS lane 1609 def VFMS_LANEH : IOpInst<"vfms_lane", "...qI", "hQh", OP_FMS_LN>; 1610 def VFMS_LANEQH : IOpInst<"vfms_laneq", "...QI", "hQh", OP_FMS_LNQ>; 1611 // FMS lane with scalar argument 1612 def FMLS_NH : SOpInst<"vfms_n", "...1", "hQh", OP_FMLS_N>; 1613 // Scalar floating foint fused multiply-subtract (scalar, by element) 1614 def SCALAR_FMLS_LANEH : IOpInst<"vfms_lane", "111.I", "Sh", OP_FMS_LN>; 1615 def SCALAR_FMLS_LANEQH : IOpInst<"vfms_laneq", "111QI", "Sh", OP_FMS_LNQ>; 1616 1617 // Mul lane 1618 def VMUL_LANEQH : IOpInst<"vmul_laneq", "..QI", "hQh", OP_MUL_LN>; 1619 // Scalar floating point multiply (scalar, by element) 1620 def SCALAR_FMUL_LANEH : IOpInst<"vmul_lane", "11.I", "Sh", OP_SCALAR_MUL_LN>; 1621 def SCALAR_FMUL_LANEQH : IOpInst<"vmul_laneq", "11QI", "Sh", OP_SCALAR_MUL_LN>; 1622 1623 // Mulx lane 1624 def VMULX_LANEH : IOpInst<"vmulx_lane", "..qI", "hQh", OP_MULX_LN>; 1625 def VMULX_LANEQH : IOpInst<"vmulx_laneq", "..QI", "hQh", OP_MULX_LN>; 1626 def VMULX_NH : IOpInst<"vmulx_n", "..1", "hQh", OP_MULX_N>; 1627 // Scalar floating point mulx (scalar, by element) 1628 def SCALAR_FMULX_LANEH : IInst<"vmulx_lane", "11.I", "Sh">; 1629 def SCALAR_FMULX_LANEQH : IInst<"vmulx_laneq", "11QI", "Sh">; 1630 1631 // ARMv8.2-A FP16 reduction vector intrinsics. 1632 def VMAXVH : SInst<"vmaxv", "1.", "hQh">; 1633 def VMINVH : SInst<"vminv", "1.", "hQh">; 1634 def FMAXNMVH : SInst<"vmaxnmv", "1.", "hQh">; 1635 def FMINNMVH : SInst<"vminnmv", "1.", "hQh">; 1636 1637 // Permutation 1638 def VTRN1H : SOpInst<"vtrn1", "...", "hQh", OP_TRN1>; 1639 def VZIP1H : SOpInst<"vzip1", "...", "hQh", OP_ZIP1>; 1640 def VUZP1H : SOpInst<"vuzp1", "...", "hQh", OP_UZP1>; 1641 def VTRN2H : SOpInst<"vtrn2", "...", "hQh", OP_TRN2>; 1642 def VZIP2H : SOpInst<"vzip2", "...", "hQh", OP_ZIP2>; 1643 def VUZP2H : SOpInst<"vuzp2", "...", "hQh", OP_UZP2>; 1644 1645 def SCALAR_VDUP_LANEH : IInst<"vdup_lane", "1.I", "Sh">; 1646 def SCALAR_VDUP_LANEQH : IInst<"vdup_laneq", "1QI", "Sh">; 1647} 1648 1649// v8.2-A dot product instructions. 1650let ArchGuard = "defined(__ARM_FEATURE_DOTPROD)" in { 1651 def DOT : SInst<"vdot", "..(<<)(<<)", "iQiUiQUi">; 1652 def DOT_LANE : SOpInst<"vdot_lane", "..(<<)(<<q)I", "iUiQiQUi", OP_DOT_LN>; 1653} 1654let ArchGuard = "defined(__ARM_FEATURE_DOTPROD) && defined(__aarch64__)" in { 1655 // Variants indexing into a 128-bit vector are A64 only. 1656 def UDOT_LANEQ : SOpInst<"vdot_laneq", "..(<<)(<<Q)I", "iUiQiQUi", OP_DOT_LNQ>; 1657} 1658 1659// v8.2-A FP16 fused multiply-add long instructions. 1660let ArchGuard = "defined(__ARM_FEATURE_FP16FML) && defined(__aarch64__)" in { 1661 def VFMLAL_LOW : SInst<"vfmlal_low", ">>..", "hQh">; 1662 def VFMLSL_LOW : SInst<"vfmlsl_low", ">>..", "hQh">; 1663 def VFMLAL_HIGH : SInst<"vfmlal_high", ">>..", "hQh">; 1664 def VFMLSL_HIGH : SInst<"vfmlsl_high", ">>..", "hQh">; 1665 1666 def VFMLAL_LANE_LOW : SOpInst<"vfmlal_lane_low", "(F>)(F>)F(Fq)I", "hQh", OP_FMLAL_LN>; 1667 def VFMLSL_LANE_LOW : SOpInst<"vfmlsl_lane_low", "(F>)(F>)F(Fq)I", "hQh", OP_FMLSL_LN>; 1668 def VFMLAL_LANE_HIGH : SOpInst<"vfmlal_lane_high", "(F>)(F>)F(Fq)I", "hQh", OP_FMLAL_LN_Hi>; 1669 def VFMLSL_LANE_HIGH : SOpInst<"vfmlsl_lane_high", "(F>)(F>)F(Fq)I", "hQh", OP_FMLSL_LN_Hi>; 1670 1671 def VFMLAL_LANEQ_LOW : SOpInst<"vfmlal_laneq_low", "(F>)(F>)F(FQ)I", "hQh", OP_FMLAL_LN>; 1672 def VFMLSL_LANEQ_LOW : SOpInst<"vfmlsl_laneq_low", "(F>)(F>)F(FQ)I", "hQh", OP_FMLSL_LN>; 1673 def VFMLAL_LANEQ_HIGH : SOpInst<"vfmlal_laneq_high", "(F>)(F>)F(FQ)I", "hQh", OP_FMLAL_LN_Hi>; 1674 def VFMLSL_LANEQ_HIGH : SOpInst<"vfmlsl_laneq_high", "(F>)(F>)F(FQ)I", "hQh", OP_FMLSL_LN_Hi>; 1675} 1676 1677// v8.3-A Vector complex addition intrinsics 1678let ArchGuard = "defined(__ARM_FEATURE_COMPLEX) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)" in { 1679 def VCADD_ROT90_FP16 : SInst<"vcadd_rot90", "...", "h">; 1680 def VCADD_ROT270_FP16 : SInst<"vcadd_rot270", "...", "h">; 1681 def VCADDQ_ROT90_FP16 : SInst<"vcaddq_rot90", "QQQ", "h">; 1682 def VCADDQ_ROT270_FP16 : SInst<"vcaddq_rot270", "QQQ", "h">; 1683} 1684let ArchGuard = "defined(__ARM_FEATURE_COMPLEX)" in { 1685 def VCADD_ROT90 : SInst<"vcadd_rot90", "...", "f">; 1686 def VCADD_ROT270 : SInst<"vcadd_rot270", "...", "f">; 1687 def VCADDQ_ROT90 : SInst<"vcaddq_rot90", "QQQ", "f">; 1688 def VCADDQ_ROT270 : SInst<"vcaddq_rot270", "QQQ", "f">; 1689} 1690let ArchGuard = "defined(__ARM_FEATURE_COMPLEX) && defined(__aarch64__)" in { 1691 def VCADDQ_ROT90_FP64 : SInst<"vcaddq_rot90", "QQQ", "d">; 1692 def VCADDQ_ROT270_FP64 : SInst<"vcaddq_rot270", "QQQ", "d">; 1693}