1/*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2010 Broadcom Corporation 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 13 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 15 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 16 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18#define SDIO_FUNC_0 0 19#define SDIO_FUNC_1 1 20#define SDIO_FUNC_2 2 21 22#define SDIOD_FBR_SIZE 0x100 23 24/* io_en */ 25#define SDIO_FUNC_ENABLE_1 0x02 26#define SDIO_FUNC_ENABLE_2 0x04 27 28/* io_rdys */ 29#define SDIO_FUNC_READY_1 0x02 30#define SDIO_FUNC_READY_2 0x04 31 32/* intr_status */ 33#define INTR_STATUS_FUNC1 0x2 34#define INTR_STATUS_FUNC2 0x4 35 36/* Maximum number of I/O funcs */ 37#define SDIOD_MAX_IOFUNCS 7 38 39/* mask of register map */ 40#define REG_F0_REG_MASK 0x7FF 41#define REG_F1_MISC_MASK 0x1FFFF 42 43/* as of sdiod rev 0, supports 3 functions */ 44#define SBSDIO_NUM_FUNCTION 3 45 46/* function 0 vendor specific CCCR registers */ 47#define SDIO_CCCR_BRCM_CARDCAP 0xf0 48#define SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT 0x02 49#define SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT 0x04 50#define SDIO_CCCR_BRCM_CARDCAP_CMD_NODEC 0x08 51#define SDIO_CCCR_BRCM_CARDCTRL 0xf1 52#define SDIO_CCCR_BRCM_CARDCTRL_WLANRESET 0x02 53#define SDIO_CCCR_BRCM_SEPINT 0xf2 54 55#define SDIO_SEPINT_MASK 0x01 56#define SDIO_SEPINT_OE 0x02 57#define SDIO_SEPINT_ACT_HI 0x04 58 59/* function 1 miscellaneous registers */ 60 61/* sprom command and status */ 62#define SBSDIO_SPROM_CS 0x10000 63/* sprom info register */ 64#define SBSDIO_SPROM_INFO 0x10001 65/* sprom indirect access data byte 0 */ 66#define SBSDIO_SPROM_DATA_LOW 0x10002 67/* sprom indirect access data byte 1 */ 68#define SBSDIO_SPROM_DATA_HIGH 0x10003 69/* sprom indirect access addr byte 0 */ 70#define SBSDIO_SPROM_ADDR_LOW 0x10004 71/* gpio select */ 72#define SBSDIO_GPIO_SELECT 0x10005 73/* gpio output */ 74#define SBSDIO_GPIO_OUT 0x10006 75/* gpio enable */ 76#define SBSDIO_GPIO_EN 0x10007 77/* rev < 7, watermark for sdio device */ 78#define SBSDIO_WATERMARK 0x10008 79/* control busy signal generation */ 80#define SBSDIO_DEVICE_CTL 0x10009 81 82/* SB Address Window Low (b15) */ 83#define SBSDIO_FUNC1_SBADDRLOW 0x1000A 84/* SB Address Window Mid (b23:b16) */ 85#define SBSDIO_FUNC1_SBADDRMID 0x1000B 86/* SB Address Window High (b31:b24) */ 87#define SBSDIO_FUNC1_SBADDRHIGH 0x1000C 88/* Frame Control (frame term/abort) */ 89#define SBSDIO_FUNC1_FRAMECTRL 0x1000D 90/* ChipClockCSR (ALP/HT ctl/status) */ 91#define SBSDIO_FUNC1_CHIPCLKCSR 0x1000E 92/* SdioPullUp (on cmd, d0-d2) */ 93#define SBSDIO_FUNC1_SDIOPULLUP 0x1000F 94/* Write Frame Byte Count Low */ 95#define SBSDIO_FUNC1_WFRAMEBCLO 0x10019 96/* Write Frame Byte Count High */ 97#define SBSDIO_FUNC1_WFRAMEBCHI 0x1001A 98/* Read Frame Byte Count Low */ 99#define SBSDIO_FUNC1_RFRAMEBCLO 0x1001B 100/* Read Frame Byte Count High */ 101#define SBSDIO_FUNC1_RFRAMEBCHI 0x1001C 102/* MesBusyCtl (rev 11) */ 103#define SBSDIO_FUNC1_MESBUSYCTRL 0x1001D 104/* Sdio Core Rev 12 */ 105#define SBSDIO_FUNC1_WAKEUPCTRL 0x1001E 106#define SBSDIO_FUNC1_WCTRL_ALPWAIT_MASK 0x1 107#define SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT 0 108#define SBSDIO_FUNC1_WCTRL_HTWAIT_MASK 0x2 109#define SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT 1 110#define SBSDIO_FUNC1_SLEEPCSR 0x1001F 111#define SBSDIO_FUNC1_SLEEPCSR_KSO_MASK 0x1 112#define SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT 0 113#define SBSDIO_FUNC1_SLEEPCSR_KSO_EN 1 114#define SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK 0x2 115#define SBSDIO_FUNC1_SLEEPCSR_DEVON_SHIFT 1 116 117#define SBSDIO_FUNC1_MISC_REG_START 0x10000 /* f1 misc register start */ 118#define SBSDIO_FUNC1_MISC_REG_LIMIT 0x1001F /* f1 misc register end */ 119 120/* function 1 OCP space */ 121 122/* sb offset addr is <= 15 bits, 32k */ 123#define SBSDIO_SB_OFT_ADDR_MASK 0x07FFF 124#define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000 125/* with b15, maps to 32-bit SB access */ 126#define SBSDIO_SB_ACCESS_2_4B_FLAG 0x08000 127 128/* valid bits in SBSDIO_FUNC1_SBADDRxxx regs */ 129 130#define SBSDIO_SBADDRLOW_MASK 0x80 /* Valid bits in SBADDRLOW */ 131#define SBSDIO_SBADDRMID_MASK 0xff /* Valid bits in SBADDRMID */ 132#define SBSDIO_SBADDRHIGH_MASK 0xffU /* Valid bits in SBADDRHIGH */ 133/* Address bits from SBADDR regs */ 134#define SBSDIO_SBWINDOW_MASK 0xffff8000 135 136#define SDIOH_READ 0 /* Read request */ 137#define SDIOH_WRITE 1 /* Write request */ 138 139#define SDIOH_DATA_FIX 0 /* Fixed addressing */ 140#define SDIOH_DATA_INC 1 /* Incremental addressing */ 141 142/* internal return code */ 143#define SUCCESS 0 144#define ERROR 1 145 146/* Packet alignment for most efficient SDIO (can change based on platform) */ 147#define BRCMF_SDALIGN (1 << 6) 148 149/** 150 * enum brcmf_sdiod_state - the state of the bus. 151 * 152 * @BRCMF_SDIOD_DOWN: Device can be accessed, no DPC. 153 * @BRCMF_SDIOD_DATA: Ready for data transfers, DPC enabled. 154 * @BRCMF_SDIOD_NOMEDIUM: No medium access to dongle possible. 155 */ 156enum brcmf_sdiod_state { 157 BRCMF_SDIOD_DOWN, 158 BRCMF_SDIOD_DATA, 159 BRCMF_SDIOD_NOMEDIUM 160}; 161