1256056Sgrehan/*- 2256056Sgrehan * Copyright (c) 1998 - 2008 S��ren Schmidt <sos@FreeBSD.org> 3256056Sgrehan * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org> 4256056Sgrehan * All rights reserved. 5256056Sgrehan * 6256056Sgrehan * Redistribution and use in source and binary forms, with or without 7256056Sgrehan * modification, are permitted provided that the following conditions 8256056Sgrehan * are met: 9256056Sgrehan * 1. Redistributions of source code must retain the above copyright 10256056Sgrehan * notice, this list of conditions and the following disclaimer, 11256056Sgrehan * without modification, immediately at the beginning of the file. 12256056Sgrehan * 2. Redistributions in binary form must reproduce the above copyright 13256056Sgrehan * notice, this list of conditions and the following disclaimer in the 14256056Sgrehan * documentation and/or other materials provided with the distribution. 15256056Sgrehan * 16256056Sgrehan * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17256056Sgrehan * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18256056Sgrehan * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19256056Sgrehan * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20256056Sgrehan * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21256056Sgrehan * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22256056Sgrehan * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23256056Sgrehan * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24256056Sgrehan * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25256056Sgrehan * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26256056Sgrehan * 27256056Sgrehan * $FreeBSD$ 28256056Sgrehan */ 29256056Sgrehan 30256056Sgrehan#ifndef _AHCI_H_ 31256056Sgrehan#define _AHCI_H_ 32256056Sgrehan 33256056Sgrehan/* ATA register defines */ 34256056Sgrehan#define ATA_DATA 0 /* (RW) data */ 35256056Sgrehan 36256056Sgrehan#define ATA_FEATURE 1 /* (W) feature */ 37256056Sgrehan#define ATA_F_DMA 0x01 /* enable DMA */ 38256056Sgrehan#define ATA_F_OVL 0x02 /* enable overlap */ 39256056Sgrehan 40256056Sgrehan#define ATA_COUNT 2 /* (W) sector count */ 41256056Sgrehan 42256056Sgrehan#define ATA_SECTOR 3 /* (RW) sector # */ 43256056Sgrehan#define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */ 44256056Sgrehan#define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */ 45256056Sgrehan#define ATA_DRIVE 6 /* (W) Sector/Drive/Head */ 46256056Sgrehan#define ATA_D_LBA 0x40 /* use LBA addressing */ 47256056Sgrehan#define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 48256056Sgrehan 49256056Sgrehan#define ATA_COMMAND 7 /* (W) command */ 50256056Sgrehan 51256056Sgrehan#define ATA_ERROR 8 /* (R) error */ 52256056Sgrehan#define ATA_E_ILI 0x01 /* illegal length */ 53256056Sgrehan#define ATA_E_NM 0x02 /* no media */ 54256056Sgrehan#define ATA_E_ABORT 0x04 /* command aborted */ 55256056Sgrehan#define ATA_E_MCR 0x08 /* media change request */ 56256056Sgrehan#define ATA_E_IDNF 0x10 /* ID not found */ 57256056Sgrehan#define ATA_E_MC 0x20 /* media changed */ 58256056Sgrehan#define ATA_E_UNC 0x40 /* uncorrectable data */ 59256056Sgrehan#define ATA_E_ICRC 0x80 /* UDMA crc error */ 60256056Sgrehan#define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */ 61256056Sgrehan 62256056Sgrehan#define ATA_IREASON 9 /* (R) interrupt reason */ 63256056Sgrehan#define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 64256056Sgrehan#define ATA_I_IN 0x02 /* read (1) | write (0) */ 65256056Sgrehan#define ATA_I_RELEASE 0x04 /* released bus (1) */ 66256056Sgrehan#define ATA_I_TAGMASK 0xf8 /* tag mask */ 67256056Sgrehan 68256056Sgrehan#define ATA_STATUS 10 /* (R) status */ 69256056Sgrehan#define ATA_ALTSTAT 11 /* (R) alternate status */ 70256056Sgrehan#define ATA_S_ERROR 0x01 /* error */ 71256056Sgrehan#define ATA_S_INDEX 0x02 /* index */ 72256056Sgrehan#define ATA_S_CORR 0x04 /* data corrected */ 73256056Sgrehan#define ATA_S_DRQ 0x08 /* data request */ 74256056Sgrehan#define ATA_S_DSC 0x10 /* drive seek completed */ 75256056Sgrehan#define ATA_S_SERVICE 0x10 /* drive needs service */ 76256056Sgrehan#define ATA_S_DWF 0x20 /* drive write fault */ 77256056Sgrehan#define ATA_S_DMA 0x20 /* DMA ready */ 78256056Sgrehan#define ATA_S_READY 0x40 /* drive ready */ 79256056Sgrehan#define ATA_S_BUSY 0x80 /* busy */ 80256056Sgrehan 81256056Sgrehan#define ATA_CONTROL 12 /* (W) control */ 82256056Sgrehan#define ATA_A_IDS 0x02 /* disable interrupts */ 83256056Sgrehan#define ATA_A_RESET 0x04 /* RESET controller */ 84256056Sgrehan#define ATA_A_4BIT 0x08 /* 4 head bits */ 85256056Sgrehan#define ATA_A_HOB 0x80 /* High Order Byte enable */ 86256056Sgrehan 87256056Sgrehan/* SATA register defines */ 88256056Sgrehan#define ATA_SSTATUS 13 89256056Sgrehan#define ATA_SS_DET_MASK 0x0000000f 90256056Sgrehan#define ATA_SS_DET_NO_DEVICE 0x00000000 91256056Sgrehan#define ATA_SS_DET_DEV_PRESENT 0x00000001 92256056Sgrehan#define ATA_SS_DET_PHY_ONLINE 0x00000003 93256056Sgrehan#define ATA_SS_DET_PHY_OFFLINE 0x00000004 94256056Sgrehan 95256056Sgrehan#define ATA_SS_SPD_MASK 0x000000f0 96256056Sgrehan#define ATA_SS_SPD_NO_SPEED 0x00000000 97256056Sgrehan#define ATA_SS_SPD_GEN1 0x00000010 98256056Sgrehan#define ATA_SS_SPD_GEN2 0x00000020 99256056Sgrehan#define ATA_SS_SPD_GEN3 0x00000040 100256056Sgrehan 101256056Sgrehan#define ATA_SS_IPM_MASK 0x00000f00 102256056Sgrehan#define ATA_SS_IPM_NO_DEVICE 0x00000000 103256056Sgrehan#define ATA_SS_IPM_ACTIVE 0x00000100 104256056Sgrehan#define ATA_SS_IPM_PARTIAL 0x00000200 105256056Sgrehan#define ATA_SS_IPM_SLUMBER 0x00000600 106256056Sgrehan 107256056Sgrehan#define ATA_SERROR 14 108256056Sgrehan#define ATA_SE_DATA_CORRECTED 0x00000001 109256056Sgrehan#define ATA_SE_COMM_CORRECTED 0x00000002 110256056Sgrehan#define ATA_SE_DATA_ERR 0x00000100 111256056Sgrehan#define ATA_SE_COMM_ERR 0x00000200 112256056Sgrehan#define ATA_SE_PROT_ERR 0x00000400 113256056Sgrehan#define ATA_SE_HOST_ERR 0x00000800 114256056Sgrehan#define ATA_SE_PHY_CHANGED 0x00010000 115256056Sgrehan#define ATA_SE_PHY_IERROR 0x00020000 116256056Sgrehan#define ATA_SE_COMM_WAKE 0x00040000 117256056Sgrehan#define ATA_SE_DECODE_ERR 0x00080000 118256056Sgrehan#define ATA_SE_PARITY_ERR 0x00100000 119256056Sgrehan#define ATA_SE_CRC_ERR 0x00200000 120256056Sgrehan#define ATA_SE_HANDSHAKE_ERR 0x00400000 121256056Sgrehan#define ATA_SE_LINKSEQ_ERR 0x00800000 122256056Sgrehan#define ATA_SE_TRANSPORT_ERR 0x01000000 123256056Sgrehan#define ATA_SE_UNKNOWN_FIS 0x02000000 124256056Sgrehan#define ATA_SE_EXCHANGED 0x04000000 125256056Sgrehan 126256056Sgrehan#define ATA_SCONTROL 15 127256056Sgrehan#define ATA_SC_DET_MASK 0x0000000f 128256056Sgrehan#define ATA_SC_DET_IDLE 0x00000000 129256056Sgrehan#define ATA_SC_DET_RESET 0x00000001 130256056Sgrehan#define ATA_SC_DET_DISABLE 0x00000004 131256056Sgrehan 132256056Sgrehan#define ATA_SC_SPD_MASK 0x000000f0 133256056Sgrehan#define ATA_SC_SPD_NO_SPEED 0x00000000 134256056Sgrehan#define ATA_SC_SPD_SPEED_GEN1 0x00000010 135256056Sgrehan#define ATA_SC_SPD_SPEED_GEN2 0x00000020 136256056Sgrehan#define ATA_SC_SPD_SPEED_GEN3 0x00000040 137256056Sgrehan 138256056Sgrehan#define ATA_SC_IPM_MASK 0x00000f00 139256056Sgrehan#define ATA_SC_IPM_NONE 0x00000000 140256056Sgrehan#define ATA_SC_IPM_DIS_PARTIAL 0x00000100 141256056Sgrehan#define ATA_SC_IPM_DIS_SLUMBER 0x00000200 142256056Sgrehan 143256056Sgrehan#define ATA_SACTIVE 16 144256056Sgrehan 145256056Sgrehan#define AHCI_MAX_PORTS 32 146256056Sgrehan#define AHCI_MAX_SLOTS 32 147256056Sgrehan 148256056Sgrehan/* SATA AHCI v1.0 register defines */ 149256056Sgrehan#define AHCI_CAP 0x00 150256056Sgrehan#define AHCI_CAP_NPMASK 0x0000001f 151256056Sgrehan#define AHCI_CAP_SXS 0x00000020 152256056Sgrehan#define AHCI_CAP_EMS 0x00000040 153256056Sgrehan#define AHCI_CAP_CCCS 0x00000080 154256056Sgrehan#define AHCI_CAP_NCS 0x00001F00 155256056Sgrehan#define AHCI_CAP_NCS_SHIFT 8 156256056Sgrehan#define AHCI_CAP_PSC 0x00002000 157256056Sgrehan#define AHCI_CAP_SSC 0x00004000 158256056Sgrehan#define AHCI_CAP_PMD 0x00008000 159256056Sgrehan#define AHCI_CAP_FBSS 0x00010000 160256056Sgrehan#define AHCI_CAP_SPM 0x00020000 161256056Sgrehan#define AHCI_CAP_SAM 0x00080000 162256056Sgrehan#define AHCI_CAP_ISS 0x00F00000 163256056Sgrehan#define AHCI_CAP_ISS_SHIFT 20 164256056Sgrehan#define AHCI_CAP_SCLO 0x01000000 165256056Sgrehan#define AHCI_CAP_SAL 0x02000000 166256056Sgrehan#define AHCI_CAP_SALP 0x04000000 167256056Sgrehan#define AHCI_CAP_SSS 0x08000000 168256056Sgrehan#define AHCI_CAP_SMPS 0x10000000 169256056Sgrehan#define AHCI_CAP_SSNTF 0x20000000 170256056Sgrehan#define AHCI_CAP_SNCQ 0x40000000 171256056Sgrehan#define AHCI_CAP_64BIT 0x80000000 172256056Sgrehan 173256056Sgrehan#define AHCI_GHC 0x04 174256056Sgrehan#define AHCI_GHC_AE 0x80000000 175256056Sgrehan#define AHCI_GHC_MRSM 0x00000004 176256056Sgrehan#define AHCI_GHC_IE 0x00000002 177256056Sgrehan#define AHCI_GHC_HR 0x00000001 178256056Sgrehan 179256056Sgrehan#define AHCI_IS 0x08 180256056Sgrehan#define AHCI_PI 0x0c 181256056Sgrehan#define AHCI_VS 0x10 182256056Sgrehan 183256056Sgrehan#define AHCI_CCCC 0x14 184256056Sgrehan#define AHCI_CCCC_TV_MASK 0xffff0000 185256056Sgrehan#define AHCI_CCCC_TV_SHIFT 16 186256056Sgrehan#define AHCI_CCCC_CC_MASK 0x0000ff00 187256056Sgrehan#define AHCI_CCCC_CC_SHIFT 8 188256056Sgrehan#define AHCI_CCCC_INT_MASK 0x000000f8 189256056Sgrehan#define AHCI_CCCC_INT_SHIFT 3 190256056Sgrehan#define AHCI_CCCC_EN 0x00000001 191256056Sgrehan#define AHCI_CCCP 0x18 192256056Sgrehan 193256056Sgrehan#define AHCI_EM_LOC 0x1C 194256056Sgrehan#define AHCI_EM_CTL 0x20 195256056Sgrehan#define AHCI_EM_MR 0x00000001 196256056Sgrehan#define AHCI_EM_TM 0x00000100 197256056Sgrehan#define AHCI_EM_RST 0x00000200 198256056Sgrehan#define AHCI_EM_LED 0x00010000 199256056Sgrehan#define AHCI_EM_SAFTE 0x00020000 200256056Sgrehan#define AHCI_EM_SES2 0x00040000 201256056Sgrehan#define AHCI_EM_SGPIO 0x00080000 202256056Sgrehan#define AHCI_EM_SMB 0x01000000 203256056Sgrehan#define AHCI_EM_XMT 0x02000000 204256056Sgrehan#define AHCI_EM_ALHD 0x04000000 205256056Sgrehan#define AHCI_EM_PM 0x08000000 206256056Sgrehan 207256056Sgrehan#define AHCI_CAP2 0x24 208256056Sgrehan#define AHCI_CAP2_BOH 0x00000001 209256056Sgrehan#define AHCI_CAP2_NVMP 0x00000002 210256056Sgrehan#define AHCI_CAP2_APST 0x00000004 211256056Sgrehan 212256056Sgrehan#define AHCI_OFFSET 0x100 213256056Sgrehan#define AHCI_STEP 0x80 214256056Sgrehan 215256056Sgrehan#define AHCI_P_CLB 0x00 216256056Sgrehan#define AHCI_P_CLBU 0x04 217256056Sgrehan#define AHCI_P_FB 0x08 218256056Sgrehan#define AHCI_P_FBU 0x0c 219256056Sgrehan#define AHCI_P_IS 0x10 220256056Sgrehan#define AHCI_P_IE 0x14 221256056Sgrehan#define AHCI_P_IX_DHR 0x00000001 222256056Sgrehan#define AHCI_P_IX_PS 0x00000002 223256056Sgrehan#define AHCI_P_IX_DS 0x00000004 224256056Sgrehan#define AHCI_P_IX_SDB 0x00000008 225256056Sgrehan#define AHCI_P_IX_UF 0x00000010 226256056Sgrehan#define AHCI_P_IX_DP 0x00000020 227256056Sgrehan#define AHCI_P_IX_PC 0x00000040 228256056Sgrehan#define AHCI_P_IX_MP 0x00000080 229256056Sgrehan 230256056Sgrehan#define AHCI_P_IX_PRC 0x00400000 231256056Sgrehan#define AHCI_P_IX_IPM 0x00800000 232256056Sgrehan#define AHCI_P_IX_OF 0x01000000 233256056Sgrehan#define AHCI_P_IX_INF 0x04000000 234256056Sgrehan#define AHCI_P_IX_IF 0x08000000 235256056Sgrehan#define AHCI_P_IX_HBD 0x10000000 236256056Sgrehan#define AHCI_P_IX_HBF 0x20000000 237256056Sgrehan#define AHCI_P_IX_TFE 0x40000000 238256056Sgrehan#define AHCI_P_IX_CPD 0x80000000 239256056Sgrehan 240256056Sgrehan#define AHCI_P_CMD 0x18 241256056Sgrehan#define AHCI_P_CMD_ST 0x00000001 242256056Sgrehan#define AHCI_P_CMD_SUD 0x00000002 243256056Sgrehan#define AHCI_P_CMD_POD 0x00000004 244256056Sgrehan#define AHCI_P_CMD_CLO 0x00000008 245256056Sgrehan#define AHCI_P_CMD_FRE 0x00000010 246256056Sgrehan#define AHCI_P_CMD_CCS_MASK 0x00001f00 247256056Sgrehan#define AHCI_P_CMD_CCS_SHIFT 8 248256056Sgrehan#define AHCI_P_CMD_ISS 0x00002000 249256056Sgrehan#define AHCI_P_CMD_FR 0x00004000 250256056Sgrehan#define AHCI_P_CMD_CR 0x00008000 251256056Sgrehan#define AHCI_P_CMD_CPS 0x00010000 252256056Sgrehan#define AHCI_P_CMD_PMA 0x00020000 253256056Sgrehan#define AHCI_P_CMD_HPCP 0x00040000 254256056Sgrehan#define AHCI_P_CMD_MPSP 0x00080000 255256056Sgrehan#define AHCI_P_CMD_CPD 0x00100000 256256056Sgrehan#define AHCI_P_CMD_ESP 0x00200000 257256056Sgrehan#define AHCI_P_CMD_FBSCP 0x00400000 258256056Sgrehan#define AHCI_P_CMD_APSTE 0x00800000 259256056Sgrehan#define AHCI_P_CMD_ATAPI 0x01000000 260256056Sgrehan#define AHCI_P_CMD_DLAE 0x02000000 261256056Sgrehan#define AHCI_P_CMD_ALPE 0x04000000 262256056Sgrehan#define AHCI_P_CMD_ASP 0x08000000 263256056Sgrehan#define AHCI_P_CMD_ICC_MASK 0xf0000000 264256056Sgrehan#define AHCI_P_CMD_NOOP 0x00000000 265256056Sgrehan#define AHCI_P_CMD_ACTIVE 0x10000000 266256056Sgrehan#define AHCI_P_CMD_PARTIAL 0x20000000 267256056Sgrehan#define AHCI_P_CMD_SLUMBER 0x60000000 268256056Sgrehan 269256056Sgrehan#define AHCI_P_TFD 0x20 270256056Sgrehan#define AHCI_P_SIG 0x24 271256056Sgrehan#define AHCI_P_SSTS 0x28 272256056Sgrehan#define AHCI_P_SCTL 0x2c 273256056Sgrehan#define AHCI_P_SERR 0x30 274256056Sgrehan#define AHCI_P_SACT 0x34 275256056Sgrehan#define AHCI_P_CI 0x38 276256056Sgrehan#define AHCI_P_SNTF 0x3C 277256056Sgrehan#define AHCI_P_FBS 0x40 278256056Sgrehan#define AHCI_P_FBS_EN 0x00000001 279256056Sgrehan#define AHCI_P_FBS_DEC 0x00000002 280256056Sgrehan#define AHCI_P_FBS_SDE 0x00000004 281256056Sgrehan#define AHCI_P_FBS_DEV 0x00000f00 282256056Sgrehan#define AHCI_P_FBS_DEV_SHIFT 8 283256056Sgrehan#define AHCI_P_FBS_ADO 0x0000f000 284256056Sgrehan#define AHCI_P_FBS_ADO_SHIFT 12 285256056Sgrehan#define AHCI_P_FBS_DWE 0x000f0000 286256056Sgrehan#define AHCI_P_FBS_DWE_SHIFT 16 287256056Sgrehan 288256056Sgrehan/* Just to be sure, if building as module. */ 289256056Sgrehan#if MAXPHYS < 512 * 1024 290256056Sgrehan#undef MAXPHYS 291256056Sgrehan#define MAXPHYS 512 * 1024 292256056Sgrehan#endif 293256056Sgrehan/* Pessimistic prognosis on number of required S/G entries */ 294256056Sgrehan#define AHCI_SG_ENTRIES (roundup(btoc(MAXPHYS) + 1, 8)) 295256056Sgrehan/* Command list. 32 commands. First, 1Kbyte aligned. */ 296256056Sgrehan#define AHCI_CL_OFFSET 0 297256056Sgrehan#define AHCI_CL_SIZE 32 298256056Sgrehan/* Command tables. Up to 32 commands, Each, 128byte aligned. */ 299256056Sgrehan#define AHCI_CT_OFFSET (AHCI_CL_OFFSET + AHCI_CL_SIZE * AHCI_MAX_SLOTS) 300256056Sgrehan#define AHCI_CT_SIZE (128 + AHCI_SG_ENTRIES * 16) 301256056Sgrehan/* Total main work area. */ 302256056Sgrehan#define AHCI_WORK_SIZE (AHCI_CT_OFFSET + AHCI_CT_SIZE * ch->numslots) 303256056Sgrehan 304256056Sgrehan#endif /* _AHCI_H_ */ 305