1251767Sgibbs/****************************************************************************** 2251767Sgibbs * arch-arm.h 3251767Sgibbs * 4251767Sgibbs * Guest OS interface to ARM Xen. 5251767Sgibbs * 6251767Sgibbs * Permission is hereby granted, free of charge, to any person obtaining a copy 7251767Sgibbs * of this software and associated documentation files (the "Software"), to 8251767Sgibbs * deal in the Software without restriction, including without limitation the 9251767Sgibbs * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 10251767Sgibbs * sell copies of the Software, and to permit persons to whom the Software is 11251767Sgibbs * furnished to do so, subject to the following conditions: 12251767Sgibbs * 13251767Sgibbs * The above copyright notice and this permission notice shall be included in 14251767Sgibbs * all copies or substantial portions of the Software. 15251767Sgibbs * 16251767Sgibbs * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17251767Sgibbs * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18251767Sgibbs * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19251767Sgibbs * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20251767Sgibbs * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21251767Sgibbs * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22251767Sgibbs * DEALINGS IN THE SOFTWARE. 23251767Sgibbs * 24251767Sgibbs * Copyright 2011 (C) Citrix Systems 25251767Sgibbs */ 26251767Sgibbs 27251767Sgibbs#ifndef __XEN_PUBLIC_ARCH_ARM_H__ 28251767Sgibbs#define __XEN_PUBLIC_ARCH_ARM_H__ 29251767Sgibbs 30251767Sgibbs/* hypercall calling convention 31251767Sgibbs * ---------------------------- 32251767Sgibbs * 33251767Sgibbs * A hypercall is issued using the ARM HVC instruction. 34251767Sgibbs * 35251767Sgibbs * A hypercall can take up to 5 arguments. These are passed in 36251767Sgibbs * registers, the first argument in r0, the second argument in r1, the 37251767Sgibbs * third in r2, the forth in r3 and the fifth in r4. 38251767Sgibbs * 39251767Sgibbs * The hypercall number is passed in r12. 40251767Sgibbs * 41251767Sgibbs * The HVC ISS must contain a Xen specific TAG: XEN_HYPERCALL_TAG. 42251767Sgibbs * 43251767Sgibbs * The return value is in r0. 44251767Sgibbs * 45251767Sgibbs * The hypercall will clobber r12 and the argument registers used by 46251767Sgibbs * that hypercall (except r0 which is the return value) i.e. a 2 47251767Sgibbs * argument hypercall will clobber r1 and a 4 argument hypercall will 48251767Sgibbs * clobber r1, r2 and r3. 49251767Sgibbs * 50251767Sgibbs */ 51251767Sgibbs 52251767Sgibbs#define XEN_HYPERCALL_TAG 0XEA1 53251767Sgibbs 54251767Sgibbs 55251767Sgibbs#ifndef __ASSEMBLY__ 56251767Sgibbs#define ___DEFINE_XEN_GUEST_HANDLE(name, type) \ 57251767Sgibbs typedef struct { type *p; } __guest_handle_ ## name 58251767Sgibbs 59251767Sgibbs#define __DEFINE_XEN_GUEST_HANDLE(name, type) \ 60251767Sgibbs ___DEFINE_XEN_GUEST_HANDLE(name, type); \ 61251767Sgibbs ___DEFINE_XEN_GUEST_HANDLE(const_##name, const type) 62251767Sgibbs#define DEFINE_XEN_GUEST_HANDLE(name) __DEFINE_XEN_GUEST_HANDLE(name, name) 63251767Sgibbs#define __XEN_GUEST_HANDLE(name) __guest_handle_ ## name 64251767Sgibbs#define XEN_GUEST_HANDLE(name) __XEN_GUEST_HANDLE(name) 65251767Sgibbs#define set_xen_guest_handle_raw(hnd, val) do { (hnd).p = val; } while (0) 66251767Sgibbs#ifdef __XEN_TOOLS__ 67251767Sgibbs#define get_xen_guest_handle(val, hnd) do { val = (hnd).p; } while (0) 68251767Sgibbs#endif 69251767Sgibbs#define set_xen_guest_handle(hnd, val) set_xen_guest_handle_raw(hnd, val) 70251767Sgibbs 71251767Sgibbsstruct cpu_user_regs 72251767Sgibbs{ 73251767Sgibbs uint32_t r0; 74251767Sgibbs uint32_t r1; 75251767Sgibbs uint32_t r2; 76251767Sgibbs uint32_t r3; 77251767Sgibbs uint32_t r4; 78251767Sgibbs uint32_t r5; 79251767Sgibbs uint32_t r6; 80251767Sgibbs uint32_t r7; 81251767Sgibbs uint32_t r8; 82251767Sgibbs uint32_t r9; 83251767Sgibbs uint32_t r10; 84251767Sgibbs union { 85251767Sgibbs uint32_t r11; 86251767Sgibbs uint32_t fp; 87251767Sgibbs }; 88251767Sgibbs uint32_t r12; 89251767Sgibbs 90251767Sgibbs uint32_t sp; /* r13 - SP: Valid for Hyp. frames only, o/w banked (see below) */ 91251767Sgibbs 92251767Sgibbs /* r14 - LR: is the same physical register as LR_usr */ 93251767Sgibbs union { 94251767Sgibbs uint32_t lr; /* r14 - LR: Valid for Hyp. Same physical register as lr_usr. */ 95251767Sgibbs uint32_t lr_usr; 96251767Sgibbs }; 97251767Sgibbs 98251767Sgibbs uint32_t pc; /* Return IP */ 99251767Sgibbs uint32_t cpsr; /* Return mode */ 100251767Sgibbs uint32_t pad0; /* Doubleword-align the kernel half of the frame */ 101251767Sgibbs 102251767Sgibbs /* Outer guest frame only from here on... */ 103251767Sgibbs 104251767Sgibbs uint32_t r8_fiq, r9_fiq, r10_fiq, r11_fiq, r12_fiq; 105251767Sgibbs 106251767Sgibbs uint32_t sp_usr; /* LR_usr is the same register as LR, see above */ 107251767Sgibbs 108251767Sgibbs uint32_t sp_svc, sp_abt, sp_und, sp_irq, sp_fiq; 109251767Sgibbs uint32_t lr_svc, lr_abt, lr_und, lr_irq, lr_fiq; 110251767Sgibbs 111251767Sgibbs uint32_t spsr_svc, spsr_abt, spsr_und, spsr_irq, spsr_fiq; 112251767Sgibbs 113251767Sgibbs uint32_t pad1; /* Doubleword-align the user half of the frame */ 114251767Sgibbs}; 115251767Sgibbstypedef struct cpu_user_regs cpu_user_regs_t; 116251767SgibbsDEFINE_XEN_GUEST_HANDLE(cpu_user_regs_t); 117251767Sgibbs 118251767Sgibbstypedef uint64_t xen_pfn_t; 119251767Sgibbs#define PRI_xen_pfn PRIx64 120251767Sgibbs 121251767Sgibbs/* Maximum number of virtual CPUs in legacy multi-processor guests. */ 122251767Sgibbs/* Only one. All other VCPUS must use VCPUOP_register_vcpu_info */ 123251767Sgibbs#define XEN_LEGACY_MAX_VCPUS 1 124251767Sgibbs 125251767Sgibbstypedef uint32_t xen_ulong_t; 126251767Sgibbs 127251767Sgibbsstruct vcpu_guest_context { 128251767Sgibbs struct cpu_user_regs user_regs; /* User-level CPU registers */ 129251767Sgibbs 130251767Sgibbs uint32_t sctlr; 131251767Sgibbs uint32_t ttbr0, ttbr1, ttbcr; 132251767Sgibbs}; 133251767Sgibbstypedef struct vcpu_guest_context vcpu_guest_context_t; 134251767SgibbsDEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t); 135251767Sgibbs 136251767Sgibbsstruct arch_vcpu_info { }; 137251767Sgibbstypedef struct arch_vcpu_info arch_vcpu_info_t; 138251767Sgibbs 139251767Sgibbsstruct arch_shared_info { }; 140251767Sgibbstypedef struct arch_shared_info arch_shared_info_t; 141251767Sgibbstypedef uint64_t xen_callback_t; 142251767Sgibbs 143251767Sgibbs#endif /* ifndef __ASSEMBLY __ */ 144251767Sgibbs 145251767Sgibbs/* PSR bits (CPSR, SPSR)*/ 146251767Sgibbs 147251767Sgibbs/* 0-4: Mode */ 148251767Sgibbs#define PSR_MODE_MASK 0x1f 149251767Sgibbs#define PSR_MODE_USR 0x10 150251767Sgibbs#define PSR_MODE_FIQ 0x11 151251767Sgibbs#define PSR_MODE_IRQ 0x12 152251767Sgibbs#define PSR_MODE_SVC 0x13 153251767Sgibbs#define PSR_MODE_MON 0x16 154251767Sgibbs#define PSR_MODE_ABT 0x17 155251767Sgibbs#define PSR_MODE_HYP 0x1a 156251767Sgibbs#define PSR_MODE_UND 0x1b 157251767Sgibbs#define PSR_MODE_SYS 0x1f 158251767Sgibbs 159251767Sgibbs#define PSR_THUMB (1<<5) /* Thumb Mode enable */ 160251767Sgibbs#define PSR_FIQ_MASK (1<<6) /* Fast Interrupt mask */ 161251767Sgibbs#define PSR_IRQ_MASK (1<<7) /* Interrupt mask */ 162251767Sgibbs#define PSR_ABT_MASK (1<<8) /* Asynchronous Abort mask */ 163251767Sgibbs#define PSR_BIG_ENDIAN (1<<9) /* Big Endian Mode */ 164251767Sgibbs#define PSR_JAZELLE (1<<24) /* Jazelle Mode */ 165251767Sgibbs 166251767Sgibbs#endif /* __XEN_PUBLIC_ARCH_ARM_H__ */ 167251767Sgibbs 168251767Sgibbs/* 169251767Sgibbs * Local variables: 170251767Sgibbs * mode: C 171251767Sgibbs * c-set-style: "BSD" 172251767Sgibbs * c-basic-offset: 4 173251767Sgibbs * tab-width: 4 174251767Sgibbs * indent-tabs-mode: nil 175251767Sgibbs * End: 176251767Sgibbs */ 177