1112399Sjake/*- 2112399Sjake * Copyright (c) 2003 Jake Burkholder. 3112399Sjake * All rights reserved. 4112399Sjake * 5112399Sjake * Redistribution and use in source and binary forms, with or without 6112399Sjake * modification, are permitted provided that the following conditions 7112399Sjake * are met: 8112399Sjake * 1. Redistributions of source code must retain the above copyright 9112399Sjake * notice, this list of conditions and the following disclaimer. 10112399Sjake * 2. Redistributions in binary form must reproduce the above copyright 11112399Sjake * notice, this list of conditions and the following disclaimer in the 12112399Sjake * documentation and/or other materials provided with the distribution. 13112399Sjake * 14112399Sjake * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15112399Sjake * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16112399Sjake * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17112399Sjake * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18112399Sjake * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19112399Sjake * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20112399Sjake * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21112399Sjake * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22112399Sjake * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23112399Sjake * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24112399Sjake * SUCH DAMAGE. 25112399Sjake */ 26112399Sjake 27176994Smarius#include <sys/cdefs.h> 28176994Smarius__FBSDID("$FreeBSD$"); 29176994Smarius 30112399Sjake#include "opt_pmap.h" 31112399Sjake 32112399Sjake#include <sys/param.h> 33181701Smarius#include <sys/systm.h> 34112399Sjake#include <sys/lock.h> 35112399Sjake#include <sys/mutex.h> 36112399Sjake#include <sys/smp.h> 37112399Sjake#include <sys/sysctl.h> 38112399Sjake 39112399Sjake#include <vm/vm.h> 40112399Sjake#include <vm/pmap.h> 41112399Sjake 42112399Sjake#include <machine/cache.h> 43112399Sjake#include <machine/cpufunc.h> 44122464Sjake#include <machine/lsu.h> 45112399Sjake#include <machine/smp.h> 46113453Sjake#include <machine/tlb.h> 47112399Sjake 48113453Sjake#define SPITFIRE_TLB_ENTRIES 64 49113453Sjake 50112399SjakePMAP_STATS_VAR(spitfire_dcache_npage_inval); 51112399SjakePMAP_STATS_VAR(spitfire_dcache_npage_inval_match); 52112399SjakePMAP_STATS_VAR(spitfire_icache_npage_inval); 53112399SjakePMAP_STATS_VAR(spitfire_icache_npage_inval_match); 54112399Sjake 55112399Sjake/* 56122464Sjake * Enable the level 1 caches. 57122464Sjake */ 58122464Sjakevoid 59204152Smariusspitfire_cache_enable(u_int cpu_impl __unused) 60122464Sjake{ 61122464Sjake u_long lsu; 62122464Sjake 63122464Sjake lsu = ldxa(0, ASI_LSU_CTL_REG); 64122464Sjake stxa_sync(0, ASI_LSU_CTL_REG, lsu | LSU_IC | LSU_DC); 65122464Sjake} 66122464Sjake 67122464Sjake/* 68122464Sjake * Flush all lines from the level 1 caches. 69122464Sjake */ 70122464Sjakevoid 71122464Sjakespitfire_cache_flush(void) 72122464Sjake{ 73122464Sjake u_long addr; 74122464Sjake 75182689Smarius for (addr = 0; addr < PCPU_GET(cache.dc_size); 76182689Smarius addr += PCPU_GET(cache.dc_linesize)) 77122464Sjake stxa_sync(addr, ASI_DCACHE_TAG, 0); 78182689Smarius for (addr = 0; addr < PCPU_GET(cache.ic_size); 79182689Smarius addr += PCPU_GET(cache.ic_linesize)) 80122464Sjake stxa_sync(addr, ASI_ICACHE_TAG, 0); 81122464Sjake} 82122464Sjake 83122464Sjake/* 84112399Sjake * Flush a physical page from the data cache. 85112399Sjake */ 86112399Sjakevoid 87113238Sjakespitfire_dcache_page_inval(vm_paddr_t pa) 88112399Sjake{ 89112399Sjake u_long target; 90112399Sjake void *cookie; 91112399Sjake u_long addr; 92112399Sjake u_long tag; 93112399Sjake 94181701Smarius KASSERT((pa & PAGE_MASK) == 0, ("%s: pa not page aligned", __func__)); 95112399Sjake PMAP_STATS_INC(spitfire_dcache_npage_inval); 96112399Sjake target = pa >> (PAGE_SHIFT - DC_TAG_SHIFT); 97112399Sjake cookie = ipi_dcache_page_inval(tl_ipi_spitfire_dcache_page_inval, pa); 98182689Smarius for (addr = 0; addr < PCPU_GET(cache.dc_size); 99182689Smarius addr += PCPU_GET(cache.dc_linesize)) { 100112399Sjake tag = ldxa(addr, ASI_DCACHE_TAG); 101112399Sjake if (((tag >> DC_VALID_SHIFT) & DC_VALID_MASK) == 0) 102112399Sjake continue; 103112399Sjake tag &= DC_TAG_MASK << DC_TAG_SHIFT; 104112399Sjake if (tag == target) { 105112399Sjake PMAP_STATS_INC(spitfire_dcache_npage_inval_match); 106112399Sjake stxa_sync(addr, ASI_DCACHE_TAG, tag); 107112399Sjake } 108112399Sjake } 109112399Sjake ipi_wait(cookie); 110112399Sjake} 111112399Sjake 112112399Sjake/* 113112399Sjake * Flush a physical page from the instruction cache. 114112399Sjake */ 115112399Sjakevoid 116113238Sjakespitfire_icache_page_inval(vm_paddr_t pa) 117112399Sjake{ 118112399Sjake register u_long tag __asm("%g1"); 119112399Sjake u_long target; 120112399Sjake void *cookie; 121112399Sjake u_long addr; 122112399Sjake 123181701Smarius KASSERT((pa & PAGE_MASK) == 0, ("%s: pa not page aligned", __func__)); 124112399Sjake PMAP_STATS_INC(spitfire_icache_npage_inval); 125112399Sjake target = pa >> (PAGE_SHIFT - IC_TAG_SHIFT); 126112399Sjake cookie = ipi_icache_page_inval(tl_ipi_spitfire_icache_page_inval, pa); 127182689Smarius for (addr = 0; addr < PCPU_GET(cache.ic_size); 128182689Smarius addr += PCPU_GET(cache.ic_linesize)) { 129112399Sjake __asm __volatile("ldda [%1] %2, %%g0" /*, %g1 */ 130112399Sjake : "=r" (tag) : "r" (addr), "n" (ASI_ICACHE_TAG)); 131112399Sjake if (((tag >> IC_VALID_SHIFT) & IC_VALID_MASK) == 0) 132112399Sjake continue; 133262620Sdim tag &= (u_long)IC_TAG_MASK << IC_TAG_SHIFT; 134112399Sjake if (tag == target) { 135112399Sjake PMAP_STATS_INC(spitfire_icache_npage_inval_match); 136112399Sjake stxa_sync(addr, ASI_ICACHE_TAG, tag); 137112399Sjake } 138112399Sjake } 139112399Sjake ipi_wait(cookie); 140112399Sjake} 141113453Sjake 142113453Sjake/* 143223719Smarius * Flush all non-locked mappings from the TLBs. 144113453Sjake */ 145113453Sjakevoid 146176994Smariusspitfire_tlb_flush_nonlocked(void) 147176994Smarius{ 148223719Smarius u_int i; 149223719Smarius u_int slot; 150176994Smarius 151176994Smarius for (i = 0; i < SPITFIRE_TLB_ENTRIES; i++) { 152223719Smarius slot = TLB_DAR_SLOT(TLB_DAR_T32, i); 153223719Smarius if ((ldxa(slot, ASI_DTLB_DATA_ACCESS_REG) & TD_L) == 0) 154223719Smarius stxa_sync(slot, ASI_DTLB_DATA_ACCESS_REG, 0); 155223719Smarius if ((ldxa(slot, ASI_ITLB_DATA_ACCESS_REG) & TD_L) == 0) 156223719Smarius stxa_sync(slot, ASI_ITLB_DATA_ACCESS_REG, 0); 157176994Smarius } 158176994Smarius} 159176994Smarius 160176994Smarius/* 161223719Smarius * Flush all user mappings from the TLBs. 162176994Smarius */ 163176994Smariusvoid 164113453Sjakespitfire_tlb_flush_user(void) 165113453Sjake{ 166113453Sjake u_long data; 167113453Sjake u_long tag; 168223719Smarius u_int i; 169223719Smarius u_int slot; 170113453Sjake 171113453Sjake for (i = 0; i < SPITFIRE_TLB_ENTRIES; i++) { 172223719Smarius slot = TLB_DAR_SLOT(TLB_DAR_T32, i); 173223719Smarius data = ldxa(slot, ASI_DTLB_DATA_ACCESS_REG); 174223719Smarius tag = ldxa(slot, ASI_DTLB_TAG_READ_REG); 175113453Sjake if ((data & TD_V) != 0 && (data & TD_L) == 0 && 176113453Sjake TLB_TAR_CTX(tag) != TLB_CTX_KERNEL) 177223719Smarius stxa_sync(slot, ASI_DTLB_DATA_ACCESS_REG, 0); 178223719Smarius data = ldxa(slot, ASI_ITLB_DATA_ACCESS_REG); 179223719Smarius tag = ldxa(slot, ASI_ITLB_TAG_READ_REG); 180113453Sjake if ((data & TD_V) != 0 && (data & TD_L) == 0 && 181113453Sjake TLB_TAR_CTX(tag) != TLB_CTX_KERNEL) 182223719Smarius stxa_sync(slot, ASI_ITLB_DATA_ACCESS_REG, 0); 183113453Sjake } 184113453Sjake} 185