180708Sjake/*- 282899Sjake * Copyright (c) 1990 The Regents of the University of California. 380708Sjake * All rights reserved. 482899Sjake * Copyright (c) 1994 John S. Dyson 582899Sjake * All rights reserved. 680708Sjake * 782899Sjake * This code is derived from software contributed to Berkeley by 882899Sjake * William Jolitz. 982899Sjake * 1080708Sjake * Redistribution and use in source and binary forms, with or without 1180708Sjake * modification, are permitted provided that the following conditions 1280708Sjake * are met: 1380708Sjake * 1. Redistributions of source code must retain the above copyright 1480708Sjake * notice, this list of conditions and the following disclaimer. 1580708Sjake * 2. Redistributions in binary form must reproduce the above copyright 1680708Sjake * notice, this list of conditions and the following disclaimer in the 1780708Sjake * documentation and/or other materials provided with the distribution. 1882899Sjake * 4. Neither the name of the University nor the names of its contributors 1982899Sjake * may be used to endorse or promote products derived from this software 2082899Sjake * without specific prior written permission. 2180708Sjake * 2282899Sjake * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 2380708Sjake * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2480708Sjake * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2582899Sjake * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 2680708Sjake * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2780708Sjake * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2880708Sjake * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2980708Sjake * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 3080708Sjake * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 3180708Sjake * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 3280708Sjake * SUCH DAMAGE. 3380708Sjake * 3482899Sjake * from: @(#)vmparam.h 5.9 (Berkeley) 5/12/91 3582899Sjake * from: FreeBSD: src/sys/i386/include/vmparam.h,v 1.33 2000/03/30 3680708Sjake * $FreeBSD$ 3780708Sjake */ 3880708Sjake 3980708Sjake#ifndef _MACHINE_VMPARAM_H_ 4080708Sjake#define _MACHINE_VMPARAM_H_ 4180708Sjake 4280708Sjake/* 4380708Sjake * Virtual memory related constants, all in bytes 4480708Sjake */ 4580708Sjake#ifndef MAXTSIZ 4680708Sjake#define MAXTSIZ (1*1024*1024*1024) /* max text size */ 4780708Sjake#endif 4880708Sjake#ifndef DFLDSIZ 4980708Sjake#define DFLDSIZ (128*1024*1024) /* initial data size limit */ 5080708Sjake#endif 5180708Sjake#ifndef MAXDSIZ 5280708Sjake#define MAXDSIZ (1*1024*1024*1024) /* max data size */ 5380708Sjake#endif 5480708Sjake#ifndef DFLSSIZ 5580708Sjake#define DFLSSIZ (128*1024*1024) /* initial stack size limit */ 5680708Sjake#endif 5780708Sjake#ifndef MAXSSIZ 5880708Sjake#define MAXSSIZ (1*1024*1024*1024) /* max stack size */ 5980708Sjake#endif 6080708Sjake#ifndef SGROWSIZ 6180708Sjake#define SGROWSIZ (128*1024) /* amount to grow stack */ 6280708Sjake#endif 6380708Sjake 6480708Sjake/* 65169291Salc * The physical address space is sparsely populated. 66169291Salc */ 67169291Salc#define VM_PHYSSEG_SPARSE 68169291Salc 69169291Salc/* 70170262Salc * The number of PHYSSEG entries must be one greater than the number 71170262Salc * of phys_avail entries because the phys_avail entry that spans the 72170262Salc * largest physical address that is accessible by ISA DMA is split 73223379Smarius * into two PHYSSEG entries. 74170262Salc */ 75170262Salc#define VM_PHYSSEG_MAX 64 76170262Salc 77170262Salc/* 78172317Salc * Create three free page pools: VM_FREEPOOL_DEFAULT is the default pool 79170262Salc * from which physical pages are allocated and VM_FREEPOOL_DIRECT is 80170262Salc * the pool from which physical pages for small UMA objects are 81170262Salc * allocated. 82170262Salc */ 83172317Salc#define VM_NFREEPOOL 3 84172317Salc#define VM_FREEPOOL_CACHE 2 85170262Salc#define VM_FREEPOOL_DEFAULT 0 86170262Salc#define VM_FREEPOOL_DIRECT 1 87170262Salc 88170262Salc/* 89170262Salc * Create two free page lists: VM_FREELIST_DEFAULT is for physical 90170262Salc * pages that are above the largest physical address that is 91170262Salc * accessible by ISA DMA and VM_FREELIST_ISADMA is for physical pages 92170262Salc * that are below that address. 93170262Salc */ 94170262Salc#define VM_NFREELIST 2 95170262Salc#define VM_FREELIST_DEFAULT 0 96170262Salc#define VM_FREELIST_ISADMA 1 97170262Salc 98170262Salc/* 99170262Salc * An allocation size of 16MB is supported in order to optimize the 100170262Salc * use of the direct map by UMA. Specifically, a cache line contains 101170262Salc * at most four TTEs, collectively mapping 16MB of physical memory. 102170262Salc * By reducing the number of distinct 16MB "pages" that are used by UMA, 103170262Salc * the physical memory allocator reduces the likelihood of both 4MB 104170262Salc * page TLB misses and cache misses caused by 4MB page TLB misses. 105170262Salc */ 106170262Salc#define VM_NFREEORDER 12 107170262Salc 108170262Salc/* 109215093Salc * Enable superpage reservations: 1 level. 110174938Salc */ 111174938Salc#ifndef VM_NRESERVLEVEL 112215093Salc#define VM_NRESERVLEVEL 1 113174938Salc#endif 114174938Salc 115174938Salc/* 116215093Salc * Level 0 reservations consist of 512 pages. 117215093Salc */ 118215093Salc#ifndef VM_LEVEL_0_ORDER 119215093Salc#define VM_LEVEL_0_ORDER 9 120215093Salc#endif 121215093Salc 122240190Sgavin/** 123108245Sjake * Address space layout. 124108245Sjake * 125108245Sjake * UltraSPARC I and II implement a 44 bit virtual address space. The address 126108245Sjake * space is split into 2 regions at each end of the 64 bit address space, with 127108245Sjake * an out of range "hole" in the middle. UltraSPARC III implements the full 128108245Sjake * 64 bit virtual address space, but we don't really have any use for it and 129108245Sjake * 43 bits of user address space is considered to be "enough", so we ignore it. 130108245Sjake * 131108245Sjake * Upper region: 0xffffffffffffffff 132223379Smarius * 0xfffff80000000000 133223379Smarius * 134108245Sjake * Hole: 0xfffff7ffffffffff 135223379Smarius * 0x0000080000000000 136108245Sjake * 137108245Sjake * Lower region: 0x000007ffffffffff 138223379Smarius * 0x0000000000000000 139108245Sjake * 140108245Sjake * In general we ignore the upper region, and use the lower region as mappable 141108245Sjake * space. 142108245Sjake * 143108245Sjake * We define some interesting address constants: 144108245Sjake * 145246554Skib * VM_MIN_ADDRESS and VM_MAX_ADDRESS define the start and end of the entire 146246554Skib * 64 bit address space, mostly just for convenience. 147108245Sjake * 148108245Sjake * VM_MIN_DIRECT_ADDRESS and VM_MAX_DIRECT_ADDRESS define the start and end 149108245Sjake * of the direct mapped region. This maps virtual addresses to physical 150108245Sjake * addresses directly using 4mb tlb entries, with the physical address encoded 151108245Sjake * in the lower 43 bits of virtual address. These mappings are convenient 152108245Sjake * because they do not require page tables, and because they never change they 153108245Sjake * do not require tlb flushes. However, since these mappings are cacheable, 154108245Sjake * we must ensure that all pages accessed this way are either not double 155108245Sjake * mapped, or that all other mappings have virtual color equal to physical 156108245Sjake * color, in order to avoid creating illegal aliases in the data cache. 157108245Sjake * 158108245Sjake * VM_MIN_KERNEL_ADDRESS and VM_MAX_KERNEL_ADDRESS define the start and end of 159108245Sjake * mappable kernel virtual address space. VM_MIN_KERNEL_ADDRESS is basically 160108245Sjake * arbitrary, a convenient address is chosen which allows both the kernel text 161108245Sjake * and data and the prom's address space to be mapped with 1 4mb tsb page. 162108245Sjake * VM_MAX_KERNEL_ADDRESS is variable, computed at startup time based on the 163108245Sjake * amount of physical memory available. Each 4mb tsb page provides 1g of 164108245Sjake * virtual address space, with the only practical limit being available 165108245Sjake * phsyical memory. 166108245Sjake * 167108245Sjake * VM_MIN_PROM_ADDRESS and VM_MAX_PROM_ADDRESS define the start and end of the 168108245Sjake * prom address space. On startup the prom's mappings are duplicated in the 169108245Sjake * kernel tsb, to allow prom memory to be accessed normally by the kernel. 170108245Sjake * 171108245Sjake * VM_MIN_USER_ADDRESS and VM_MAX_USER_ADDRESS define the start and end of the 172108245Sjake * user address space. There are some hardware errata about using addresses 173108245Sjake * at the boundary of the va hole, so we allow just under 43 bits of user 174108245Sjake * address space. Note that the kernel and user address spaces overlap, but 175108245Sjake * this doesn't matter because they use different tlb contexts, and because 176108245Sjake * the kernel address space is not mapped into each process' address space. 17788653Sjake */ 178108245Sjake#define VM_MIN_ADDRESS (0x0000000000000000UL) 179108245Sjake#define VM_MAX_ADDRESS (0xffffffffffffffffUL) 18080708Sjake 181108245Sjake#define VM_MIN_DIRECT_ADDRESS (0xfffff80000000000UL) 182108245Sjake#define VM_MAX_DIRECT_ADDRESS (VM_MAX_ADDRESS) 18388653Sjake 184108245Sjake#define VM_MIN_KERNEL_ADDRESS (0x00000000c0000000UL) 185108245Sjake#define VM_MAX_KERNEL_ADDRESS (vm_max_kernel_address) 18680708Sjake 187108245Sjake#define VM_MIN_PROM_ADDRESS (0x00000000f0000000UL) 188181642Smarius#define VM_MAX_PROM_ADDRESS (0x00000000ffffffffUL) 189108245Sjake 190108245Sjake#define VM_MIN_USER_ADDRESS (0x0000000000000000UL) 191108245Sjake#define VM_MAX_USER_ADDRESS (0x000007fe00000000UL) 192108245Sjake 193108245Sjake#define VM_MINUSER_ADDRESS (VM_MIN_USER_ADDRESS) 194108245Sjake#define VM_MAXUSER_ADDRESS (VM_MAX_USER_ADDRESS) 195108245Sjake 196108245Sjake#define KERNBASE (VM_MIN_KERNEL_ADDRESS) 197188455Smarius#define PROMBASE (VM_MIN_PROM_ADDRESS) 198108245Sjake#define USRSTACK (VM_MAX_USER_ADDRESS) 199108245Sjake 20080708Sjake/* 201266204Sian * How many physical pages per kmem arena virtual page. 20280708Sjake */ 203266204Sian#ifndef VM_KMEM_SIZE_SCALE 204266204Sian#define VM_KMEM_SIZE_SCALE (tsb_kernel_ldd_phys == 0 ? 3 : 2) 20580708Sjake#endif 20680708Sjake 20785241Sjake/* 208266204Sian * Optional floor (in bytes) on the size of the kmem arena. 20991974Sjake */ 210266204Sian#ifndef VM_KMEM_SIZE_MIN 211266204Sian#define VM_KMEM_SIZE_MIN (16 * 1024 * 1024) 21291974Sjake#endif 21391974Sjake 21491974Sjake/* 215266204Sian * Optional ceiling (in bytes) on the size of the kmem arena: 60% of the 216266204Sian * kernel map. 217216016Sfjoe */ 218216016Sfjoe#ifndef VM_KMEM_SIZE_MAX 219216625Smarius#define VM_KMEM_SIZE_MAX ((VM_MAX_KERNEL_ADDRESS - \ 220216625Smarius VM_MIN_KERNEL_ADDRESS + 1) * 3 / 5) 221216016Sfjoe#endif 222216016Sfjoe 223216016Sfjoe/* 22480708Sjake * Initial pagein size of beginning of executable file. 22580708Sjake */ 22680708Sjake#ifndef VM_INITIAL_PAGEIN 22780708Sjake#define VM_INITIAL_PAGEIN 16 22880708Sjake#endif 22980708Sjake 230108332Sjake#define UMA_MD_SMALL_ALLOC 231108332Sjake 232223378Smariusextern u_int tsb_kernel_ldd_phys; 233101653Sjakeextern vm_offset_t vm_max_kernel_address; 234101653Sjake 235221855Smdf/* 236221855Smdf * Older sparc64 machines have a virtually indexed L1 data cache of 16KB. 237221855Smdf * Consequently, mapping the same physical page multiple times may have 238221855Smdf * caching disabled. 239221855Smdf */ 240221855Smdf#define ZERO_REGION_SIZE PAGE_SIZE 241221855Smdf 24280708Sjake#endif /* !_MACHINE_VMPARAM_H_ */ 243