143166Snsouch/*- 243166Snsouch * Copyright (c) 1998, 1999 Takanori Watanabe 343166Snsouch * All rights reserved. 443166Snsouch * 543166Snsouch * Redistribution and use in source and binary forms, with or without 643166Snsouch * modification, are permitted provided that the following conditions 743166Snsouch * are met: 843166Snsouch * 1. Redistributions of source code must retain the above copyright 943166Snsouch * notice, this list of conditions and the following disclaimer. 1043166Snsouch * 2. Redistributions in binary form must reproduce the above copyright 1143166Snsouch * notice, this list of conditions and the following disclaimer in the 1243166Snsouch * documentation and/or other materials provided with the distribution. 1343166Snsouch * 1443166Snsouch * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1543166Snsouch * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1643166Snsouch * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1743166Snsouch * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1843166Snsouch * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1943166Snsouch * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2043166Snsouch * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2143166Snsouch * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2243166Snsouch * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2343166Snsouch * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2443166Snsouch * SUCH DAMAGE. 2543166Snsouch * 2650477Speter * $FreeBSD$ 2743166Snsouch */ 2843166Snsouch 29162289Sjhb#ifndef __INTPMREG_H__ 30162289Sjhb#define __INTPMREG_H__ 31162289Sjhb 32162289Sjhb/* Register definitions for non-ICH Intel Chipset SMBUS controllers. */ 33162289Sjhb 34162289Sjhb/* PCI Config Registers. */ 35162289Sjhb#define PCI_BASE_ADDR_SMB 0x90 /* IO BAR. */ 36162289Sjhb#define PCI_BASE_ADDR_PM 0x40 37165951Sjhb#define PCI_HST_CFG_SMB 0xd2 /* Host Configuration */ 38197128Savg#define PCI_INTR_SMB_MASK 0xe 39162289Sjhb#define PCI_INTR_SMB_SMI 0 40197128Savg#define PCI_INTR_SMB_IRQ_PCI 2 41162289Sjhb#define PCI_INTR_SMB_IRQ9 8 42162289Sjhb#define PCI_INTR_SMB_ENABLE 1 43162289Sjhb#define PCI_SLV_CMD_SMB 0xd3 /*SLAVE COMMAND*/ 44162289Sjhb#define PCI_SLV_SDW_SMB_1 0xd4 /*SLAVE SHADOW PORT 1*/ 45162289Sjhb#define PCI_SLV_SDW_SMB_2 0xd5 /*SLAVE SHADOW PORT 2*/ 46162289Sjhb#define PCI_REVID_SMB 0xd6 47162289Sjhb 48162289Sjhb/* PIXX4 SMBus Registers in the SMB BAR. */ 49162289Sjhb#define PIIX4_SMBHSTSTS 0x00 50162289Sjhb#define PIIX4_SMBHSTSTAT_BUSY (1<<0) 51162289Sjhb#define PIIX4_SMBHSTSTAT_INTR (1<<1) 52162289Sjhb#define PIIX4_SMBHSTSTAT_ERR (1<<2) 53162289Sjhb#define PIIX4_SMBHSTSTAT_BUSC (1<<3) 54162289Sjhb#define PIIX4_SMBHSTSTAT_FAIL (1<<4) 55162289Sjhb#define PIIX4_SMBSLVSTS 0x01 56162289Sjhb#define PIIX4_SMBSLVSTS_ALART (1<<5) 57162289Sjhb#define PIIX4_SMBSLVSTS_SDW2 (1<<4) 58162289Sjhb#define PIIX4_SMBSLVSTS_SDW1 (1<<3) 59162289Sjhb#define PIIX4_SMBSLVSTS_SLV (1<<2) 60162289Sjhb#define PIIX4_SMBSLVSTS_BUSY (1<<0) 61162289Sjhb#define PIIX4_SMBHSTCNT 0x02 62162289Sjhb#define PIIX4_SMBHSTCNT_START (1<<6) 63162289Sjhb#define PIIX4_SMBHSTCNT_PROT_QUICK 0 64162289Sjhb#define PIIX4_SMBHSTCNT_PROT_BYTE (1<<2) 65162289Sjhb#define PIIX4_SMBHSTCNT_PROT_BDATA (2<<2) 66162289Sjhb#define PIIX4_SMBHSTCNT_PROT_WDATA (3<<2) 67162289Sjhb#define PIIX4_SMBHSTCNT_PROT_BLOCK (5<<2) 68162289Sjhb#define PIIX4_SMBHSTCNT_KILL (1<<1) 69162289Sjhb#define PIIX4_SMBHSTCNT_INTREN (1) 70162289Sjhb#define PIIX4_SMBHSTCMD 0x03 71162289Sjhb#define PIIX4_SMBHSTADD 0x04 72162289Sjhb#define LSB 0x1 73162289Sjhb#define PIIX4_SMBHSTDAT0 0x05 74162289Sjhb#define PIIX4_SMBHSTDAT1 0x06 75162289Sjhb#define PIIX4_SMBBLKDAT 0x07 76162289Sjhb#define PIIX4_SMBSLVCNT 0x08 77162289Sjhb#define PIIX4_SMBSLVCNT_ALTEN (1<<3) 78162289Sjhb#define PIIX4_SMBSLVCNT_SD2EN (1<<2) 79162289Sjhb#define PIIX4_SMBSLVCNT_SD1EN (1<<1) 80162289Sjhb#define PIIX4_SMBSLVCNT_SLVEN (1) 81162289Sjhb#define PIIX4_SMBSLVCMD 0x09 82162289Sjhb#define PIIX4_SMBSLVEVT 0x0a 83162289Sjhb#define PIIX4_SMBSLVDAT 0x0c 84162289Sjhb 85162289Sjhb/* SMBus alert response address. */ 86162289Sjhb#define SMBALTRESP 0x18 87162289Sjhb 88162289Sjhb#define SMBBLOCKTRANS_MAX 32 89162289Sjhb 90162289Sjhb#endif /* !__INTPMREG_H__ */ 91