1178172Simp/*	$OpenBSD: regnum.h,v 1.3 1999/01/27 04:46:06 imp Exp $	*/
2178172Simp
3178172Simp/*-
4178172Simp * Copyright (c) 1988 University of Utah.
5178172Simp * Copyright (c) 1992, 1993
6178172Simp *	The Regents of the University of California.  All rights reserved.
7178172Simp *
8178172Simp * This code is derived from software contributed to Berkeley by
9178172Simp * the Systems Programming Group of the University of Utah Computer
10178172Simp * Science Department and Ralph Campbell.
11178172Simp *
12178172Simp * Redistribution and use in source and binary forms, with or without
13178172Simp * modification, are permitted provided that the following conditions
14178172Simp * are met:
15178172Simp * 1. Redistributions of source code must retain the above copyright
16178172Simp *    notice, this list of conditions and the following disclaimer.
17178172Simp * 2. Redistributions in binary form must reproduce the above copyright
18178172Simp *    notice, this list of conditions and the following disclaimer in the
19178172Simp *    documentation and/or other materials provided with the distribution.
20178172Simp * 4. Neither the name of the University nor the names of its contributors
21178172Simp *    may be used to endorse or promote products derived from this software
22178172Simp *    without specific prior written permission.
23178172Simp *
24178172Simp * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25178172Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26178172Simp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27178172Simp * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28178172Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29178172Simp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30178172Simp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31178172Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32178172Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33178172Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34178172Simp * SUCH DAMAGE.
35178172Simp *
36178172Simp *	from: Utah Hdr: reg.h 1.1 90/07/09
37178172Simp *	@(#)reg.h	8.2 (Berkeley) 1/11/94
38178172Simp *	JNPR: regnum.h,v 1.6 2007/08/09 11:23:32 katta
39178172Simp * $FreeBSD$
40178172Simp */
41178172Simp
42178172Simp#ifndef _MACHINE_REGNUM_H_
43178172Simp#define	_MACHINE_REGNUM_H_
44178172Simp
45249523Simp/*
46178172Simp * Location of the saved registers relative to ZERO.
47178172Simp * This must match struct trapframe defined in frame.h exactly.
48249523Simp * This must also match regdef.h.
49178172Simp */
50178172Simp#define	ZERO	0
51178172Simp#define	AST	1
52178172Simp#define	V0	2
53178172Simp#define	V1	3
54178172Simp#define	A0	4
55178172Simp#define	A1	5
56178172Simp#define	A2	6
57178172Simp#define	A3	7
58249523Simp#if defined(__mips_n32) || defined(__mips_n64)
59249523Simp#define	A4	8
60249523Simp#define	A5	9
61249523Simp#define	A6	10
62249523Simp#define	A7	11
63249523Simp#define	T0	12
64249523Simp#define	T1	13
65249523Simp#define	T2	14
66249523Simp#define	T3	15
67249523Simp#else
68178172Simp#define	T0	8
69178172Simp#define	T1	9
70178172Simp#define	T2	10
71178172Simp#define	T3	11
72249790Simp#define	T4	12
73249790Simp#define	T5	13
74249790Simp#define	T6	14
75249790Simp#define	T7	15
76249523Simp#endif
77178172Simp#define	S0	16
78178172Simp#define	S1	17
79178172Simp#define	S2	18
80178172Simp#define	S3	19
81178172Simp#define	S4	20
82178172Simp#define	S5	21
83178172Simp#define	S6	22
84178172Simp#define	S7	23
85178172Simp#define	T8	24
86178172Simp#define	T9	25
87178172Simp#define	K0	26
88178172Simp#define	K1	27
89178172Simp#define	GP	28
90178172Simp#define	SP	29
91178172Simp#define	S8	30
92178172Simp#define	RA	31
93178172Simp#define	SR	32
94178172Simp#define	PS	SR	/* alias for SR */
95178172Simp#define	MULLO	33
96178172Simp#define	MULHI	34
97178172Simp#define	BADVADDR 35
98178172Simp#define	CAUSE	36
99178172Simp#define	PC	37
100178172Simp/*
101178172Simp * IC is valid only on RM7K and RM9K processors. Access to this is
102178172Simp * controlled by IC_INT_REG which defined in kernel config
103178172Simp */
104178172Simp#define	IC	38
105178172Simp#define	DUMMY	39	/* for 8 byte alignment */
106178172Simp#define	NUMSAVEREGS 40
107178172Simp
108178172Simp/*
109249523Simp * Pseudo registers so we save a complete set of registers regardless of
110249551Simp * the ABI. See regdef.h for a more complete explanation.
111249523Simp */
112249523Simp#if defined(__mips_n32) || defined(__mips_n64)
113249523Simp#define	TA0	8
114249523Simp#define	TA1	9
115249523Simp#define	TA2	10
116249523Simp#define	TA3	11
117249523Simp#else
118249523Simp#define	TA0	12
119249523Simp#define	TA1	13
120249523Simp#define	TA2	14
121249523Simp#define	TA3	15
122249523Simp#endif
123249523Simp
124249523Simp
125249523Simp/*
126178172Simp * Index of FP registers in 'struct frame', counting from the beginning
127178172Simp * of the frame (i.e., including the general registers).
128178172Simp */
129178172Simp#define	FPBASE	NUMSAVEREGS
130178172Simp#define	F0	(FPBASE+0)
131178172Simp#define	F1	(FPBASE+1)
132178172Simp#define	F2	(FPBASE+2)
133178172Simp#define	F3	(FPBASE+3)
134178172Simp#define	F4	(FPBASE+4)
135178172Simp#define	F5	(FPBASE+5)
136178172Simp#define	F6	(FPBASE+6)
137178172Simp#define	F7	(FPBASE+7)
138178172Simp#define	F8	(FPBASE+8)
139178172Simp#define	F9	(FPBASE+9)
140178172Simp#define	F10	(FPBASE+10)
141178172Simp#define	F11	(FPBASE+11)
142178172Simp#define	F12	(FPBASE+12)
143178172Simp#define	F13	(FPBASE+13)
144178172Simp#define	F14	(FPBASE+14)
145178172Simp#define	F15	(FPBASE+15)
146178172Simp#define	F16	(FPBASE+16)
147178172Simp#define	F17	(FPBASE+17)
148178172Simp#define	F18	(FPBASE+18)
149178172Simp#define	F19	(FPBASE+19)
150178172Simp#define	F20	(FPBASE+20)
151178172Simp#define	F21	(FPBASE+21)
152178172Simp#define	F22	(FPBASE+22)
153178172Simp#define	F23	(FPBASE+23)
154178172Simp#define	F24	(FPBASE+24)
155178172Simp#define	F25	(FPBASE+25)
156178172Simp#define	F26	(FPBASE+26)
157178172Simp#define	F27	(FPBASE+27)
158178172Simp#define	F28	(FPBASE+28)
159178172Simp#define	F29	(FPBASE+29)
160178172Simp#define	F30	(FPBASE+30)
161178172Simp#define	F31	(FPBASE+31)
162178172Simp#define	FSR	(FPBASE+32)
163178172Simp#define FSR_DUMMY (FPBASE+33) /* For 8 byte alignment */
164178172Simp
165178172Simp#define	NUMFPREGS	34
166178172Simp
167178172Simp#define	NREGS	(NUMSAVEREGS + NUMFPREGS)
168178172Simp
169178172Simp/*
170178172Simp * Index of FP registers in 'struct frame', relative to the base
171178172Simp * of the FP registers in frame (i.e., *not* including the general
172178172Simp * registers).
173178172Simp */
174178172Simp#define	F0_NUM	(0)
175178172Simp#define	F1_NUM	(1)
176178172Simp#define	F2_NUM	(2)
177178172Simp#define	F3_NUM	(3)
178178172Simp#define	F4_NUM	(4)
179178172Simp#define	F5_NUM	(5)
180178172Simp#define	F6_NUM	(6)
181178172Simp#define	F7_NUM	(7)
182178172Simp#define	F8_NUM	(8)
183178172Simp#define	F9_NUM	(9)
184178172Simp#define	F10_NUM	(10)
185178172Simp#define	F11_NUM	(11)
186178172Simp#define	F12_NUM	(12)
187178172Simp#define	F13_NUM	(13)
188178172Simp#define	F14_NUM	(14)
189178172Simp#define	F15_NUM	(15)
190178172Simp#define	F16_NUM	(16)
191178172Simp#define	F17_NUM	(17)
192178172Simp#define	F18_NUM	(18)
193178172Simp#define	F19_NUM	(19)
194178172Simp#define	F20_NUM	(20)
195178172Simp#define	F21_NUM	(21)
196178172Simp#define	F22_NUM	(22)
197178172Simp#define	F23_NUM	(23)
198178172Simp#define	F24_NUM	(24)
199178172Simp#define	F25_NUM	(25)
200178172Simp#define	F26_NUM	(26)
201178172Simp#define	F27_NUM	(27)
202178172Simp#define	F28_NUM	(28)
203178172Simp#define	F29_NUM	(29)
204178172Simp#define	F30_NUM	(30)
205178172Simp#define	F31_NUM	(31)
206178172Simp#define	FSR_NUM	(32)
207178172Simp
208178172Simp#endif /* !_MACHINE_REGNUM_H_ */
209