1178172Simp/* $NetBSD: asm.h,v 1.29 2000/12/14 21:29:51 jeffs Exp $ */ 2178172Simp 3178172Simp/* 4178172Simp * Copyright (c) 1992, 1993 5178172Simp * The Regents of the University of California. All rights reserved. 6178172Simp * 7178172Simp * This code is derived from software contributed to Berkeley by 8178172Simp * Ralph Campbell. 9178172Simp * 10178172Simp * Redistribution and use in source and binary forms, with or without 11178172Simp * modification, are permitted provided that the following conditions 12178172Simp * are met: 13178172Simp * 1. Redistributions of source code must retain the above copyright 14178172Simp * notice, this list of conditions and the following disclaimer. 15178172Simp * 2. Redistributions in binary form must reproduce the above copyright 16178172Simp * notice, this list of conditions and the following disclaimer in the 17178172Simp * documentation and/or other materials provided with the distribution. 18178172Simp * 4. Neither the name of the University nor the names of its contributors 19178172Simp * may be used to endorse or promote products derived from this software 20178172Simp * without specific prior written permission. 21178172Simp * 22178172Simp * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23178172Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24178172Simp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25178172Simp * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26178172Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27178172Simp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28178172Simp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29178172Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30178172Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31178172Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32178172Simp * SUCH DAMAGE. 33178172Simp * 34178172Simp * @(#)machAsmDefs.h 8.1 (Berkeley) 6/10/93 35178172Simp * JNPR: asm.h,v 1.10 2007/08/09 11:23:32 katta 36178172Simp * $FreeBSD$ 37178172Simp */ 38178172Simp 39178172Simp/* 40178172Simp * machAsmDefs.h -- 41178172Simp * 42178172Simp * Macros used when writing assembler programs. 43178172Simp * 44178172Simp * Copyright (C) 1989 Digital Equipment Corporation. 45178172Simp * Permission to use, copy, modify, and distribute this software and 46178172Simp * its documentation for any purpose and without fee is hereby granted, 47178172Simp * provided that the above copyright notice appears in all copies. 48178172Simp * Digital Equipment Corporation makes no representations about the 49178172Simp * suitability of this software for any purpose. It is provided "as is" 50178172Simp * without express or implied warranty. 51178172Simp * 52178172Simp * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAsmDefs.h, 53178172Simp * v 1.2 89/08/15 18:28:24 rab Exp SPRITE (DECWRL) 54178172Simp */ 55178172Simp 56178172Simp#ifndef _MACHINE_ASM_H_ 57178172Simp#define _MACHINE_ASM_H_ 58178172Simp 59178172Simp#include <machine/regdef.h> 60178172Simp#include <machine/endian.h> 61202031Simp#include <machine/cdefs.h> 62178172Simp 63178172Simp#undef __FBSDID 64178172Simp#if !defined(lint) && !defined(STRIP_FBSDID) 65178172Simp#define __FBSDID(s) .ident s 66178172Simp#else 67178172Simp#define __FBSDID(s) /* nothing */ 68178172Simp#endif 69178172Simp 70178172Simp/* 71178172Simp * Define -pg profile entry code. 72178172Simp * Must always be noreorder, must never use a macro instruction 73178172Simp * Final addiu to t9 must always equal the size of this _KERN_MCOUNT 74178172Simp */ 75178172Simp#define _KERN_MCOUNT \ 76178172Simp .set push; \ 77178172Simp .set noreorder; \ 78178172Simp .set noat; \ 79178172Simp subu sp,sp,16; \ 80178172Simp sw t9,12(sp); \ 81178172Simp move AT,ra; \ 82178172Simp lui t9,%hi(_mcount); \ 83178172Simp addiu t9,t9,%lo(_mcount); \ 84178172Simp jalr t9; \ 85178172Simp nop; \ 86178172Simp lw t9,4(sp); \ 87178172Simp addiu sp,sp,8; \ 88178172Simp addiu t9,t9,40; \ 89178172Simp .set pop; 90178172Simp 91178172Simp#ifdef GPROF 92178172Simp#define MCOUNT _KERN_MCOUNT 93178172Simp#else 94178172Simp#define MCOUNT 95178172Simp#endif 96178172Simp 97178172Simp#define _C_LABEL(x) x 98178172Simp 99178172Simp#ifdef USE_AENT 100178172Simp#define AENT(x) \ 101178172Simp .aent x, 0 102178172Simp#else 103178172Simp#define AENT(x) 104178172Simp#endif 105178172Simp 106178172Simp/* 107178172Simp * WARN_REFERENCES: create a warning if the specified symbol is referenced 108178172Simp */ 109178172Simp#define WARN_REFERENCES(_sym,_msg) \ 110178172Simp .section .gnu.warning. ## _sym ; .ascii _msg ; .text 111178172Simp 112178172Simp#ifdef __ELF__ 113178172Simp# define _C_LABEL(x) x 114178172Simp#else 115178172Simp# define _C_LABEL(x) _ ## x 116178172Simp#endif 117178172Simp 118178172Simp/* 119178172Simp * WEAK_ALIAS: create a weak alias. 120178172Simp */ 121178172Simp#define WEAK_ALIAS(alias,sym) \ 122178172Simp .weak alias; \ 123178172Simp alias = sym 124178172Simp 125178172Simp/* 126178172Simp * STRONG_ALIAS: create a strong alias. 127178172Simp */ 128178172Simp#define STRONG_ALIAS(alias,sym) \ 129178172Simp .globl alias; \ 130178172Simp alias = sym 131178172Simp 132178172Simp#define GLOBAL(sym) \ 133178172Simp .globl sym; sym: 134178172Simp 135178172Simp#define ENTRY(sym) \ 136178172Simp .text; .globl sym; .ent sym; sym: 137178172Simp 138178172Simp#define ASM_ENTRY(sym) \ 139178172Simp .text; .globl sym; .type sym,@function; sym: 140178172Simp 141178172Simp/* 142178172Simp * LEAF 143178172Simp * A leaf routine does 144178172Simp * - call no other function, 145178172Simp * - never use any register that callee-saved (S0-S8), and 146178172Simp * - not use any local stack storage. 147178172Simp */ 148178172Simp#define LEAF(x) \ 149178172Simp .globl _C_LABEL(x); \ 150178172Simp .ent _C_LABEL(x), 0; \ 151178172Simp_C_LABEL(x): ; \ 152178172Simp .frame sp, 0, ra; \ 153178172Simp MCOUNT 154178172Simp 155178172Simp/* 156178172Simp * LEAF_NOPROFILE 157178172Simp * No profilable leaf routine. 158178172Simp */ 159178172Simp#define LEAF_NOPROFILE(x) \ 160178172Simp .globl _C_LABEL(x); \ 161178172Simp .ent _C_LABEL(x), 0; \ 162178172Simp_C_LABEL(x): ; \ 163178172Simp .frame sp, 0, ra 164178172Simp 165178172Simp/* 166178172Simp * XLEAF 167178172Simp * declare alternate entry to leaf routine 168178172Simp */ 169178172Simp#define XLEAF(x) \ 170178172Simp .globl _C_LABEL(x); \ 171178172Simp AENT (_C_LABEL(x)); \ 172178172Simp_C_LABEL(x): 173178172Simp 174178172Simp/* 175178172Simp * NESTED 176178172Simp * A function calls other functions and needs 177178172Simp * therefore stack space to save/restore registers. 178178172Simp */ 179178172Simp#define NESTED(x, fsize, retpc) \ 180178172Simp .globl _C_LABEL(x); \ 181178172Simp .ent _C_LABEL(x), 0; \ 182178172Simp_C_LABEL(x): ; \ 183178172Simp .frame sp, fsize, retpc; \ 184178172Simp MCOUNT 185178172Simp 186178172Simp/* 187178172Simp * NESTED_NOPROFILE(x) 188178172Simp * No profilable nested routine. 189178172Simp */ 190178172Simp#define NESTED_NOPROFILE(x, fsize, retpc) \ 191178172Simp .globl _C_LABEL(x); \ 192178172Simp .ent _C_LABEL(x), 0; \ 193178172Simp_C_LABEL(x): ; \ 194178172Simp .frame sp, fsize, retpc 195178172Simp 196178172Simp/* 197178172Simp * XNESTED 198178172Simp * declare alternate entry point to nested routine. 199178172Simp */ 200178172Simp#define XNESTED(x) \ 201178172Simp .globl _C_LABEL(x); \ 202178172Simp AENT (_C_LABEL(x)); \ 203178172Simp_C_LABEL(x): 204178172Simp 205178172Simp/* 206178172Simp * END 207178172Simp * Mark end of a procedure. 208178172Simp */ 209178172Simp#define END(x) \ 210178172Simp .end _C_LABEL(x) 211178172Simp 212178172Simp/* 213178172Simp * IMPORT -- import external symbol 214178172Simp */ 215178172Simp#define IMPORT(sym, size) \ 216178172Simp .extern _C_LABEL(sym),size 217178172Simp 218178172Simp/* 219178172Simp * EXPORT -- export definition of symbol 220178172Simp */ 221178172Simp#define EXPORT(x) \ 222178172Simp .globl _C_LABEL(x); \ 223178172Simp_C_LABEL(x): 224178172Simp 225178172Simp/* 226178172Simp * VECTOR 227178172Simp * exception vector entrypoint 228178172Simp * XXX: regmask should be used to generate .mask 229178172Simp */ 230178172Simp#define VECTOR(x, regmask) \ 231178172Simp .ent _C_LABEL(x),0; \ 232178172Simp EXPORT(x); \ 233178172Simp 234178172Simp#define VECTOR_END(x) \ 235178172Simp EXPORT(x ## End); \ 236178172Simp END(x) 237178172Simp 238178172Simp/* 239178172Simp * Macros to panic and printf from assembly language. 240178172Simp */ 241178172Simp#define PANIC(msg) \ 242202031Simp PTR_LA a0, 9f; \ 243178172Simp jal _C_LABEL(panic); \ 244178172Simp nop; \ 245178172Simp MSG(msg) 246178172Simp 247178172Simp#define PANIC_KSEG0(msg, reg) PANIC(msg) 248178172Simp 249178172Simp#define PRINTF(msg) \ 250202031Simp PTR_LA a0, 9f; \ 251178172Simp jal _C_LABEL(printf); \ 252178172Simp nop; \ 253178172Simp MSG(msg) 254178172Simp 255178172Simp#define MSG(msg) \ 256178172Simp .rdata; \ 257178172Simp9: .asciiz msg; \ 258178172Simp .text 259178172Simp 260178172Simp#define ASMSTR(str) \ 261178172Simp .asciiz str; \ 262178172Simp .align 3 263178172Simp 264178172Simp/* 265178172Simp * Call ast if required 266206717Sjmallett * 267206717Sjmallett * XXX Do we really need to disable interrupts? 268178172Simp */ 269178172Simp#define DO_AST \ 270178172Simp44: \ 271206717Sjmallett mfc0 t0, MIPS_COP_0_STATUS ;\ 272206717Sjmallett and a0, t0, MIPS_SR_INT_IE ;\ 273206717Sjmallett xor t0, a0, t0 ;\ 274206717Sjmallett mtc0 t0, MIPS_COP_0_STATUS ;\ 275206717Sjmallett COP0_SYNC ;\ 276178172Simp GET_CPU_PCPU(s1) ;\ 277206717Sjmallett PTR_L s3, PC_CURPCB(s1) ;\ 278206717Sjmallett PTR_L s1, PC_CURTHREAD(s1) ;\ 279178172Simp lw s2, TD_FLAGS(s1) ;\ 280178172Simp li s0, TDF_ASTPENDING | TDF_NEEDRESCHED;\ 281178172Simp and s2, s0 ;\ 282206717Sjmallett mfc0 t0, MIPS_COP_0_STATUS ;\ 283206717Sjmallett or t0, a0, t0 ;\ 284206717Sjmallett mtc0 t0, MIPS_COP_0_STATUS ;\ 285206717Sjmallett COP0_SYNC ;\ 286178172Simp beq s2, zero, 4f ;\ 287178172Simp nop ;\ 288202031Simp PTR_LA s0, _C_LABEL(ast) ;\ 289178172Simp jalr s0 ;\ 290202031Simp PTR_ADDU a0, s3, U_PCB_REGS ;\ 291206717Sjmallett j 44b ;\ 292178172Simp nop ;\ 293178172Simp4: 294178172Simp 295178172Simp 296178172Simp/* 297178172Simp * XXX retain dialects XXX 298178172Simp */ 299178172Simp#define ALEAF(x) XLEAF(x) 300178172Simp#define NLEAF(x) LEAF_NOPROFILE(x) 301178172Simp#define NON_LEAF(x, fsize, retpc) NESTED(x, fsize, retpc) 302178172Simp#define NNON_LEAF(x, fsize, retpc) NESTED_NOPROFILE(x, fsize, retpc) 303178172Simp 304204557Simp#if defined(__mips_o32) 305204557Simp#define SZREG 4 306204557Simp#else 307204557Simp#define SZREG 8 308204557Simp#endif 309204557Simp 310204557Simp#if defined(__mips_o32) || defined(__mips_o64) 311204557Simp#define ALSK 7 /* stack alignment */ 312204557Simp#define ALMASK -7 /* stack alignment */ 313204557Simp#define SZFPREG 4 314204557Simp#define FP_L lwc1 315204557Simp#define FP_S swc1 316204557Simp#else 317204557Simp#define ALSK 15 /* stack alignment */ 318204557Simp#define ALMASK -15 /* stack alignment */ 319204557Simp#define SZFPREG 8 320204557Simp#define FP_L ldc1 321204557Simp#define FP_S sdc1 322204557Simp#endif 323204557Simp 324178172Simp/* 325178172Simp * standard callframe { 326204557Simp * register_t cf_pad[N]; o32/64 (N=0), n32 (N=1) n64 (N=1) 327204557Simp * register_t cf_args[4]; arg0 - arg3 (only on o32 and o64) 328204557Simp * register_t cf_gp; global pointer (only on n32 and n64) 329178172Simp * register_t cf_sp; frame pointer 330178172Simp * register_t cf_ra; return address 331178172Simp * }; 332178172Simp */ 333204557Simp#if defined(__mips_o32) || defined(__mips_o64) 334204557Simp#define CALLFRAME_SIZ (SZREG * (4 + 2)) 335204557Simp#define CALLFRAME_S0 0 336204557Simp#elif defined(__mips_n32) || defined(__mips_n64) 337204557Simp#define CALLFRAME_SIZ (SZREG * 4) 338204557Simp#define CALLFRAME_S0 (CALLFRAME_SIZ - 4 * SZREG) 339204557Simp#endif 340204557Simp#ifndef _KERNEL 341204557Simp#define CALLFRAME_GP (CALLFRAME_SIZ - 3 * SZREG) 342204557Simp#endif 343204557Simp#define CALLFRAME_SP (CALLFRAME_SIZ - 2 * SZREG) 344204557Simp#define CALLFRAME_RA (CALLFRAME_SIZ - 1 * SZREG) 345178172Simp 346178172Simp/* 347206717Sjmallett * Endian-independent assembly-code aliases for unaligned memory accesses. 348206717Sjmallett */ 349206717Sjmallett#if _BYTE_ORDER == _LITTLE_ENDIAN 350206717Sjmallett# define LWHI lwr 351206717Sjmallett# define LWLO lwl 352206717Sjmallett# define SWHI swr 353206717Sjmallett# define SWLO swl 354206717Sjmallett# if SZREG == 4 355206717Sjmallett# define REG_LHI lwr 356206717Sjmallett# define REG_LLO lwl 357206717Sjmallett# define REG_SHI swr 358206717Sjmallett# define REG_SLO swl 359206717Sjmallett# else 360206717Sjmallett# define REG_LHI ldr 361206717Sjmallett# define REG_LLO ldl 362206717Sjmallett# define REG_SHI sdr 363206717Sjmallett# define REG_SLO sdl 364206717Sjmallett# endif 365206717Sjmallett#endif 366206717Sjmallett 367206717Sjmallett#if _BYTE_ORDER == _BIG_ENDIAN 368206717Sjmallett# define LWHI lwl 369206717Sjmallett# define LWLO lwr 370206717Sjmallett# define SWHI swl 371206717Sjmallett# define SWLO swr 372206717Sjmallett# if SZREG == 4 373206717Sjmallett# define REG_LHI lwl 374206717Sjmallett# define REG_LLO lwr 375206717Sjmallett# define REG_SHI swl 376206717Sjmallett# define REG_SLO swr 377206717Sjmallett# else 378206717Sjmallett# define REG_LHI ldl 379206717Sjmallett# define REG_LLO ldr 380206717Sjmallett# define REG_SHI sdl 381206717Sjmallett# define REG_SLO sdr 382206717Sjmallett# endif 383206717Sjmallett#endif 384206717Sjmallett 385206717Sjmallett/* 386178172Simp * While it would be nice to be compatible with the SGI 387178172Simp * REG_L and REG_S macros, because they do not take parameters, it 388178172Simp * is impossible to use them with the _MIPS_SIM_ABIX32 model. 389178172Simp * 390178172Simp * These macros hide the use of mips3 instructions from the 391178172Simp * assembler to prevent the assembler from generating 64-bit style 392178172Simp * ABI calls. 393178172Simp */ 394204557Simp#if _MIPS_SZPTR == 32 395204557Simp#define PTR_ADD add 396204557Simp#define PTR_ADDI addi 397204557Simp#define PTR_ADDU addu 398204557Simp#define PTR_ADDIU addiu 399204557Simp#define PTR_SUB add 400204557Simp#define PTR_SUBI subi 401204557Simp#define PTR_SUBU subu 402204557Simp#define PTR_SUBIU subu 403204557Simp#define PTR_L lw 404204557Simp#define PTR_LA la 405206717Sjmallett#define PTR_LI li 406204557Simp#define PTR_S sw 407204557Simp#define PTR_SLL sll 408204557Simp#define PTR_SLLV sllv 409204557Simp#define PTR_SRL srl 410204557Simp#define PTR_SRLV srlv 411204557Simp#define PTR_SRA sra 412204557Simp#define PTR_SRAV srav 413204557Simp#define PTR_LL ll 414204557Simp#define PTR_SC sc 415204557Simp#define PTR_WORD .word 416204557Simp#define PTR_SCALESHIFT 2 417204557Simp#else /* _MIPS_SZPTR == 64 */ 418204557Simp#define PTR_ADD dadd 419204557Simp#define PTR_ADDI daddi 420204557Simp#define PTR_ADDU daddu 421204557Simp#define PTR_ADDIU daddiu 422204557Simp#define PTR_SUB dadd 423204557Simp#define PTR_SUBI dsubi 424204557Simp#define PTR_SUBU dsubu 425204557Simp#define PTR_SUBIU dsubu 426204557Simp#define PTR_L ld 427204557Simp#define PTR_LA dla 428206717Sjmallett#define PTR_LI dli 429204557Simp#define PTR_S sd 430204557Simp#define PTR_SLL dsll 431204557Simp#define PTR_SLLV dsllv 432204557Simp#define PTR_SRL dsrl 433204557Simp#define PTR_SRLV dsrlv 434204557Simp#define PTR_SRA dsra 435204557Simp#define PTR_SRAV dsrav 436204557Simp#define PTR_LL lld 437204557Simp#define PTR_SC scd 438204557Simp#define PTR_WORD .dword 439204557Simp#define PTR_SCALESHIFT 3 440204557Simp#endif /* _MIPS_SZPTR == 64 */ 441178172Simp 442204557Simp#if _MIPS_SZINT == 32 443204557Simp#define INT_ADD add 444204557Simp#define INT_ADDI addi 445204557Simp#define INT_ADDU addu 446204557Simp#define INT_ADDIU addiu 447204557Simp#define INT_SUB add 448204557Simp#define INT_SUBI subi 449204557Simp#define INT_SUBU subu 450204557Simp#define INT_SUBIU subu 451204557Simp#define INT_L lw 452204557Simp#define INT_LA la 453204557Simp#define INT_S sw 454204557Simp#define INT_SLL sll 455204557Simp#define INT_SLLV sllv 456204557Simp#define INT_SRL srl 457204557Simp#define INT_SRLV srlv 458204557Simp#define INT_SRA sra 459204557Simp#define INT_SRAV srav 460204557Simp#define INT_LL ll 461204557Simp#define INT_SC sc 462204557Simp#define INT_WORD .word 463204557Simp#define INT_SCALESHIFT 2 464204557Simp#else 465204557Simp#define INT_ADD dadd 466204557Simp#define INT_ADDI daddi 467204557Simp#define INT_ADDU daddu 468204557Simp#define INT_ADDIU daddiu 469204557Simp#define INT_SUB dadd 470204557Simp#define INT_SUBI dsubi 471204557Simp#define INT_SUBU dsubu 472204557Simp#define INT_SUBIU dsubu 473204557Simp#define INT_L ld 474204557Simp#define INT_LA dla 475204557Simp#define INT_S sd 476204557Simp#define INT_SLL dsll 477204557Simp#define INT_SLLV dsllv 478204557Simp#define INT_SRL dsrl 479204557Simp#define INT_SRLV dsrlv 480204557Simp#define INT_SRA dsra 481204557Simp#define INT_SRAV dsrav 482204557Simp#define INT_LL lld 483204557Simp#define INT_SC scd 484204557Simp#define INT_WORD .dword 485204557Simp#define INT_SCALESHIFT 3 486204557Simp#endif 487204557Simp 488204557Simp#if _MIPS_SZLONG == 32 489204557Simp#define LONG_ADD add 490204557Simp#define LONG_ADDI addi 491204557Simp#define LONG_ADDU addu 492204557Simp#define LONG_ADDIU addiu 493204557Simp#define LONG_SUB add 494204557Simp#define LONG_SUBI subi 495204557Simp#define LONG_SUBU subu 496204557Simp#define LONG_SUBIU subu 497204557Simp#define LONG_L lw 498204557Simp#define LONG_LA la 499204557Simp#define LONG_S sw 500204557Simp#define LONG_SLL sll 501204557Simp#define LONG_SLLV sllv 502204557Simp#define LONG_SRL srl 503204557Simp#define LONG_SRLV srlv 504204557Simp#define LONG_SRA sra 505204557Simp#define LONG_SRAV srav 506204557Simp#define LONG_LL ll 507204557Simp#define LONG_SC sc 508204557Simp#define LONG_WORD .word 509204557Simp#define LONG_SCALESHIFT 2 510204557Simp#else 511204557Simp#define LONG_ADD dadd 512204557Simp#define LONG_ADDI daddi 513204557Simp#define LONG_ADDU daddu 514204557Simp#define LONG_ADDIU daddiu 515204557Simp#define LONG_SUB dadd 516204557Simp#define LONG_SUBI dsubi 517204557Simp#define LONG_SUBU dsubu 518204557Simp#define LONG_SUBIU dsubu 519204557Simp#define LONG_L ld 520204557Simp#define LONG_LA dla 521204557Simp#define LONG_S sd 522204557Simp#define LONG_SLL dsll 523204557Simp#define LONG_SLLV dsllv 524204557Simp#define LONG_SRL dsrl 525204557Simp#define LONG_SRLV dsrlv 526204557Simp#define LONG_SRA dsra 527204557Simp#define LONG_SRAV dsrav 528204557Simp#define LONG_LL lld 529204557Simp#define LONG_SC scd 530204557Simp#define LONG_WORD .dword 531204557Simp#define LONG_SCALESHIFT 3 532204557Simp#endif 533204557Simp 534204557Simp#if SZREG == 4 535178172Simp#define REG_L lw 536178172Simp#define REG_S sw 537178172Simp#define REG_LI li 538204557Simp#define REG_ADDU addu 539204557Simp#define REG_SLL sll 540204557Simp#define REG_SLLV sllv 541204557Simp#define REG_SRL srl 542204557Simp#define REG_SRLV srlv 543204557Simp#define REG_SRA sra 544204557Simp#define REG_SRAV srav 545204557Simp#define REG_LL ll 546204557Simp#define REG_SC sc 547204557Simp#define REG_SCALESHIFT 2 548178172Simp#else 549178172Simp#define REG_L ld 550178172Simp#define REG_S sd 551178172Simp#define REG_LI dli 552204557Simp#define REG_ADDU daddu 553204557Simp#define REG_SLL dsll 554204557Simp#define REG_SLLV dsllv 555204557Simp#define REG_SRL dsrl 556204557Simp#define REG_SRLV dsrlv 557204557Simp#define REG_SRA dsra 558204557Simp#define REG_SRAV dsrav 559204557Simp#define REG_LL lld 560204557Simp#define REG_SC scd 561204557Simp#define REG_SCALESHIFT 3 562204557Simp#endif 563204557Simp 564204557Simp#if _MIPS_ISA == _MIPS_ISA_MIPS1 || _MIPS_ISA == _MIPS_ISA_MIPS2 || \ 565204557Simp _MIPS_ISA == _MIPS_ISA_MIPS32 566204557Simp#define MFC0 mfc0 567204557Simp#define MTC0 mtc0 568204557Simp#endif 569204557Simp#if _MIPS_ISA == _MIPS_ISA_MIPS3 || _MIPS_ISA == _MIPS_ISA_MIPS4 || \ 570204557Simp _MIPS_ISA == _MIPS_ISA_MIPS64 571204557Simp#define MFC0 dmfc0 572204557Simp#define MTC0 dmtc0 573204557Simp#endif 574204557Simp 575204557Simp#if defined(__mips_o32) || defined(__mips_o64) 576204557Simp 577204557Simp#ifdef __ABICALLS__ 578204557Simp#define CPRESTORE(r) .cprestore r 579204557Simp#define CPLOAD(r) .cpload r 580204557Simp#else 581204557Simp#define CPRESTORE(r) /* not needed */ 582204557Simp#define CPLOAD(r) /* not needed */ 583204557Simp#endif 584204557Simp 585204557Simp#define SETUP_GP \ 586204557Simp .set push; \ 587204557Simp .set noreorder; \ 588204557Simp .cpload t9; \ 589204557Simp .set pop 590204557Simp#define SETUP_GPX(r) \ 591204557Simp .set push; \ 592204557Simp .set noreorder; \ 593204557Simp move r,ra; /* save old ra */ \ 594204557Simp bal 7f; \ 595204557Simp nop; \ 596204557Simp 7: .cpload ra; \ 597204557Simp move ra,r; \ 598204557Simp .set pop 599204557Simp#define SETUP_GPX_L(r,lbl) \ 600204557Simp .set push; \ 601204557Simp .set noreorder; \ 602204557Simp move r,ra; /* save old ra */ \ 603204557Simp bal lbl; \ 604204557Simp nop; \ 605204557Simp lbl: .cpload ra; \ 606204557Simp move ra,r; \ 607204557Simp .set pop 608204557Simp#define SAVE_GP(x) .cprestore x 609204557Simp 610204557Simp#define SETUP_GP64(a,b) /* n32/n64 specific */ 611204557Simp#define SETUP_GP64_R(a,b) /* n32/n64 specific */ 612204557Simp#define SETUP_GPX64(a,b) /* n32/n64 specific */ 613204557Simp#define SETUP_GPX64_L(a,b,c) /* n32/n64 specific */ 614204557Simp#define RESTORE_GP64 /* n32/n64 specific */ 615204557Simp#define USE_ALT_CP(a) /* n32/n64 specific */ 616204557Simp#endif /* __mips_o32 || __mips_o64 */ 617204557Simp 618204557Simp#if defined(__mips_o32) || defined(__mips_o64) 619204557Simp#define REG_PROLOGUE .set push 620204557Simp#define REG_EPILOGUE .set pop 621204557Simp#endif 622204557Simp#if defined(__mips_n32) || defined(__mips_n64) 623178172Simp#define REG_PROLOGUE .set push ; .set mips3 624178172Simp#define REG_EPILOGUE .set pop 625204557Simp#endif 626178172Simp 627204557Simp#if defined(__mips_n32) || defined(__mips_n64) 628204557Simp#define SETUP_GP /* o32 specific */ 629204557Simp#define SETUP_GPX(r) /* o32 specific */ 630204557Simp#define SETUP_GPX_L(r,lbl) /* o32 specific */ 631204557Simp#define SAVE_GP(x) /* o32 specific */ 632204557Simp#define SETUP_GP64(a,b) .cpsetup $25, a, b 633204557Simp#define SETUP_GPX64(a,b) \ 634204557Simp .set push; \ 635204557Simp move b,ra; \ 636204557Simp .set noreorder; \ 637204557Simp bal 7f; \ 638204557Simp nop; \ 639204557Simp 7: .set pop; \ 640204557Simp .cpsetup ra, a, 7b; \ 641204557Simp move ra,b 642204557Simp#define SETUP_GPX64_L(a,b,c) \ 643204557Simp .set push; \ 644204557Simp move b,ra; \ 645204557Simp .set noreorder; \ 646204557Simp bal c; \ 647204557Simp nop; \ 648204557Simp c: .set pop; \ 649204557Simp .cpsetup ra, a, c; \ 650204557Simp move ra,b 651204557Simp#define RESTORE_GP64 .cpreturn 652204557Simp#define USE_ALT_CP(a) .cplocal a 653204557Simp#endif /* __mips_n32 || __mips_n64 */ 654204557Simp 655178172Simp#define GET_CPU_PCPU(reg) \ 656206717Sjmallett PTR_L reg, _C_LABEL(pcpup); 657178172Simp 658178172Simp/* 659178172Simp * Description of the setjmp buffer 660178172Simp * 661178172Simp * word 0 magic number (dependant on creator) 662178172Simp * 1 RA 663178172Simp * 2 S0 664178172Simp * 3 S1 665178172Simp * 4 S2 666178172Simp * 5 S3 667178172Simp * 6 S4 668178172Simp * 7 S5 669178172Simp * 8 S6 670178172Simp * 9 S7 671178172Simp * 10 SP 672178172Simp * 11 S8 673209500Sjchandra * 12 GP (dependent on ABI) 674209500Sjchandra * 13 signal mask (dependant on magic) 675178172Simp * 14 (con't) 676178172Simp * 15 (con't) 677209500Sjchandra * 16 (con't) 678178172Simp * 679178172Simp * The magic number number identifies the jmp_buf and 680178172Simp * how the buffer was created as well as providing 681178172Simp * a sanity check 682178172Simp * 683178172Simp */ 684178172Simp 685178172Simp#define _JB_MAGIC__SETJMP 0xBADFACED 686178172Simp#define _JB_MAGIC_SETJMP 0xFACEDBAD 687178172Simp 688178172Simp/* Valid for all jmp_buf's */ 689178172Simp 690178172Simp#define _JB_MAGIC 0 691178172Simp#define _JB_REG_RA 1 692178172Simp#define _JB_REG_S0 2 693178172Simp#define _JB_REG_S1 3 694178172Simp#define _JB_REG_S2 4 695178172Simp#define _JB_REG_S3 5 696178172Simp#define _JB_REG_S4 6 697178172Simp#define _JB_REG_S5 7 698178172Simp#define _JB_REG_S6 8 699178172Simp#define _JB_REG_S7 9 700178172Simp#define _JB_REG_SP 10 701178172Simp#define _JB_REG_S8 11 702209500Sjchandra#if defined(__mips_n32) || defined(__mips_n64) 703209500Sjchandra#define _JB_REG_GP 12 704209500Sjchandra#endif 705178172Simp 706178172Simp/* Only valid with the _JB_MAGIC_SETJMP magic */ 707178172Simp 708209500Sjchandra#define _JB_SIGMASK 13 709178172Simp 710210161Simp/* 711210161Simp * Various macros for dealing with TLB hazards 712210161Simp * (a) why so many? 713210161Simp * (b) when to use? 714210161Simp * (c) why not used everywhere? 715210161Simp */ 716210161Simp/* 717210161Simp * Assume that w alaways need nops to escape CP0 hazard 718210161Simp * TODO: Make hazard delays configurable. Stuck with 5 cycles on the moment 719210161Simp * For more info on CP0 hazards see Chapter 7 (p.99) of "MIPS32 Architecture 720210161Simp * For Programmers Volume III: The MIPS32 Privileged Resource Architecture" 721210161Simp */ 722227658Sjchandra#if defined(CPU_NLM) 723227658Sjchandra#define HAZARD_DELAY sll $0,3 724227658Sjchandra#define ITLBNOPFIX sll $0,3 725227658Sjchandra#elif defined(CPU_RMI) 726227658Sjchandra#define HAZARD_DELAY 727227658Sjchandra#define ITLBNOPFIX 728256172Sadrian#elif defined(CPU_MIPS74KC) 729256172Sadrian#define HAZARD_DELAY sll $0,$0,3 730256172Sadrian#define ITLBNOPFIX sll $0,$0,3 731227658Sjchandra#else 732256172Sadrian#define ITLBNOPFIX nop;nop;nop;nop;nop;nop;nop;nop;nop;sll $0,$0,3; 733256172Sadrian#define HAZARD_DELAY nop;nop;nop;nop;sll $0,$0,3; 734227658Sjchandra#endif 735227658Sjchandra 736178172Simp#endif /* !_MACHINE_ASM_H_ */ 737