1139790Simp/*- 250769Sdfr * Copyright (c) 1996, Sujal M. Patel 350769Sdfr * All rights reserved. 450769Sdfr * 550769Sdfr * Redistribution and use in source and binary forms, with or without 650769Sdfr * modification, are permitted provided that the following conditions 750769Sdfr * are met: 850769Sdfr * 1. Redistributions of source code must retain the above copyright 950769Sdfr * notice, this list of conditions and the following disclaimer. 1050769Sdfr * 2. Redistributions in binary form must reproduce the above copyright 1150769Sdfr * notice, this list of conditions and the following disclaimer in the 1250769Sdfr * documentation and/or other materials provided with the distribution. 1350769Sdfr * 3. All advertising materials mentioning features or use of this software 1450769Sdfr * must display the following acknowledgement: 1550769Sdfr * This product includes software developed by Sujal M. Patel 1650769Sdfr * 4. Neither the name of the author nor the names of any co-contributors 1750769Sdfr * may be used to endorse or promote products derived from this software 1850769Sdfr * without specific prior written permission. 1950769Sdfr * 2050769Sdfr * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 2150769Sdfr * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2250769Sdfr * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2350769Sdfr * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 2450769Sdfr * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2550769Sdfr * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2650769Sdfr * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2750769Sdfr * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2850769Sdfr * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2950769Sdfr * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 3050769Sdfr * SUCH DAMAGE. 3150769Sdfr * 3250769Sdfr * $FreeBSD$ 3350769Sdfr * from: pnp.h,v 1.7 1998/09/13 22:15:44 eivind Exp 3450769Sdfr */ 3550769Sdfr 3650769Sdfr#ifndef _ISA_PNPREG_H_ 3750769Sdfr#define _ISA_PNPREG_H_ 3850769Sdfr 3950769Sdfr/* Maximum Number of PnP Devices. 8 should be plenty */ 4050769Sdfr#define PNP_MAX_CARDS 8 4150769Sdfr 4250769Sdfr/* Static ports to access PnP state machine */ 4360374Snyan#ifdef PC98 4450769Sdfr#define _PNP_ADDRESS 0x259 4550769Sdfr#define _PNP_WRITE_DATA 0xa59 4650769Sdfr#else 4750769Sdfr#define _PNP_ADDRESS 0x279 4850769Sdfr#define _PNP_WRITE_DATA 0xa79 4950769Sdfr#endif 5050769Sdfr 5150769Sdfr/* PnP Registers. Write to ADDRESS and then use WRITE/READ_DATA */ 5250769Sdfr#define PNP_SET_RD_DATA 0x00 5350769Sdfr /*** 5450769Sdfr Writing to this location modifies the address of the port used for 5550769Sdfr reading from the Plug and Play ISA cards. Bits[7:0] become I/O 5650769Sdfr read port address bits[9:2]. Reads from this register are ignored. 5750769Sdfr ***/ 5850769Sdfr 5950769Sdfr#define PNP_SERIAL_ISOLATION 0x01 6050769Sdfr /*** 6150769Sdfr A read to this register causes a Plug and Play cards in the Isolation 6250769Sdfr state to compare one bit of the boards ID. 6350769Sdfr This register is read only. 6450769Sdfr ***/ 6550769Sdfr 6650769Sdfr#define PNP_CONFIG_CONTROL 0x02 6750769Sdfr#define PNP_CONFIG_CONTROL_RESET_CSN 0x04 6850769Sdfr#define PNP_CONFIG_CONTROL_WAIT_FOR_KEY 0x02 6950769Sdfr#define PNP_CONFIG_CONTROL_RESET 0x01 7050769Sdfr /*** 7150769Sdfr Bit[2] Reset CSN to 0 7250769Sdfr Bit[1] Return to the Wait for Key state 7350769Sdfr Bit[0] Reset all logical devices and restore configuration 7450769Sdfr registers to their power-up values. 7550769Sdfr 7650769Sdfr A write to bit[0] of this register performs a reset function on 7750769Sdfr all logical devices. This resets the contents of configuration 7850769Sdfr registers to their default state. All card's logical devices 7950769Sdfr enter their default state and the CSN is preserved. 8050769Sdfr 8150769Sdfr A write to bit[1] of this register causes all cards to enter the 8250769Sdfr Wait for Key state but all CSNs are preserved and logical devices 8350769Sdfr are not affected. 8450769Sdfr 8550769Sdfr A write to bit[2] of this register causes all cards to reset their 8650769Sdfr CSN to zero . 8750769Sdfr 8850769Sdfr This register is write-only. The values are not sticky, that is, 8950769Sdfr hardware will automatically clear them and there is no need for 9050769Sdfr software to clear the bits. 9150769Sdfr ***/ 9250769Sdfr 9350769Sdfr#define PNP_WAKE 0x03 9450769Sdfr /*** 9550769Sdfr A write to this port will cause all cards that have a CSN that 9650769Sdfr matches the write data[7:0] to go from the Sleep state to the either 9750769Sdfr the Isolation state if the write data for this command is zero or 9850769Sdfr the Config state if the write data is not zero. Additionally, the 9950769Sdfr pointer to the byte-serial device is reset. This register is 10050769Sdfr writeonly. 10150769Sdfr ***/ 10250769Sdfr 10350769Sdfr#define PNP_RESOURCE_DATA 0x04 10450769Sdfr /*** 10550769Sdfr A read from this address reads the next byte of resource information. 10650769Sdfr The Status register must be polled until bit[0] is set before this 10750769Sdfr register may be read. This register is read only. 10850769Sdfr ***/ 10950769Sdfr 11050769Sdfr#define PNP_STATUS 0x05 11150769Sdfr /*** 11250769Sdfr Bit[0] when set indicates it is okay to read the next data byte 11350769Sdfr from the Resource Data register. This register is readonly. 11450769Sdfr ***/ 11550769Sdfr 11650769Sdfr#define PNP_SET_CSN 0x06 11750769Sdfr /*** 11850769Sdfr A write to this port sets a card's CSN. The CSN is a value uniquely 11950769Sdfr assigned to each ISA card after the serial identification process 12050769Sdfr so that each card may be individually selected during a Wake[CSN] 12150769Sdfr command. This register is read/write. 12250769Sdfr ***/ 12350769Sdfr 12450769Sdfr#define PNP_SET_LDN 0x07 12550769Sdfr /*** 12650769Sdfr Selects the current logical device. All reads and writes of memory, 12750769Sdfr I/O, interrupt and DMA configuration information access the registers 12850769Sdfr of the logical device written here. In addition, the I/O Range 12950769Sdfr Check and Activate commands operate only on the selected logical 13050769Sdfr device. This register is read/write. If a card has only 1 logical 13150769Sdfr device, this location should be a read-only value of 0x00. 13250769Sdfr ***/ 13350769Sdfr 13450769Sdfr/*** addresses 0x08 - 0x1F Card Level Reserved for future use ***/ 13550769Sdfr/*** addresses 0x20 - 0x2F Card Level, Vendor Defined ***/ 13650769Sdfr 13750769Sdfr#define PNP_ACTIVATE 0x30 13850769Sdfr /*** 13950769Sdfr For each logical device there is one activate register that controls 14050769Sdfr whether or not the logical device is active on the ISA bus. Bit[0], 14150769Sdfr if set, activates the logical device. Bits[7:1] are reserved and 14250769Sdfr must return 0 on reads. This is a read/write register. Before a 14350769Sdfr logical device is activated, I/O range check must be disabled. 14450769Sdfr ***/ 14550769Sdfr 14650769Sdfr#define PNP_IO_RANGE_CHECK 0x31 14750769Sdfr#define PNP_IO_RANGE_CHECK_ENABLE 0x02 14850769Sdfr#define PNP_IO_RANGE_CHECK_READ_AS_55 0x01 14950769Sdfr /*** 15050769Sdfr This register is used to perform a conflict check on the I/O port 15150769Sdfr range programmed for use by a logical device. 15250769Sdfr 15350769Sdfr Bit[7:2] Reserved and must return 0 on reads 15450769Sdfr Bit[1] Enable I/O Range check, if set then I/O Range Check 15550769Sdfr is enabled. I/O range check is only valid when the logical 15650769Sdfr device is inactive. 15750769Sdfr 15850769Sdfr Bit[0], if set, forces the logical device to respond to I/O reads 15950769Sdfr of the logical device's assigned I/O range with a 0x55 when I/O 16050769Sdfr range check is in operation. If clear, the logical device drives 16150769Sdfr 0xAA. This register is read/write. 16250769Sdfr ***/ 16350769Sdfr 16450769Sdfr/*** addr 0x32 - 0x37 Logical Device Control Reserved for future use ***/ 16550769Sdfr/*** addr 0x38 - 0x3F Logical Device Control Vendor Define ***/ 16650769Sdfr 16750769Sdfr#define PNP_MEM_BASE_HIGH(i) (0x40 + 8*(i)) 16850769Sdfr#define PNP_MEM_BASE_LOW(i) (0x41 + 8*(i)) 16950769Sdfr#define PNP_MEM_CONTROL(i) (0x42 * 8*(i)) 17050769Sdfr#define PNP_MEM_CONTROL_16BIT 0x2 17150769Sdfr#define PNP_MEM_CONTROL_LIMIT 0x1 17250769Sdfr#define PNP_MEM_RANGE_HIGH(i) (0x43 + 8*(i)) 17350769Sdfr#define PNP_MEM_RANGE_LOW(i) (0x44 + 8*(i)) 17450769Sdfr /*** 17550769Sdfr Four memory resource registers per range, four ranges. 17650769Sdfr Fill with 0 if no ranges are enabled. 17750769Sdfr 17850769Sdfr Offset 0: RW Memory base address bits[23:16] 17950769Sdfr Offset 1: RW Memory base address bits[15:8] 18050769Sdfr Offset 2: Memory control 18150769Sdfr Bit[1] specifies 8/16-bit control. This bit is set to indicate 18250769Sdfr 16-bit memory, and cleared to indicate 8-bit memory. 18350769Sdfr Bit[0], if cleared, indicates the next field can be used as a range 18450769Sdfr length for decode (implies range length and base alignment of memory 18550769Sdfr descriptor are equal). 18650769Sdfr Bit[0], if set, indicates the next field is the upper limit for 18750769Sdfr the address. - - Bit[0] is read-only. 18850769Sdfr Offset 3: RW upper limit or range len, bits[23:16] 18950769Sdfr Offset 4: RW upper limit or range len, bits[15:8] 19050769Sdfr Offset 5-Offset 7: filler, unused. 19150769Sdfr ***/ 19250769Sdfr 19350769Sdfr#define PNP_IO_BASE_HIGH(i) (0x60 + 2*(i)) 19450769Sdfr#define PNP_IO_BASE_LOW(i) (0x61 + 2*(i)) 19550769Sdfr /*** 19650769Sdfr Eight ranges, two bytes per range. 19750769Sdfr Offset 0: I/O port base address bits[15:8] 19850769Sdfr Offset 1: I/O port base address bits[7:0] 19950769Sdfr ***/ 20050769Sdfr 20150769Sdfr#define PNP_IRQ_LEVEL(i) (0x70 + 2*(i)) 20250769Sdfr#define PNP_IRQ_TYPE(i) (0x71 + 2*(i)) 20350769Sdfr /*** 20450769Sdfr Two entries, two bytes per entry. 20550769Sdfr Offset 0: RW interrupt level (1..15, 0=unused). 20650769Sdfr Offset 1: Bit[1]: level(1:hi, 0:low), 20750769Sdfr Bit[0]: type (1:level, 0:edge) 20850769Sdfr byte 1 can be readonly if 1 type of int is used. 20950769Sdfr ***/ 21050769Sdfr 21150769Sdfr#define PNP_DMA_CHANNEL(i) (0x74 + 1*(i)) 21250769Sdfr /*** 21350769Sdfr Two entries, one byte per entry. Bits[2:0] select 21450769Sdfr which DMA channel is in use for DMA 0. Zero selects DMA channel 21550769Sdfr 0, seven selects DMA channel 7. DMA channel 4, the cascade channel 21650769Sdfr is used to indicate no DMA channel is active. 21750769Sdfr ***/ 21850769Sdfr 21950769Sdfr/*** 32-bit memory accesses are at 0x76 ***/ 22050769Sdfr 22150769Sdfr/* Macros to parse Resource IDs */ 22250769Sdfr#define PNP_RES_TYPE(a) (a >> 7) 22350769Sdfr#define PNP_SRES_NUM(a) (a >> 3) 22450769Sdfr#define PNP_SRES_LEN(a) (a & 0x07) 22550769Sdfr#define PNP_LRES_NUM(a) (a & 0x7f) 22650769Sdfr 22750769Sdfr/* Small Resource Item names */ 22850769Sdfr#define PNP_TAG_VERSION 0x1 22950784Speter#define PNP_TAG_LOGICAL_DEVICE 0x2 23050769Sdfr#define PNP_TAG_COMPAT_DEVICE 0x3 23150769Sdfr#define PNP_TAG_IRQ_FORMAT 0x4 23250769Sdfr#define PNP_TAG_DMA_FORMAT 0x5 23350769Sdfr#define PNP_TAG_START_DEPENDANT 0x6 23450769Sdfr#define PNP_TAG_END_DEPENDANT 0x7 23550769Sdfr#define PNP_TAG_IO_RANGE 0x8 23650769Sdfr#define PNP_TAG_IO_FIXED 0x9 23750769Sdfr#define PNP_TAG_RESERVED 0xa-0xd 23850769Sdfr#define PNP_TAG_VENDOR 0xe 23950769Sdfr#define PNP_TAG_END 0xf 24050769Sdfr 24150769Sdfr/* Large Resource Item names */ 24250769Sdfr#define PNP_TAG_MEMORY_RANGE 0x1 24350769Sdfr#define PNP_TAG_ID_ANSI 0x2 24450769Sdfr#define PNP_TAG_ID_UNICODE 0x3 24550769Sdfr#define PNP_TAG_LARGE_VENDOR 0x4 24650769Sdfr#define PNP_TAG_MEMORY32_RANGE 0x5 24750769Sdfr#define PNP_TAG_MEMORY32_FIXED 0x6 24850769Sdfr#define PNP_TAG_LARGE_RESERVED 0x7-0x7f 24950769Sdfr 25050769Sdfr#endif /* !_ISA_PNPREG_H_ */ 251