1146214Snyan/*- 2146214Snyan * Copyright (C) 2005 TAKAHASHI Yoshihiro. All rights reserved. 3146214Snyan * 4146214Snyan * Redistribution and use in source and binary forms, with or without 5146214Snyan * modification, are permitted provided that the following conditions 6146214Snyan * are met: 7146214Snyan * 1. Redistributions of source code must retain the above copyright 8146214Snyan * notice, this list of conditions and the following disclaimer. 9146214Snyan * 2. Redistributions in binary form must reproduce the above copyright 10146214Snyan * notice, this list of conditions and the following disclaimer in the 11146214Snyan * documentation and/or other materials provided with the distribution. 12146214Snyan * 13146214Snyan * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14146214Snyan * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15146214Snyan * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16146214Snyan * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17146214Snyan * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18146214Snyan * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19146214Snyan * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20146214Snyan * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21146214Snyan * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22146214Snyan * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23146214Snyan * SUCH DAMAGE. 24146214Snyan * 25146214Snyan * $FreeBSD$ 26146214Snyan */ 27146214Snyan 28146214Snyan#ifndef _ISA_ISA_DMAREG_H_ 29146214Snyan#define _ISA_ISA_DMAREG_H_ 30146214Snyan 31146214Snyan#include <dev/ic/i8237.h> 32146214Snyan 33146214Snyan#define IO_DMA1 0x00 /* 8237A DMA Controller #1 */ 34146214Snyan#define IO_DMA2 0xC0 /* 8237A DMA Controller #2 */ 35146214Snyan 36146214Snyan/* 37146214Snyan * Register definitions for DMA controller 1 (channels 0..3): 38146214Snyan */ 39146214Snyan#define DMA1_CHN(c) (IO_DMA1 + 1*(2*(c))) /* addr reg for channel c */ 40146214Snyan#define DMA1_STATUS (IO_DMA1 + 1*8) /* status register */ 41146214Snyan#define DMA1_SMSK (IO_DMA1 + 1*10) /* single mask register */ 42146214Snyan#define DMA1_MODE (IO_DMA1 + 1*11) /* mode register */ 43146214Snyan#define DMA1_FFC (IO_DMA1 + 1*12) /* clear first/last FF */ 44146214Snyan#define DMA1_RESET (IO_DMA1 + 1*13) /* reset */ 45146214Snyan 46146214Snyan/* 47146214Snyan * Register definitions for DMA controller 2 (channels 4..7): 48146214Snyan */ 49146214Snyan#define DMA2_CHN(c) (IO_DMA2 + 2*(2*(c))) /* addr reg for channel c */ 50146214Snyan#define DMA2_STATUS (IO_DMA2 + 2*8) /* status register */ 51146214Snyan#define DMA2_SMSK (IO_DMA2 + 2*10) /* single mask register */ 52146214Snyan#define DMA2_MODE (IO_DMA2 + 2*11) /* mode register */ 53146214Snyan#define DMA2_FFC (IO_DMA2 + 2*12) /* clear first/last FF */ 54146214Snyan#define DMA2_RESET (IO_DMA2 + 2*13) /* reset */ 55146214Snyan 56146214Snyan#endif /* _ISA_ISA_DMAREG_H_ */ 57