1/*- 2 * Copyright (c) 2011 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29#include <machine/asm.h> 30#include <machine/ia64_cpu.h> 31#include <machine/pte.h> 32#include <assym.s> 33 34/* 35 * AP wake-up entry point. The handoff state is similar as for the BSP, 36 * as described on page 3-9 of the IPF SAL Specification. The difference 37 * lies in the contents of register b0. For APs this register holds the 38 * return address into the SAL rendezvous routine. 39 * 40 * Note that we're responsible for clearing the IRR bit by reading cr.ivr 41 * and issuing the EOI to the local SAPIC. 42 */ 43 .align 32 44ENTRY_NOPROFILE(os_boot_rendez,0) 45{ .mmi 46 st8 [gp] = gp // trace = 0x00 47 mov r8 = cr.ivr // clear IRR bit 48 add r2 = 8, gp 49 ;; 50} 51{ .mmi 52 srlz.d 53 mov cr.eoi = r0 // ACK the wake-up 54 add r3 = 16, gp 55 ;; 56} 57{ .mmi 58 srlz.d 59 rsm IA64_PSR_IC | IA64_PSR_I 60 mov r16 = (IA64_PBVM_RR << 8) | (IA64_PBVM_PAGE_SHIFT << 2) 61 ;; 62} 63{ .mmi 64 srlz.d 65 st8 [gp] = r2 // trace = 0x08 66 dep.z r17 = IA64_PBVM_RR, 61, 3 67 ;; 68} 69{ .mlx 70 mov rr[r17] = r16 71 movl r18 = IA64_PBVM_PGTBL 72 ;; 73} 74{ .mmi 75 srlz.i 76 ;; 77 st8 [gp] = r3 // trace = 0x10 78 nop 0 79 ;; 80} 81{ .mmi 82 ld8 r16 = [r2], 16 // as_pgtbl_pte 83 ld8 r17 = [r3], 16 // as_pgtbl_itir 84 nop 0 85 ;; 86} 87{ .mmi 88 mov cr.itir = r17 89 mov cr.ifa = r18 90 nop 0 91 ;; 92} 93{ .mmi 94 srlz.d 95 ptr.d r18, r17 96 nop 0 97 ;; 98} 99{ .mmi 100 srlz.d 101 st8 [gp] = r2 // trace = 0x18 102 mov r8 = r0 103 ;; 104} 105{ .mmi 106 itr.d dtr[r8] = r16 107 ;; 108 srlz.d 109 mov r9 = r0 110 ;; 111} 112{ .mmi 113 ld8 r16 = [r2], 16 // as_text_va 114 st8 [gp] = r3 // trace = 0x20 115 add r8 = 1, r8 116 ;; 117} 118{ .mmi 119 ld8 r17 = [r3], 16 // as_text_pte 120 ld8 r18 = [r2], 16 // as_text_itir 121 nop 0 122 ;; 123} 124{ .mmi 125 mov cr.ifa = r16 126 mov cr.itir = r18 127 nop 0 128 ;; 129} 130{ .mmi 131 srlz.d 132 ptr.d r16, r18 133 nop 0 134 ;; 135} 136{ .mmi 137 srlz.d 138 st8 [gp] = r3 // trace = 0x30 139 nop 0 140 ;; 141} 142{ .mmi 143 itr.d dtr[r8] = r17 144 ;; 145 srlz.d 146 nop 0 147} 148{ .mmi 149 st8 [gp] = r2 // trace = 0x38 150 ptr.i r16, r18 151 add r8 = 1, r8 152 ;; 153} 154{ .mmi 155 srlz.i 156 ;; 157 itr.i itr[r9] = r17 158 nop 0 159 ;; 160} 161{ .mmi 162 srlz.i 163 ;; 164 ld8 r16 = [r3], 16 // as_data_va 165 add r9 = 1, r9 166 ;; 167} 168{ .mmi 169 st8 [gp] = r3 // trace = 0x40 170 ld8 r17 = [r2], 16 // as_data_pte 171 nop 0 172 ;; 173} 174{ .mmi 175 mov cr.ifa = r16 176 ld8 r18 = [r3], 16 // as_data_itir 177 nop 0 178 ;; 179} 180{ .mmi 181 mov cr.itir = r18 182 ;; 183 srlz.d 184 nop 0 185 ;; 186} 187{ .mmi 188 ptr.d r16, r18 189 ;; 190 srlz.d 191 mov r19 = IA64_DCR_DEFAULT 192 ;; 193} 194{ .mmi 195 itr.d dtr[r8] = r17 196 ;; 197 srlz.d 198 add r8 = 1, r8 199 ;; 200} 201{ .mmi 202 st8 [gp] = r2 // trace = 0x48 203 ;; 204 ld8 r16 = [r2], 16 // as_kstack 205 nop 0 206} 207{ .mmi 208 ld8 r17 = [r3], 16 // as_kstack_top 209 mov cr.dcr = r19 210 nop 0 211 ;; 212} 213{ .mlx 214 srlz.i 215 movl r18 = IA64_PSR_BN | IA64_PSR_IT | IA64_PSR_DT | IA64_PSR_IC | \ 216 IA64_PSR_RT | IA64_PSR_DFH 217 ;; 218} 219{ .mlx 220 mov cr.ipsr = r18 221 movl r19 = ia64_vector_table // set up IVT early 222 ;; 223} 224{ .mlx 225 mov cr.iva = r19 226 movl r18 = 1f 227 ;; 228} 229{ .mmi 230 mov cr.iip = r18 231 mov cr.ifs = r0 232 nop 0 233 ;; 234} 235{ .mmb 236 srlz.d 237 st8 [gp] = r2 // trace = 0x58 238 rfi 239 ;; 240} 241 242 .align 32 2431: 244{ .mlx 245 mov ar.bspstore = r16 246 movl gp = __gp 247 ;; 248} 249{ .mmi 250 loadrs 251 add sp = -16, r17 252 nop 0 253 ;; 254} 255{ .mmi 256 mov ar.rsc = 3 257 ;; 258 alloc r18 = ar.pfs, 0, 0, 0, 0 259 ;; 260} 261{ .mib 262 nop 0 263 nop 0 264 br.call.sptk.few rp = ia64_ap_startup 265 ;; 266} 267 /* NOT REACHED */ 2689: 269{ .mib 270 nop 0 271 nop 0 272 br.sptk 9b 273 ;; 274} 275END(os_boot_rendez) 276