1221167Sgnn/*- 2221167Sgnn * Copyright(c) 2002-2011 Exar Corp. 3221167Sgnn * All rights reserved. 4221167Sgnn * 5221167Sgnn * Redistribution and use in source and binary forms, with or without 6221167Sgnn * modification are permitted provided the following conditions are met: 7221167Sgnn * 8221167Sgnn * 1. Redistributions of source code must retain the above copyright notice, 9221167Sgnn * this list of conditions and the following disclaimer. 10221167Sgnn * 11221167Sgnn * 2. Redistributions in binary form must reproduce the above copyright 12221167Sgnn * notice, this list of conditions and the following disclaimer in the 13221167Sgnn * documentation and/or other materials provided with the distribution. 14221167Sgnn * 15221167Sgnn * 3. Neither the name of the Exar Corporation nor the names of its 16221167Sgnn * contributors may be used to endorse or promote products derived from 17221167Sgnn * this software without specific prior written permission. 18221167Sgnn * 19221167Sgnn * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20221167Sgnn * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21221167Sgnn * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22221167Sgnn * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23221167Sgnn * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24221167Sgnn * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25221167Sgnn * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26221167Sgnn * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27221167Sgnn * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28221167Sgnn * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29221167Sgnn * POSSIBILITY OF SUCH DAMAGE. 30221167Sgnn */ 31221167Sgnn/*$FreeBSD$*/ 32221167Sgnn 33221167Sgnn#ifndef VXGE_HAL_LL_H 34221167Sgnn#define VXGE_HAL_LL_H 35221167Sgnn 36221167Sgnn#include <dev/vxge/include/vxgehal-version.h> 37221167Sgnn#include <dev/vxge/include/vxge-defs.h> 38221167Sgnn#include <dev/vxge/include/vxge-os-pal.h> 39221167Sgnn#include "vxgehal-status.h" 40221167Sgnn#include <dev/vxge/include/vxgehal-types.h> 41221167Sgnn#include <dev/vxge/include/vxge-debug.h> 42221167Sgnn#include <dev/vxge/include/vxge-list.h> 43221167Sgnn#include <dev/vxge/include/vxge-queue.h> 44221167Sgnn#include <dev/vxge/include/vxgehal-config.h> 45221167Sgnn#include <dev/vxge/include/vxgehal-stats.h> 46221167Sgnn#include <dev/vxge/include/vxgehal-mgmt.h> 47221167Sgnn#include <dev/vxge/include/vxgehal-mgmtaux.h> 48221167Sgnn 49221167Sgnn__EXTERN_BEGIN_DECLS 50221167Sgnn 51221167Sgnn/* 52221167Sgnn * Driver 53221167Sgnn */ 54221167Sgnn 55221167Sgnn/* 56221167Sgnn * enum vxge_hal_xpak_alarm_type_e - XPAK Alarm types 57221167Sgnn * @VXGE_HAL_XPAK_ALARM_EXCESS_TEMP: Excess temparature alarm 58221167Sgnn * @VXGE_HAL_XPAK_ALARM_EXCESS_BIAS_CURRENT: Excess bias current alarm 59221167Sgnn * @VXGE_HAL_XPAK_ALARM_EXCESS_LASER_OUTPUT: Excess laser output alarm 60221167Sgnn * 61221167Sgnn * XPAK alarm types 62221167Sgnn */ 63221167Sgnntypedef enum vxge_hal_xpak_alarm_type_e { 64221167Sgnn VXGE_HAL_XPAK_ALARM_EXCESS_TEMP = 1, 65221167Sgnn VXGE_HAL_XPAK_ALARM_EXCESS_BIAS_CURRENT = 2, 66221167Sgnn VXGE_HAL_XPAK_ALARM_EXCESS_LASER_OUTPUT = 3, 67221167Sgnn} vxge_hal_xpak_alarm_type_e; 68221167Sgnn 69221167Sgnn/* 70221167Sgnn * function vxge_uld_sched_timer_cb_f - Per-device periodic timer 71221167Sgnn * callback. 72221167Sgnn * @devh: HAL device handle. 73221167Sgnn * @userdata: Per-device user data (a.k.a. context) specified via 74221167Sgnn * vxge_hal_device_initialize(). 75221167Sgnn * 76221167Sgnn * Periodic or one-shot timer callback. If specified (that is, not NULL) 77221167Sgnn * HAL invokes this callback periodically. The call is performed in the 78221167Sgnn * interrupt context, or more exactly, in the context of HAL's ISR 79221167Sgnn * vxge_hal_device_continue_irq(). 80221167Sgnn * 81221167Sgnn * See also: vxge_hal_device_initialize {} 82221167Sgnn */ 83221167Sgnntypedef void (*vxge_uld_sched_timer_cb_f) ( 84221167Sgnn vxge_hal_device_h devh, 85221167Sgnn void *userdata); 86221167Sgnn 87221167Sgnn/* 88221167Sgnn * function vxge_uld_link_up_f - Link-Up callback provided by upper-layer 89221167Sgnn * driver. 90221167Sgnn * @devh: HAL device handle. 91221167Sgnn * @userdata: Opaque context set by the ULD via 92221167Sgnn * vxge_hal_device_private_set() 93221167Sgnn * (typically - at HAL device iinitialization time). 94221167Sgnn * 95221167Sgnn * Link-up notification callback provided by the ULD. 96221167Sgnn * This is one of the per-driver callbacks, see vxge_hal_uld_cbs_t {}. 97221167Sgnn * 98221167Sgnn * See also: vxge_hal_uld_cbs_t {}, vxge_uld_link_down_f {}, 99221167Sgnn * vxge_hal_driver_initialize(), vxge_hal_device_private_set(). 100221167Sgnn */ 101221167Sgnntypedef void (*vxge_uld_link_up_f) ( 102221167Sgnn vxge_hal_device_h devh, 103221167Sgnn void *userdata); 104221167Sgnn 105221167Sgnn/* 106221167Sgnn * function vxge_uld_link_down_f - Link-Down callback provided by 107221167Sgnn * upper-layer driver. 108221167Sgnn * @devh: HAL device handle. 109221167Sgnn * @userdata: Opaque context set by the ULD via 110221167Sgnn * vxge_hal_device_private_set() 111221167Sgnn * (typically - at HAL device iinitialization time). 112221167Sgnn * 113221167Sgnn * Link-Down notification callback provided by the upper-layer driver. 114221167Sgnn * This is one of the per-driver callbacks, see vxge_hal_uld_cbs_t {}. 115221167Sgnn * 116221167Sgnn * See also: vxge_hal_uld_cbs_t {}, vxge_uld_link_up_f {}, 117221167Sgnn * vxge_hal_driver_initialize(), vxge_hal_device_private_set(). 118221167Sgnn */ 119221167Sgnntypedef void (*vxge_uld_link_down_f) ( 120221167Sgnn vxge_hal_device_h devh, 121221167Sgnn void *userdata); 122221167Sgnn 123221167Sgnn/* 124221167Sgnn * function vxge_uld_crit_err_f - Critical Error notification callback. 125221167Sgnn * @devh: HAL device handle. 126221167Sgnn * @userdata: Opaque context set by the ULD via 127221167Sgnn * vxge_hal_device_private_set() 128221167Sgnn * (typically - at HAL device iinitialization time). 129221167Sgnn * @type: Enumerated hw error, e.g.: double ECC. 130221167Sgnn * @serr_data: X3100 status. 131221167Sgnn * @ext_data: Extended data. The contents depends on the @type. 132221167Sgnn * 133221167Sgnn * Critical error notification callback provided by the upper-layer driver. 134221167Sgnn * This is one of the per-driver callbacks, see vxge_hal_uld_cbs_t {}. 135221167Sgnn * 136221167Sgnn * See also: vxge_hal_uld_cbs_t {}, vxge_hal_event_e {}, 137221167Sgnn * vxge_hal_device_private_set(), vxge_hal_driver_initialize(). 138221167Sgnn */ 139221167Sgnntypedef void (*vxge_uld_crit_err_f) ( 140221167Sgnn vxge_hal_device_h devh, 141221167Sgnn void *userdata, 142221167Sgnn vxge_hal_event_e type, 143221167Sgnn u64 ext_data); 144221167Sgnn 145221167Sgnn/* 146221167Sgnn * function vxge_uld_xpak_alarm_log_f - ULD "XPAK alarm log" callback. 147221167Sgnn * @devh: HAL device handle. 148221167Sgnn * @port: Port number 149221167Sgnn * @type: XPAK Alarm type 150221167Sgnn * 151221167Sgnn * Unless NULL is specified, HAL invokes the callback after checking XPAK 152221167Sgnn * counters 153221167Sgnn */ 154221167Sgnntypedef void (*vxge_uld_xpak_alarm_log_f) ( 155221167Sgnn vxge_hal_device_h devh, 156221167Sgnn u32 port, 157221167Sgnn vxge_hal_xpak_alarm_type_e type); 158221167Sgnn 159221167Sgnn/* 160221167Sgnn * struct vxge_hal_uld_cbs_t - Upper-layer driver "slow-path" callbacks. 161221167Sgnn * @link_up: See vxge_uld_link_up_f {}. 162221167Sgnn * @link_down: See vxge_uld_link_down_f {}. 163221167Sgnn * @crit_err: See vxge_uld_crit_err_f {}. 164221167Sgnn * @sched_timer: See vxge_uld_sched_timer_cb_f {}. 165221167Sgnn * @xpak_alarm_log: 166221167Sgnn * 167221167Sgnn * Upper layer driver slow-path (per-driver) callbacks. 168221167Sgnn * Implemented by ULD and provided to HAL via 169221167Sgnn * vxge_hal_driver_initialize(). 170221167Sgnn * Note that these callbacks are not mandatory: HAL will not invoke 171221167Sgnn * a callback if NULL is specified. 172221167Sgnn * 173221167Sgnn * See also: vxge_hal_driver_initialize(). 174221167Sgnn */ 175221167Sgnntypedef struct vxge_hal_uld_cbs_t { 176221167Sgnn vxge_uld_link_up_f link_up; 177221167Sgnn vxge_uld_link_down_f link_down; 178221167Sgnn vxge_uld_crit_err_f crit_err; 179221167Sgnn vxge_uld_sched_timer_cb_f sched_timer; 180221167Sgnn vxge_uld_xpak_alarm_log_f xpak_alarm_log; 181221167Sgnn} vxge_hal_uld_cbs_t; 182221167Sgnn 183221167Sgnn/* 184221167Sgnn * vxge_hal_driver_initialize - Initialize HAL. 185221167Sgnn * @config: HAL configuration, see vxge_hal_driver_config_t {}. 186221167Sgnn * @uld_callbacks: Upper-layer driver callbacks, e.g. link-up. 187221167Sgnn * 188221167Sgnn * HAL initialization entry point. Not to confuse with device initialization 189221167Sgnn * (note that HAL "contains" zero or more X3100 devices). 190221167Sgnn * 191221167Sgnn * Returns: VXGE_HAL_OK - success; 192221167Sgnn * VXGE_HAL_ERR_BAD_DRIVER_CONFIG - Driver configuration params invalid. 193221167Sgnn * 194221167Sgnn */ 195221167Sgnnvxge_hal_status_e 196221167Sgnnvxge_hal_driver_initialize( 197221167Sgnn vxge_hal_driver_config_t *config, 198221167Sgnn vxge_hal_uld_cbs_t *uld_callbacks); 199221167Sgnn 200221167Sgnn/* 201221167Sgnn * vxge_hal_driver_debug_set - Set the debug module, level and timestamp 202221167Sgnn * @level: Debug level as defined in enum vxge_debug_level_e 203221167Sgnn * 204221167Sgnn * This routine is used to dynamically change the debug output 205221167Sgnn */ 206221167Sgnnvoid 207221167Sgnnvxge_hal_driver_debug_set( 208221167Sgnn vxge_debug_level_e level); 209221167Sgnn 210221167Sgnn/* 211221167Sgnn * vxge_hal_driver_debug_get - Get the debug level 212221167Sgnn * 213221167Sgnn * This routine returns the current debug level set 214221167Sgnn */ 215221167Sgnnu32 216221167Sgnnvxge_hal_driver_debug_get(void); 217221167Sgnn 218221167Sgnn/* 219221167Sgnn * vxge_hal_driver_terminate - Terminate HAL. 220221167Sgnn * 221221167Sgnn * HAL termination entry point. 222221167Sgnn */ 223221167Sgnnvoid 224221167Sgnnvxge_hal_driver_terminate(void); 225221167Sgnn 226221167Sgnnvoid * 227221167Sgnnvxge_hal_device_get_legacy_reg(pci_dev_h pdev, pci_reg_h regh, u8 *bar0); 228221167Sgnn 229221167Sgnn/* 230221167Sgnn * RX Descriptor 231221167Sgnn */ 232221167Sgnn/* 233221167Sgnn * enum vxge_hal_rxd_state_e - Descriptor (RXD) state. 234221167Sgnn * @VXGE_HAL_RXD_STATE_NONE: Invalid state. 235221167Sgnn * @VXGE_HAL_RXD_STATE_AVAIL: Descriptor is available for reservation. 236221167Sgnn * @VXGE_HAL_RXD_STATE_POSTED: Descriptor is posted for processing by the 237221167Sgnn * device. 238221167Sgnn * @VXGE_HAL_RXD_STATE_FREED: Descriptor is free and can be reused for 239221167Sgnn * filling-in and posting later. 240221167Sgnn * 241221167Sgnn * X3100/HAL descriptor states. 242221167Sgnn * 243221167Sgnn */ 244221167Sgnntypedef enum vxge_hal_rxd_state_e { 245221167Sgnn VXGE_HAL_RXD_STATE_NONE = 0, 246221167Sgnn VXGE_HAL_RXD_STATE_AVAIL = 1, 247221167Sgnn VXGE_HAL_RXD_STATE_POSTED = 2, 248221167Sgnn VXGE_HAL_RXD_STATE_FREED = 3 249221167Sgnn} vxge_hal_rxd_state_e; 250221167Sgnn 251221167Sgnn/* 252221167Sgnn * Ring 253221167Sgnn */ 254221167Sgnn 255221167Sgnn/* 256221167Sgnn * struct vxge_hal_ring_rxd_info_t - Extended information associated with a 257221167Sgnn * completed ring descriptor. 258221167Sgnn * @syn_flag: SYN flag 259221167Sgnn * @is_icmp: Is ICMP 260221167Sgnn * @fast_path_eligible: Fast Path Eligible flag 261221167Sgnn * @l3_cksum_valid: in L3 checksum is valid 262221167Sgnn * @l3_cksum: Result of IP checksum check (by X3100 hardware). 263221167Sgnn * This field containing VXGE_HAL_L3_CKSUM_OK would mean that 264221167Sgnn * the checksum is correct, otherwise - the datagram is 265221167Sgnn * corrupted. 266221167Sgnn * @l4_cksum_valid: in L4 checksum is valid 267221167Sgnn * @l4_cksum: Result of TCP/UDP checksum check (by X3100 hardware). 268221167Sgnn * This field containing VXGE_HAL_L4_CKSUM_OK would mean that 269221167Sgnn * the checksum is correct. Otherwise - the packet is 270221167Sgnn * corrupted. 271221167Sgnn * @frame: Zero or more of vxge_hal_frame_type_e flags. 272221167Sgnn * See vxge_hal_frame_type_e {}. 273221167Sgnn * @proto: zero or more of vxge_hal_frame_proto_e flags. Reporting bits for 274221167Sgnn * various higher-layer protocols, including (but note restricted to) 275221167Sgnn * TCP and UDP. See vxge_hal_frame_proto_e {}. 276221167Sgnn * @is_vlan: If vlan tag is valid 277221167Sgnn * @vlan: VLAN tag extracted from the received frame. 278221167Sgnn * @rth_bucket: RTH bucket 279221167Sgnn * @rth_it_hit: Set, If RTH hash value calculated by the X3100 hardware 280221167Sgnn * has a matching entry in the Indirection table. 281221167Sgnn * @rth_spdm_hit: Set, If RTH hash value calculated by the X3100 hardware 282221167Sgnn * has a matching entry in the Socket Pair Direct Match table. 283221167Sgnn * @rth_hash_type: RTH hash code of the function used to calculate the hash. 284221167Sgnn * @rth_value: Receive Traffic Hashing(RTH) hash value. Produced by X3100 285221167Sgnn * hardware if RTH is enabled. 286221167Sgnn */ 287221167Sgnntypedef struct vxge_hal_ring_rxd_info_t { 288221167Sgnn u32 syn_flag; 289221167Sgnn u32 is_icmp; 290221167Sgnn u32 fast_path_eligible; 291221167Sgnn u32 l3_cksum_valid; 292221167Sgnn u32 l3_cksum; 293221167Sgnn u32 l4_cksum_valid; 294221167Sgnn u32 l4_cksum; 295221167Sgnn u32 frame; 296221167Sgnn u32 proto; 297221167Sgnn u32 is_vlan; 298221167Sgnn#define VXGE_HAL_VLAN_VID_MASK 0xfff 299221167Sgnn u32 vlan; 300221167Sgnn u32 rth_bucket; 301221167Sgnn u32 rth_it_hit; 302221167Sgnn u32 rth_spdm_hit; 303221167Sgnn u32 rth_hash_type; 304221167Sgnn u32 rth_value; 305221167Sgnn} vxge_hal_ring_rxd_info_t; 306221167Sgnn 307221167Sgnn/* 308221167Sgnn * enum vxge_hal_frame_type_e - Ethernet frame format. 309221167Sgnn * @VXGE_HAL_FRAME_TYPE_DIX: DIX (Ethernet II) format. 310221167Sgnn * @VXGE_HAL_FRAME_TYPE_LLC: LLC format. 311221167Sgnn * @VXGE_HAL_FRAME_TYPE_SNAP: SNAP format. 312221167Sgnn * @VXGE_HAL_FRAME_TYPE_IPX: IPX format. 313221167Sgnn * 314221167Sgnn * Ethernet frame format. 315221167Sgnn */ 316221167Sgnntypedef enum vxge_hal_frame_type_e { 317221167Sgnn VXGE_HAL_FRAME_TYPE_DIX = 0x0, 318221167Sgnn VXGE_HAL_FRAME_TYPE_LLC = 0x1, 319221167Sgnn VXGE_HAL_FRAME_TYPE_SNAP = 0x2, 320221167Sgnn VXGE_HAL_FRAME_TYPE_IPX = 0x3, 321221167Sgnn} vxge_hal_frame_type_e; 322221167Sgnn 323221167Sgnntypedef enum vxge_hal_tcp_option_e { 324221167Sgnn 325221167Sgnn VXGE_HAL_TCPOPT_NOP = 1, /* Padding */ 326221167Sgnn VXGE_HAL_TCPOPT_EOL = 0, /* End of options */ 327221167Sgnn VXGE_HAL_TCPOPT_MSS = 2, /* Segment size negotiating */ 328221167Sgnn VXGE_HAL_TCPOPT_WINDOW = 3, /* Window scaling */ 329221167Sgnn VXGE_HAL_TCPOPT_SACK_PERM = 4, /* SACK Permitted */ 330221167Sgnn VXGE_HAL_TCPOPT_SACK = 5, /* SACK Block */ 331221167Sgnn VXGE_HAL_TCPOPT_TIMESTAMP = 8, /* Better RTT estimations/PAWS */ 332221167Sgnn VXGE_HAL_TCPOPT_MD5SIG = 19, /* MD5 Signature (RFC2385) */ 333221167Sgnn VXGE_HAL_TCPOLEN_TIMESTAMP = 10, 334221167Sgnn VXGE_HAL_TCPOLEN_TSTAMP_ALIGNED = 12 335221167Sgnn 336221167Sgnn} vxge_hal_tcp_option_e; 337221167Sgnn 338221167Sgnn/* 339221167Sgnn * enum vxge_hal_frame_proto_e - Higher-layer ethernet protocols. 340221167Sgnn * @VXGE_HAL_FRAME_PROTO_VLAN_TAGGED: VLAN. 341221167Sgnn * @VXGE_HAL_FRAME_PROTO_IPV4: IPv4. 342221167Sgnn * @VXGE_HAL_FRAME_PROTO_IPV6: IPv6. 343221167Sgnn * @VXGE_HAL_FRAME_PROTO_IP_FRAG: IP fragmented. 344221167Sgnn * @VXGE_HAL_FRAME_PROTO_TCP: TCP. 345221167Sgnn * @VXGE_HAL_FRAME_PROTO_UDP: UDP. 346221167Sgnn * @VXGE_HAL_FRAME_PROTO_TCP_OR_UDP: TCP or UDP. 347221167Sgnn * 348221167Sgnn * Higher layer ethernet protocols and options. 349221167Sgnn */ 350221167Sgnntypedef enum vxge_hal_frame_proto_e { 351221167Sgnn VXGE_HAL_FRAME_PROTO_VLAN_TAGGED = 0x80, 352221167Sgnn VXGE_HAL_FRAME_PROTO_IPV4 = 0x10, 353221167Sgnn VXGE_HAL_FRAME_PROTO_IPV6 = 0x08, 354221167Sgnn VXGE_HAL_FRAME_PROTO_IP_FRAG = 0x04, 355221167Sgnn VXGE_HAL_FRAME_PROTO_TCP = 0x02, 356221167Sgnn VXGE_HAL_FRAME_PROTO_UDP = 0x01, 357221167Sgnn VXGE_HAL_FRAME_PROTO_TCP_OR_UDP = (VXGE_HAL_FRAME_PROTO_TCP | \ 358221167Sgnn VXGE_HAL_FRAME_PROTO_UDP) 359221167Sgnn} vxge_hal_frame_proto_e; 360221167Sgnn 361221167Sgnn/* 362221167Sgnn * enum vxge_hal_ring_tcode_e - Transfer codes returned by adapter 363221167Sgnn * @VXGE_HAL_RING_T_CODE_OK: Transfer ok. 364221167Sgnn * @VXGE_HAL_RING_T_CODE_L3_CKSUM_MISMATCH: Layer 3 checksum presentation 365221167Sgnn * configuration mismatch. 366221167Sgnn * @VXGE_HAL_RING_T_CODE_L4_CKSUM_MISMATCH: Layer 4 checksum presentation 367221167Sgnn * configuration mismatch. 368221167Sgnn * @VXGE_HAL_RING_T_CODE_L3_L4_CKSUM_MISMATCH: Layer 3 and Layer 4 checksum 369221167Sgnn * presentation configuration mismatch. 370230135Suqs * @VXGE_HAL_RING_T_CODE_L3_PKT_ERR: Layer 3 error: unparseable packet, 371221167Sgnn * such as unknown IPv6 header. 372230135Suqs * @VXGE_HAL_RING_T_CODE_L2_FRM_ERR: Layer 2 error: frame integrity 373221167Sgnn * error, such as FCS or ECC). 374230135Suqs * @VXGE_HAL_RING_T_CODE_BUF_SIZE_ERR: Buffer size error: the RxD buffer(s) 375230135Suqs * were not appropriately sized and data loss occurred. 376230135Suqs * @VXGE_HAL_RING_T_CODE_INT_ECC_ERR: Internal ECC error: RxD corrupted. 377230135Suqs * @VXGE_HAL_RING_T_CODE_BENIGN_OVFLOW: Benign overflow: the contents of 378221167Sgnn * Segment1 exceeded the capacity of Buffer1 and the remainder 379221167Sgnn * was placed in Buffer2. Segment2 now starts in Buffer3. 380221167Sgnn * No data loss or errors occurred. 381230135Suqs * @VXGE_HAL_RING_T_CODE_ZERO_LEN_BUFF: Buffer size 0: one of the RxDs 382221167Sgnn * assigned buffers has a size of 0 bytes. 383230135Suqs * @VXGE_HAL_RING_T_CODE_FRM_DROP: Frame dropped: either due to 384221167Sgnn * VPath Reset or because of a VPIN mismatch. 385221167Sgnn * @VXGE_HAL_RING_T_CODE_UNUSED: Unused 386230135Suqs * @VXGE_HAL_RING_T_CODE_MULTI_ERR: Multiple errors: more than one 387221167Sgnn * transfer code condition occurred. 388221167Sgnn * 389221167Sgnn * Transfer codes returned by adapter. 390221167Sgnn */ 391221167Sgnntypedef enum vxge_hal_ring_tcode_e { 392221167Sgnn VXGE_HAL_RING_T_CODE_OK = 0x0, 393221167Sgnn VXGE_HAL_RING_T_CODE_L3_CKSUM_MISMATCH = 0x1, 394221167Sgnn VXGE_HAL_RING_T_CODE_L4_CKSUM_MISMATCH = 0x2, 395221167Sgnn VXGE_HAL_RING_T_CODE_L3_L4_CKSUM_MISMATCH = 0x3, 396221167Sgnn VXGE_HAL_RING_T_CODE_L3_PKT_ERR = 0x5, 397221167Sgnn VXGE_HAL_RING_T_CODE_L2_FRM_ERR = 0x6, 398221167Sgnn VXGE_HAL_RING_T_CODE_BUF_SIZE_ERR = 0x7, 399221167Sgnn VXGE_HAL_RING_T_CODE_INT_ECC_ERR = 0x8, 400221167Sgnn VXGE_HAL_RING_T_CODE_BENIGN_OVFLOW = 0x9, 401221167Sgnn VXGE_HAL_RING_T_CODE_ZERO_LEN_BUFF = 0xA, 402221167Sgnn VXGE_HAL_RING_T_CODE_FRM_DROP = 0xC, 403221167Sgnn VXGE_HAL_RING_T_CODE_UNUSED = 0xE, 404221167Sgnn VXGE_HAL_RING_T_CODE_MULTI_ERR = 0xF 405221167Sgnn} vxge_hal_ring_tcode_e; 406221167Sgnn 407221167Sgnn/* 408221167Sgnn * enum vxge_hal_ring_hash_type_e - RTH hash types 409221167Sgnn * @VXGE_HAL_RING_HASH_TYPE_NONE: No Hash 410221167Sgnn * @VXGE_HAL_RING_HASH_TYPE_TCP_IPV4: TCP IPv4 411221167Sgnn * @VXGE_HAL_RING_HASH_TYPE_UDP_IPV4: UDP IPv4 412221167Sgnn * @VXGE_HAL_RING_HASH_TYPE_IPV4: IPv4 413221167Sgnn * @VXGE_HAL_RING_HASH_TYPE_TCP_IPV6: TCP IPv6 414221167Sgnn * @VXGE_HAL_RING_HASH_TYPE_UDP_IPV6: UDP IPv6 415221167Sgnn * @VXGE_HAL_RING_HASH_TYPE_IPV6: IPv6 416221167Sgnn * @VXGE_HAL_RING_HASH_TYPE_TCP_IPV6_EX: TCP IPv6 extension 417221167Sgnn * @VXGE_HAL_RING_HASH_TYPE_UDP_IPV6_EX: UDP IPv6 extension 418221167Sgnn * @VXGE_HAL_RING_HASH_TYPE_IPV6_EX: IPv6 extension 419221167Sgnn * 420221167Sgnn * RTH hash types 421221167Sgnn */ 422221167Sgnntypedef enum vxge_hal_ring_hash_type_e { 423221167Sgnn VXGE_HAL_RING_HASH_TYPE_NONE = 0x0, 424221167Sgnn VXGE_HAL_RING_HASH_TYPE_TCP_IPV4 = 0x1, 425221167Sgnn VXGE_HAL_RING_HASH_TYPE_UDP_IPV4 = 0x2, 426221167Sgnn VXGE_HAL_RING_HASH_TYPE_IPV4 = 0x3, 427221167Sgnn VXGE_HAL_RING_HASH_TYPE_TCP_IPV6 = 0x4, 428221167Sgnn VXGE_HAL_RING_HASH_TYPE_UDP_IPV6 = 0x5, 429221167Sgnn VXGE_HAL_RING_HASH_TYPE_IPV6 = 0x6, 430221167Sgnn VXGE_HAL_RING_HASH_TYPE_TCP_IPV6_EX = 0x7, 431221167Sgnn VXGE_HAL_RING_HASH_TYPE_UDP_IPV6_EX = 0x8, 432221167Sgnn VXGE_HAL_RING_HASH_TYPE_IPV6_EX = 0x9 433221167Sgnn} vxge_hal_ring_hash_type_e; 434221167Sgnn 435221167Sgnn/* 436221167Sgnn * struct vxge_hal_ring_rxd_1_t - One buffer mode RxD for ring 437221167Sgnn * @host_control: This field is exclusively for host use and is "readonly" 438221167Sgnn * from the adapter's perspective. 439221167Sgnn * @control_0:Bits 0 to 6 - RTH_Bucket get 440221167Sgnn * Bit 7 - Own Descriptor ownership bit. This bit is set to 1 by the 441221167Sgnn * host, and is set to 0 by the adapter. 442221167Sgnn * 0 - Host owns RxD and buffer. 443221167Sgnn * 1 - The adapter owns RxD and buffer. 444221167Sgnn * Bit 8 - Fast_Path_Eligible When set, indicates that the received 445221167Sgnn * frame meets all of the criteria for fast path processing. 446221167Sgnn * The required criteria are as follows: 447221167Sgnn * !SYN & 448221167Sgnn * (Transfer_Code == "Transfer OK") & 449221167Sgnn * (!Is_IP_Fragment) & 450221167Sgnn * ((Is_IPv4 & computed_L3_checksum == 0xFFFF) | 451221167Sgnn * (Is_IPv6)) & 452221167Sgnn * ((Is_TCP & computed_L4_checksum == 0xFFFF) | 453221167Sgnn * (Is_UDP & (computed_L4_checksum == 0xFFFF | 454221167Sgnn * computed _L4_checksum == 0x0000))) 455221167Sgnn * (same meaning for all RxD buffer modes) 456221167Sgnn * Bit 9 - L3 Checksum Correct 457221167Sgnn * Bit 10 - L4 Checksum Correct 458221167Sgnn * Bit 11 - Reserved 459221167Sgnn * Bit 12 to 15 - This field is written by the adapter. It is used 460221167Sgnn * to report the status of the frame transfer to the host. 461221167Sgnn * 0x0 - Transfer OK 462221167Sgnn * 0x4 - RDA Failure During Transfer 463221167Sgnn * 0x5 - Unparseable Packet, such as unknown IPv6 header. 464221167Sgnn * 0x6 - Frame integrity error (FCS or ECC). 465221167Sgnn * 0x7 - Buffer Size Error. The provided buffer(s) were not 466221167Sgnn * appropriately sized and data loss occurred. 467221167Sgnn * 0x8 - Internal ECC Error. RxD corrupted. 468221167Sgnn * 0x9 - IPv4 Checksum error 469221167Sgnn * 0xA - TCP/UDP Checksum error 470221167Sgnn * 0xF - Unknown Error or Multiple Error. Indicates an unknown 471221167Sgnn * problem or that more than one of transfer codes is set. 472221167Sgnn * Bit 16 - SYN The adapter sets this field to indicate that the 473221167Sgnn * incoming frame contained a TCP segment with its SYN bit set 474221167Sgnn * and its ACK bit NOT set. (same meaning for all RxD buffer modes) 475221167Sgnn * Bit 17 - Is ICMP 476221167Sgnn * Bit 18 - RTH_SPDM_HIT Set to 1 if there was a match in the 477221167Sgnn * Socket 478221167Sgnn * Pair Direct Match Table and the frame was steered based on SPDM. 479221167Sgnn * Bit 19 - RTH_IT_HIT Set to 1 if there was a match in the 480221167Sgnn * Indirection Table and the frame was steered based on hash 481221167Sgnn * indirection. 482221167Sgnn * Bit 20 to 23 - RTH_HASH_TYPE Indicates the function (hash type) 483221167Sgnn * that was used to calculate the hash. 484221167Sgnn * Bit 19 - IS_VLAN Set to '1' if the frame was/is VLAN tagged. 485221167Sgnn * Bit 25 to 26 - ETHER_ENCAP Reflects the Ethernet encapsulation 486221167Sgnn * of the received frame. 487221167Sgnn * 0x0 - Ethernet DIX 488221167Sgnn * 0x1 - LLC 489221167Sgnn * 0x2 - SNAP (includes Jumbo-SNAP) 490221167Sgnn * 0x3 - IPX 491221167Sgnn * Bit 27 - IS_IPV4 Set to '1' if the frame contains IPv4 packet. 492221167Sgnn * Bit 28 - IS_IPV6 Set to '1' if the frame contains IPv6 packet. 493221167Sgnn * Bit 29 - IS_IP_FRAG Set to '1' if the frame contains a 494221167Sgnn * fragmented IP packet. 495221167Sgnn * Bit 30 - IS_TCP Set to '1' if the frame contains a TCP segment. 496221167Sgnn * Bit 31 - IS_UDP Set to '1' if the frame contains a UDP message. 497221167Sgnn * Bit 32 to 47 - L3_Checksum[0:15] The IPv4 checksum value that 498221167Sgnn * arrived with the frame. If the resulting computed IPv4 header 499221167Sgnn * checksum for the frame did not produce the expected 0xFFFF value, 500221167Sgnn * then the transfer code would be set to 0x9. 501221167Sgnn * Bit 48 to 63 - L4_Checksum[0:15] TCP/UDP checksum value that 502221167Sgnn * arrived with the frame. If the resulting computed TCP/UDP checksum 503221167Sgnn * for the frame did not produce the expected 0xFFFF value, then the 504221167Sgnn * transfer code would be set to 0xA. 505221167Sgnn * @control_1:Bits 0 to 1 - Reserved 506221167Sgnn * Bits 2 to 15 - Buffer0_Size.This field is set by the host and 507221167Sgnn * eventually overwritten by the adapter. The host writes the 508221167Sgnn * available buffer size in bytes when it passes the descriptor to 509221167Sgnn * the adapter. When a frame is delivered the host, the adapter 510221167Sgnn * populates this field with the number of bytes written into the 511221167Sgnn * buffer. The largest supported buffer is 16, 383 bytes. 512221167Sgnn * Bit 16 to 47 - RTH Hash Value 32-bit RTH hash value. Only valid 513221167Sgnn * if RTH_HASH_TYPE (Control_0, bits 20:23) is nonzero. 514221167Sgnn * Bit 48 to 63 - VLAN_Tag[0:15] The contents of the variable 515221167Sgnn * portion of the VLAN tag, if one was detected by the adapter. 516221167Sgnn * This field is populated even if VLAN-tag stripping is enabled. 517221167Sgnn * @buffer0_ptr: Pointer to buffer. This field is populated by the driver. 518221167Sgnn * 519221167Sgnn * One buffer mode RxD for ring structure 520221167Sgnn */ 521221167Sgnntypedef struct vxge_hal_ring_rxd_1_t { 522221167Sgnn u64 host_control; 523221167Sgnn u64 control_0; 524221167Sgnn#define VXGE_HAL_RING_RXD_RTH_BUCKET_GET(ctrl0) bVAL7(ctrl0, 0) 525221167Sgnn#define VXGE_HAL_RING_RXD_RTH_BUCKET_ADAPTER vBIT(val, 0, 7) 526221167Sgnn 527221167Sgnn#define VXGE_HAL_RING_RXD_LIST_OWN_GET(ctrl0) bVAL1(ctrl0, 7) 528221167Sgnn#define VXGE_HAL_RING_RXD_LIST_OWN_ADAPTER mBIT(7) 529221167Sgnn 530221167Sgnn#define VXGE_HAL_RING_RXD_FAST_PATH_ELIGIBLE_GET(ctrl0) bVAL1(ctrl0, 8) 531221167Sgnn#define VXGE_HAL_RING_RXD_FAST_PATH_ELIGIBLE mBIT(8) 532221167Sgnn 533221167Sgnn#define VXGE_HAL_RING_RXD_L3_CKSUM_CORRECT_GET(ctrl0) bVAL1(ctrl0, 9) 534221167Sgnn#define VXGE_HAL_RING_RXD_L3_CKSUM_CORRECT mBIT(9) 535221167Sgnn 536221167Sgnn#define VXGE_HAL_RING_RXD_L4_CKSUM_CORRECT_GET(ctrl0) bVAL1(ctrl0, 10) 537221167Sgnn#define VXGE_HAL_RING_RXD_L4_CKSUM_CORRECT mBIT(10) 538221167Sgnn 539221167Sgnn#define VXGE_HAL_RING_RXD_T_CODE_GET(ctrl0) bVAL4(ctrl0, 12) 540221167Sgnn#define VXGE_HAL_RING_RXD_T_CODE(val) vBIT(val, 12, 4) 541221167Sgnn#define VXGE_HAL_RING_RXD_T_CODE_OK VXGE_HAL_RING_T_CODE_OK 542221167Sgnn#define VXGE_HAL_RING_RXD_T_CODE_L3_CKSUM_MISMATCH \ 543221167Sgnn VXGE_HAL_RING_T_CODE_L3_CKSUM_MISMATCH 544221167Sgnn#define VXGE_HAL_RING_RXD_T_CODE_L4_CKSUM_MISMATCH \ 545221167Sgnn VXGE_HAL_RING_T_CODE_L4_CKSUM_MISMATCH 546221167Sgnn#define VXGE_HAL_RING_RXD_T_CODE_L3_L4_CKSUM_MISMATCH \ 547221167Sgnn VXGE_HAL_RING_T_CODE_L3_L4_CKSUM_MISMATCH 548221167Sgnn#define VXGE_HAL_RING_RXD_T_CODE_L3_PKT_ERR VXGE_HAL_RING_T_CODE_L3_PKT_ERR 549221167Sgnn#define VXGE_HAL_RING_RXD_T_CODE_L2_FRM_ERR VXGE_HAL_RING_T_CODE_L2_FRM_ERR 550221167Sgnn#define VXGE_HAL_RING_RXD_T_CODE_BUF_SIZE_ERR \ 551221167Sgnn VXGE_HAL_RING_T_CODE_BUF_SIZE_ERR 552221167Sgnn#define VXGE_HAL_RING_RXD_T_CODE_INT_ECC_ERR VXGE_HAL_RING_T_CODE_INT_ECC_ERR 553221167Sgnn#define VXGE_HAL_RING_RXD_T_CODE_BENIGN_OVFLOW \ 554221167Sgnn VXGE_HAL_RING_T_CODE_BENIGN_OVFLOW 555221167Sgnn#define VXGE_HAL_RING_RXD_T_CODE_ZERO_LEN_BUFF \ 556221167Sgnn VXGE_HAL_RING_T_CODE_ZERO_LEN_BUFF 557221167Sgnn#define VXGE_HAL_RING_RXD_T_CODE_FRM_DROP VXGE_HAL_RING_T_CODE_FRM_DROP 558221167Sgnn#define VXGE_HAL_RING_RXD_T_CODE_UNUSED VXGE_HAL_RING_T_CODE_UNUSED 559221167Sgnn#define VXGE_HAL_RING_RXD_T_CODE_MULTI_ERR VXGE_HAL_RING_T_CODE_MULTI_ERR 560221167Sgnn 561221167Sgnn#define VXGE_HAL_RING_RXD_SYN_GET(ctrl0) bVAL1(ctrl0, 16) 562221167Sgnn#define VXGE_HAL_RING_RXD_SYN mBIT(16) 563221167Sgnn 564221167Sgnn#define VXGE_HAL_RING_RXD_IS_ICMP_GET(ctrl0) bVAL1(ctrl0, 17) 565221167Sgnn#define VXGE_HAL_RING_RXD_IS_ICMP mBIT(17) 566221167Sgnn 567221167Sgnn#define VXGE_HAL_RING_RXD_RTH_SPDM_HIT_GET(ctrl0) bVAL1(ctrl0, 18) 568221167Sgnn#define VXGE_HAL_RING_RXD_RTH_SPDM_HIT mBIT(18) 569221167Sgnn 570221167Sgnn#define VXGE_HAL_RING_RXD_RTH_IT_HIT_GET(ctrl0) bVAL1(ctrl0, 19) 571221167Sgnn#define VXGE_HAL_RING_RXD_RTH_IT_HIT mBIT(19) 572221167Sgnn 573221167Sgnn#define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_GET(ctrl0) bVAL4(ctrl0, 20) 574221167Sgnn#define VXGE_HAL_RING_RXD_RTH_HASH_TYPE(val) vBIT(val, 20, 4) 575221167Sgnn#define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_NONE VXGE_HAL_RING_HASH_TYPE_NONE 576221167Sgnn#define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_TCP_IPV4 \ 577221167Sgnn VXGE_HAL_RING_HASH_TYPE_TCP_IPV4 578221167Sgnn#define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_UDP_IPV4 \ 579221167Sgnn VXGE_HAL_RING_HASH_TYPE_UDP_IPV4 580221167Sgnn#define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_IPV4 VXGE_HAL_RING_HASH_TYPE_IPV4 581221167Sgnn#define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_TCP_IPV6 \ 582221167Sgnn VXGE_HAL_RING_HASH_TYPE_TCP_IPV6 583221167Sgnn#define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_UDP_IPV6 \ 584221167Sgnn VXGE_HAL_RING_HASH_TYPE_UDP_IPV6 585221167Sgnn#define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_IPV6 VXGE_HAL_RING_HASH_TYPE_IPV6 586221167Sgnn#define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_TCP_IPV6_EX \ 587221167Sgnn VXGE_HAL_RING_HASH_TYPE_TCP_IPV6_EX 588221167Sgnn#define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_UDP_IPV6_EX \ 589221167Sgnn VXGE_HAL_RING_HASH_TYPE_UDP_IPV6_EX 590221167Sgnn#define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_IPV6_EX VXGE_HAL_RING_HASH_TYPE_IPV6_EX 591221167Sgnn 592221167Sgnn#define VXGE_HAL_RING_RXD_IS_VLAN_GET(ctrl0) bVAL1(ctrl0, 24) 593221167Sgnn#define VXGE_HAL_RING_RXD_IS_VLAN mBIT(24) 594221167Sgnn 595221167Sgnn#define VXGE_HAL_RING_RXD_ETHER_ENCAP_GET(ctrl0) bVAL2(ctrl0, 25) 596221167Sgnn#define VXGE_HAL_RING_RXD_ETHER_ENCAP(val) vBIT(val, 25, 2) 597221167Sgnn#define VXGE_HAL_RING_RXD_ETHER_ENCAP_DIX VXGE_HAL_FRAME_TYPE_DIX 598221167Sgnn#define VXGE_HAL_RING_RXD_ETHER_ENCAP_LLC VXGE_HAL_FRAME_TYPE_LLC 599221167Sgnn#define VXGE_HAL_RING_RXD_ETHER_ENCAP_SNAP VXGE_HAL_FRAME_TYPE_SNAP 600221167Sgnn#define VXGE_HAL_RING_RXD_ETHER_ENCAP_IPX VXGE_HAL_FRAME_TYPE_IPX 601221167Sgnn 602221167Sgnn#define VXGE_HAL_RING_RXD_IS_IPV4_GET(ctrl0) bVAL1(ctrl0, 27) 603221167Sgnn#define VXGE_HAL_RING_RXD_IS_IPV4 mBIT(27) 604221167Sgnn 605221167Sgnn#define VXGE_HAL_RING_RXD_IS_IPV6_GET(ctrl0) bVAL1(ctrl0, 28) 606221167Sgnn#define VXGE_HAL_RING_RXD_IS_IPV6 mBIT(28) 607221167Sgnn 608221167Sgnn#define VXGE_HAL_RING_RXD_IS_IPV_FRAG_GET(ctrl0) bVAL1(ctrl0, 29) 609221167Sgnn#define VXGE_HAL_RING_RXD_IS_IPV_FRAG mBIT(29) 610221167Sgnn 611221167Sgnn#define VXGE_HAL_RING_RXD_IS_TCP_GET(ctrl0) bVAL1(ctrl0, 30) 612221167Sgnn#define VXGE_HAL_RING_RXD_IS_TCP mBIT(30) 613221167Sgnn 614221167Sgnn#define VXGE_HAL_RING_RXD_IS_UDP_GET(ctrl0) bVAL1(ctrl0, 31) 615221167Sgnn#define VXGE_HAL_RING_RXD_IS_UDP mBIT(31) 616221167Sgnn 617221167Sgnn#define VXGE_HAL_RING_RXD_FRAME_PROTO_GET(ctrl0) bVAL5(ctrl0, 27) 618221167Sgnn#define VXGE_HAL_RING_RXD_FRAME_PROTO(val) vBIT(val, 27, 5) 619221167Sgnn#define VXGE_HAL_RING_RXD_FRAME_PROTO_IPV4 VXGE_HAL_FRAME_PROTO_IPV4 620221167Sgnn#define VXGE_HAL_RING_RXD_FRAME_PROTO_IPV6 VXGE_HAL_FRAME_PROTO_IPV6 621221167Sgnn#define VXGE_HAL_RING_RXD_FRAME_PROTO_IP_FRAG VXGE_HAL_FRAME_PROTO_IP_FRAG 622221167Sgnn#define VXGE_HAL_RING_RXD_FRAME_PROTO_TCP VXGE_HAL_FRAME_PROTO_TCP 623221167Sgnn#define VXGE_HAL_RING_RXD_FRAME_PROTO_UDP VXGE_HAL_FRAME_PROTO_UDP 624221167Sgnn#define VXGE_HAL_RING_RXD_FRAME_PROTO_TCP_OR_UDP (VXGE_HAL_FRAME_PROTO_TCP |\ 625221167Sgnn VXGE_HAL_FRAME_PROTO_UDP) 626221167Sgnn 627221167Sgnn#define VXGE_HAL_RING_RXD_L3_CKSUM_GET(ctrl0) bVAL16(ctrl0, 32) 628221167Sgnn#define VXGE_HAL_RING_RXD_L3_CKSUM(val) vBIT(val, 32, 16) 629221167Sgnn 630221167Sgnn#define VXGE_HAL_RING_RXD_L4_CKSUM_GET(ctrl0) bVAL16(ctrl0, 48) 631221167Sgnn#define VXGE_HAL_RING_RXD_L4_CKSUM(val) vBIT(val, 48, 16) 632221167Sgnn 633221167Sgnn u64 control_1; 634221167Sgnn#define VXGE_HAL_RING_RXD_LIST_TAIL_OWN_ADAPTER mBIT(0) 635221167Sgnn 636221167Sgnn#define VXGE_HAL_RING_RXD_1_BUFFER0_SIZE_GET(ctrl1) bVAL14(ctrl1, 2) 637221167Sgnn#define VXGE_HAL_RING_RXD_1_BUFFER0_SIZE(val) vBIT(val, 2, 14) 638221167Sgnn#define VXGE_HAL_RING_RXD_1_BUFFER0_SIZE_MASK vBIT(0x3FFF, 2, 14) 639221167Sgnn 640221167Sgnn#define VXGE_HAL_RING_RXD_1_RTH_HASH_VAL_GET(ctrl1) bVAL32(ctrl1, 16) 641221167Sgnn#define VXGE_HAL_RING_RXD_1_RTH_HASH_VAL(val) vBIT(val, 16, 32) 642221167Sgnn 643221167Sgnn#define VXGE_HAL_RING_RXD_VLAN_TAG_GET(ctrl1) bVAL16(ctrl1, 48) 644221167Sgnn#define VXGE_HAL_RING_RXD_VLAN_TAG(val) vBIT(val, 48, 16) 645221167Sgnn 646221167Sgnn u64 buffer0_ptr; 647221167Sgnn 648221167Sgnn} vxge_hal_ring_rxd_1_t; 649221167Sgnn 650221167Sgnn/* 651221167Sgnn * struct vxge_hal_ring_rxd_3_t - Three buffer mode RxD for ring 652221167Sgnn * @host_control: This field is exclusively for host use and is "readonly" 653221167Sgnn * from the adapter's perspective. 654221167Sgnn * @control_0:Bits 0 to 6 - RTH_Bucket get 655221167Sgnn * Bit 7 - Own Descriptor ownership bit. This bit is set to 1 656221167Sgnn * by the host, and is set to 0 by the adapter. 657221167Sgnn * 0 - Host owns RxD and buffer. 658221167Sgnn * 1 - The adapter owns RxD and buffer. 659221167Sgnn * Bit 8 - Fast_Path_Eligible When set, indicates that the 660221167Sgnn * received frame meets all of the criteria for fast path processing. 661221167Sgnn * The required criteria are as follows: 662221167Sgnn * !SYN & 663221167Sgnn * (Transfer_Code == "Transfer OK") & 664221167Sgnn * (!Is_IP_Fragment) & 665221167Sgnn * ((Is_IPv4 & computed_L3_checksum == 0xFFFF) | 666221167Sgnn * (Is_IPv6)) & 667221167Sgnn * ((Is_TCP & computed_L4_checksum == 0xFFFF) | 668221167Sgnn * (Is_UDP & (computed_L4_checksum == 0xFFFF | 669221167Sgnn * computed _L4_checksum == 0x0000))) 670221167Sgnn * (same meaning for all RxD buffer modes) 671221167Sgnn * Bit 9 - L3 Checksum Correct 672221167Sgnn * Bit 10 - L4 Checksum Correct 673221167Sgnn * Bit 11 - Reserved 674221167Sgnn * Bit 12 to 15 - This field is written by the adapter. It is used 675221167Sgnn * to report the status of the frame transfer to the host. 676221167Sgnn * 0x0 - Transfer OK 677221167Sgnn * 0x4 - RDA Failure During Transfer 678221167Sgnn * 0x5 - Unparseable Packet, such as unknown IPv6 header. 679221167Sgnn * 0x6 - Frame integrity error (FCS or ECC). 680221167Sgnn * 0x7 - Buffer Size Error. The provided buffer(s) were not 681221167Sgnn * appropriately sized and data loss occurred. 682221167Sgnn * 0x8 - Internal ECC Error. RxD corrupted. 683221167Sgnn * 0x9 - IPv4 Checksum error 684221167Sgnn * 0xA - TCP/UDP Checksum error 685221167Sgnn * 0xF - Unknown Error or Multiple Error. Indicates an unknown 686221167Sgnn * problem or that more than one of transfer codes is set. 687221167Sgnn * Bit 16 - SYN The adapter sets this field to indicate that the 688221167Sgnn * incoming frame contained a TCP segment with its SYN bit set 689221167Sgnn * and its ACK bit NOT set. (same meaning for all RxD buffer modes) 690221167Sgnn * Bit 17 - Is ICMP 691221167Sgnn * Bit 18 - RTH_SPDM_HIT Set to 1 if there was a match in the 692221167Sgnn * Socket 693221167Sgnn * Pair Direct Match Table and the frame was steered based on SPDM. 694221167Sgnn * Bit 19 - RTH_IT_HIT Set to 1 if there was a match in the 695221167Sgnn * Indirection Table and the frame was steered based on hash 696221167Sgnn * indirection. 697221167Sgnn * Bit 20 to 23 - RTH_HASH_TYPE Indicates the function (hash type) 698221167Sgnn * that was used to calculate the hash. 699221167Sgnn * Bit 19 - IS_VLAN Set to '1' if the frame was/is VLAN tagged. 700221167Sgnn * Bit 25 to 26 - ETHER_ENCAP Reflects the Ethernet encapsulation 701221167Sgnn * of the received frame. 702221167Sgnn * 0x0 - Ethernet DIX 703221167Sgnn * 0x1 - LLC 704221167Sgnn * 0x2 - SNAP (includes Jumbo-SNAP) 705221167Sgnn * 0x3 - IPX 706221167Sgnn * Bit 27 - IS_IPV4 Set to '1' if the frame contains IPv4 packet. 707221167Sgnn * Bit 28 - IS_IPV6 Set to '1' if the frame contains IPv6 packet. 708221167Sgnn * Bit 29 - IS_IP_FRAG Set to '1' if the frame contains a 709221167Sgnn * fragmented IP packet. 710221167Sgnn * Bit 30 - IS_TCP Set to '1' if the frame contains a TCP segment. 711221167Sgnn * Bit 31 - IS_UDP Set to '1' if the frame contains a UDP message. 712221167Sgnn * Bit 32 to 47 - L3_Checksum[0:15] The IPv4 checksum value that 713221167Sgnn * arrived with the frame. If the resulting computed IPv4 header 714221167Sgnn * checksum for the frame did not produce the expected 0xFFFF value, 715221167Sgnn * then the transfer code would be set to 0x9. 716221167Sgnn * Bit 48 to 63 - L4_Checksum[0:15] TCP/UDP checksum value that 717221167Sgnn * arrived with the frame. If the resulting computed TCP/UDP checksum 718221167Sgnn * for the frame did not produce the expected 0xFFFF value, then the 719221167Sgnn * transfer code would be set to 0xA. 720221167Sgnn * @control_1:Bit 0 - This field must be used in conjunction with the Ownership 721221167Sgnn * field (above). 722221167Sgnn * 1 - Set by the host to indicate that the RxD points to fresh 723221167Sgnn * buffers. 724221167Sgnn * 0 - Cleared by the adapter to indicate that frame data has been 725221167Sgnn * placed into the assigned buffers, and that the host once again 726221167Sgnn * owns the descriptor. 727221167Sgnn * (Note: Please observe the usage guidelines outlined in the 728221167Sgnn * Ownership field (above)). 729221167Sgnn * Bit 1 - Unused. Ignored by Adapter on RxD read. Set to 0 730221167Sgnn * by Adapter on RxD write. 731221167Sgnn * Bits 2 to 15 - This field is written by the host and by X3100. 732221167Sgnn * The host writes the available buffer 0 size in bytes when it 733221167Sgnn * passes the descriptor to the X3100. The X3100 writes the number 734221167Sgnn * of bytes written to the buffer when it passes the descriptor back 735221167Sgnn * to the host. 736221167Sgnn * Bits 16 to 17 - Reserved 737221167Sgnn * Bits 18 to 31 - This field is set by the host and eventually 738221167Sgnn * overwritten by the adapter. The host writes the available 739221167Sgnn * buffer 1size in bytes when it passes the descriptor to the adapter. 740221167Sgnn * When a frame is delivered the host, the adapter populates this field 741221167Sgnn * with the number of bytes written into the buffer 1. The largest 742221167Sgnn * supported buffer is 16, 383 bytes. 743221167Sgnn * Bits 32 to 33 - Reserved 744221167Sgnn * Bits 34 to 47 - This field is set by the host and eventually 745221167Sgnn * overwritten by the adapter. The host writes the available 746221167Sgnn * buffer 2 size in bytes when it passes the descriptor to the adapter. 747221167Sgnn * When a frame is delivered the host, the adapter populates this field 748221167Sgnn * with the number of bytes written into the buffer 2. The largest 749221167Sgnn * supported buffer is 16, 383 bytes. 750221167Sgnn * Bit 48 to 63 - VLAN_Tag[0:15] The contents of the variable 751221167Sgnn * portion of the VLAN tag, if one was detected by the adapter. This 752221167Sgnn * field is populated even if VLAN-tag stripping is enabled. 753221167Sgnn * @buffer0_ptr: Pointer to buffer 0. This field is populated by the driver. 754221167Sgnn * In 3-buffer mode, when the RxD is returned to the host, 755221167Sgnn * buffer0_ptr field will be overwritten if the following conditions 756221167Sgnn * are met: 757221167Sgnn * 1 - RTH_Disable in the PRC_CTRL register is not set. 758221167Sgnn * 2 - RTH is enabled and a valid hash value was calculated for the 759221167Sgnn * frame. This will be indicated by a non-zero value in the 760221167Sgnn * RTH_HASH_TYPE field (Control_0, bits 20:23). In the event that the 761221167Sgnn * pointer is overwritten on return to the host, bits 0:31 will be 762221167Sgnn * all zeroes while bits 32:63 will contain the calculated hash value. 763221167Sgnn * @buffer1_ptr: Pointer to buffer 1. This field is populated by the driver. 764221167Sgnn * @buffer2_ptr: Pointer to buffer 2. This field is populated by the driver. 765221167Sgnn * 766221167Sgnn * Three buffer mode RxD for ring structure 767221167Sgnn */ 768221167Sgnntypedef struct vxge_hal_ring_rxd_3_t { 769221167Sgnn u64 host_control; 770221167Sgnn u64 control_0; 771221167Sgnn/* 772221167Sgnn * The following bit fields are common in all the three buffer modes and are 773221167Sgnn * defined in vxge_hal_ring_rxd_1_t 774221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_BUCKET_GET(ctrl0) bVAL7(ctrl0, 0) 775221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_BUCKET_ADAPTER vBIT(val, 0, 7) 776221167Sgnn * 777221167Sgnn * #define VXGE_HAL_RING_RXD_LIST_OWN_GET(ctrl0) bVAL1(ctrl0, 7) 778221167Sgnn * #define VXGE_HAL_RING_RXD_LIST_OWN_ADAPTER mBIT(7) 779221167Sgnn * 780221167Sgnn * #define VXGE_HAL_RING_RXD_FAST_PATH_ELIGIBLE_GET(ctrl0) \ 781221167Sgnn * bVAL1(ctrl0, 8) 782221167Sgnn * #define VXGE_HAL_RING_RXD_FAST_PATH_ELIGIBLE mBIT(8) 783221167Sgnn * 784221167Sgnn * #define VXGE_HAL_RING_RXD_L3_CKSUM_CORRECT_GET(ctrl0) \ 785221167Sgnn * bVAL1(ctrl0, 9) 786221167Sgnn * #define VXGE_HAL_RING_RXD_L3_CKSUM_CORRECT mBIT(9) 787221167Sgnn * 788221167Sgnn * #define VXGE_HAL_RING_RXD_L4_CKSUM_CORRECT_GET(ctrl0) \ 789221167Sgnn * bVAL1(ctrl0, 10) 790221167Sgnn * #define VXGE_HAL_RING_RXD_L4_CKSUM_CORRECT mBIT(10) 791221167Sgnn * 792221167Sgnn * #define VXGE_HAL_RING_RXD_T_CODE_GET(ctrl0) bVAL4(ctrl0, 12) 793221167Sgnn * #define VXGE_HAL_RING_RXD_T_CODE(val) vBIT(val, 12, 4) 794221167Sgnn * #define VXGE_HAL_RING_RXD_T_CODE_OK VXGE_HAL_RING_T_CODE_OK 795221167Sgnn * #define VXGE_HAL_RING_RXD_T_CODE_L3_CKSUM_MISMATCH \ 796221167Sgnn * VXGE_HAL_RING_T_CODE_L3_CKSUM_MISMATCH 797221167Sgnn * #define VXGE_HAL_RING_RXD_T_CODE_L4_CKSUM_MISMATCH \ 798221167Sgnn * VXGE_HAL_RING_T_CODE_L4_CKSUM_MISMATCH 799221167Sgnn * #define VXGE_HAL_RING_RXD_T_CODE_L3_L4_CKSUM_MISMATCH \ 800221167Sgnn * VXGE_HAL_RING_T_CODE_L3_L4_CKSUM_MISMATCH 801221167Sgnn * #define VXGE_HAL_RING_RXD_T_CODE_L3_PKT_ERR \ 802221167Sgnn * VXGE_HAL_RING_T_CODE_L3_PKT_ERR 803221167Sgnn * #define VXGE_HAL_RING_RXD_T_CODE_L2_FRM_ERR \ 804221167Sgnn * VXGE_HAL_RING_T_CODE_L2_FRM_ERR 805221167Sgnn * #define VXGE_HAL_RING_RXD_T_CODE_BUF_SIZE_ERR \ 806221167Sgnn * VXGE_HAL_RING_T_CODE_BUF_SIZE_ERR 807221167Sgnn * #define VXGE_HAL_RING_RXD_T_CODE_INT_ECC_ERR \ 808221167Sgnn * VXGE_HAL_RING_T_CODE_INT_ECC_ERR 809221167Sgnn * #define VXGE_HAL_RING_RXD_T_CODE_BENIGN_OVFLOW \ 810221167Sgnn * VXGE_HAL_RING_T_CODE_BENIGN_OVFLOW 811221167Sgnn * #define VXGE_HAL_RING_RXD_T_CODE_ZERO_LEN_BUFF \ 812221167Sgnn * VXGE_HAL_RING_T_CODE_ZERO_LEN_BUFF 813221167Sgnn * #define VXGE_HAL_RING_RXD_T_CODE_FRM_DROP VXGE_HAL_RING_T_CODE_FRM_DROP 814221167Sgnn * #define VXGE_HAL_RING_RXD_T_CODE_UNUSED VXGE_HAL_RING_T_CODE_UNUSED 815221167Sgnn * #define VXGE_HAL_RING_RXD_T_CODE_MULTI_ERR \ 816221167Sgnn * VXGE_HAL_RING_T_CODE_MULTI_ERR 817221167Sgnn * 818221167Sgnn * #define VXGE_HAL_RING_RXD_SYN_GET(ctrl0) bVAL1(ctrl0, 16) 819221167Sgnn * #define VXGE_HAL_RING_RXD_SYN mBIT(16) 820221167Sgnn * 821221167Sgnn * #define VXGE_HAL_RING_RXD_IS_ICMP_GET(ctrl0) bVAL1(ctrl0, 17) 822221167Sgnn * #define VXGE_HAL_RING_RXD_IS_ICMP mBIT(17) 823221167Sgnn * 824221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_SPDM_HIT_GET(ctrl0) bVAL1(ctrl0, 18) 825221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_SPDM_HIT mBIT(18) 826221167Sgnn * 827221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_IT_HIT_GET(ctrl0) bVAL1(ctrl0, 19) 828221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_IT_HIT mBIT(19) 829221167Sgnn * 830221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_GET(ctrl0) bVAL4(ctrl0, 20) 831221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE(val) vBIT(val, 20, 4) 832221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_NONE \ 833221167Sgnn * VXGE_HAL_RING_HASH_TYPE_NONE 834221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_TCP_IPV4 \ 835221167Sgnn * VXGE_HAL_RING_HASH_TYPE_TCP_IPV4 836221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_UDP_IPV4 \ 837221167Sgnn * VXGE_HAL_RING_HASH_TYPE_UDP_IPV4 838221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_IPV4 \ 839221167Sgnn * VXGE_HAL_RING_HASH_TYPE_IPV4 840221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_TCP_IPV6 \ 841221167Sgnn * VXGE_HAL_RING_HASH_TYPE_TCP_IPV6 842221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_UDP_IPV6 \ 843221167Sgnn * VXGE_HAL_RING_HASH_TYPE_UDP_IPV6 844221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_IPV6 \ 845221167Sgnn * VXGE_HAL_RING_HASH_TYPE_IPV6 846221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_TCP_IPV6_EX \ 847221167Sgnn * VXGE_HAL_RING_HASH_TYPE_TCP_IPV6_EX 848221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_UDP_IPV6_EX \ 849221167Sgnn * VXGE_HAL_RING_HASH_TYPE_UDP_IPV6_EX 850221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_IPV6_EX \ 851221167Sgnn * VXGE_HAL_RING_HASH_TYPE_IPV6_EX 852221167Sgnn * 853221167Sgnn * #define VXGE_HAL_RING_RXD_IS_VLAN_GET(ctrl0) bVAL1(ctrl0, 24) 854221167Sgnn * #define VXGE_HAL_RING_RXD_IS_VLAN mBIT(24) 855221167Sgnn * 856221167Sgnn * #define VXGE_HAL_RING_RXD_ETHER_ENCAP_GET(ctrl0) bVAL2(ctrl0, 25) 857221167Sgnn * #define VXGE_HAL_RING_RXD_ETHER_ENCAP(val) vBIT(val, 25, 2) 858221167Sgnn * #define VXGE_HAL_RING_RXD_ETHER_ENCAP_DIX VXGE_HAL_FRAME_TYPE_DIX 859221167Sgnn * #define VXGE_HAL_RING_RXD_ETHER_ENCAP_LLC VXGE_HAL_FRAME_TYPE_LLC 860221167Sgnn * #define VXGE_HAL_RING_RXD_ETHER_ENCAP_SNAP VXGE_HAL_FRAME_TYPE_SNAP 861221167Sgnn * #define VXGE_HAL_RING_RXD_ETHER_ENCAP_IPX VXGE_HAL_FRAME_TYPE_IPX 862221167Sgnn * 863221167Sgnn * #define VXGE_HAL_RING_RXD_IS_IPV4_GET(ctrl0) bVAL1(ctrl0, 27) 864221167Sgnn * #define VXGE_HAL_RING_RXD_IS_IPV4 mBIT(27) 865221167Sgnn * 866221167Sgnn * #define VXGE_HAL_RING_RXD_IS_IPV6_GET(ctrl0) bVAL1(ctrl0, 28) 867221167Sgnn * #define VXGE_HAL_RING_RXD_IS_IPV6 mBIT(28) 868221167Sgnn * 869221167Sgnn * #define VXGE_HAL_RING_RXD_IS_IPV_FRAG_GET(ctrl0) bVAL1(ctrl0, 29) 870221167Sgnn * #define VXGE_HAL_RING_RXD_IS_IPV_FRAG mBIT(29) 871221167Sgnn * 872221167Sgnn * #define VXGE_HAL_RING_RXD_IS_TCP_GET(ctrl0) bVAL1(ctrl0, 30) 873221167Sgnn * #define VXGE_HAL_RING_RXD_IS_TCP mBIT(30) 874221167Sgnn * 875221167Sgnn * #define VXGE_HAL_RING_RXD_IS_UDP_GET(ctrl0) bVAL1(ctrl0, 31) 876221167Sgnn * #define VXGE_HAL_RING_RXD_IS_UDP mBIT(31) 877221167Sgnn * 878221167Sgnn * #define VXGE_HAL_RING_RXD_FRAME_PROTO_GET(ctrl0) bVAL5(ctrl0, 27) 879221167Sgnn * #define VXGE_HAL_RING_RXD_FRAME_PROTO(val) vBIT(val, 27, 5) 880221167Sgnn * #define VXGE_HAL_RING_RXD_FRAME_PROTO_IPV4 \ 881221167Sgnn * VXGE_HAL_FRAME_PROTO_IPV4 882221167Sgnn * #define VXGE_HAL_RING_RXD_FRAME_PROTO_IPV6 \ 883221167Sgnn * VXGE_HAL_FRAME_PROTO_IPV6 884221167Sgnn * #define VXGE_HAL_RING_RXD_FRAME_PROTO_IP_FRAG \ 885221167Sgnn * VXGE_HAL_FRAME_PROTO_IP_FRAG 886221167Sgnn * #define VXGE_HAL_RING_RXD_FRAME_PROTO_TCP \ 887221167Sgnn * VXGE_HAL_FRAME_PROTO_TCP 888221167Sgnn * #define VXGE_HAL_RING_RXD_FRAME_PROTO_UDP \ 889221167Sgnn * VXGE_HAL_FRAME_PROTO_UDP 890221167Sgnn * #define VXGE_HAL_RING_RXD_FRAME_PROTO_TCP_OR_UDP \ 891221167Sgnn * (VXGE_HAL_FRAME_PROTO_TCP | VXGE_HAL_FRAME_PROTO_UDP) 892221167Sgnn * 893221167Sgnn * #define VXGE_HAL_RING_RXD_L3_CKSUM_GET(ctrl0) bVAL16(ctrl0, 32) 894221167Sgnn * #define VXGE_HAL_RING_RXD_L3_CKSUM(val) vBIT(val, 32, 16) 895221167Sgnn * 896221167Sgnn * #define VXGE_HAL_RING_RXD_L4_CKSUM_GET(ctrl0) bVAL16(ctrl0, 48) 897221167Sgnn * #define VXGE_HAL_RING_RXD_L4_CKSUM(val) vBIT(val, 48, 16) 898221167Sgnn */ 899221167Sgnn 900221167Sgnn u64 control_1; 901221167Sgnn#define VXGE_HAL_RING_RXD_3_BUFFER_EMPTY_GET(ctrl1) bVAL1(ctrl1, 0) 902221167Sgnn#define VXGE_HAL_RING_RXD_3_BUFFER_EMPTY mBIT(0) 903221167Sgnn 904221167Sgnn#define VXGE_HAL_RING_RXD_3_BUFFER0_SIZE_GET(ctrl1) bVAL14(ctrl1, 2) 905221167Sgnn#define VXGE_HAL_RING_RXD_3_BUFFER0_SIZE(val) vBIT(val, 2, 14) 906221167Sgnn#define VXGE_HAL_RING_RXD_3_BUFFER0_SIZE_MASK vBIT(0x3FFc, 2, 14) 907221167Sgnn 908221167Sgnn#define VXGE_HAL_RING_RXD_3_BUFFER1_SIZE_GET(ctrl1) bVAL14(ctrl1, 18) 909221167Sgnn#define VXGE_HAL_RING_RXD_3_BUFFER1_SIZE(val) vBIT(val, 18, 14) 910221167Sgnn#define VXGE_HAL_RING_RXD_3_BUFFER1_SIZE_MASK vBIT(0x3FFc, 18, 14) 911221167Sgnn 912221167Sgnn#define VXGE_HAL_RING_RXD_3_BUFFER2_SIZE_GET(ctrl1) bVAL14(ctrl1, 34) 913221167Sgnn#define VXGE_HAL_RING_RXD_3_BUFFER2_SIZE(val) vBIT(val, 34, 14) 914221167Sgnn#define VXGE_HAL_RING_RXD_3_BUFFER2_SIZE_MASK vBIT(0x3FFc, 34, 14) 915221167Sgnn 916221167Sgnn/* 917221167Sgnn * The following bit fields are common in all the three buffer modes and are 918221167Sgnn * defined in vxge_hal_ring_rxd_1_t 919221167Sgnn * #define VXGE_HAL_RING_RXD_VLAN_TAG_GET(ctrl1) bVAL16(ctrl1, 48) 920221167Sgnn * #define VXGE_HAL_RING_RXD_VLAN_TAG(val) vBIT(val, 48, 16) 921221167Sgnn */ 922221167Sgnn u64 buffer0_ptr; 923221167Sgnn#define VXGE_HAL_RING_RXD_3_RTH_HASH_VALUE_GET(b0_ptr) bVAL32(b0_ptr, 32) 924221167Sgnn#define VXGE_HAL_RING_RXD_3_RTH_HASH_VALUE(val) vBIT(val, 32, 32) 925221167Sgnn 926221167Sgnn u64 buffer1_ptr; 927221167Sgnn 928221167Sgnn u64 buffer2_ptr; 929221167Sgnn 930221167Sgnn} vxge_hal_ring_rxd_3_t; 931221167Sgnn 932221167Sgnn/* 933221167Sgnn * struct vxge_hal_ring_rxd_5_t - Five buffer mode RxD for ring 934221167Sgnn * @host_control: This 32 bitfield is exclusively for host use and is "readonly" 935221167Sgnn * from the adapter's perspective. 936221167Sgnn * @control_2: Bits 0 to 1 - Reserved 937221167Sgnn * Bits 2 to 15 - This field is set by the host and eventually 938221167Sgnn * overwritten by the adapter. The host writes the available buffer 939221167Sgnn * 3 size in bytes when it pas ses the descriptor to the adapter. 940221167Sgnn * When a frame is delivered the host, the adapter populates this 941221167Sgnn * field with the number of bytes written into the buffer. The 942221167Sgnn * largest supported buffer is 16, 383 bytes. 943221167Sgnn * Bits 16 to 17 - Reserved 944221167Sgnn * Bits 18 to 31 - This field is set by the host and eventually 945221167Sgnn * overwritten by the adapter. The host writes the available buffer 946221167Sgnn * 4 size in bytes when it passes the descriptor to the adapter. 947221167Sgnn * When a frame is delivered the host, the adapter populates this 948221167Sgnn * field with the number of bytes written into the buffer. 949221167Sgnn * The largest supported buffer is 16, 383 bytes. 950221167Sgnn * @control_0: Bits 0 to 6 - RTH_Bucket get 951221167Sgnn * Bit 7 - Own Descriptor ownership bit. This bit is set to 1 by 952221167Sgnn * the host, and is set to 0 by the adapter. 953221167Sgnn * 0 - Host owns RxD and buffer. 954221167Sgnn * 1 - The adapter owns RxD and buffer. 955221167Sgnn * Bit 8 - Fast_Path_Eligible When set,indicates that the received 956221167Sgnn * frame meets all of the criteria for fast path processing. 957221167Sgnn * The required criteria are as follows: 958221167Sgnn * !SYN & 959221167Sgnn * (Transfer_Code == "Transfer OK") & 960221167Sgnn * (!Is_IP_Fragment) & 961221167Sgnn * ((Is_IPv4 & computed_L3_checksum == 0xFFFF) | 962221167Sgnn * (Is_IPv6)) & 963221167Sgnn * ((Is_TCP & computed_L4_checksum == 0xFFFF) | 964221167Sgnn * (Is_UDP & (computed_L4_checksum == 0xFFFF | 965221167Sgnn * computed _L4_checksum == 0x0000))) 966221167Sgnn * (same meaning for all RxD buffer modes) 967221167Sgnn * Bit 9 - L3 Checksum Correct 968221167Sgnn * Bit 10 - L4 Checksum Correct 969221167Sgnn * Bit 11 - Reserved 970221167Sgnn * Bit 12 to 15 - This field is written by the adapter. It is used 971221167Sgnn * to report the status of the frame transfer to the host. 972221167Sgnn * 0x0 - Transfer OK 973221167Sgnn * 0x4 - RDA Failure During Transfer 974221167Sgnn * 0x5 - Unparseable Packet, such as unknown IPv6 header. 975221167Sgnn * 0x6 - Frame integrity error (FCS or ECC). 976221167Sgnn * 0x7 - Buffer Size Error. The provided buffer(s) were not 977221167Sgnn * appropriately sized and data loss occurred. 978221167Sgnn * 0x8 - Internal ECC Error. RxD corrupted. 979221167Sgnn * 0x9 - IPv4 Checksum error 980221167Sgnn * 0xA - TCP/UDP Checksum error 981221167Sgnn * 0xF - Unknown Error or Multiple Error. Indicates an unknown 982221167Sgnn * problem or that more than one of transfer codes is set. 983221167Sgnn * Bit 16 - SYN The adapter sets this field to indicate that the 984221167Sgnn * incoming frame contained a TCP segment with its SYN bit set 985221167Sgnn * and its ACK bit NOT set. (same meaning for all RxD buffer modes) 986221167Sgnn * Bit 17 - Is ICMP 987221167Sgnn * Bit 18 - RTH_SPDM_HIT Set to 1 if there was a match in the 988221167Sgnn * Socket Pair Direct Match Table and the frame was steered based on 989221167Sgnn * SPDM. 990221167Sgnn * Bit 19 - RTH_IT_HIT Set to 1 if there was a match in the 991221167Sgnn * Indirection Table and the frame was steered based on hash 992221167Sgnn * indirection. 993221167Sgnn * Bit 20 to 23 - RTH_HASH_TYPE Indicates the function (hash type) 994221167Sgnn * that was used to calculate the hash. 995221167Sgnn * Bit 19 - IS_VLAN Set to '1' if the frame was/is VLAN tagged. 996221167Sgnn * Bit 25 to 26 - ETHER_ENCAP Reflects the Ethernet encapsulation 997221167Sgnn * of the received frame. 998221167Sgnn * 0x0 - Ethernet DIX 999221167Sgnn * 0x1 - LLC 1000221167Sgnn * 0x2 - SNAP (includes Jumbo-SNAP) 1001221167Sgnn * 0x3 - IPX 1002221167Sgnn * Bit 27 - IS_IPV4 Set to '1' if the frame contains IPv4 packet. 1003221167Sgnn * Bit 28 - IS_IPV6 Set to '1' if the frame contains IPv6 packet. 1004221167Sgnn * Bit 29 - IS_IP_FRAG Set to '1' if the frame contains a 1005221167Sgnn * fragmented IP packet. 1006221167Sgnn * Bit 30 - IS_TCP Set to '1' if the frame contains a TCP segment. 1007221167Sgnn * Bit 31 - IS_UDP Set to '1' if the frame contains a UDP message. 1008221167Sgnn * Bit 32 to 47 - L3_Checksum[0:15] The IPv4 checksum value that 1009221167Sgnn * arrived with the frame. If the resulting computed IPv4 header 1010221167Sgnn * checksum for the frame did not produce the expected 0xFFFF value, 1011221167Sgnn * then the transfer code would be set to 0x9. 1012221167Sgnn * Bit 48 to 63 - L4_Checksum[0:15] TCP/UDP checksum value that 1013221167Sgnn * arrived with the frame. If the resulting computed TCP/UDP checksum 1014221167Sgnn * for the frame did not produce the expected 0xFFFF value, then the 1015221167Sgnn * transfer code would be set to 0xA. 1016221167Sgnn * @control_1: Bits 0 to 1 - Reserved. 1017221167Sgnn * Bits 2 to 15 - This field is written by the host and by X3100. 1018221167Sgnn * The host writes the available buffer 0 size in bytes when it 1019221167Sgnn * passes the descriptor to the X3100. The X3100 writes the number 1020221167Sgnn * of bytes written to the buffer when it passes the descriptor back 1021221167Sgnn * to the host. 1022221167Sgnn * Bits 16 to 17 - Reserved 1023221167Sgnn * Bits 18 to 31 - This field is set by the host and eventually 1024221167Sgnn * overwritten by the adapter. The host writes the available 1025221167Sgnn * buffer 1 size in bytes when it passes the descriptor to the adapter. 1026221167Sgnn * When a frame is delivered the host, the adapter populates this field 1027221167Sgnn * with the number of bytes written into the buffer 1. The largest 1028221167Sgnn * supported buffer is 16, 383 bytes. 1029221167Sgnn * Bits 32 to 33 - Reserved 1030221167Sgnn * Bits 34 to 47 - This field is set by the host and eventually 1031221167Sgnn * overwritten by the adapter. The host writes the available 1032221167Sgnn * buffer 2 size in bytes when it passes the descriptor to the adapter. 1033221167Sgnn * When a frame is delivered the host, the adapter populates this field 1034221167Sgnn * with the number of bytes written into the buffer 2. The largest 1035221167Sgnn * supported buffer is 16, 383 bytes. 1036221167Sgnn * Bit 48 to 63 - VLAN_Tag[0:15] The contents of the variable 1037221167Sgnn * portion of the VLAN tag, if one was detected by the adapter. This 1038221167Sgnn * field is populated even if VLAN-tag stripping is enabled. 1039221167Sgnn * @buffer0_ptr: Pointer to buffer 0. This field is populated by the driver. 1040221167Sgnn * In 5-buffer mode, when the RxD is returned to the host, 1041221167Sgnn * buffer0_ptr field will be overwritten if the following conditions 1042221167Sgnn * are met: 1043221167Sgnn * 1 - RTH_Disable in the PRC_CTRL register is not set. 1044221167Sgnn * 2 - RTH is enabled and a valid hash value was calculated for the 1045221167Sgnn * frame. This will be indicated by a non-zero value in the 1046221167Sgnn * RTH_HASH_TYPE field (Control_0, bits 20:23). In the event that the 1047221167Sgnn * pointer is overwritten on return to the host, bits 0:31 will be 1048221167Sgnn * all zeroes while bits 32:63 will contain the calculated hash value. 1049221167Sgnn * @buffer1_ptr: Pointer to buffer 1. This field is populated by the driver. 1050221167Sgnn * @buffer2_ptr: Pointer to buffer 2. This field is populated by the driver. 1051221167Sgnn * @buffer3_ptr: Pointer to buffer 3. This field is populated by the driver. 1052221167Sgnn * @buffer4_ptr: Pointer to buffer 4. This field is populated by the driver. 1053221167Sgnn * @pad: Pad to align at cache line boundary 1054221167Sgnn * 1055221167Sgnn * Three buffer mode RxD for ring structure 1056221167Sgnn */ 1057221167Sgnntypedef struct vxge_hal_ring_rxd_5_t { 1058221167Sgnn#if defined(VXGE_OS_HOST_BIG_ENDIAN) 1059221167Sgnn u32 host_control; 1060221167Sgnn u32 control_2; 1061221167Sgnn#else 1062221167Sgnn u32 control_2; 1063221167Sgnn u32 host_control; 1064221167Sgnn#endif 1065221167Sgnn 1066221167Sgnn#define VXGE_HAL_RING_RXD_5_BUFFER3_SIZE_GET(ctrl2) bVAL14(ctrl2, 34) 1067221167Sgnn#define VXGE_HAL_RING_RXD_5_BUFFER3_SIZE(val) vBIT(val, 34, 14) 1068221167Sgnn#define VXGE_HAL_RING_RXD_5_BUFFER3_SIZE_MASK vBIT(0x3FFF, 34, 14) 1069221167Sgnn 1070221167Sgnn#define VXGE_HAL_RING_RXD_5_BUFFER4_SIZE_GET(ctrl2) bVAL14(ctrl2, 50) 1071221167Sgnn#define VXGE_HAL_RING_RXD_5_BUFFER4_SIZE(val) vBIT(val, 50, 14) 1072221167Sgnn#define VXGE_HAL_RING_RXD_5_BUFFER4_SIZE_MASK vBIT(0x3FFF, 50, 14) 1073221167Sgnn 1074221167Sgnn 1075221167Sgnn u64 control_0; 1076221167Sgnn/* 1077221167Sgnn * The following bit fields are common in all the three buffer modes and are 1078221167Sgnn * defined in vxge_hal_ring_rxd_1_t 1079221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_BUCKET_GET(ctrl0) bVAL7(ctrl0, 0) 1080221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_BUCKET_ADAPTER vBIT(val, 0, 7) 1081221167Sgnn * 1082221167Sgnn * #define VXGE_HAL_RING_RXD_LIST_OWN_GET(ctrl0) bVAL1(ctrl0, 7) 1083221167Sgnn * #define VXGE_HAL_RING_RXD_LIST_OWN_ADAPTER mBIT(7) 1084221167Sgnn * 1085221167Sgnn * #define VXGE_HAL_RING_RXD_FAST_PATH_ELIGIBLE_GET(ctrl0 \ 1086221167Sgnn * bVAL1(ctrl0, 8) 1087221167Sgnn * #define VXGE_HAL_RING_RXD_FAST_PATH_ELIGIBLE mBIT(8) 1088221167Sgnn * 1089221167Sgnn * #define VXGE_HAL_RING_RXD_L3_CKSUM_CORRECT_GET(ctrl0) \ 1090221167Sgnn * bVAL1(ctrl0, 9) 1091221167Sgnn * #define VXGE_HAL_RING_RXD_L3_CKSUM_CORRECT mBIT(9) 1092221167Sgnn * 1093221167Sgnn * #define VXGE_HAL_RING_RXD_L4_CKSUM_CORRECT_GET(ctrl0) \ 1094221167Sgnn * bVAL1(ctrl0, 10) 1095221167Sgnn * #define VXGE_HAL_RING_RXD_L4_CKSUM_CORRECT mBIT(10) 1096221167Sgnn * 1097221167Sgnn * #define VXGE_HAL_RING_RXD_T_CODE_GET(ctrl0) bVAL4(ctrl0, 12) 1098221167Sgnn * #define VXGE_HAL_RING_RXD_T_CODE(val) vBIT(val, 12, 4) 1099221167Sgnn * #define VXGE_HAL_RING_RXD_T_CODE_OK \ 1100221167Sgnn * VXGE_HAL_RING_T_CODE_OK 1101221167Sgnn * #define VXGE_HAL_RING_RXD_T_CODE_L3_CKSUM_MISMATCH \ 1102221167Sgnn * VXGE_HAL_RING_T_CODE_L3_CKSUM_MISMATCH 1103221167Sgnn * #define VXGE_HAL_RING_RXD_T_CODE_L4_CKSUM_MISMATCH \ 1104221167Sgnn * VXGE_HAL_RING_T_CODE_L4_CKSUM_MISMATCH 1105221167Sgnn * #define VXGE_HAL_RING_RXD_T_CODE_L3_L4_CKSUM_MISMATCH \ 1106221167Sgnn * VXGE_HAL_RING_T_CODE_L3_L4_CKSUM_MISMATCH 1107221167Sgnn * #define VXGE_HAL_RING_RXD_T_CODE_L3_PKT_ERR \ 1108221167Sgnn * VXGE_HAL_RING_T_CODE_L3_PKT_ERR 1109221167Sgnn * #define VXGE_HAL_RING_RXD_T_CODE_L2_FRM_ERR \ 1110221167Sgnn * VXGE_HAL_RING_T_CODE_L2_FRM_ERR 1111221167Sgnn * #define VXGE_HAL_RING_RXD_T_CODE_BUF_SIZE_ERR \ 1112221167Sgnn * VXGE_HAL_RING_T_CODE_BUF_SIZE_ERR 1113221167Sgnn * #define VXGE_HAL_RING_RXD_T_CODE_INT_ECC_ERR \ 1114221167Sgnn * VXGE_HAL_RING_T_CODE_INT_ECC_ERR 1115221167Sgnn * #define VXGE_HAL_RING_RXD_T_CODE_BENIGN_OVFLOW \ 1116221167Sgnn * VXGE_HAL_RING_T_CODE_BENIGN_OVFLOW 1117221167Sgnn * #define VXGE_HAL_RING_RXD_T_CODE_ZERO_LEN_BUFF \ 1118221167Sgnn * VXGE_HAL_RING_T_CODE_ZERO_LEN_BUFF 1119221167Sgnn * #define VXGE_HAL_RING_RXD_T_CODE_FRM_DROP \ 1120221167Sgnn * VXGE_HAL_RING_T_CODE_FRM_DROP 1121221167Sgnn * #define VXGE_HAL_RING_RXD_T_CODE_UNUSED \ 1122221167Sgnn * VXGE_HAL_RING_T_CODE_UNUSED 1123221167Sgnn * #define VXGE_HAL_RING_RXD_T_CODE_MULTI_ERR \ 1124221167Sgnn * VXGE_HAL_RING_T_CODE_MULTI_ERR 1125221167Sgnn * 1126221167Sgnn * #define VXGE_HAL_RING_RXD_SYN_GET(ctrl0) bVAL1(ctrl0, 16) 1127221167Sgnn * #define VXGE_HAL_RING_RXD_SYN mBIT(16) 1128221167Sgnn * 1129221167Sgnn * #define VXGE_HAL_RING_RXD_IS_ICMP_GET(ctrl0) bVAL1(ctrl0, 17) 1130221167Sgnn * #define VXGE_HAL_RING_RXD_IS_ICMP mBIT(17) 1131221167Sgnn * 1132221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_SPDM_HIT_GET(ctrl0) bVAL1(ctrl0, 18) 1133221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_SPDM_HIT mBIT(18) 1134221167Sgnn * 1135221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_IT_HIT_GET(ctrl0) bVAL1(ctrl0, 19) 1136221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_IT_HIT mBIT(19) 1137221167Sgnn * 1138221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_GET(ctrl0) bVAL4(ctrl0, 20) 1139221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE(val) vBIT(val, 20, 4) 1140221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_NONE \ 1141221167Sgnn * VXGE_HAL_RING_HASH_TYPE_NONE 1142221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_TCP_IPV4 \ 1143221167Sgnn * VXGE_HAL_RING_HASH_TYPE_TCP_IPV4 1144221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_UDP_IPV4 \ 1145221167Sgnn * VXGE_HAL_RING_HASH_TYPE_UDP_IPV4 1146221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_IPV4 \ 1147221167Sgnn * VXGE_HAL_RING_HASH_TYPE_IPV4 1148221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_TCP_IPV6 \ 1149221167Sgnn * VXGE_HAL_RING_HASH_TYPE_TCP_IPV6 1150221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_UDP_IPV6 \ 1151221167Sgnn * VXGE_HAL_RING_HASH_TYPE_UDP_IPV6 1152221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_IPV6 \ 1153221167Sgnn * VXGE_HAL_RING_HASH_TYPE_IPV6 1154221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_TCP_IPV6_EX \ 1155221167Sgnn * VXGE_HAL_RING_HASH_TYPE_TCP_IPV6_EX 1156221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_UDP_IPV6_EX \ 1157221167Sgnn * VXGE_HAL_RING_HASH_TYPE_UDP_IPV6_EX 1158221167Sgnn * #define VXGE_HAL_RING_RXD_RTH_HASH_TYPE_IPV6_EX \ 1159221167Sgnn * VXGE_HAL_RING_HASH_TYPE_IPV6_EX 1160221167Sgnn * 1161221167Sgnn * #define VXGE_HAL_RING_RXD_IS_VLAN_GET(ctrl0) bVAL1(ctrl0, 24) 1162221167Sgnn * #define VXGE_HAL_RING_RXD_IS_VLAN mBIT(24) 1163221167Sgnn * 1164221167Sgnn * #define VXGE_HAL_RING_RXD_ETHER_ENCAP_GET(ctrl0) bVAL2(ctrl0, 25) 1165221167Sgnn * #define VXGE_HAL_RING_RXD_ETHER_ENCAP(val) vBIT(val, 25, 2) 1166221167Sgnn * #define VXGE_HAL_RING_RXD_ETHER_ENCAP_DIX VXGE_HAL_FRAME_TYPE_DIX 1167221167Sgnn * #define VXGE_HAL_RING_RXD_ETHER_ENCAP_LLC VXGE_HAL_FRAME_TYPE_LLC 1168221167Sgnn * #define VXGE_HAL_RING_RXD_ETHER_ENCAP_SNAP VXGE_HAL_FRAME_TYPE_SNAP 1169221167Sgnn * #define VXGE_HAL_RING_RXD_ETHER_ENCAP_IPX VXGE_HAL_FRAME_TYPE_IPX 1170221167Sgnn * 1171221167Sgnn * #define VXGE_HAL_RING_RXD_IS_IPV4_GET(ctrl0) bVAL1(ctrl0, 27) 1172221167Sgnn * #define VXGE_HAL_RING_RXD_IS_IPV4 mBIT(27) 1173221167Sgnn * 1174221167Sgnn * #define VXGE_HAL_RING_RXD_IS_IPV6_GET(ctrl0) bVAL1(ctrl0, 28) 1175221167Sgnn * #define VXGE_HAL_RING_RXD_IS_IPV6 mBIT(28) 1176221167Sgnn * 1177221167Sgnn * #define VXGE_HAL_RING_RXD_IS_IPV_FRAG_GET(ctrl0) bVAL1(ctrl0, 29) 1178221167Sgnn * #define VXGE_HAL_RING_RXD_IS_IPV_FRAG mBIT(29) 1179221167Sgnn * 1180221167Sgnn * #define VXGE_HAL_RING_RXD_IS_TCP_GET(ctrl0) bVAL1(ctrl0, 30) 1181221167Sgnn * #define VXGE_HAL_RING_RXD_IS_TCP mBIT(30) 1182221167Sgnn * 1183221167Sgnn * #define VXGE_HAL_RING_RXD_IS_UDP_GET(ctrl0) bVAL1(ctrl0, 31) 1184221167Sgnn * #define VXGE_HAL_RING_RXD_IS_UDP mBIT(31) 1185221167Sgnn * 1186221167Sgnn * #define VXGE_HAL_RING_RXD_FRAME_PROTO_GET(ctrl0) bVAL5(ctrl0, 27) 1187221167Sgnn * #define VXGE_HAL_RING_RXD_FRAME_PROTO(val) vBIT(val, 27, 5) 1188221167Sgnn * #define VXGE_HAL_RING_RXD_FRAME_PROTO_IPV4 VXGE_HAL_FRAME_PROTO_IPV4 1189221167Sgnn * #define VXGE_HAL_RING_RXD_FRAME_PROTO_IPV6 VXGE_HAL_FRAME_PROTO_IPV6 1190221167Sgnn * #define VXGE_HAL_RING_RXD_FRAME_PROTO_IP_FRAG \ 1191221167Sgnn * VXGE_HAL_FRAME_PROTO_IP_FRAG 1192221167Sgnn * #define VXGE_HAL_RING_RXD_FRAME_PROTO_TCP VXGE_HAL_FRAME_PROTO_TCP 1193221167Sgnn * #define VXGE_HAL_RING_RXD_FRAME_PROTO_UDP VXGE_HAL_FRAME_PROTO_UDP 1194221167Sgnn * #define VXGE_HAL_RING_RXD_FRAME_PROTO_TCP_OR_UDP \ 1195221167Sgnn * (VXGE_HAL_FRAME_PROTO_TCP | VXGE_HAL_FRAME_PROTO_UDP) 1196221167Sgnn * 1197221167Sgnn * #define VXGE_HAL_RING_RXD_L3_CKSUM_GET(ctrl0) bVAL16(ctrl0, 32) 1198221167Sgnn * #define VXGE_HAL_RING_RXD_L3_CKSUM(val) vBIT(val, 32, 16) 1199221167Sgnn * 1200221167Sgnn * #define VXGE_HAL_RING_RXD_L4_CKSUM_GET(ctrl0) bVAL16(ctrl0, 48) 1201221167Sgnn * #define VXGE_HAL_RING_RXD_L4_CKSUM(val) vBIT(val, 48, 16) 1202221167Sgnn */ 1203221167Sgnn 1204221167Sgnn u64 control_1; 1205221167Sgnn 1206221167Sgnn#define VXGE_HAL_RING_RXD_5_BUFFER0_SIZE_GET(ctrl1) bVAL14(ctrl1, 2) 1207221167Sgnn#define VXGE_HAL_RING_RXD_5_BUFFER0_SIZE(val) vBIT(val, 2, 14) 1208221167Sgnn#define VXGE_HAL_RING_RXD_5_BUFFER0_SIZE_MASK vBIT(0x3FFF, 2, 14) 1209221167Sgnn 1210221167Sgnn#define VXGE_HAL_RING_RXD_5_BUFFER1_SIZE_GET(ctrl1) bVAL14(ctrl1, 18) 1211221167Sgnn#define VXGE_HAL_RING_RXD_5_BUFFER1_SIZE(val) vBIT(val, 18, 14) 1212221167Sgnn#define VXGE_HAL_RING_RXD_5_BUFFER1_SIZE_MASK vBIT(0x3FFF, 18, 14) 1213221167Sgnn 1214221167Sgnn#define VXGE_HAL_RING_RXD_5_BUFFER2_SIZE_GET(ctrl1) bVAL14(ctrl1, 34) 1215221167Sgnn#define VXGE_HAL_RING_RXD_5_BUFFER2_SIZE(val) vBIT(val, 34, 14) 1216221167Sgnn#define VXGE_HAL_RING_RXD_5_BUFFER2_SIZE_MASK vBIT(0xFFFF, 34, 14) 1217221167Sgnn 1218221167Sgnn/* 1219221167Sgnn * The following bit fields are common in all the three buffer modes and are 1220221167Sgnn * defined in vxge_hal_ring_rxd_1_t 1221221167Sgnn * #define VXGE_HAL_RING_RXD_VLAN_TAG_GET(ctrl1) bVAL16(ctrl1, 48) 1222221167Sgnn * #define VXGE_HAL_RING_RXD_VLAN_TAG(val) vBIT(val, 48, 16) 1223221167Sgnn */ 1224221167Sgnn 1225221167Sgnn u64 buffer0_ptr; 1226221167Sgnn#define VXGE_HAL_RING_RXD_5_RTH_HASH_VALUE_GET(b0_ptr) bVAL32(b0_ptr, 32) 1227221167Sgnn#define VXGE_HAL_RING_RXD_5_RTH_HASH_VALUE(val) vBIT(val, 32, 32) 1228221167Sgnn 1229221167Sgnn u64 buffer1_ptr; 1230221167Sgnn u64 buffer2_ptr; 1231221167Sgnn u64 buffer3_ptr; 1232221167Sgnn u64 buffer4_ptr; 1233221167Sgnn} vxge_hal_ring_rxd_5_t; 1234221167Sgnn 1235221167Sgnn/* 1236221167Sgnn * function vxge_hal_ring_callback_f - Ring callback. 1237221167Sgnn * @vpath_handle: Virtual Path whose Ring "containing" 1 or more completed 1238221167Sgnn * descriptors. 1239221167Sgnn * @rxdh: First completed descriptor. 1240221167Sgnn * @rxd_priv: Pointer to per rxd space allocated 1241221167Sgnn * @t_code: Transfer code, as per X3100 User Guide. 1242221167Sgnn * Returned by HAL. 1243221167Sgnn * @userdata: Opaque per-ring data specified at ring open 1244221167Sgnn * time, via vxge_hal_vpath_open(). 1245221167Sgnn * 1246221167Sgnn * ring completion callback (type declaration). A single per-ring 1247221167Sgnn * callback is specified at virtual path open time, via 1248221167Sgnn * vxge_hal_vpath_open(). 1249221167Sgnn * Typically gets called as part of the processing of the Interrupt 1250221167Sgnn * Service Routine. 1251221167Sgnn * 1252221167Sgnn * ring callback gets called by HAL if, and only if, there is at least 1253221167Sgnn * one new completion on a given ring . Upon processing the first @rxdh 1254221167Sgnn * ULD is _supposed_ to continue consuming completions 1255221167Sgnn * using - vxge_hal_ring_rxd_next_completed(). 1256221167Sgnn * 1257221167Sgnn * Note that failure to process new completions in a timely fashion 1258221167Sgnn * leads to VXGE_HAL_INF_OUT_OF_DESCRIPTORS condition. 1259221167Sgnn * 1260221167Sgnn * Non-zero @t_code means failure to process receive descriptor. 1261221167Sgnn * 1262221167Sgnn * In the "transmit" case the failure could happen, for instance, when the 1263221167Sgnn * link is down, in which case X3100 completes the descriptor because it 1264221167Sgnn * is not able to send the data out. 1265221167Sgnn * 1266221167Sgnn * For details please refer to X3100 User Guide. 1267221167Sgnn * 1268221167Sgnn * See also: vxge_hal_ring_rxd_next_completed(), vxge_hal_ring_rxd_term_f {}. 1269221167Sgnn */ 1270221167Sgnntypedef vxge_hal_status_e(*vxge_hal_ring_callback_f) ( 1271221167Sgnn vxge_hal_vpath_h vpath_handle, 1272221167Sgnn vxge_hal_rxd_h rxdh, 1273221167Sgnn void *rxd_priv, 1274221167Sgnn u8 t_code, 1275221167Sgnn void *userdata); 1276221167Sgnn 1277221167Sgnn/* 1278221167Sgnn * function vxge_hal_ring_rxd_init_f - Initialize descriptor callback. 1279221167Sgnn * @vpath_handle: Virtual path whose ring "containing" the @rxdh descriptor. 1280221167Sgnn * @rxdh: Descriptor. 1281221167Sgnn * @rxd_priv: Pointer to per rxd space allocated 1282221167Sgnn * @index: Index of the descriptor in the ring's set of descriptors. 1283221167Sgnn * @userdata: Per-ring user data (a.k.a. context) specified at 1284221167Sgnn * ring open time, via vxge_hal_vpath_open(). 1285221167Sgnn * @reopen: See vxge_hal_reopen_e {}. 1286221167Sgnn * 1287221167Sgnn * Initialize descriptor callback. Unless NULL is specified in the 1288221167Sgnn * vxge_hal_ring_attr_t {} structure passed to vxge_hal_vpath_open()), 1289221167Sgnn * HAL invokes the callback as part of the ring create in vxge_hal_vpath_open() 1290221167Sgnn * implementation. 1291221167Sgnn * The ULD is expected to fill in this descriptor with buffer(s) 1292221167Sgnn * and control information. 1293221167Sgnn * 1294221167Sgnn * See also: vxge_hal_ring_attr_t {}, vxge_hal_ring_rxd_term_f {}. 1295221167Sgnn */ 1296221167Sgnntypedef vxge_hal_status_e(*vxge_hal_ring_rxd_init_f) ( 1297221167Sgnn vxge_hal_vpath_h vpath_handle, 1298221167Sgnn vxge_hal_rxd_h rxdh, 1299221167Sgnn void *rxd_priv, 1300221167Sgnn u32 index, 1301221167Sgnn void *userdata, 1302221167Sgnn vxge_hal_reopen_e reopen); 1303221167Sgnn 1304221167Sgnn/* 1305221167Sgnn * function vxge_hal_ring_rxd_term_f - Terminate descriptor callback. 1306221167Sgnn * @vpath_handle: Virtual path whose ring "containing" the @rxdh descriptor. 1307221167Sgnn * @rxdh: First completed descriptor. 1308221167Sgnn * @rxd_priv: Pointer to per rxd space allocated 1309221167Sgnn * @state: One of the vxge_hal_rxd_state_e {} enumerated states. 1310221167Sgnn * @userdata: Per-ring user data (a.k.a. context) specified at 1311221167Sgnn * ring open time, via vxge_hal_vpath_open(). 1312221167Sgnn * @reopen: See vxge_hal_reopen_e {}. 1313221167Sgnn * 1314221167Sgnn * Terminate descriptor callback. Unless NULL is specified in the 1315221167Sgnn * vxge_hal_ring_attr_t {} structure passed to vxge_hal_vpath_open()), 1316221167Sgnn * HAL invokes the callback as part of closing the corresponding 1317221167Sgnn * ring, prior to de-allocating the ring and associated data 1318221167Sgnn * structures (including descriptors). 1319221167Sgnn * ULD should utilize the callback to (for instance) unmap 1320221167Sgnn * and free DMA data buffers associated with the posted (state = 1321221167Sgnn * VXGE_HAL_RXD_STATE_POSTED) descriptors, 1322221167Sgnn * as well as other relevant cleanup functions. 1323221167Sgnn * 1324221167Sgnn * See also: vxge_hal_ring_attr_t {}, vxge_hal_ring_rxd_init_f {}. 1325221167Sgnn */ 1326221167Sgnntypedef void (*vxge_hal_ring_rxd_term_f) ( 1327221167Sgnn vxge_hal_vpath_h vpath_handle, 1328221167Sgnn vxge_hal_rxd_h rxdh, 1329221167Sgnn void *rxd_priv, 1330221167Sgnn vxge_hal_rxd_state_e state, 1331221167Sgnn void *userdata, 1332221167Sgnn vxge_hal_reopen_e reopen); 1333221167Sgnn 1334221167Sgnn/* 1335221167Sgnn * struct vxge_hal_ring_attr_t - Ring open "template". 1336221167Sgnn * @callback: Ring completion callback. HAL invokes the callback when there 1337221167Sgnn * are new completions on that ring. In many implementations 1338221167Sgnn * the @callback executes in the hw interrupt context. 1339221167Sgnn * @rxd_init: Ring's descriptor-initialize callback. 1340221167Sgnn * See vxge_hal_ring_rxd_init_f {}. 1341221167Sgnn * If not NULL, HAL invokes the callback when opening 1342221167Sgnn * the ring. 1343221167Sgnn * @rxd_term: Ring's descriptor-terminate callback. If not NULL, 1344221167Sgnn * HAL invokes the callback when closing the corresponding ring. 1345221167Sgnn * See also vxge_hal_ring_rxd_term_f {}. 1346221167Sgnn * @userdata: User-defined "context" of _that_ ring. Passed back to the 1347221167Sgnn * user as one of the @callback, @rxd_init, and @rxd_term arguments. 1348221167Sgnn * @per_rxd_space: If specified (i.e., greater than zero): extra space 1349221167Sgnn * reserved by HAL per each receive descriptor. Can be used to store, 1350221167Sgnn * and retrieve on completion, information specific 1351221167Sgnn * to the upper-layer. 1352221167Sgnn * 1353221167Sgnn * Ring open "template". User fills the structure with ring 1354221167Sgnn * attributes and passes it to vxge_hal_vpath_open(). 1355221167Sgnn */ 1356221167Sgnntypedef struct vxge_hal_ring_attr_t { 1357221167Sgnn vxge_hal_ring_callback_f callback; 1358221167Sgnn vxge_hal_ring_rxd_init_f rxd_init; 1359221167Sgnn vxge_hal_ring_rxd_term_f rxd_term; 1360221167Sgnn void *userdata; 1361221167Sgnn u32 per_rxd_space; 1362221167Sgnn} vxge_hal_ring_attr_t; 1363221167Sgnn 1364221167Sgnn 1365221167Sgnn/* 1366221167Sgnn * vxge_hal_ring_rxd_size_get - Get the size of ring descriptor. 1367221167Sgnn * @buf_mode: Buffer mode (1, 3 or 5) 1368221167Sgnn * 1369221167Sgnn * This function returns the size of RxD for given buffer mode 1370221167Sgnn */ 1371221167Sgnnstatic inline u32 1372221167Sgnn/* LINTED */ 1373221167Sgnnvxge_hal_ring_rxd_size_get( 1374221167Sgnn u32 buf_mode) 1375221167Sgnn{ 1376221167Sgnn return ((u32) (buf_mode == 1 ? sizeof(vxge_hal_ring_rxd_1_t) : \ 1377221167Sgnn (buf_mode == 3 ? sizeof(vxge_hal_ring_rxd_3_t) : \ 1378221167Sgnn sizeof(vxge_hal_ring_rxd_5_t)))); 1379221167Sgnn 1380221167Sgnn} 1381221167Sgnn 1382221167Sgnn/* 1383221167Sgnn * vxge_hal_ring_rxds_per_block_get - Get the number of rxds per block. 1384221167Sgnn * @buf_mode: Buffer mode (1, 3 or 5) 1385221167Sgnn * 1386221167Sgnn * This function returns the number of RxD for RxD block for given buffer mode 1387221167Sgnn */ 1388221167Sgnnstatic inline u32 1389221167Sgnn/* LINTED */ 1390221167Sgnnvxge_hal_ring_rxds_per_block_get( 1391221167Sgnn u32 buf_mode) 1392221167Sgnn{ 1393221167Sgnn return ((u32) ((VXGE_OS_HOST_PAGE_SIZE - 16) / 1394221167Sgnn ((buf_mode == 1) ? sizeof(vxge_hal_ring_rxd_1_t) : 1395221167Sgnn ((buf_mode == 3) ? sizeof(vxge_hal_ring_rxd_3_t) : 1396221167Sgnn sizeof(vxge_hal_ring_rxd_5_t))))); 1397221167Sgnn} 1398221167Sgnn 1399221167Sgnn/* 1400221167Sgnn * vxge_hal_ring_rxd_reserve - Reserve ring descriptor. 1401221167Sgnn * @vpath_handle: virtual Path handle. 1402221167Sgnn * @rxdh: Reserved descriptor. On success HAL fills this "out" parameter 1403221167Sgnn * with a valid handle. 1404221167Sgnn * @rxd_priv: Buffer to return the pointer to per rxd space allocated 1405221167Sgnn * 1406221167Sgnn * Reserve Rx descriptor for the subsequent filling-in (by upper layer 1407221167Sgnn * driver (ULD)) and posting on the corresponding ring 1408221167Sgnn * via vxge_hal_ring_rxd_post(). 1409221167Sgnn * 1410221167Sgnn * Returns: VXGE_HAL_OK - success. 1411221167Sgnn * VXGE_HAL_INF_OUT_OF_DESCRIPTORS - Currently no descriptors available. 1412221167Sgnn * 1413221167Sgnn */ 1414221167Sgnnvxge_hal_status_e 1415221167Sgnnvxge_hal_ring_rxd_reserve( 1416221167Sgnn vxge_hal_vpath_h vpath_handle, 1417221167Sgnn vxge_hal_rxd_h *rxdh, 1418221167Sgnn void **rxd_priv); 1419221167Sgnn 1420221167Sgnn/* 1421221167Sgnn * vxge_hal_ring_rxd_1b_set - Prepare 1-buffer-mode descriptor. 1422221167Sgnn * @rxdh: Descriptor handle. 1423221167Sgnn * @dma_pointer: DMA address of a single receive buffer this descriptor 1424221167Sgnn * should carry. Note that by the time 1425221167Sgnn * vxge_hal_ring_rxd_1b_set is called, the 1426221167Sgnn * receive buffer should be already mapped 1427221167Sgnn * to the corresponding X3100 device. 1428221167Sgnn * @size: Size of the receive @dma_pointer buffer. 1429221167Sgnn * 1430221167Sgnn * Prepare 1-buffer-mode Rx descriptor for posting 1431221167Sgnn * (via vxge_hal_ring_rxd_post()). 1432221167Sgnn * 1433221167Sgnn * This inline helper-function does not return any parameters and always 1434221167Sgnn * succeeds. 1435221167Sgnn * 1436221167Sgnn */ 1437221167Sgnnstatic inline 1438221167Sgnn/* LINTED */ 1439221167Sgnnvoid vxge_hal_ring_rxd_1b_set( 1440221167Sgnn vxge_hal_rxd_h rxdh, 1441221167Sgnn dma_addr_t dma_pointer, 1442221167Sgnn int size) 1443221167Sgnn{ 1444221167Sgnn vxge_hal_ring_rxd_1_t *rxdp = (vxge_hal_ring_rxd_1_t *) rxdh; 1445221167Sgnn rxdp->buffer0_ptr = dma_pointer; 1446221167Sgnn rxdp->control_1 &= ~VXGE_HAL_RING_RXD_1_BUFFER0_SIZE_MASK; 1447221167Sgnn rxdp->control_1 |= VXGE_HAL_RING_RXD_1_BUFFER0_SIZE(size); 1448221167Sgnn} 1449221167Sgnn 1450221167Sgnn/* 1451221167Sgnn * vxge_hal_ring_rxd_3b_set - Prepare 3-buffer-mode descriptor. 1452221167Sgnn * @rxdh: Descriptor handle. 1453221167Sgnn * @dma_pointers: Array of DMA addresses. Contains exactly 3 receive buffers 1454221167Sgnn * _this_ descriptor should carry. Note that by the time 1455221167Sgnn * vxge_hal_ring_rxd_3b_set is called, the receive buffers should 1456221167Sgnn * be mapped to the corresponding X3100 device. 1457221167Sgnn * @sizes: Array of receive buffer sizes. Contains 3 sizes: one size per 1458221167Sgnn * buffer from @dma_pointers. 1459221167Sgnn * 1460221167Sgnn * Prepare 3-buffer-mode Rx descriptor for posting (via 1461221167Sgnn * vxge_hal_ring_rxd_post()). 1462221167Sgnn * This inline helper-function does not return any parameters and always 1463221167Sgnn * succeeds. 1464221167Sgnn * 1465221167Sgnn */ 1466221167Sgnnstatic inline 1467221167Sgnn/* LINTED */ 1468221167Sgnnvoid vxge_hal_ring_rxd_3b_set( 1469221167Sgnn vxge_hal_rxd_h rxdh, 1470221167Sgnn dma_addr_t dma_pointers[], 1471221167Sgnn u32 sizes[]) 1472221167Sgnn{ 1473221167Sgnn vxge_hal_ring_rxd_3_t *rxdp = (vxge_hal_ring_rxd_3_t *) rxdh; 1474221167Sgnn rxdp->buffer0_ptr = dma_pointers[0]; 1475221167Sgnn rxdp->control_1 &= (~VXGE_HAL_RING_RXD_3_BUFFER0_SIZE_MASK); 1476221167Sgnn rxdp->control_1 |= VXGE_HAL_RING_RXD_3_BUFFER0_SIZE(sizes[0]); 1477221167Sgnn rxdp->buffer1_ptr = dma_pointers[1]; 1478221167Sgnn rxdp->control_1 &= (~VXGE_HAL_RING_RXD_3_BUFFER1_SIZE_MASK); 1479221167Sgnn rxdp->control_1 |= VXGE_HAL_RING_RXD_3_BUFFER1_SIZE(sizes[1]); 1480221167Sgnn rxdp->buffer2_ptr = dma_pointers[2]; 1481221167Sgnn rxdp->control_1 &= (~VXGE_HAL_RING_RXD_3_BUFFER2_SIZE_MASK); 1482221167Sgnn rxdp->control_1 |= VXGE_HAL_RING_RXD_3_BUFFER2_SIZE(sizes[2]); 1483221167Sgnn} 1484221167Sgnn 1485221167Sgnn/* 1486221167Sgnn * vxge_hal_ring_rxd_5b_set - Prepare 5-buffer-mode descriptor. 1487221167Sgnn * @rxdh: Descriptor handle. 1488221167Sgnn * @dma_pointers: Array of DMA addresses. Contains exactly 5 receive buffers 1489221167Sgnn * _this_ descriptor should carry. Note that by the time 1490221167Sgnn * vxge_hal_ring_rxd_5b_set is called, the receive buffers should 1491221167Sgnn * be mapped to the corresponding X3100 device. 1492221167Sgnn * @sizes: Array of receive buffer sizes. Contains 5 sizes: one size per buffer 1493221167Sgnn * from @dma_pointers. 1494221167Sgnn * 1495221167Sgnn * Prepare 5-buffer-mode Rx descriptor for posting 1496221167Sgnn * (via vxge_hal_ring_rxd_post()). 1497221167Sgnn * This inline helper-function does not return any 1498221167Sgnn * values and always succeeds. 1499221167Sgnn * 1500221167Sgnn * See also: vxge_hal_ring_rxd_1b_set(), vxge_hal_ring_rxd_3b_set(). 1501221167Sgnn */ 1502221167Sgnnstatic inline 1503221167Sgnn/* LINTED */ 1504221167Sgnnvoid vxge_hal_ring_rxd_5b_set( 1505221167Sgnn vxge_hal_rxd_h rxdh, 1506221167Sgnn dma_addr_t dma_pointers[], 1507221167Sgnn u32 sizes[]) 1508221167Sgnn{ 1509221167Sgnn vxge_hal_ring_rxd_5_t *rxdp = (vxge_hal_ring_rxd_5_t *) rxdh; 1510221167Sgnn 1511221167Sgnn rxdp->buffer0_ptr = dma_pointers[0]; 1512221167Sgnn rxdp->control_1 &= (~VXGE_HAL_RING_RXD_5_BUFFER0_SIZE_MASK); 1513221167Sgnn rxdp->control_1 |= VXGE_HAL_RING_RXD_5_BUFFER0_SIZE(sizes[0]); 1514221167Sgnn rxdp->buffer1_ptr = dma_pointers[1]; 1515221167Sgnn rxdp->control_1 &= (~VXGE_HAL_RING_RXD_5_BUFFER1_SIZE_MASK); 1516221167Sgnn rxdp->control_1 |= VXGE_HAL_RING_RXD_5_BUFFER1_SIZE(sizes[1]); 1517221167Sgnn rxdp->buffer2_ptr = dma_pointers[2]; 1518221167Sgnn rxdp->control_1 &= (~VXGE_HAL_RING_RXD_5_BUFFER2_SIZE_MASK); 1519221167Sgnn rxdp->control_1 |= VXGE_HAL_RING_RXD_5_BUFFER2_SIZE(sizes[2]); 1520221167Sgnn rxdp->buffer3_ptr = dma_pointers[3]; 1521221167Sgnn rxdp->control_2 &= (~VXGE_HAL_RING_RXD_5_BUFFER3_SIZE_MASK); 1522221167Sgnn rxdp->control_2 |= VXGE_HAL_RING_RXD_5_BUFFER3_SIZE(sizes[3]); 1523221167Sgnn rxdp->buffer4_ptr = dma_pointers[4]; 1524221167Sgnn rxdp->control_2 &= (~VXGE_HAL_RING_RXD_5_BUFFER4_SIZE_MASK); 1525221167Sgnn rxdp->control_2 |= VXGE_HAL_RING_RXD_5_BUFFER4_SIZE(sizes[4]); 1526221167Sgnn} 1527221167Sgnn 1528221167Sgnn/* 1529221167Sgnn * vxge_hal_ring_rxd_pre_post - Prepare rxd and post 1530221167Sgnn * @vpath_handle: virtual Path handle. 1531221167Sgnn * @rxdh: Descriptor handle. 1532221167Sgnn * 1533221167Sgnn * This routine prepares a rxd and posts 1534221167Sgnn */ 1535221167Sgnnvoid 1536221167Sgnnvxge_hal_ring_rxd_pre_post( 1537221167Sgnn vxge_hal_vpath_h vpath_handle, 1538221167Sgnn vxge_hal_rxd_h rxdh); 1539221167Sgnn 1540221167Sgnn/* 1541221167Sgnn * vxge_hal_ring_rxd_post_post - Process rxd after post. 1542221167Sgnn * @vpath_handle: virtual Path handle. 1543221167Sgnn * @rxdh: Descriptor handle. 1544221167Sgnn * 1545221167Sgnn * Processes rxd after post 1546221167Sgnn */ 1547221167Sgnnvoid 1548221167Sgnnvxge_hal_ring_rxd_post_post( 1549221167Sgnn vxge_hal_vpath_h vpath_handle, 1550221167Sgnn vxge_hal_rxd_h rxdh); 1551221167Sgnn 1552221167Sgnn/* 1553221167Sgnn * vxge_hal_ring_rxd_post_post_db - Post Doorbell after posting the rxd(s). 1554221167Sgnn * @vpath_handle: virtual Path handle. 1555221167Sgnn * 1556221167Sgnn * Post Doorbell after posting the rxd(s). 1557221167Sgnn */ 1558221167Sgnnvoid 1559221167Sgnnvxge_hal_ring_rxd_post_post_db( 1560221167Sgnn vxge_hal_vpath_h vpath_handle); 1561221167Sgnn 1562221167Sgnn/* 1563221167Sgnn * vxge_hal_ring_rxd_post_post_wmb - Process rxd after post with memory barrier 1564221167Sgnn * @vpath_handle: virtual Path handle. 1565221167Sgnn * @rxdh: Descriptor handle. 1566221167Sgnn * 1567221167Sgnn * Processes rxd after post with memory barrier. 1568221167Sgnn */ 1569221167Sgnnvoid 1570221167Sgnnvxge_hal_ring_rxd_post_post_wmb( 1571221167Sgnn vxge_hal_vpath_h vpath_handle, 1572221167Sgnn vxge_hal_rxd_h rxdh); 1573221167Sgnn 1574221167Sgnn/* 1575221167Sgnn * vxge_hal_ring_rxd_post - Post descriptor on the ring. 1576221167Sgnn * @vpath_handle: virtual Path handle. 1577221167Sgnn * @rxdh: Descriptor obtained via vxge_hal_ring_rxd_reserve(). 1578221167Sgnn * 1579221167Sgnn * Post descriptor on the ring. 1580221167Sgnn * Prior to posting the descriptor should be filled in accordance with 1581221167Sgnn * Host/X3100 interface specification for a given service (LL, etc.). 1582221167Sgnn * 1583221167Sgnn */ 1584221167Sgnnvoid 1585221167Sgnnvxge_hal_ring_rxd_post( 1586221167Sgnn vxge_hal_vpath_h vpath_handle, 1587221167Sgnn vxge_hal_rxd_h rxdh); 1588221167Sgnn 1589221167Sgnn/* 1590221167Sgnn * vxge_hal_ring_is_next_rxd_completed - Check if the next rxd is completed 1591221167Sgnn * @vpath_handle: Virtual Path handle. 1592221167Sgnn * 1593226436Seadler * Checks if the _next_ completed descriptor is in host memory 1594221167Sgnn * 1595221167Sgnn * Returns: VXGE_HAL_OK - success. 1596221167Sgnn * VXGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS - No completed descriptors 1597221167Sgnn * are currently available for processing. 1598221167Sgnn */ 1599221167Sgnnvxge_hal_status_e 1600221167Sgnnvxge_hal_ring_is_next_rxd_completed( 1601221167Sgnn vxge_hal_vpath_h vpath_handle); 1602221167Sgnn 1603221167Sgnn/* 1604221167Sgnn * vxge_hal_ring_rxd_next_completed - Get the _next_ completed descriptor. 1605221167Sgnn * @vpath_handle: Virtual path handle. 1606221167Sgnn * @rxdh: Descriptor handle. Returned by HAL. 1607221167Sgnn * @rxd_priv: Buffer to return a pointer to the per rxd space allocated 1608221167Sgnn * @t_code: Transfer code, as per X3100 User Guide, 1609221167Sgnn * Receive Descriptor Format. Returned by HAL. 1610221167Sgnn * 1611221167Sgnn * Retrieve the _next_ completed descriptor. 1612221167Sgnn * HAL uses ring callback (*vxge_hal_ring_callback_f) to notifiy 1613221167Sgnn * upper-layer driver (ULD) of new completed descriptors. After that 1614221167Sgnn * the ULD can use vxge_hal_ring_rxd_next_completed to retrieve the rest 1615221167Sgnn * completions (the very first completion is passed by HAL via 1616221167Sgnn * vxge_hal_ring_callback_f). 1617221167Sgnn * 1618221167Sgnn * Implementation-wise, the upper-layer driver is free to call 1619221167Sgnn * vxge_hal_ring_rxd_next_completed either immediately from inside the 1620221167Sgnn * ring callback, or in a deferred fashion and separate (from HAL) 1621221167Sgnn * context. 1622221167Sgnn * 1623221167Sgnn * Non-zero @t_code means failure to fill-in receive buffer(s) 1624221167Sgnn * of the descriptor. 1625221167Sgnn * For instance, parity error detected during the data transfer. 1626221167Sgnn * In this case X3100 will complete the descriptor and indicate 1627221167Sgnn * for the host that the received data is not to be used. 1628221167Sgnn * For details please refer to X3100 User Guide. 1629221167Sgnn * 1630221167Sgnn * Returns: VXGE_HAL_OK - success. 1631221167Sgnn * VXGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS - No completed descriptors 1632221167Sgnn * are currently available for processing. 1633221167Sgnn * 1634221167Sgnn * See also: vxge_hal_ring_callback_f {}, 1635221167Sgnn * vxge_hal_fifo_txdl_next_completed(), vxge_hal_status_e {}. 1636221167Sgnn */ 1637221167Sgnnvxge_hal_status_e 1638221167Sgnnvxge_hal_ring_rxd_next_completed( 1639221167Sgnn vxge_hal_vpath_h vpath_handle, 1640221167Sgnn vxge_hal_rxd_h *rxdh, 1641221167Sgnn void **rxd_priv, 1642221167Sgnn u8 *t_code); 1643221167Sgnn 1644221167Sgnn/* 1645221167Sgnn * vxge_hal_ring_handle_tcode - Handle transfer code. 1646221167Sgnn * @vpath_handle: Virtual Path handle. 1647221167Sgnn * @rxdh: Descriptor handle. 1648221167Sgnn * @t_code: One of the enumerated (and documented in the X3100 user guide) 1649221167Sgnn * "transfer codes". 1650221167Sgnn * 1651221167Sgnn * Handle descriptor's transfer code. The latter comes with each completed 1652221167Sgnn * descriptor. 1653221167Sgnn * 1654221167Sgnn * Returns: one of the vxge_hal_status_e {} enumerated types. 1655221167Sgnn * VXGE_HAL_OK - for success. 1656221167Sgnn * VXGE_HAL_ERR_CRITICAL - when encounters critical error. 1657221167Sgnn */ 1658221167Sgnnvxge_hal_status_e 1659221167Sgnnvxge_hal_ring_handle_tcode( 1660221167Sgnn vxge_hal_vpath_h vpath_handle, 1661221167Sgnn vxge_hal_rxd_h rxdh, 1662221167Sgnn u8 t_code); 1663221167Sgnn 1664221167Sgnn/* 1665221167Sgnn * vxge_hal_ring_rxd_1b_get - Get data from the completed 1-buf 1666221167Sgnn * descriptor. 1667221167Sgnn * @vpath_handle: Virtual Path handle. 1668221167Sgnn * @rxdh: Descriptor handle. 1669221167Sgnn * @dma_pointer: DMA address of a single receive buffer _this_ descriptor 1670221167Sgnn * carries. Returned by HAL. 1671221167Sgnn * @pkt_length: Length (in bytes) of the data in the buffer pointed by 1672221167Sgnn * @dma_pointer. Returned by HAL. 1673221167Sgnn * 1674221167Sgnn * Retrieve protocol data from the completed 1-buffer-mode Rx descriptor. 1675221167Sgnn * This inline helper-function uses completed descriptor to populate receive 1676221167Sgnn * buffer pointer and other "out" parameters. The function always succeeds. 1677221167Sgnn * 1678221167Sgnn */ 1679221167Sgnnstatic inline 1680221167Sgnn/* LINTED */ 1681221167Sgnnvoid vxge_hal_ring_rxd_1b_get( 1682221167Sgnn vxge_hal_vpath_h vpath_handle, 1683221167Sgnn vxge_hal_rxd_h rxdh, 1684221167Sgnn dma_addr_t *dma_pointer, 1685221167Sgnn u32 *pkt_length) 1686221167Sgnn{ 1687221167Sgnn vxge_hal_ring_rxd_1_t *rxdp = (vxge_hal_ring_rxd_1_t *) rxdh; 1688221167Sgnn 1689221167Sgnn *pkt_length = 1690221167Sgnn (u32) VXGE_HAL_RING_RXD_1_BUFFER0_SIZE_GET(rxdp->control_1); 1691221167Sgnn *dma_pointer = rxdp->buffer0_ptr; 1692221167Sgnn} 1693221167Sgnn 1694221167Sgnn/* 1695221167Sgnn * vxge_hal_ring_rxd_3b_get - Get data from the completed 3-buf 1696221167Sgnn * descriptor. 1697221167Sgnn * @vpath_handle: Virtual Path handle. 1698221167Sgnn * @rxdh: Descriptor handle. 1699221167Sgnn * @dma_pointers: DMA addresses of the 3 receive buffers _this_ descriptor 1700221167Sgnn * carries. The first two buffers contain ethernet and 1701221167Sgnn * (IP + transport) headers. The 3rd buffer contains packet 1702221167Sgnn * data. 1703221167Sgnn * @sizes: Array of receive buffer sizes. Contains 3 sizes: one size per 1704221167Sgnn * buffer from @dma_pointers. Returned by HAL. 1705221167Sgnn * 1706221167Sgnn * Retrieve protocol data from the completed 3-buffer-mode Rx descriptor. 1707221167Sgnn * This inline helper-function uses completed descriptor to populate receive 1708221167Sgnn * buffer pointer and other "out" parameters. The function always succeeds. 1709221167Sgnn * 1710221167Sgnn */ 1711221167Sgnnstatic inline 1712221167Sgnn/* LINTED */ 1713221167Sgnnvoid vxge_hal_ring_rxd_3b_get( 1714221167Sgnn vxge_hal_vpath_h vpath_handle, 1715221167Sgnn vxge_hal_rxd_h rxdh, 1716221167Sgnn dma_addr_t dma_pointers[], 1717221167Sgnn u32 sizes[]) 1718221167Sgnn{ 1719221167Sgnn vxge_hal_ring_rxd_3_t *rxdp = (vxge_hal_ring_rxd_3_t *) rxdh; 1720221167Sgnn 1721221167Sgnn dma_pointers[0] = rxdp->buffer0_ptr; 1722221167Sgnn sizes[0] = (u32) VXGE_HAL_RING_RXD_3_BUFFER0_SIZE_GET(rxdp->control_1); 1723221167Sgnn 1724221167Sgnn dma_pointers[1] = rxdp->buffer1_ptr; 1725221167Sgnn sizes[1] = (u32) VXGE_HAL_RING_RXD_3_BUFFER1_SIZE_GET(rxdp->control_1); 1726221167Sgnn 1727221167Sgnn dma_pointers[2] = rxdp->buffer2_ptr; 1728221167Sgnn sizes[2] = (u32) VXGE_HAL_RING_RXD_3_BUFFER2_SIZE_GET(rxdp->control_1); 1729221167Sgnn} 1730221167Sgnn 1731221167Sgnn/* 1732221167Sgnn * vxge_hal_ring_rxd_5b_get - Get data from the completed 5-buf descriptor. 1733221167Sgnn * @vpath_handle: Virtual Path handle. 1734221167Sgnn * @rxdh: Descriptor handle. 1735221167Sgnn * @dma_pointers: DMA addresses of the 5 receive buffers _this_ descriptor 1736221167Sgnn * carries. The first 4 buffers contains L2 (ethernet) through 1737221167Sgnn * L5 headers. The 5th buffer contain received (applicaion) 1738221167Sgnn * data. Returned by HAL. 1739221167Sgnn * @sizes: Array of receive buffer sizes. Contains 5 sizes: one size per 1740221167Sgnn * buffer from @dma_pointers. Returned by HAL. 1741221167Sgnn * 1742221167Sgnn * Retrieve protocol data from the completed 5-buffer-mode Rx descriptor. 1743221167Sgnn * This inline helper-function uses completed descriptor to populate receive 1744221167Sgnn * buffer pointer and other "out" parameters. The function always succeeds. 1745221167Sgnn * 1746221167Sgnn * See also: vxge_hal_ring_rxd_3b_get(), vxge_hal_ring_rxd_5b_get(). 1747221167Sgnn */ 1748221167Sgnnstatic inline 1749221167Sgnn/* LINTED */ 1750221167Sgnnvoid vxge_hal_ring_rxd_5b_get( 1751221167Sgnn vxge_hal_vpath_h vpath_handle, 1752221167Sgnn vxge_hal_rxd_h rxdh, 1753221167Sgnn dma_addr_t dma_pointers[], 1754221167Sgnn int sizes[]) 1755221167Sgnn{ 1756221167Sgnn vxge_hal_ring_rxd_5_t *rxdp = (vxge_hal_ring_rxd_5_t *) rxdh; 1757221167Sgnn 1758221167Sgnn dma_pointers[0] = rxdp->buffer0_ptr; 1759221167Sgnn sizes[0] = (u32) VXGE_HAL_RING_RXD_5_BUFFER0_SIZE_GET(rxdp->control_1); 1760221167Sgnn 1761221167Sgnn dma_pointers[1] = rxdp->buffer1_ptr; 1762221167Sgnn sizes[1] = (u32) VXGE_HAL_RING_RXD_5_BUFFER1_SIZE_GET(rxdp->control_1); 1763221167Sgnn 1764221167Sgnn dma_pointers[2] = rxdp->buffer2_ptr; 1765221167Sgnn sizes[2] = (u32) VXGE_HAL_RING_RXD_5_BUFFER2_SIZE_GET(rxdp->control_1); 1766221167Sgnn 1767221167Sgnn dma_pointers[3] = rxdp->buffer3_ptr; 1768221167Sgnn sizes[3] = (u32) VXGE_HAL_RING_RXD_5_BUFFER3_SIZE_GET(rxdp->control_2); 1769221167Sgnn 1770221167Sgnn dma_pointers[4] = rxdp->buffer4_ptr; 1771221167Sgnn sizes[4] = (u32) VXGE_HAL_RING_RXD_5_BUFFER3_SIZE_GET(rxdp->control_2); 1772221167Sgnn} 1773221167Sgnn 1774221167Sgnn/* 1775221167Sgnn * vxge_hal_ring_rxd_1b_info_get - Get extended information associated with 1776221167Sgnn * a completed receive descriptor for 1b mode. 1777221167Sgnn * @vpath_handle: Virtual Path handle. 1778221167Sgnn * @rxdh: Descriptor handle. 1779221167Sgnn * @rxd_info: Descriptor information 1780221167Sgnn * 1781221167Sgnn * Retrieve extended information associated with a completed receive descriptor. 1782221167Sgnn * 1783221167Sgnn */ 1784221167Sgnnstatic inline 1785221167Sgnn/* LINTED */ 1786221167Sgnnvoid vxge_hal_ring_rxd_1b_info_get( 1787221167Sgnn vxge_hal_vpath_h vpath_handle, 1788221167Sgnn vxge_hal_rxd_h rxdh, 1789221167Sgnn vxge_hal_ring_rxd_info_t *rxd_info) 1790221167Sgnn{ 1791221167Sgnn vxge_hal_ring_rxd_1_t *rxdp = (vxge_hal_ring_rxd_1_t *) rxdh; 1792221167Sgnn 1793221167Sgnn rxd_info->syn_flag = 1794221167Sgnn (u32) VXGE_HAL_RING_RXD_SYN_GET(rxdp->control_0); 1795221167Sgnn rxd_info->is_icmp = 1796221167Sgnn (u32) VXGE_HAL_RING_RXD_IS_ICMP_GET(rxdp->control_0); 1797221167Sgnn rxd_info->fast_path_eligible = 1798221167Sgnn (u32) VXGE_HAL_RING_RXD_FAST_PATH_ELIGIBLE_GET(rxdp->control_0); 1799221167Sgnn rxd_info->l3_cksum_valid = 1800221167Sgnn (u32) VXGE_HAL_RING_RXD_L3_CKSUM_CORRECT_GET(rxdp->control_0); 1801221167Sgnn rxd_info->l3_cksum = 1802221167Sgnn (u32) VXGE_HAL_RING_RXD_L3_CKSUM_GET(rxdp->control_0); 1803221167Sgnn rxd_info->l4_cksum_valid = 1804221167Sgnn (u32) VXGE_HAL_RING_RXD_L4_CKSUM_CORRECT_GET(rxdp->control_0); 1805221167Sgnn rxd_info->l4_cksum = 1806221167Sgnn (u32) VXGE_HAL_RING_RXD_L4_CKSUM_GET(rxdp->control_0); 1807221167Sgnn rxd_info->frame = 1808221167Sgnn (u32) VXGE_HAL_RING_RXD_ETHER_ENCAP_GET(rxdp->control_0); 1809221167Sgnn rxd_info->proto = 1810221167Sgnn (u32) VXGE_HAL_RING_RXD_FRAME_PROTO_GET(rxdp->control_0); 1811221167Sgnn rxd_info->is_vlan = 1812221167Sgnn (u32) VXGE_HAL_RING_RXD_IS_VLAN_GET(rxdp->control_0); 1813221167Sgnn rxd_info->vlan = 1814221167Sgnn (u32) VXGE_HAL_RING_RXD_VLAN_TAG_GET(rxdp->control_1); 1815221167Sgnn rxd_info->rth_bucket = 1816221167Sgnn (u32) VXGE_HAL_RING_RXD_RTH_BUCKET_GET(rxdp->control_0); 1817221167Sgnn rxd_info->rth_it_hit = 1818221167Sgnn (u32) VXGE_HAL_RING_RXD_RTH_IT_HIT_GET(rxdp->control_0); 1819221167Sgnn rxd_info->rth_spdm_hit = 1820221167Sgnn (u32) VXGE_HAL_RING_RXD_RTH_SPDM_HIT_GET(rxdp->control_0); 1821221167Sgnn rxd_info->rth_hash_type = 1822221167Sgnn (u32) VXGE_HAL_RING_RXD_RTH_HASH_TYPE_GET(rxdp->control_0); 1823221167Sgnn rxd_info->rth_value = 1824221167Sgnn (u32) VXGE_HAL_RING_RXD_1_RTH_HASH_VAL_GET(rxdp->control_1); 1825221167Sgnn} 1826221167Sgnn 1827221167Sgnn/* 1828221167Sgnn * vxge_hal_ring_rxd_3b_5b_info_get - Get extended information associated with 1829221167Sgnn * a completed receive descriptor for 3b & 5b mode. 1830221167Sgnn * @vpath_handle: Virtual Path handle. 1831221167Sgnn * @rxdh: Descriptor handle. 1832221167Sgnn * @rxd_info: Descriptor information 1833221167Sgnn * 1834221167Sgnn * Retrieve extended information associated with a completed receive descriptor. 1835221167Sgnn * 1836221167Sgnn */ 1837221167Sgnnstatic inline 1838221167Sgnn/* LINTED */ 1839221167Sgnnvoid vxge_hal_ring_rxd_3b_5b_info_get( 1840221167Sgnn vxge_hal_vpath_h vpath_handle, 1841221167Sgnn vxge_hal_rxd_h rxdh, 1842221167Sgnn vxge_hal_ring_rxd_info_t *rxd_info) 1843221167Sgnn{ 1844221167Sgnn vxge_hal_ring_rxd_3_t *rxdp = (vxge_hal_ring_rxd_3_t *) rxdh; 1845221167Sgnn 1846221167Sgnn rxd_info->syn_flag = 1847221167Sgnn (u32) VXGE_HAL_RING_RXD_SYN_GET(rxdp->control_0); 1848221167Sgnn rxd_info->is_icmp = 1849221167Sgnn (u32) VXGE_HAL_RING_RXD_IS_ICMP_GET(rxdp->control_0); 1850221167Sgnn rxd_info->fast_path_eligible = 1851221167Sgnn (u32) VXGE_HAL_RING_RXD_FAST_PATH_ELIGIBLE_GET(rxdp->control_0); 1852221167Sgnn rxd_info->l3_cksum_valid = 1853221167Sgnn (u32) VXGE_HAL_RING_RXD_L3_CKSUM_CORRECT_GET(rxdp->control_0); 1854221167Sgnn rxd_info->l3_cksum = 1855221167Sgnn (u32) VXGE_HAL_RING_RXD_L3_CKSUM_GET(rxdp->control_0); 1856221167Sgnn rxd_info->l4_cksum_valid = 1857221167Sgnn (u32) VXGE_HAL_RING_RXD_L4_CKSUM_CORRECT_GET(rxdp->control_0); 1858221167Sgnn rxd_info->l4_cksum = 1859221167Sgnn (u32) VXGE_HAL_RING_RXD_L4_CKSUM_GET(rxdp->control_0); 1860221167Sgnn rxd_info->frame = 1861221167Sgnn (u32) VXGE_HAL_RING_RXD_ETHER_ENCAP_GET(rxdp->control_0); 1862221167Sgnn rxd_info->proto = 1863221167Sgnn (u32) VXGE_HAL_RING_RXD_FRAME_PROTO_GET(rxdp->control_0); 1864221167Sgnn rxd_info->is_vlan = 1865221167Sgnn (u32) VXGE_HAL_RING_RXD_IS_VLAN_GET(rxdp->control_0); 1866221167Sgnn rxd_info->vlan = 1867221167Sgnn (u32) VXGE_HAL_RING_RXD_VLAN_TAG_GET(rxdp->control_1); 1868221167Sgnn rxd_info->rth_bucket = 1869221167Sgnn (u32) VXGE_HAL_RING_RXD_RTH_BUCKET_GET(rxdp->control_0); 1870221167Sgnn rxd_info->rth_it_hit = 1871221167Sgnn (u32) VXGE_HAL_RING_RXD_RTH_IT_HIT_GET(rxdp->control_0); 1872221167Sgnn rxd_info->rth_spdm_hit = 1873221167Sgnn (u32) VXGE_HAL_RING_RXD_RTH_SPDM_HIT_GET(rxdp->control_0); 1874221167Sgnn rxd_info->rth_hash_type = 1875221167Sgnn (u32) VXGE_HAL_RING_RXD_RTH_HASH_TYPE_GET(rxdp->control_0); 1876221167Sgnn rxd_info->rth_value = (u32) VXGE_HAL_RING_RXD_3_RTH_HASH_VALUE_GET( 1877221167Sgnn rxdp->buffer0_ptr); 1878221167Sgnn} 1879221167Sgnn 1880221167Sgnn/* 1881221167Sgnn * vxge_hal_device_is_privileged 1882221167Sgnn * @host_type: host type. 1883221167Sgnn * @func_id: function id. 1884221167Sgnn * 1885221167Sgnn */ 1886221167Sgnnvxge_hal_status_e 1887221167Sgnnvxge_hal_device_is_privileged( 1888221167Sgnn u32 host_type, 1889221167Sgnn u32 func_id); 1890221167Sgnn 1891221167Sgnn/* 1892221167Sgnn * vxge_hal_ring_rxd_private_get - Get ULD private per-descriptor data 1893221167Sgnn * @vpath_handle: Virtual Path handle. 1894221167Sgnn * @rxdh: Descriptor handle. 1895221167Sgnn * 1896221167Sgnn * Returns: private ULD info associated with the descriptor. 1897221167Sgnn * ULD requests per-descriptor space via vxge_hal_ring_attr. 1898221167Sgnn * 1899221167Sgnn */ 1900221167Sgnnvoid * 1901221167Sgnnvxge_hal_ring_rxd_private_get( 1902221167Sgnn vxge_hal_vpath_h vpath_handle, 1903221167Sgnn vxge_hal_rxd_h rxdh); 1904221167Sgnn 1905221167Sgnn/* 1906221167Sgnn * vxge_hal_ring_rxd_free - Free descriptor. 1907221167Sgnn * @vpath_handle: Virtual Path handle. 1908221167Sgnn * @rxdh: Descriptor handle. 1909221167Sgnn * 1910221167Sgnn * Free the reserved descriptor. This operation is "symmetrical" to 1911221167Sgnn * vxge_hal_ring_rxd_reserve. The "free-ing" completes the descriptor's 1912221167Sgnn * lifecycle. 1913221167Sgnn * 1914221167Sgnn * After free-ing (see vxge_hal_ring_rxd_free()) the descriptor again can 1915221167Sgnn * be: 1916221167Sgnn * 1917221167Sgnn * - reserved (vxge_hal_ring_rxd_reserve); 1918221167Sgnn * 1919221167Sgnn * - posted (vxge_hal_ring_rxd_post); 1920221167Sgnn * 1921221167Sgnn * - completed (vxge_hal_ring_rxd_next_completed); 1922221167Sgnn * 1923221167Sgnn * - and recycled again (vxge_hal_ring_rxd_free). 1924221167Sgnn * 1925221167Sgnn * For alternative state transitions and more details please refer to 1926221167Sgnn * the design doc. 1927221167Sgnn * 1928221167Sgnn */ 1929221167Sgnnvoid 1930221167Sgnnvxge_hal_ring_rxd_free( 1931221167Sgnn vxge_hal_vpath_h vpath_handle, 1932221167Sgnn vxge_hal_rxd_h rxdh); 1933221167Sgnn 1934221167Sgnn 1935221167Sgnn/* 1936221167Sgnn * Fifo 1937221167Sgnn */ 1938221167Sgnn/* 1939221167Sgnn * TX Descriptor 1940221167Sgnn */ 1941221167Sgnn/* 1942221167Sgnn * enum vxge_hal_txdl_state_e - Descriptor (TXDL) state. 1943221167Sgnn * @VXGE_HAL_TXDL_STATE_NONE: Invalid state. 1944221167Sgnn * @VXGE_HAL_TXDL_STATE_AVAIL: Descriptor is available for reservation. 1945221167Sgnn * @VXGE_HAL_TXDL_STATE_POSTED: Descriptor is posted for processing by the 1946221167Sgnn * device. 1947221167Sgnn * @VXGE_HAL_TXDL_STATE_FREED: Descriptor is free and can be reused for 1948221167Sgnn * filling-in and posting later. 1949221167Sgnn * 1950221167Sgnn * X3100/HAL descriptor states. 1951221167Sgnn * 1952221167Sgnn */ 1953221167Sgnntypedef enum vxge_hal_txdl_state_e { 1954221167Sgnn VXGE_HAL_TXDL_STATE_NONE = 0, 1955221167Sgnn VXGE_HAL_TXDL_STATE_AVAIL = 1, 1956221167Sgnn VXGE_HAL_TXDL_STATE_POSTED = 2, 1957221167Sgnn VXGE_HAL_TXDL_STATE_FREED = 3 1958221167Sgnn} vxge_hal_txdl_state_e; 1959221167Sgnn 1960221167Sgnn/* 1961221167Sgnn * enum vxge_hal_fifo_tcode_e - tcodes used in fifo 1962221167Sgnn * @VXGE_HAL_FIFO_T_CODE_OK: Transfer OK 1963221167Sgnn * @VXGE_HAL_FIFO_T_CODE_PCI_READ_CORRUPT: PCI read transaction (either TxD or 1964221167Sgnn * frame data) returned with corrupt data. 1965221167Sgnn * @VXGE_HAL_FIFO_T_CODE_PCI_READ_FAIL:PCI read transaction was returned 1966221167Sgnn * with no data. 1967221167Sgnn * @VXGE_HAL_FIFO_T_CODE_INVALID_MSS: The host attempted to send either a 1968221167Sgnn * frame or LSO MSS that was too long (>9800B). 1969221167Sgnn * @VXGE_HAL_FIFO_T_CODE_LSO_ERROR: Error detected during TCP/UDP Large Send 1970221167Sgnn * Offload operation, due to improper header template, 1971221167Sgnn * unsupported protocol, etc. 1972221167Sgnn * @VXGE_HAL_FIFO_T_CODE_UNUSED: Unused 1973221167Sgnn * @VXGE_HAL_FIFO_T_CODE_MULTI_ERROR: Set to 1 by the adapter if multiple 1974221167Sgnn * data buffer transfer errors are encountered (see below). 1975221167Sgnn * Otherwise it is set to 0. 1976221167Sgnn * 1977221167Sgnn * These tcodes are returned in various API for TxD status 1978221167Sgnn */ 1979221167Sgnntypedef enum vxge_hal_fifo_tcode_e { 1980221167Sgnn VXGE_HAL_FIFO_T_CODE_OK = 0x0, 1981221167Sgnn VXGE_HAL_FIFO_T_CODE_PCI_READ_CORRUPT = 0x1, 1982221167Sgnn VXGE_HAL_FIFO_T_CODE_PCI_READ_FAIL = 0x2, 1983221167Sgnn VXGE_HAL_FIFO_T_CODE_INVALID_MSS = 0x3, 1984221167Sgnn VXGE_HAL_FIFO_T_CODE_LSO_ERROR = 0x4, 1985221167Sgnn VXGE_HAL_FIFO_T_CODE_UNUSED = 0x7, 1986221167Sgnn VXGE_HAL_FIFO_T_CODE_MULTI_ERROR = 0x8 1987221167Sgnn} vxge_hal_fifo_tcode_e; 1988221167Sgnn 1989221167Sgnn/* 1990221167Sgnn * enum vxge_hal_fifo_host_steer_e - Host steer type 1991221167Sgnn * @VXGE_HAL_FIFO_HOST_STEER_NORMAL: Normal. Use Destination/MAC Address 1992221167Sgnn * lookup to determine the transmit porte 1993221167Sgnn * @VXGE_HAL_FIFO_HOST_STEER_PORT1: Send on physical Port1 1994221167Sgnn * @VXGE_HAL_FIFO_HOST_STEER_PORT0: Send on physical Port0 1995221167Sgnn * @VXGE_HAL_FIFO_HOST_STEER_BOTH: Send on both ports. 1996221167Sgnn * 1997221167Sgnn * Host steer type 1998221167Sgnn */ 1999221167Sgnntypedef enum vxge_hal_fifo_host_steer_e { 2000221167Sgnn VXGE_HAL_FIFO_HOST_STEER_NORMAL = 0x0, 2001221167Sgnn VXGE_HAL_FIFO_HOST_STEER_PORT1 = 0x1, 2002221167Sgnn VXGE_HAL_FIFO_HOST_STEER_PORT0 = 0x2, 2003221167Sgnn VXGE_HAL_FIFO_HOST_STEER_BOTH = 0x3 2004221167Sgnn} vxge_hal_fifo_host_steer_e; 2005221167Sgnn 2006221167Sgnn/* 2007221167Sgnn * enum vxge_hal_fifo_gather_code_e - Gather codes used in fifo TxD 2008221167Sgnn * @VXGE_HAL_FIFO_GATHER_CODE_FIRST: First TxDL 2009221167Sgnn * @VXGE_HAL_FIFO_GATHER_CODE_MIDDLE: Middle TxDL 2010221167Sgnn * @VXGE_HAL_FIFO_GATHER_CODE_LAST: Last TxDL 2011221167Sgnn * @VXGE_HAL_FIFO_GATHER_CODE_FIRST_LAST: First and Last TxDL. 2012221167Sgnn * 2013221167Sgnn * These gather codes are used to indicate the position of a TxD in a TxD list 2014221167Sgnn */ 2015221167Sgnntypedef enum vxge_hal_fifo_gather_code_e { 2016221167Sgnn VXGE_HAL_FIFO_GATHER_CODE_FIRST = 0x2, 2017221167Sgnn VXGE_HAL_FIFO_GATHER_CODE_MIDDLE = 0x0, 2018221167Sgnn VXGE_HAL_FIFO_GATHER_CODE_LAST = 0x1, 2019221167Sgnn VXGE_HAL_FIFO_GATHER_CODE_FIRST_LAST = 0x3 2020221167Sgnn} vxge_hal_fifo_gather_code_e; 2021221167Sgnn 2022221167Sgnn/* 2023221167Sgnn * enum vxge_hal_fifo_lso_frm_encap_e - LSO Frame Encapsulation 2024221167Sgnn * @VXGE_HAL_FIFO_LSO_FRM_ENCAP_AUTO: auto mode (best guess) 2025221167Sgnn * @VXGE_HAL_FIFO_LSO_FRM_ENCAP_LLC: LLC 2026221167Sgnn * @VXGE_HAL_FIFO_LSO_FRM_ENCAP_SNAP: SNAP 2027221167Sgnn * @VXGE_HAL_FIFO_LSO_FRM_ENCAP_DIX: DIX 2028221167Sgnn * 2029221167Sgnn * LSO Frame Encapsulation type 2030221167Sgnn */ 2031221167Sgnntypedef enum vxge_hal_fifo_lso_frm_encap_e { 2032221167Sgnn VXGE_HAL_FIFO_LSO_FRM_ENCAP_AUTO = 0x0, 2033221167Sgnn VXGE_HAL_FIFO_LSO_FRM_ENCAP_LLC = 0x1, 2034221167Sgnn VXGE_HAL_FIFO_LSO_FRM_ENCAP_SNAP = 0x2, 2035221167Sgnn VXGE_HAL_FIFO_LSO_FRM_ENCAP_DIX = 0x3 2036221167Sgnn} vxge_hal_fifo_lso_frm_encap_e; 2037221167Sgnn 2038221167Sgnn/* 2039221167Sgnn * struct vxge_hal_fifo_txd_t - Transmit Descriptor 2040221167Sgnn * @control_0: Bits 0 to 6 - Reserved. 2041221167Sgnn * Bit 7 - List Ownership. This field should be initialized 2042221167Sgnn * to '1' by the driver before the transmit list pointer is 2043221167Sgnn * written to the adapter. This field will be set to '0' by the 2044221167Sgnn * adapter once it has completed transmitting the frame or frames 2045221167Sgnn * in the list. Note - This field is only valid in TxD0. 2046221167Sgnn * Additionally, for multi-list sequences, the driver should not 2047221167Sgnn * release any buffers until the ownership of the last list in the 2048221167Sgnn * multi-list sequence has been returned to the host. 2049221167Sgnn * Bits 8 to 11 - Reserved 2050221167Sgnn * Bits 12 to 15 - Transfer_Code. This field is only valid in 2051221167Sgnn * TxD0. It is used to describe the status of the transmit data 2052221167Sgnn * buffer transfer. This field is always overwritten by the 2053221167Sgnn * adapter, so this field may be initialized to any value. 2054221167Sgnn * Bits 16 to 17 - Host steering. This field allows the host to 2055221167Sgnn * override the selection of the physical transmit port. 2056221167Sgnn * Attention: 2057221167Sgnn * Normal sounds as if learned from the switch rather than from 2058221167Sgnn * the aggregation algorythms. 2059221167Sgnn * 00: Normal. Use Destination/MAC Address 2060221167Sgnn * lookup to determine the transmit port. 2061221167Sgnn * 01: Send on physical Port1. 2062221167Sgnn * 10: Send on physical Port0. 2063221167Sgnn * 11: Send on both ports. 2064221167Sgnn * Bits 18 to 21 - Reserved 2065221167Sgnn * Bits 22 to 23 - Gather_Code. This field is set by the host and 2066221167Sgnn * is used to describe how individual buffers comprise a frame. 2067221167Sgnn * 10: First descriptor of a frame. 2068221167Sgnn * 00: Middle of a multi-descriptor frame. 2069221167Sgnn * 01: Last descriptor of a frame. 2070221167Sgnn * 11: First and last descriptor of a frame (the entire frame 2071221167Sgnn * resides in a single buffer). 2072221167Sgnn * For multi-descriptor frames, the only valid gather code sequence 2073221167Sgnn * is {10, [00], 01}. In other words,the descriptors must be placed 2074221167Sgnn * in the list in the correct order. 2075221167Sgnn * Bits 24 to 27 - Reserved 2076221167Sgnn * Bits 28 to 29 - LSO_Frm_Encap. LSO Frame Encapsulation 2077221167Sgnn * definition. Only valid in TxD0. This field allows the host to 2078221167Sgnn * indicate the Ethernet encapsulation of an outbound LSO packet. 2079221167Sgnn * 00 - classic mode (best guess) 2080221167Sgnn * 01 - LLC 2081221167Sgnn * 10 - SNAP 2082221167Sgnn * 11 - DIX 2083221167Sgnn * If "classic mode" is selected, the adapter will attempt to 2084221167Sgnn * decode the frame's Ethernet encapsulation by examining the L/T 2085221167Sgnn * field as follows: 2086221167Sgnn * <= 0x05DC LLC/SNAP encoding; must examine DSAP/SSAP to determine 2087221167Sgnn * if packet is IPv4 or IPv6. 2088221167Sgnn * 0x8870 Jumbo-SNAP encoding. 2089221167Sgnn * 0x0800 IPv4 DIX encoding 2090221167Sgnn * 0x86DD IPv6 DIX encoding 2091221167Sgnn * others illegal encapsulation 2092221167Sgnn * Bits 30 - LSO_ Flag. Large Send Offload (LSO) flag. 2093221167Sgnn * Set to 1 to perform segmentation offload for TCP/UDP. 2094221167Sgnn * This field is valid only in TxD0. 2095221167Sgnn * Bits 31 to 33 - Reserved. 2096221167Sgnn * Bits 34 to 47 - LSO_MSS. TCP/UDP LSO Maximum Segment Size 2097221167Sgnn * This field is meaningful only when LSO_Control is non-zero. 2098221167Sgnn * When LSO_Control is set to TCP_LSO, the single (possibly large) 2099221167Sgnn * TCP segment described by this TxDL will be sent as a series of 2100221167Sgnn * TCP segments each of which contains no more than LSO_MSS 2101221167Sgnn * payload bytes. 2102221167Sgnn * When LSO_Control is set to UDP_LSO, the single (possibly large) 2103221167Sgnn * UDP datagram described by this TxDL will be sent as a series of 2104221167Sgnn * UDP datagrams each of which contains no more than LSO_MSS 2105221167Sgnn * payload bytes. 2106221167Sgnn * All outgoing frames from this TxDL will have LSO_MSS bytes of 2107221167Sgnn * UDP or TCP payload, with the exception of the last, which will 2108221167Sgnn * have <= LSO_MSS bytes of payload. 2109221167Sgnn * Bits 48 to 63 - Buffer_Size. Number of valid bytes in the 2110221167Sgnn * buffer to be read by the adapter. This field is written by the 2111221167Sgnn * host. A value of 0 is illegal. 2112221167Sgnn * Bits 32 to 63 - This value is written by the adapter upon 2113221167Sgnn * completion of a UDP or TCP LSO operation and indicates the 2114221167Sgnn * number of UDP or TCP payload bytes that were transmitted. 2115221167Sgnn * 0x0000 will bereturned for any non-LSO operation. 2116221167Sgnn * @control_1: Bits 0 to 4 - Reserved. 2117221167Sgnn * Bit 5 - Tx_CKO_IPv4 Set to a '1' to enable IPv4 header checksum 2118221167Sgnn * offload. This field is only valid in the first TxD of a frame. 2119221167Sgnn * Bit 6 - Tx_CKO_TCP Set to a '1' to enable TCP checksum offload. 2120221167Sgnn * This field is only valid in the first TxD of a frame (the TxD's 2121221167Sgnn * gather code must be 10 or 11). The driver should only set this 2122221167Sgnn * Bit if it can guarantee that TCP is present. 2123221167Sgnn * Bit 7 - Tx_CKO_UDP Set to a '1' to enable UDP checksum offload. 2124221167Sgnn * This field is only valid in the first TxD of a frame (the TxD's 2125221167Sgnn * gather code must be 10 or 11). The driver should only set this 2126221167Sgnn * Bit if it can guarantee that UDP is present. 2127221167Sgnn * Bits 8 to 14 - Reserved. 2128221167Sgnn * Bit 15 - Tx_VLAN_Enable VLAN tag insertion flag. Set to a '1' to 2129221167Sgnn * instruct the adapter to insert the VLAN tag specified by the 2130221167Sgnn * Tx_VLAN_Tag field. This field is only valid in the first TxD of 2131221167Sgnn * a frame. 2132221167Sgnn * Bits 16 to 31 - Tx_VLAN_Tag. Variable portion of the VLAN tag 2133221167Sgnn * to be inserted into the frame by the adapter(the first two bytes 2134221167Sgnn * of a VLAN tag are always 0x8100).This field is only valid if the 2135221167Sgnn * Tx_VLAN_Enable field is set to '1'. 2136221167Sgnn * Bits 32 to 33 - Reserved. 2137221167Sgnn * Bits 34 to 39 - Tx_Int_Number. Indicates which Tx interrupt 2138221167Sgnn * number the frame associated with. This field is written by the 2139221167Sgnn * host. It is only valid in the first TxD of a frame. 2140221167Sgnn * Bits 40 to 42 - Reserved. 2141221167Sgnn * Bit 43 - Set to 1 to exclude the frame from bandwidth metering 2142221167Sgnn * functions. This field is valid only in the first TxD 2143221167Sgnn * of a frame. 2144221167Sgnn * Bits 44 to 45 - Reserved. 2145221167Sgnn * Bit 46 - Tx_Int_Per_List Set to a '1' to instruct the adapter to 2146221167Sgnn * generate an interrupt as soon as all of the frames in the list 2147221167Sgnn * have been transmitted. In order to have per-frame interrupts, 2148221167Sgnn * the driver should place a maximum of one frame per list. This 2149221167Sgnn * field is only valid in the first TxD of a frame. 2150221167Sgnn * Bit 47 - Tx_Int_Utilization Set to a '1' to instruct the adapter 2151221167Sgnn * to count the frame toward the utilization interrupt specified in 2152221167Sgnn * the Tx_Int_Number field. This field is only valid in the first 2153221167Sgnn * TxD of a frame. 2154221167Sgnn * Bits 48 to 63 - Reserved. 2155221167Sgnn * @buffer_pointer: Buffer start address. 2156221167Sgnn * @host_control: Host_Control.Opaque 64bit data stored by ULD inside the X3100 2157221167Sgnn * descriptor prior to posting the latter on the fifo 2158221167Sgnn * via vxge_hal_fifo_txdl_post().The %host_control is returned as is to 2159221167Sgnn * the ULD with each completed descriptor. 2160221167Sgnn * 2161221167Sgnn * Transmit descriptor (TxD).Fifo descriptor contains configured number 2162221167Sgnn * (list) of TxDs. * For more details please refer to X3100 User Guide, 2163221167Sgnn * Section 5.4.2 "Transmit Descriptor (TxD) Format". 2164221167Sgnn */ 2165221167Sgnntypedef struct vxge_hal_fifo_txd_t { 2166221167Sgnn u64 control_0; 2167221167Sgnn#define VXGE_HAL_FIFO_TXD_LIST_OWN_GET(ctrl0) bVAL1(ctrl0, 7) 2168221167Sgnn#define VXGE_HAL_FIFO_TXD_LIST_OWN_ADAPTER mBIT(7) 2169221167Sgnn 2170221167Sgnn#define VXGE_HAL_FIFO_TXD_T_CODE_GET(ctrl0) bVAL4(ctrl0, 12) 2171221167Sgnn#define VXGE_HAL_FIFO_TXD_T_CODE(val) vBIT(val, 12, 4) 2172221167Sgnn#define VXGE_HAL_FIFO_TXD_T_CODE_OK VXGE_HAL_FIFO_T_CODE_OK 2173221167Sgnn#define VXGE_HAL_FIFO_TXD_T_CODE_PCI_READ_CORRUPT \ 2174221167Sgnn VXGE_HAL_FIFO_T_CODE_PCI_READ_CORRUPT 2175221167Sgnn#define VXGE_HAL_FIFO_TXD_T_CODE_PCI_READ_FAIL \ 2176221167Sgnn VXGE_HAL_FIFO_T_CODE_PCI_READ_FAIL 2177221167Sgnn#define VXGE_HAL_FIFO_TXD_T_CODE_INVALID_MSS VXGE_HAL_FIFO_T_CODE_INVALID_MSS 2178221167Sgnn#define VXGE_HAL_FIFO_TXD_T_CODE_LSO_ERROR VXGE_HAL_FIFO_T_CODE_LSO_ERROR 2179221167Sgnn#define VXGE_HAL_FIFO_TXD_T_CODE_UNUSED VXGE_HAL_FIFO_T_CODE_UNUSED 2180221167Sgnn#define VXGE_HAL_FIFO_TXD_T_CODE_MULTI_ERROR VXGE_HAL_FIFO_T_CODE_MULTI_ERROR 2181221167Sgnn 2182221167Sgnn#define VXGE_HAL_FIFO_TXD_HOST_STEER_GET(ctrl0) bVAL2(ctrl0, 16) 2183221167Sgnn#define VXGE_HAL_FIFO_TXD_HOST_STEER(val) vBIT(val, 16, 2) 2184221167Sgnn#define VXGE_HAL_FIFO_TXD_HOST_STEER_NORMAL VXGE_HAL_FIFO_HOST_STEER_NORMAL 2185221167Sgnn#define VXGE_HAL_FIFO_TXD_HOST_STEER_PORT1 VXGE_HAL_FIFO_HOST_STEER_PORT1 2186221167Sgnn#define VXGE_HAL_FIFO_TXD_HOST_STEER_PORT0 VXGE_HAL_FIFO_HOST_STEER_PORT0 2187221167Sgnn#define VXGE_HAL_FIFO_TXD_HOST_STEER_BOTH VXGE_HAL_FIFO_HOST_STEER_BOTH 2188221167Sgnn 2189221167Sgnn#define VXGE_HAL_FIFO_TXD_GATHER_CODE_GET(ctrl0) bVAL2(ctrl0, 22) 2190221167Sgnn#define VXGE_HAL_FIFO_TXD_GATHER_CODE(val) vBIT(val, 22, 2) 2191221167Sgnn#define VXGE_HAL_FIFO_TXD_GATHER_CODE_FIRST VXGE_HAL_FIFO_GATHER_CODE_FIRST 2192221167Sgnn#define VXGE_HAL_FIFO_TXD_GATHER_CODE_MIDDLE VXGE_HAL_FIFO_GATHER_CODE_MIDDLE 2193221167Sgnn#define VXGE_HAL_FIFO_TXD_GATHER_CODE_LAST VXGE_HAL_FIFO_GATHER_CODE_LAST 2194221167Sgnn#define VXGE_HAL_FIFO_TXD_GATHER_CODE_FIRST_LAST \ 2195221167Sgnn VXGE_HAL_FIFO_GATHER_CODE_FIRST_LAST 2196221167Sgnn 2197221167Sgnn#define VXGE_HAL_FIFO_TXD_LSO_FRM_ENCAP_GET(ctrl0) bVAL2(ctrl0, 28) 2198221167Sgnn#define VXGE_HAL_FIFO_TXD_LSO_FRM_ENCAP(val) vBIT(val, 28, 2) 2199221167Sgnn#define VXGE_HAL_FIFO_TXD_LSO_FRM_ENCAP_AUTO VXGE_HAL_FIFO_LSO_FRM_ENCAP_AUTO 2200221167Sgnn#define VXGE_HAL_FIFO_TXD_LSO_FRM_ENCAP_LLC VXGE_HAL_FIFO_LSO_FRM_ENCAP_LLC 2201221167Sgnn#define VXGE_HAL_FIFO_TXD_LSO_FRM_ENCAP_SNAP VXGE_HAL_FIFO_LSO_FRM_ENCAP_SNAP 2202221167Sgnn#define VXGE_HAL_FIFO_TXD_LSO_FRM_ENCAP_DIX VXGE_HAL_FIFO_LSO_FRM_ENCAP_DIX 2203221167Sgnn 2204221167Sgnn#define VXGE_HAL_FIFO_TXD_LSO_FLAG_GET(ctrl0) bVAL1(ctrl0, 30) 2205221167Sgnn#define VXGE_HAL_FIFO_TXD_LSO_FLAG mBIT(30) 2206221167Sgnn 2207221167Sgnn#define VXGE_HAL_FIFO_TXD_LSO_MSS_GET(ctrl0) bVAL14(ctrl0, 34) 2208221167Sgnn#define VXGE_HAL_FIFO_TXD_LSO_MSS(val) vBIT(val, 34, 14) 2209221167Sgnn 2210221167Sgnn#define VXGE_HAL_FIFO_TXD_BUFFER_SIZE_GET(ctrl0) bVAL16(ctrl0, 48) 2211221167Sgnn#define VXGE_HAL_FIFO_TXD_BUFFER_SIZE(val) vBIT(val, 48, 16) 2212221167Sgnn 2213221167Sgnn#define VXGE_HAL_FIFO_TXD_LSO_BYTES_SENT_GET(ctrl0) bVAL32(ctrl0, 32) 2214221167Sgnn#define VXGE_HAL_FIFO_TXD_LSO_BYTES_SENT(val) vBIT(val, 32, 32) 2215221167Sgnn 2216221167Sgnn u64 control_1; 2217221167Sgnn#define VXGE_HAL_FIFO_TXD_TX_CKO_IPV4_EN_GET(ctrl1) bVAL1(ctrl1, 5) 2218221167Sgnn#define VXGE_HAL_FIFO_TXD_TX_CKO_IPV4_EN mBIT(5) 2219221167Sgnn 2220221167Sgnn#define VXGE_HAL_FIFO_TXD_TX_CKO_TCP_EN_GET(ctrl1) bVAL1(ctrl1, 6) 2221221167Sgnn#define VXGE_HAL_FIFO_TXD_TX_CKO_TCP_EN mBIT(6) 2222221167Sgnn 2223221167Sgnn#define VXGE_HAL_FIFO_TXD_TX_CKO_UDP_EN_GET(ctrl1) bVAL1(ctrl1, 7) 2224221167Sgnn#define VXGE_HAL_FIFO_TXD_TX_CKO_UDP_EN mBIT(7) 2225221167Sgnn 2226221167Sgnn#define VXGE_HAL_FIFO_TXD_TX_CKO_CONTROL (mBIT(5)|mBIT(6)|mBIT(7)) 2227221167Sgnn 2228221167Sgnn#define VXGE_HAL_FIFO_TXD_VLAN_ENABLE_GET(ctrl1) bVAL1(ctrl1, 15) 2229221167Sgnn#define VXGE_HAL_FIFO_TXD_VLAN_ENABLE mBIT(15) 2230221167Sgnn 2231221167Sgnn#define VXGE_HAL_FIFO_TXD_VLAN_TAG_GET(ctrl1) bVAL16(ctrl1, 16) 2232221167Sgnn#define VXGE_HAL_FIFO_TXD_VLAN_TAG(val) vBIT(val, 16, 16) 2233221167Sgnn 2234221167Sgnn#define VXGE_HAL_FIFO_TXD_INT_NUMBER_GET(ctrl1) bVAL6(ctrl1, 34) 2235221167Sgnn#define VXGE_HAL_FIFO_TXD_INT_NUMBER(val) vBIT(val, 34, 6) 2236221167Sgnn 2237221167Sgnn#define VXGE_HAL_FIFO_TXD_NO_BW_LIMIT_GET(ctrl1) bVAL1(ctrl1, 43) 2238221167Sgnn#define VXGE_HAL_FIFO_TXD_NO_BW_LIMIT mBIT(43) 2239221167Sgnn 2240221167Sgnn#define VXGE_HAL_FIFO_TXD_INT_TYPE_PER_LIST_GET(ctrl1) bVAL1(ctrl1, 46) 2241221167Sgnn#define VXGE_HAL_FIFO_TXD_INT_TYPE_PER_LIST mBIT(46) 2242221167Sgnn 2243221167Sgnn#define VXGE_HAL_FIFO_TXD_INT_TYPE_UTILZ_GET(ctrl1) bVAL1(ctrl1, 47) 2244221167Sgnn#define VXGE_HAL_FIFO_TXD_INT_TYPE_UTILZ mBIT(47) 2245221167Sgnn 2246221167Sgnn u64 buffer_pointer; 2247221167Sgnn 2248221167Sgnn u64 host_control; 2249221167Sgnn 2250221167Sgnn} vxge_hal_fifo_txd_t; 2251221167Sgnn 2252221167Sgnntypedef vxge_hal_fifo_txd_t *vxge_hal_fifo_txdl_t; 2253221167Sgnn 2254221167Sgnn/* 2255221167Sgnn * function vxge_hal_fifo_callback_f - FIFO callback. 2256221167Sgnn * @vpath_handle: Virtual path whose Fifo "containing" 1 or more completed 2257221167Sgnn * descriptors. 2258221167Sgnn * @txdlh: First completed descriptor. 2259221167Sgnn * @txdl_priv: Pointer to per txdl space allocated 2260221167Sgnn * @t_code: Transfer code, as per X3100 User Guide. 2261221167Sgnn * Returned by HAL. 2262221167Sgnn * @host_control: Opaque 64bit data stored by ULD inside the X3100 2263221167Sgnn * descriptor prior to posting the latter on the fifo 2264221167Sgnn * via vxge_hal_fifo_txdl_post(). The @host_control is returned 2265221167Sgnn * as is to the ULD with each completed descriptor. 2266221167Sgnn * @userdata: Opaque per-fifo data specified at fifo open 2267221167Sgnn * time, via vxge_hal_vpath_open(). 2268221167Sgnn * 2269221167Sgnn * Fifo completion callback (type declaration). A single per-fifo 2270221167Sgnn * callback is specified at fifo open time, via 2271221167Sgnn * vxge_hal_vpath_open(). Typically gets called as part of the processing 2272221167Sgnn * of the Interrupt Service Routine. 2273221167Sgnn * 2274221167Sgnn * Fifo callback gets called by HAL if, and only if, there is at least 2275221167Sgnn * one new completion on a given fifo. Upon processing the first @txdlh ULD 2276221167Sgnn * is _supposed_ to continue consuming completions using: 2277221167Sgnn * - vxge_hal_fifo_txdl_next_completed() 2278221167Sgnn * 2279221167Sgnn * Note that failure to process new completions in a timely fashion 2280221167Sgnn * leads to VXGE_HAL_INF_OUT_OF_DESCRIPTORS condition. 2281221167Sgnn * 2282221167Sgnn * Non-zero @t_code means failure to process transmit descriptor. 2283221167Sgnn * 2284221167Sgnn * In the "transmit" case the failure could happen, for instance, when the 2285221167Sgnn * link is down, in which case X3100 completes the descriptor because it 2286221167Sgnn * is not able to send the data out. 2287221167Sgnn * 2288221167Sgnn * For details please refer to X3100 User Guide. 2289221167Sgnn * 2290221167Sgnn * See also: vxge_hal_fifo_txdl_next_completed(), vxge_hal_fifo_txdl_term_f {}. 2291221167Sgnn */ 2292221167Sgnntypedef vxge_hal_status_e(*vxge_hal_fifo_callback_f) ( 2293221167Sgnn vxge_hal_vpath_h vpath_handle, 2294221167Sgnn vxge_hal_txdl_h txdlh, 2295221167Sgnn void *txdl_priv, 2296221167Sgnn vxge_hal_fifo_tcode_e t_code, 2297221167Sgnn void *userdata); 2298221167Sgnn 2299221167Sgnn/* 2300221167Sgnn * function vxge_hal_fifo_txdl_init_f - Initialize descriptor callback. 2301221167Sgnn * @vpath_handle: Virtual path whose Fifo "containing" the @txdlh descriptor. 2302221167Sgnn * @txdlh: Descriptor. 2303221167Sgnn * @txdl_priv: Pointer to per txdl space allocated 2304221167Sgnn * @index: Index of the descriptor in the fifo's set of descriptors. 2305221167Sgnn * @userdata: Per-fifo user data (a.k.a. context) specified at 2306221167Sgnn * fifo open time, via vxge_hal_vpath_open(). 2307221167Sgnn * @reopen: See vxge_hal_reopen_e {}. 2308221167Sgnn * 2309221167Sgnn * Initialize descriptor callback. Unless NULL is specified in the 2310221167Sgnn * vxge_hal_fifo_attr_t {} structure passed to vxge_hal_vpath_open()), 2311221167Sgnn * HAL invokes the callback as part of the vxge_hal_vpath_open() 2312221167Sgnn * implementation. 2313221167Sgnn * The ULD could use the callback to pre-set DMA mappings and/or alignment 2314221167Sgnn * buffers. 2315221167Sgnn * 2316221167Sgnn * See also: vxge_hal_fifo_attr_t {}, vxge_hal_fifo_txdl_term_f {}. 2317221167Sgnn */ 2318221167Sgnntypedef vxge_hal_status_e(*vxge_hal_fifo_txdl_init_f) ( 2319221167Sgnn vxge_hal_vpath_h vpath_handle, 2320221167Sgnn vxge_hal_txdl_h txdlh, 2321221167Sgnn void *txdl_priv, 2322221167Sgnn u32 index, 2323221167Sgnn void *userdata, 2324221167Sgnn vxge_hal_reopen_e reopen); 2325221167Sgnn 2326221167Sgnn/* 2327221167Sgnn * function vxge_hal_fifo_txdl_term_f - Terminate descriptor callback. 2328221167Sgnn * @vpath_handle: Virtual path whose Fifo "containing" the @txdlh descriptor. 2329221167Sgnn * @txdlh: First completed descriptor. 2330221167Sgnn * @txdl_priv: Pointer to per txdl space allocated 2331221167Sgnn * @state: One of the vxge_hal_txdl_state_e {} enumerated states. 2332221167Sgnn * @userdata: Per-fifo user data (a.k.a. context) specified at 2333221167Sgnn * fifo open time, via vxge_hal_vpath_open(). 2334221167Sgnn * @reopen: See vxge_hal_reopen_e {}. 2335221167Sgnn * 2336221167Sgnn * Terminate descriptor callback. Unless NULL is specified in the 2337221167Sgnn * vxge_hal_fifo_attr_t {} structure passed to vxge_hal_vpath_open()), 2338221167Sgnn * HAL invokes the callback as part of closing fifo, prior to 2339221167Sgnn * de-allocating the ring and associated data structures 2340221167Sgnn * (including descriptors). 2341221167Sgnn * ULD should utilize the callback to (for instance) unmap 2342221167Sgnn * and free DMA data buffers associated with the posted (state = 2343221167Sgnn * VXGE_HAL_TXDL_STATE_POSTED) descriptors, 2344221167Sgnn * as well as other relevant cleanup functions. 2345221167Sgnn * 2346221167Sgnn * See also: vxge_hal_fifo_attr_t {}, vxge_hal_fifo_txdl_init_f {}. 2347221167Sgnn */ 2348221167Sgnntypedef void (*vxge_hal_fifo_txdl_term_f) ( 2349221167Sgnn vxge_hal_vpath_h vpath_handle, 2350221167Sgnn vxge_hal_txdl_h txdlh, 2351221167Sgnn void *txdl_priv, 2352221167Sgnn vxge_hal_txdl_state_e state, 2353221167Sgnn void *userdata, 2354221167Sgnn vxge_hal_reopen_e reopen); 2355221167Sgnn 2356221167Sgnn/* 2357221167Sgnn * struct vxge_hal_fifo_attr_t - Fifo open "template". 2358221167Sgnn * @callback: Fifo completion callback. HAL invokes the callback when there 2359221167Sgnn * are new completions on that fifo. In many implementations 2360221167Sgnn * the @callback executes in the hw interrupt context. 2361221167Sgnn * @txdl_init: Fifo's descriptor-initialize callback. 2362221167Sgnn * See vxge_hal_fifo_txdl_init_f {}. 2363221167Sgnn * If not NULL, HAL invokes the callback when opening 2364221167Sgnn * the fifo via vxge_hal_vpath_open(). 2365221167Sgnn * @txdl_term: Fifo's descriptor-terminate callback. If not NULL, 2366221167Sgnn * HAL invokes the callback when closing the corresponding fifo. 2367221167Sgnn * See also vxge_hal_fifo_txdl_term_f {}. 2368221167Sgnn * @userdata: User-defined "context" of _that_ fifo. Passed back to the 2369221167Sgnn * user as one of the @callback, @txdl_init, and @txdl_term arguments. 2370221167Sgnn * @per_txdl_space: If specified (i.e., greater than zero): extra space 2371221167Sgnn * reserved by HAL per each transmit descriptor. Can be used to 2372221167Sgnn * store, and retrieve on completion, information specific 2373221167Sgnn * to the upper-layer. 2374221167Sgnn * 2375221167Sgnn * Fifo open "template". User fills the structure with fifo 2376221167Sgnn * attributes and passes it to vxge_hal_vpath_open(). 2377221167Sgnn */ 2378221167Sgnntypedef struct vxge_hal_fifo_attr_t { 2379221167Sgnn vxge_hal_fifo_callback_f callback; 2380221167Sgnn vxge_hal_fifo_txdl_init_f txdl_init; 2381221167Sgnn vxge_hal_fifo_txdl_term_f txdl_term; 2382221167Sgnn void *userdata; 2383221167Sgnn u32 per_txdl_space; 2384221167Sgnn} vxge_hal_fifo_attr_t; 2385221167Sgnn 2386221167Sgnn/* 2387221167Sgnn * vxge_hal_fifo_doorbell_reset - Resets the doorbell fifo 2388221167Sgnn * @vpath_handle: Vpath Handle 2389221167Sgnn * 2390221167Sgnn * This function resets the doorbell fifo during if fifo error occurs 2391221167Sgnn */ 2392221167Sgnnvxge_hal_status_e 2393221167Sgnnvxge_hal_fifo_doorbell_reset( 2394221167Sgnn vxge_hal_vpath_h vpath_handle); 2395221167Sgnn 2396221167Sgnn/* 2397221167Sgnn * vxge_hal_fifo_txdl_reserve - Reserve fifo descriptor. 2398221167Sgnn * @vpath_handle: virtual path handle. 2399221167Sgnn * @txdlh: Reserved descriptor. On success HAL fills this "out" parameter 2400221167Sgnn * with a valid handle. 2401221167Sgnn * @txdl_priv: Buffer to return the pointer to per txdl space allocated 2402221167Sgnn * 2403221167Sgnn * Reserve a single TxDL (that is, fifo descriptor) 2404221167Sgnn * for the subsequent filling-in by upper layerdriver (ULD)) 2405221167Sgnn * and posting on the corresponding fifo 2406221167Sgnn * via vxge_hal_fifo_txdl_post(). 2407221167Sgnn * 2408221167Sgnn * Note: it is the responsibility of ULD to reserve multiple descriptors 2409221167Sgnn * for lengthy (e.g., LSO) transmit operation. A single fifo descriptor 2410221167Sgnn * carries up to configured number (fifo.max_frags) of contiguous buffers. 2411221167Sgnn * 2412221167Sgnn * Returns: VXGE_HAL_OK - success; 2413221167Sgnn * VXGE_HAL_INF_OUT_OF_DESCRIPTORS - Currently no descriptors available 2414221167Sgnn * 2415221167Sgnn */ 2416221167Sgnnvxge_hal_status_e 2417221167Sgnnvxge_hal_fifo_txdl_reserve( 2418221167Sgnn vxge_hal_vpath_h vpath_handle, 2419221167Sgnn vxge_hal_txdl_h *txdlh, 2420221167Sgnn void **txdl_priv); 2421221167Sgnn 2422221167Sgnn 2423221167Sgnn/* 2424221167Sgnn * vxge_hal_fifo_txdl_cksum_set_bits - Offload checksum. 2425221167Sgnn * @txdlh: Descriptor handle. 2426221167Sgnn * @cksum_bits: Specifies which checksums are to be offloaded: IPv4, 2427221167Sgnn * and/or TCP and/or UDP. 2428221167Sgnn * 2429221167Sgnn * Ask X3100 to calculate IPv4 & transport checksums for _this_ transmit 2430221167Sgnn * descriptor. 2431221167Sgnn * This API is part of the preparation of the transmit descriptor for posting 2432221167Sgnn * (via vxge_hal_fifo_txdl_post()). The related "preparation" APIs include 2433221167Sgnn * vxge_hal_fifo_txdl_mss_set(), vxge_hal_fifo_txdl_buffer_set_aligned(), 2434221167Sgnn * and vxge_hal_fifo_txdl_buffer_set(). 2435221167Sgnn * All these APIs fill in the fields of the fifo descriptor, 2436221167Sgnn * in accordance with the X3100 specification. 2437221167Sgnn * 2438221167Sgnn */ 2439221167Sgnnstatic inline 2440221167Sgnn/* LINTED */ 2441221167Sgnnvoid vxge_hal_fifo_txdl_cksum_set_bits( 2442221167Sgnn vxge_hal_txdl_h txdlh, 2443221167Sgnn u64 cksum_bits) 2444221167Sgnn{ 2445221167Sgnn vxge_hal_fifo_txd_t *txdp = (vxge_hal_fifo_txd_t *) txdlh; 2446221167Sgnn 2447221167Sgnn txdp->control_1 |= cksum_bits; 2448221167Sgnn 2449221167Sgnn} 2450221167Sgnn 2451221167Sgnn/* 2452221167Sgnn * vxge_hal_fifo_txdl_interrupt_type_set - Set the interrupt type for the txdl 2453221167Sgnn * @txdlh: Descriptor handle. 2454221167Sgnn * @interrupt_type: utiliz based interupt or List interrupt 2455221167Sgnn * 2456221167Sgnn * vxge_hal_fifo_txdl_interrupt_type_set is used to set the interrupt type for 2457221167Sgnn * each xmit txdl dynamically 2458221167Sgnn */ 2459221167Sgnnstatic inline 2460221167Sgnn/* LINTED */ 2461221167Sgnnvoid vxge_hal_fifo_txdl_interrupt_type_set( 2462221167Sgnn vxge_hal_txdl_h txdlh, 2463221167Sgnn u64 interrupt_type) 2464221167Sgnn{ 2465221167Sgnn vxge_hal_fifo_txd_t *txdp = (vxge_hal_fifo_txd_t *) txdlh; 2466221167Sgnn 2467221167Sgnn txdp->control_1 |= interrupt_type; 2468221167Sgnn} 2469221167Sgnn 2470221167Sgnn/* 2471221167Sgnn * vxge_hal_fifo_txdl_lso_set - Set LSO Parameters. 2472221167Sgnn * @txdlh: Descriptor handle. 2473221167Sgnn * @encap: LSO Encapsulation 2474221167Sgnn * @mss: MSS size for LSO. 2475221167Sgnn * 2476221167Sgnn * This API is part of the preparation of the transmit descriptor for posting 2477221167Sgnn * (via vxge_hal_fifo_txdl_post()). The related "preparation" APIs include 2478221167Sgnn * vxge_hal_fifo_txdl_buffer_set(), vxge_hal_fifo_txdl_buffer_set_aligned(), 2479221167Sgnn * and vxge_hal_fifo_txdl_cksum_set_bits(). 2480221167Sgnn * All these APIs fill in the fields of the fifo descriptor, 2481221167Sgnn * in accordance with the X3100 specification. 2482221167Sgnn * 2483221167Sgnn */ 2484221167Sgnnstatic inline 2485221167Sgnn/* LINTED */ 2486221167Sgnnvoid vxge_hal_fifo_txdl_lso_set( 2487221167Sgnn vxge_hal_txdl_h txdlh, 2488221167Sgnn u32 encap, 2489221167Sgnn u32 mss) 2490221167Sgnn{ 2491221167Sgnn vxge_hal_fifo_txd_t *txdp = (vxge_hal_fifo_txd_t *) txdlh; 2492221167Sgnn 2493221167Sgnn txdp->control_0 |= VXGE_HAL_FIFO_TXD_LSO_FRM_ENCAP(encap) | 2494221167Sgnn VXGE_HAL_FIFO_TXD_LSO_FLAG | VXGE_HAL_FIFO_TXD_LSO_MSS(mss); 2495221167Sgnn} 2496221167Sgnn 2497221167Sgnn/* 2498221167Sgnn * vxge_hal_fifo_txdl_lso_bytes_sent - Get the lso bytes sent. 2499221167Sgnn * @txdlh: Descriptor handle. 2500221167Sgnn * 2501221167Sgnn * Returns the lso bytes sent 2502221167Sgnn */ 2503221167Sgnnstatic inline 2504221167Sgnn/* LINTED */ 2505221167Sgnnu32 vxge_hal_fifo_txdl_lso_bytes_sent( 2506221167Sgnn vxge_hal_txdl_h txdlh) 2507221167Sgnn{ 2508221167Sgnn vxge_hal_fifo_txd_t *txdp = (vxge_hal_fifo_txd_t *) txdlh; 2509221167Sgnn 2510221167Sgnn return (u32) VXGE_HAL_FIFO_TXD_LSO_BYTES_SENT_GET(txdp->control_0); 2511221167Sgnn} 2512221167Sgnn 2513221167Sgnn/* 2514221167Sgnn * vxge_hal_fifo_txdl_vlan_set - Set VLAN tag. 2515221167Sgnn * @txdlh: Descriptor handle. 2516221167Sgnn * @vlan_tag: 16bit VLAN tag. 2517221167Sgnn * 2518221167Sgnn * Insert VLAN tag into specified transmit descriptor. 2519221167Sgnn * The actual insertion of the tag into outgoing frame is done by the hardware. 2520221167Sgnn */ 2521221167Sgnnstatic inline 2522221167Sgnn/* LINTED */ 2523221167Sgnnvoid vxge_hal_fifo_txdl_vlan_set( 2524221167Sgnn vxge_hal_txdl_h txdlh, 2525221167Sgnn u16 vlan_tag) 2526221167Sgnn{ 2527221167Sgnn vxge_hal_fifo_txd_t *txdp = (vxge_hal_fifo_txd_t *) txdlh; 2528221167Sgnn 2529221167Sgnn txdp->control_1 |= VXGE_HAL_FIFO_TXD_VLAN_ENABLE; 2530221167Sgnn txdp->control_1 |= VXGE_HAL_FIFO_TXD_VLAN_TAG(vlan_tag); 2531221167Sgnn} 2532221167Sgnn 2533221167Sgnn/* 2534221167Sgnn * vxge_hal_fifo_txdl_buffer_set - Set transmit buffer pointer in the 2535221167Sgnn * descriptor. 2536221167Sgnn * @vpath_handle: virtual path handle. 2537221167Sgnn * @txdlh: Descriptor handle. 2538230135Suqs * @frag_idx: Index of the data buffer in the caller's scatter-gather list 2539221167Sgnn * (of buffers). 2540221167Sgnn * @dma_pointer: DMA address of the data buffer referenced by @frag_idx. 2541221167Sgnn * @size: Size of the data buffer (in bytes). 2542221167Sgnn * 2543221167Sgnn * This API is part of the preparation of the transmit descriptor for posting 2544221167Sgnn * (via vxge_hal_fifo_txdl_post()). The related "preparation" APIs include 2545221167Sgnn * vxge_hal_fifo_txdl_mss_set() and vxge_hal_fifo_txdl_cksum_set_bits(). 2546221167Sgnn * All three APIs fill in the fields of the fifo descriptor, 2547221167Sgnn * in accordance with the X3100 specification. 2548221167Sgnn * 2549221167Sgnn */ 2550221167Sgnnvoid 2551221167Sgnnvxge_hal_fifo_txdl_buffer_set( 2552221167Sgnn vxge_hal_vpath_h vpath_handle, 2553221167Sgnn vxge_hal_txdl_h txdlh, 2554221167Sgnn u32 frag_idx, 2555221167Sgnn dma_addr_t dma_pointer, 2556221167Sgnn unsigned long size); 2557221167Sgnn 2558221167Sgnn/* 2559221167Sgnn * vxge_hal_fifo_txdl_buffer_set_aligned - Align transmit buffer and fill 2560221167Sgnn * in fifo descriptor. 2561221167Sgnn * @vpath_handle: Virtual path handle. 2562221167Sgnn * @txdlh: Descriptor handle. 2563230135Suqs * @frag_idx: Index of the data buffer in the caller's scatter-gather list 2564221167Sgnn * (of buffers). 2565221167Sgnn * @vaddr: Virtual address of the data buffer. 2566221167Sgnn * @dma_pointer: DMA address of the data buffer referenced by @frag_idx. 2567221167Sgnn * @size: Size of the data buffer (in bytes). 2568221167Sgnn * @misaligned_size: Size (in bytes) of the misaligned portion of the 2569221167Sgnn * data buffer. Calculated by the caller, based on the platform/OS/other 2570221167Sgnn * specific criteria, which is outside of HAL's domain. See notes below. 2571221167Sgnn * 2572221167Sgnn * This API is part of the transmit descriptor preparation for posting 2573221167Sgnn * (via vxge_hal_fifo_txdl_post()). The related "preparation" APIs include 2574221167Sgnn * vxge_hal_fifo_txdl_mss_set() and vxge_hal_fifo_txdl_cksum_set_bits(). 2575221167Sgnn * All three APIs fill in the fields of the fifo descriptor, 2576221167Sgnn * in accordance with the X3100 specification. 2577221167Sgnn * On the PCI-X based systems aligning transmit data typically provides better 2578221167Sgnn * transmit performance. The typical alignment granularity: L2 cacheline size. 2579221167Sgnn * However, HAL does not make assumptions in terms of the alignment granularity; 2580221167Sgnn * this is specified via additional @misaligned_size parameter described above. 2581221167Sgnn * Prior to calling vxge_hal_fifo_txdl_buffer_set_aligned(), 2582221167Sgnn * ULD is supposed to check alignment of a given fragment/buffer. For this HAL 2583221167Sgnn * provides a separate vxge_hal_check_alignment() API sufficient to cover 2584221167Sgnn * most (but not all) possible alignment criteria. 2585221167Sgnn * If the buffer appears to be aligned, the ULD calls 2586221167Sgnn * vxge_hal_fifo_txdl_buffer_set(). 2587221167Sgnn * Otherwise, ULD calls vxge_hal_fifo_txdl_buffer_set_aligned(). 2588221167Sgnn * 2589221167Sgnn * Note; This API is a "superset" of vxge_hal_fifo_txdl_buffer_set(). In 2590221167Sgnn * addition to filling in the specified descriptor it aligns transmit data on 2591221167Sgnn * the specified boundary. 2592221167Sgnn * Note: Decision on whether to align or not to align a given contiguous 2593221167Sgnn * transmit buffer is outside of HAL's domain. To this end ULD can use any 2594221167Sgnn * programmable criteria, which can help to 1) boost transmit performance, 2595221167Sgnn * and/or 2) provide a workaround for PCI bridge bugs, if any. 2596221167Sgnn * 2597221167Sgnn */ 2598221167Sgnnvxge_hal_status_e 2599221167Sgnnvxge_hal_fifo_txdl_buffer_set_aligned( 2600221167Sgnn vxge_hal_vpath_h vpath_handle, 2601221167Sgnn vxge_hal_txdl_h txdlh, 2602221167Sgnn u32 frag_idx, 2603221167Sgnn void *vaddr, 2604221167Sgnn dma_addr_t dma_pointer, 2605221167Sgnn u32 size, 2606221167Sgnn u32 misaligned_size); 2607221167Sgnn 2608221167Sgnn/* 2609221167Sgnn * vxge_hal_fifo_txdl_buffer_append - Append the contents of virtually 2610221167Sgnn * contiguous data buffer to a single physically contiguous buffer. 2611221167Sgnn * @vpath_handle: Virtual path handle. 2612221167Sgnn * @txdlh: Descriptor handle. 2613221167Sgnn * @vaddr: Virtual address of the data buffer. 2614221167Sgnn * @size: Size of the data buffer (in bytes). 2615221167Sgnn * 2616221167Sgnn * This API is part of the transmit descriptor preparation for posting 2617221167Sgnn * (via vxge_hal_fifo_txdl_post()). 2618221167Sgnn * The main difference of this API wrt to the APIs 2619221167Sgnn * vxge_hal_fifo_txdl_buffer_set_aligned() is that this API appends the 2620221167Sgnn * contents of virtually contiguous data buffers received from 2621221167Sgnn * upper layer into a single physically contiguous data buffer and the 2622221167Sgnn * device will do a DMA from this buffer. 2623221167Sgnn * 2624221167Sgnn * See Also: vxge_hal_fifo_txdl_buffer_finalize(), 2625221167Sgnn * vxge_hal_fifo_txdl_buffer_set(), 2626221167Sgnn * vxge_hal_fifo_txdl_buffer_set_aligned(). 2627221167Sgnn */ 2628221167Sgnnvxge_hal_status_e 2629221167Sgnnvxge_hal_fifo_txdl_buffer_append( 2630221167Sgnn vxge_hal_vpath_h vpath_handle, 2631221167Sgnn vxge_hal_txdl_h txdlh, 2632221167Sgnn void *vaddr, 2633221167Sgnn u32 size); 2634221167Sgnn/* 2635221167Sgnn * vxge_hal_fifo_txdl_buffer_finalize - Prepares a descriptor that contains the 2636221167Sgnn * single physically contiguous buffer. 2637221167Sgnn * 2638221167Sgnn * @vpath_handle: Virtual path handle. 2639221167Sgnn * @txdlh: Descriptor handle. 2640221167Sgnn * @frag_idx: Index of the data buffer in the Txdl list. 2641221167Sgnn * 2642221167Sgnn * This API in conjuction with vxge_hal_fifo_txdl_buffer_append() prepares 2643221167Sgnn * a descriptor that consists of a single physically contiguous buffer 2644221167Sgnn * which inturn contains the contents of one or more virtually contiguous 2645221167Sgnn * buffers received from the upper layer. 2646221167Sgnn * 2647221167Sgnn * See Also: vxge_hal_fifo_txdl_buffer_append(). 2648221167Sgnn */ 2649221167Sgnnvoid 2650221167Sgnnvxge_hal_fifo_txdl_buffer_finalize( 2651221167Sgnn vxge_hal_vpath_h vpath_handle, 2652221167Sgnn vxge_hal_txdl_h txdlh, 2653221167Sgnn u32 frag_idx); 2654221167Sgnn 2655221167Sgnn/* 2656221167Sgnn * vxge_hal_fifo_txdl_new_frame_set - Start the new packet by setting TXDL flags 2657221167Sgnn * @vpath_handle: virtual path handle. 2658221167Sgnn * @txdlh: Descriptor handle. 2659221167Sgnn * 2660221167Sgnn * This API is part of the preparation of the transmit descriptor for posting 2661221167Sgnn * (via vxge_hal_fifo_txdl_post()). This api is used to mark the end of previous 2662221167Sgnn * frame and start of a new frame. 2663221167Sgnn * 2664221167Sgnn */ 2665221167Sgnnvoid 2666221167Sgnnvxge_hal_fifo_txdl_new_frame_set( 2667221167Sgnn vxge_hal_vpath_h vpath_handle, 2668221167Sgnn vxge_hal_txdl_h txdlh, 2669221167Sgnn u32 tagged); 2670221167Sgnn 2671221167Sgnn/* 2672221167Sgnn * vxge_hal_fifo_txdl_post - Post descriptor on the fifo. 2673221167Sgnn * @vpath_handle: Virtual path handle. 2674221167Sgnn * @txdlh: Descriptor obtained via vxge_hal_fifo_txdl_reserve() 2675221167Sgnn * 2676221167Sgnn * Post descriptor on the fifo for transmission. 2677221167Sgnn * Prior to posting the descriptor should be filled in accordance with 2678221167Sgnn * Host/X3100 interface specification for a given service (LL, etc.). 2679221167Sgnn * 2680221167Sgnn */ 2681221167Sgnnvoid 2682221167Sgnnvxge_hal_fifo_txdl_post( 2683221167Sgnn vxge_hal_vpath_h vpath_handle, 2684221167Sgnn vxge_hal_txdl_h txdlh, 2685221167Sgnn u32 tagged); 2686221167Sgnn 2687221167Sgnn/* 2688221167Sgnn * vxge_hal_fifo_is_next_txdl_completed - Checks if the next txdl is completed 2689221167Sgnn * @vpath_handle: Virtual path handle. 2690221167Sgnn */ 2691221167Sgnnvxge_hal_status_e 2692221167Sgnnvxge_hal_fifo_is_next_txdl_completed( 2693221167Sgnn vxge_hal_vpath_h vpath_handle); 2694221167Sgnn 2695221167Sgnn/* 2696221167Sgnn * vxge_hal_fifo_free_txdl_count_get - returns the number of txdls available 2697221167Sgnn * in the fifo 2698221167Sgnn * @vpath_handle: Virtual path handle. 2699221167Sgnn */ 2700221167Sgnnu32 2701221167Sgnnvxge_hal_fifo_free_txdl_count_get( 2702221167Sgnn vxge_hal_vpath_h vpath_handle); 2703221167Sgnn 2704221167Sgnn/* 2705221167Sgnn * vxge_hal_fifo_txdl_next_completed - Retrieve next completed descriptor. 2706221167Sgnn * @vpath_handle: Virtual path handle. 2707221167Sgnn * @txdlh: Descriptor handle. Returned by HAL. 2708221167Sgnn * @txdl_priv: Buffer to return the pointer to per txdl space allocated 2709221167Sgnn * @t_code: Transfer code, as per X3100 User Guide, 2710221167Sgnn * Transmit Descriptor Format. 2711221167Sgnn * Returned by HAL. 2712221167Sgnn * 2713221167Sgnn * Retrieve the _next_ completed descriptor. 2714221167Sgnn * HAL uses fifo callback (*vxge_hal_fifo_callback_f) to notifiy 2715221167Sgnn * upper-layer driver (ULD) of new completed descriptors. After that 2716221167Sgnn * the ULD can use vxge_hal_fifo_txdl_next_completed to retrieve the rest 2717221167Sgnn * completions (the very first completion is passed by HAL via 2718221167Sgnn * vxge_hal_fifo_callback_f). 2719221167Sgnn * 2720221167Sgnn * Implementation-wise, the upper-layer driver is free to call 2721221167Sgnn * vxge_hal_fifo_txdl_next_completed either immediately from inside the 2722221167Sgnn * fifo callback, or in a deferred fashion and separate (from HAL) 2723221167Sgnn * context. 2724221167Sgnn * 2725221167Sgnn * Non-zero @t_code means failure to process the descriptor. 2726221167Sgnn * The failure could happen, for instance, when the link is 2727221167Sgnn * down, in which case X3100 completes the descriptor because it 2728221167Sgnn * is not able to send the data out. 2729221167Sgnn * 2730221167Sgnn * For details please refer to X3100 User Guide. 2731221167Sgnn * 2732221167Sgnn * Returns: VXGE_HAL_OK - success. 2733221167Sgnn * VXGE_HAL_INF_NO_MORE_COMPLETED_DESCRIPTORS - No completed descriptors 2734221167Sgnn * are currently available for processing. 2735221167Sgnn * 2736221167Sgnn */ 2737221167Sgnnvxge_hal_status_e 2738221167Sgnnvxge_hal_fifo_txdl_next_completed( 2739221167Sgnn vxge_hal_vpath_h vpath_handle, 2740221167Sgnn vxge_hal_txdl_h *txdlh, 2741221167Sgnn void **txdl_priv, 2742221167Sgnn vxge_hal_fifo_tcode_e *t_code); 2743221167Sgnn 2744221167Sgnn/* 2745221167Sgnn * vxge_hal_fifo_handle_tcode - Handle transfer code. 2746221167Sgnn * @vpath_handle: Virtual Path handle. 2747221167Sgnn * @txdlh: Descriptor handle. 2748221167Sgnn * @t_code: One of the enumerated (and documented in the X3100 user guide) 2749221167Sgnn * "transfer codes". 2750221167Sgnn * 2751221167Sgnn * Handle descriptor's transfer code. The latter comes with each completed 2752221167Sgnn * descriptor. 2753221167Sgnn * 2754221167Sgnn * Returns: one of the vxge_hal_status_e {} enumerated types. 2755221167Sgnn * VXGE_HAL_OK - for success. 2756221167Sgnn * VXGE_HAL_ERR_CRITICAL - when encounters critical error. 2757221167Sgnn */ 2758221167Sgnnvxge_hal_status_e 2759221167Sgnnvxge_hal_fifo_handle_tcode( 2760221167Sgnn vxge_hal_vpath_h vpath_handle, 2761221167Sgnn vxge_hal_txdl_h txdlh, 2762221167Sgnn vxge_hal_fifo_tcode_e t_code); 2763221167Sgnn 2764221167Sgnn/* 2765221167Sgnn * vxge_hal_fifo_txdl_private_get - Retrieve per-descriptor private data. 2766221167Sgnn * @vpath_handle: Virtual path handle. 2767221167Sgnn * @txdlh: Descriptor handle. 2768221167Sgnn * 2769221167Sgnn * Retrieve per-descriptor private data. 2770221167Sgnn * Note that ULD requests per-descriptor space via 2771221167Sgnn * vxge_hal_fifo_attr_t passed to 2772221167Sgnn * vxge_hal_vpath_open(). 2773221167Sgnn * 2774221167Sgnn * Returns: private ULD data associated with the descriptor. 2775221167Sgnn */ 2776221167Sgnnvoid * 2777221167Sgnnvxge_hal_fifo_txdl_private_get( 2778221167Sgnn vxge_hal_vpath_h vpath_handle, 2779221167Sgnn vxge_hal_txdl_h txdlh); 2780221167Sgnn 2781221167Sgnn/* 2782221167Sgnn * vxge_hal_fifo_txdl_free - Free descriptor. 2783221167Sgnn * @vpath_handle: Virtual path handle. 2784221167Sgnn * @txdlh: Descriptor handle. 2785221167Sgnn * 2786221167Sgnn * Free the reserved descriptor. This operation is "symmetrical" to 2787221167Sgnn * vxge_hal_fifo_txdl_reserve. The "free-ing" completes the descriptor's 2788221167Sgnn * lifecycle. 2789221167Sgnn * 2790221167Sgnn * After free-ing (see vxge_hal_fifo_txdl_free()) the descriptor again can 2791221167Sgnn * be: 2792221167Sgnn * 2793221167Sgnn * - reserved (vxge_hal_fifo_txdl_reserve); 2794221167Sgnn * 2795221167Sgnn * - posted (vxge_hal_fifo_txdl_post); 2796221167Sgnn * 2797221167Sgnn * - completed (vxge_hal_fifo_txdl_next_completed); 2798221167Sgnn * 2799221167Sgnn * - and recycled again (vxge_hal_fifo_txdl_free). 2800221167Sgnn * 2801221167Sgnn * For alternative state transitions and more details please refer to 2802221167Sgnn * the design doc. 2803221167Sgnn * 2804221167Sgnn */ 2805221167Sgnnvoid 2806221167Sgnnvxge_hal_fifo_txdl_free( 2807221167Sgnn vxge_hal_vpath_h vpath_handle, 2808221167Sgnn vxge_hal_txdl_h txdlh); 2809221167Sgnn 2810221167Sgnn/* 2811221167Sgnn * Device 2812221167Sgnn */ 2813221167Sgnn 2814221167Sgnn/* 2815221167Sgnn * enum vxge_hal_card_e - X3100 adapter type. 2816221167Sgnn * @VXGE_HAL_CARD_UNKNOWN: Unknown device. 2817221167Sgnn * @VXGE_HAL_CARD_TITAN: X3100 device. 2818221167Sgnn * 2819221167Sgnn * Enumerates X3100 adapter types. 2820221167Sgnn * 2821221167Sgnn * See also: vxge_hal_device_check_id(). 2822221167Sgnn */ 2823221167Sgnntypedef enum vxge_hal_card_e { 2824221167Sgnn VXGE_HAL_CARD_UNKNOWN = 0, 2825221167Sgnn VXGE_HAL_CARD_TITAN_1 = 1, 2826221167Sgnn VXGE_HAL_CARD_TITAN_1A = 2, 2827221167Sgnn VXGE_HAL_CARD_TITAN_2 = 3 2828221167Sgnn} vxge_hal_card_e; 2829221167Sgnn 2830221167Sgnn/* 2831221167Sgnn * struct vxge_hal_device_attr_t - Device memory spaces. 2832221167Sgnn * @regh0: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev 2833221167Sgnn * (Linux and the rest.) 2834221167Sgnn * @regh1: BAR1 mapped memory handle. Same comment as above. 2835221167Sgnn * @regh2: BAR2 mapped memory handle. Same comment as above. 2836221167Sgnn * @bar0: BAR0 virtual address. 2837221167Sgnn * @bar1: BAR1 virtual address. 2838221167Sgnn * @bar2: BAR2 virtual address. 2839221167Sgnn * @irqh: IRQ handle (Solaris). 2840221167Sgnn * @cfgh: Configuration space handle (Solaris), or PCI device @pdev (Linux). 2841221167Sgnn * @pdev: PCI device object. 2842221167Sgnn * 2843221167Sgnn * Device memory spaces. Includes configuration, BAR0, BAR1, etc. per device 2844221167Sgnn * mapped memories. Also, includes a pointer to OS-specific PCI device object. 2845221167Sgnn */ 2846221167Sgnntypedef struct vxge_hal_device_attr_t { 2847221167Sgnn pci_reg_h regh0; 2848221167Sgnn pci_reg_h regh1; 2849221167Sgnn pci_reg_h regh2; 2850221167Sgnn u8 *bar0; 2851221167Sgnn u8 *bar1; 2852221167Sgnn u8 *bar2; 2853221167Sgnn pci_irq_h irqh; 2854221167Sgnn pci_cfg_h cfgh; 2855221167Sgnn pci_dev_h pdev; 2856221167Sgnn} vxge_hal_device_attr_t; 2857221167Sgnn 2858221167Sgnn/* 2859221167Sgnn * enum vxge_hal_device_link_state_e - Link state enumeration. 2860221167Sgnn * @VXGE_HAL_LINK_NONE: Invalid link state. 2861221167Sgnn * @VXGE_HAL_LINK_DOWN: Link is down. 2862221167Sgnn * @VXGE_HAL_LINK_UP: Link is up. 2863221167Sgnn * 2864221167Sgnn */ 2865221167Sgnntypedef enum vxge_hal_device_link_state_e { 2866221167Sgnn VXGE_HAL_LINK_NONE, 2867221167Sgnn VXGE_HAL_LINK_DOWN, 2868221167Sgnn VXGE_HAL_LINK_UP 2869221167Sgnn} vxge_hal_device_link_state_e; 2870221167Sgnn 2871221167Sgnn/* 2872221167Sgnn * enum vxge_hal_device_data_rate_e - Data rate enumeration. 2873221167Sgnn * @VXGE_HAL_DATA_RATE_UNKNOWN: Unknown . 2874221167Sgnn * @VXGE_HAL_DATA_RATE_1G: 1G. 2875221167Sgnn * @VXGE_HAL_DATA_RATE_10G: 10G. 2876221167Sgnn * 2877221167Sgnn */ 2878221167Sgnntypedef enum vxge_hal_device_data_rate_e { 2879221167Sgnn VXGE_HAL_DATA_RATE_UNKNOWN, 2880221167Sgnn VXGE_HAL_DATA_RATE_1G, 2881221167Sgnn VXGE_HAL_DATA_RATE_10G 2882221167Sgnn} vxge_hal_device_data_rate_e; 2883221167Sgnn 2884221167Sgnn/* 2885221167Sgnn * enum vxge_hal_device_lag_mode_e - X3100 adapter lag mode 2886221167Sgnn * @VXGE_HAL_DEVICE_LAG_MODE_UNKNOWN: Unknown mode. 2887221167Sgnn * @VXGE_HAL_DEVICE_LAG_MODE_HW_LACP: Hardware Link Aggregation. 2888221167Sgnn * @VXGE_HAL_DEVICE_LAG_MODE_ACTIVE_PASSIVE: Active Passive. 2889221167Sgnn * @VXGE_HAL_DEVICE_LAG_MODE_SINGLE_PORT: Single Port. 2890221167Sgnn * @VXGE_HAL_DEVICE_LAG_MODE_DUAL_PORT: Dual Port. 2891221167Sgnn * @VXGE_HAL_DEVICE_LAG_MODE_DISABLED: Disabled. 2892221167Sgnn * 2893221167Sgnn * Enumerates X3100 adapter lag modes. 2894221167Sgnn * 2895221167Sgnn */ 2896221167Sgnntypedef enum vxge_hal_device_lag_mode_e { 2897221167Sgnn VXGE_HAL_DEVICE_LAG_MODE_UNKNOWN = 0, 2898221167Sgnn VXGE_HAL_DEVICE_LAG_MODE_HW_LACP, 2899221167Sgnn VXGE_HAL_DEVICE_LAG_MODE_ACTIVE_PASSIVE, 2900221167Sgnn VXGE_HAL_DEVICE_LAG_MODE_SINGLE_PORT, 2901221167Sgnn VXGE_HAL_DEVICE_LAG_MODE_DUAL_PORT, 2902221167Sgnn VXGE_HAL_DEVICE_LAG_MODE_DISABLED 2903221167Sgnn} vxge_hal_device_lag_mode_e; 2904221167Sgnn 2905221167Sgnn/* 2906221167Sgnn * enum vxge_hal_pci_e_signalling_rate_e - PCI-E Lane signalling rate 2907221167Sgnn * @VXGE_HAL_PCI_E_SIGNALLING_RATE_2_5GB: PCI-E signalling rate 2.5 GB 2908221167Sgnn * @VXGE_HAL_PCI_E_SIGNALLING_RATE_5GB: PCI-E signalling rate 5 GB 2909221167Sgnn * @VXGE_HAL_PCI_E_SIGNALLING_RATE_UNKNOWN: Unrecognized PCI bus frequency 2910221167Sgnn * 2911221167Sgnn * PCI-E Lane signalling rate 2912221167Sgnn */ 2913221167Sgnntypedef enum vxge_hal_pci_e_signalling_rate_e { 2914221167Sgnn VXGE_HAL_PCI_E_SIGNALLING_RATE_2_5GB = 1, 2915221167Sgnn VXGE_HAL_PCI_E_SIGNALLING_RATE_5GB = 2, 2916221167Sgnn VXGE_HAL_PCI_E_SIGNALLING_RATE_UNKNOWN = 0 2917221167Sgnn} vxge_hal_pci_e_signalling_rate_e; 2918221167Sgnn 2919221167Sgnn/* 2920221167Sgnn * enum vxge_hal_pci_e_link_width_e - PCI-E Link width enumeration. 2921221167Sgnn * @VXGE_HAL_PCI_E_LINK_WIDTH_X1: 1 Lane. 2922221167Sgnn * @VXGE_HAL_PCI_E_LINK_WIDTH_X2: 2 Lane. 2923221167Sgnn * @VXGE_HAL_PCI_E_LINK_WIDTH_X4: 4 Lane. 2924221167Sgnn * @VXGE_HAL_PCI_E_LINK_WIDTH_X8: 8 Lane. 2925221167Sgnn * @VXGE_HAL_PCI_E_LINK_WIDTH_X12: 12 Lane. 2926221167Sgnn * @VXGE_HAL_PCI_E_LINK_WIDTH_X16: 16 Lane. 2927221167Sgnn * @VXGE_HAL_PCI_E_LINK_WIDTH_X32: 32 Lane. 2928221167Sgnn * @VXGE_HAL_PCI_E_LINK_WIDTH_UNKNOWN: Unknown 2929221167Sgnn * 2930221167Sgnn * PCI-E Link width enumeration. 2931221167Sgnn */ 2932221167Sgnntypedef enum vxge_hal_pci_e_link_width_e { 2933221167Sgnn VXGE_HAL_PCI_E_LINK_WIDTH_X1 = 1, 2934221167Sgnn VXGE_HAL_PCI_E_LINK_WIDTH_X2 = 2, 2935221167Sgnn VXGE_HAL_PCI_E_LINK_WIDTH_X4 = 4, 2936221167Sgnn VXGE_HAL_PCI_E_LINK_WIDTH_X8 = 8, 2937221167Sgnn VXGE_HAL_PCI_E_LINK_WIDTH_X12 = 12, 2938221167Sgnn VXGE_HAL_PCI_E_LINK_WIDTH_X16 = 16, 2939221167Sgnn VXGE_HAL_PCI_E_LINK_WIDTH_X32 = 32, 2940221167Sgnn VXGE_HAL_PCI_E_LINK_WIDTH_UNKNOWN = 0 2941221167Sgnn} vxge_hal_pci_e_link_width_e; 2942221167Sgnn 2943221167Sgnn#define VXGE_HAL_DEVICE_STATS_SW_INFO_NOT_TRAFFIC_INTR(hldev) \ 2944221167Sgnn ((vxge_hal_device_t *)hldev)->not_traffic_intr_cnt++ 2945221167Sgnn 2946221167Sgnn#define VXGE_HAL_DEVICE_STATS_SW_INFO_TRAFFIC_INTR(hldev) \ 2947221167Sgnn ((vxge_hal_device_t *)hldev)->traffic_intr_cnt++ 2948221167Sgnn 2949221167Sgnn/* 2950221167Sgnn * struct vxge_hal_device_t - Hal device object 2951221167Sgnn * @magic: Magic Number 2952221167Sgnn * @device_id: PCI Device Id of the adapter 2953221167Sgnn * @revision: PCI Device major revision 2954221167Sgnn * @upper_layer_data: Private data set by LL driver 2955221167Sgnn * @signalling_rate: PCI-E signalling rate 2956221167Sgnn * @link_width: see vxge_hal_pci_e_link_width_e {} 2957221167Sgnn * @regh0: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev 2958221167Sgnn * (Linux and the rest.) 2959221167Sgnn * @regh1: BAR1 mapped memory handle. Same comment as above. 2960221167Sgnn * @regh2: BAR2 mapped memory handle. Same comment as above. 2961221167Sgnn * @bar0: BAR0 virtual address. 2962221167Sgnn * @bar1: BAR1 virtual address. 2963221167Sgnn * @bar2: BAR2 virtual address. 2964221167Sgnn * @irqh: IRQ handle 2965221167Sgnn * @cfgh: Configuration space handle 2966221167Sgnn * @pdev: Physical device handle 2967221167Sgnn * @config: Confguration passed by the LL driver at initialization 2968221167Sgnn * @is_initialized: Flag to specify if device is initialized 2969221167Sgnn * @msix_enabled: Flag to indicate if msix is enabled 2970221167Sgnn * @terminating: Flag to specify if the device is terminating 2971221167Sgnn * @link_state: Link state 2972221167Sgnn * @data_rate: Data rate 2973221167Sgnn * @not_traffic_intr_cnt: Number of times the host was interrupted 2974221167Sgnn * without new completions. 2975221167Sgnn * "Non-traffic interrupt counter". 2976221167Sgnn * @traffic_intr_cnt: Number of traffic interrupts for the device. 2977221167Sgnn * @debug_module_mask: Debug module mask 2978221167Sgnn * @debug_level: Debug Level 2979221167Sgnn * 2980221167Sgnn * HAL device object. Represents Titan adapter 2981221167Sgnn */ 2982221167Sgnntypedef struct vxge_hal_device_t { 2983221167Sgnn u32 magic; 2984221167Sgnn#define VXGE_HAL_DEVICE_MAGIC 0x12345678 2985221167Sgnn#define VXGE_HAL_DEVICE_DEAD 0xDEADDEAD 2986221167Sgnn u16 device_id; 2987221167Sgnn u16 revision; 2988221167Sgnn void *upper_layer_data; 2989221167Sgnn vxge_hal_pci_e_signalling_rate_e signalling_rate; 2990221167Sgnn vxge_hal_pci_e_link_width_e link_width; 2991221167Sgnn pci_reg_h regh0; 2992221167Sgnn pci_reg_h regh1; 2993221167Sgnn pci_reg_h regh2; 2994221167Sgnn u8 *bar0; 2995221167Sgnn u8 *bar1; 2996221167Sgnn u8 *bar2; 2997221167Sgnn pci_irq_h irqh; 2998221167Sgnn pci_cfg_h cfgh; 2999221167Sgnn pci_dev_h pdev; 3000221167Sgnn vxge_hal_device_config_t config; 3001221167Sgnn volatile u32 is_initialized; 3002221167Sgnn volatile u32 msix_enabled; 3003221167Sgnn volatile u32 terminating; 3004221167Sgnn volatile vxge_hal_device_link_state_e link_state; 3005221167Sgnn volatile vxge_hal_device_data_rate_e data_rate; 3006221167Sgnn volatile u32 not_traffic_intr_cnt; 3007221167Sgnn volatile u32 traffic_intr_cnt; 3008221167Sgnn u32 debug_module_mask; 3009221167Sgnn u32 debug_level; 3010221167Sgnn} vxge_hal_device_t; 3011221167Sgnn 3012221167Sgnn/* 3013221167Sgnn * struct vxge_hal_device_date_t - Date Format 3014221167Sgnn * @day: Day 3015221167Sgnn * @month: Month 3016221167Sgnn * @year: Year 3017221167Sgnn * @date: Date in string format 3018221167Sgnn * 3019221167Sgnn * Structure for returning date 3020221167Sgnn */ 3021221167Sgnntypedef struct vxge_hal_device_date_t { 3022221167Sgnn u32 day; 3023221167Sgnn u32 month; 3024221167Sgnn u32 year; 3025221167Sgnn char date[16]; 3026221167Sgnn} vxge_hal_device_date_t; 3027221167Sgnn 3028221167Sgnn/* 3029221167Sgnn * struct vxge_hal_device_version_t - Version Format 3030221167Sgnn * @major: Major Version 3031221167Sgnn * @minor: Minor Version 3032221167Sgnn * @build: Build Number 3033221167Sgnn * @version: Version in string format 3034221167Sgnn * 3035221167Sgnn * Structure for returning version 3036221167Sgnn */ 3037221167Sgnntypedef struct vxge_hal_device_version_t { 3038221167Sgnn u32 major; 3039221167Sgnn u32 minor; 3040221167Sgnn u32 build; 3041221167Sgnn char version[32]; 3042221167Sgnn} vxge_hal_device_version_t; 3043221167Sgnn 3044221167Sgnn/* 3045221167Sgnn * struct vxge_hal_device_pmd_info_t - PMD Information 3046221167Sgnn * @type: PMD Type 3047221167Sgnn * @vendor: Vender name 3048221167Sgnn * @part_num: PMD Part Number 3049221167Sgnn * @ser_num: PMD Serial Number 3050221167Sgnn * 3051221167Sgnn * Structure for returning PMD info 3052221167Sgnn */ 3053221167Sgnntypedef struct vxge_hal_device_pmd_info_t { 3054221167Sgnn u32 type; 3055221167Sgnn#define VXGE_HAL_DEVICE_PMD_TYPE_UNKNOWN 0 3056221167Sgnn#define VXGE_HAL_DEVICE_PMD_TYPE_10G_SR 1 3057221167Sgnn#define VXGE_HAL_DEVICE_PMD_TYPE_10G_LR 2 3058221167Sgnn#define VXGE_HAL_DEVICE_PMD_TYPE_10G_LRM 3 3059221167Sgnn#define VXGE_HAL_DEVICE_PMD_TYPE_10G_DIRECT 4 3060221167Sgnn#define VXGE_HAL_DEVICE_PMD_TYPE_10G_CX4 5 3061221167Sgnn#define VXGE_HAL_DEVICE_PMD_TYPE_10G_BASE_T 6 3062221167Sgnn#define VXGE_HAL_DEVICE_PMD_TYPE_10G_OTHER 7 3063221167Sgnn#define VXGE_HAL_DEVICE_PMD_TYPE_1G_SX 8 3064221167Sgnn#define VXGE_HAL_DEVICE_PMD_TYPE_1G_LX 9 3065221167Sgnn#define VXGE_HAL_DEVICE_PMD_TYPE_1G_CX 10 3066221167Sgnn#define VXGE_HAL_DEVICE_PMD_TYPE_1G_DIRECT 11 3067221167Sgnn#define VXGE_HAL_DEVICE_PMD_TYPE_1G_CX4 12 3068221167Sgnn#define VXGE_HAL_DEVICE_PMD_TYPE_1G_BASE_T 13 3069221167Sgnn#define VXGE_HAL_DEVICE_PMD_TYPE_1G_OTHER 14 3070221167Sgnn u32 unused; 3071221167Sgnn char vendor[24]; 3072221167Sgnn char part_num[24]; 3073221167Sgnn char ser_num[24]; 3074221167Sgnn} vxge_hal_device_pmd_info_t; 3075221167Sgnn 3076221167Sgnn 3077221167Sgnn/* 3078221167Sgnn * struct vxge_hal_device_hw_info_t - Device information 3079221167Sgnn * @host_type: Host Type 3080221167Sgnn * @function_mode: PCI Function Mode 3081221167Sgnn * @func_id: Function Id 3082221167Sgnn * @vpath_mask: vpath bit mask 3083221167Sgnn * @fw_version: Firmware version 3084221167Sgnn * @fw_date: Firmware Date 3085221167Sgnn * @flash_version: Firmware version 3086221167Sgnn * @flash_date: Firmware Date 3087221167Sgnn * @serial_number: Card Serial Number 3088221167Sgnn * @part_number: Card Part Number 3089221167Sgnn * @product_description: Card Product Description 3090221167Sgnn * @unused: For Solaris alignment purpose 3091221167Sgnn * @ports: Number of ports present 3092221167Sgnn * @pmd_port0: Port 0 PMD Info 3093221167Sgnn * @pmd_port1: Port 1 PMD Info 3094221167Sgnn * @mac_addrs: Mac addresses for each vpath 3095221167Sgnn * @mac_addr_masks: Mac address masks for each vpath 3096221167Sgnn * 3097221167Sgnn * Returns the vpath mask that has the bits set for each vpath allocated 3098240520Seadler * for the driver and the first mac addresse for each vpath 3099221167Sgnn */ 3100221167Sgnntypedef struct vxge_hal_device_hw_info_t { 3101221167Sgnn u32 host_type; 3102221167Sgnn#define VXGE_HAL_NO_MR_NO_SR_NORMAL_FUNCTION 0 3103221167Sgnn#define VXGE_HAL_MR_NO_SR_VH0_BASE_FUNCTION 1 3104221167Sgnn#define VXGE_HAL_NO_MR_SR_VH0_FUNCTION0 2 3105221167Sgnn#define VXGE_HAL_NO_MR_SR_VH0_VIRTUAL_FUNCTION 3 3106221167Sgnn#define VXGE_HAL_MR_SR_VH0_INVALID_CONFIG 4 3107221167Sgnn#define VXGE_HAL_SR_VH_FUNCTION0 5 3108221167Sgnn#define VXGE_HAL_SR_VH_VIRTUAL_FUNCTION 6 3109221167Sgnn#define VXGE_HAL_VH_NORMAL_FUNCTION 7 3110221167Sgnn u64 function_mode; 3111221167Sgnn u32 func_id; 3112221167Sgnn u64 vpath_mask; 3113221167Sgnn vxge_hal_device_version_t fw_version; 3114221167Sgnn vxge_hal_device_date_t fw_date; 3115221167Sgnn vxge_hal_device_version_t flash_version; 3116221167Sgnn vxge_hal_device_date_t flash_date; 3117221167Sgnn u8 serial_number[24]; 3118221167Sgnn u8 part_number[24]; 3119221167Sgnn u8 product_description[72]; 3120221167Sgnn u32 unused; 3121221167Sgnn u32 ports; 3122221167Sgnn vxge_hal_device_pmd_info_t pmd_port0; 3123221167Sgnn vxge_hal_device_pmd_info_t pmd_port1; 3124221167Sgnn macaddr_t mac_addrs[VXGE_HAL_MAX_VIRTUAL_PATHS]; 3125221167Sgnn macaddr_t mac_addr_masks[VXGE_HAL_MAX_VIRTUAL_PATHS]; 3126221167Sgnn} vxge_hal_device_hw_info_t; 3127221167Sgnn 3128221167Sgnn/* 3129221167Sgnn * vxge_hal_device_hw_info_get - Get the hw information 3130221167Sgnn * @pdev: PCI device object. 3131221167Sgnn * @regh0: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev 3132221167Sgnn * (Linux and the rest.) 3133221167Sgnn * @bar0: Address of BAR0 in PCI config 3134221167Sgnn * @hw_info: Buffer to return vxge_hal_device_hw_info_t {} structure 3135221167Sgnn * 3136221167Sgnn * Returns the vpath mask that has the bits set for each vpath allocated 3137221167Sgnn * for the driver, FW version information and the first mac addresse for 3138221167Sgnn * each vpath 3139221167Sgnn */ 3140221167Sgnnvxge_hal_status_e 3141221167Sgnnvxge_hal_device_hw_info_get( 3142221167Sgnn pci_dev_h pdev, 3143221167Sgnn pci_reg_h regh0, 3144221167Sgnn u8 *bar0, 3145221167Sgnn vxge_hal_device_hw_info_t *hw_info); 3146221167Sgnn 3147221167Sgnn/* 3148221167Sgnn * vxge_hal_device_config_default_get - Initialize device config with defaults. 3149221167Sgnn * @device_config: Configuration structure to be initialized, 3150221167Sgnn * For the X3100 configuration "knobs" please 3151221167Sgnn * refer to vxge_hal_device_config_t and X3100 3152221167Sgnn * User Guide. 3153221167Sgnn * 3154221167Sgnn * Initialize X3100 device config with default values. 3155221167Sgnn * 3156221167Sgnn * See also: vxge_hal_device_initialize(), vxge_hal_device_terminate(), 3157221167Sgnn * vxge_hal_status_e {} vxge_hal_device_attr_t {}. 3158221167Sgnn */ 3159221167Sgnnvxge_hal_status_e 3160221167Sgnnvxge_hal_device_config_default_get( 3161221167Sgnn vxge_hal_device_config_t *device_config); 3162221167Sgnn 3163221167Sgnn/* 3164221167Sgnn * vxge_hal_device_initialize - Initialize X3100 device. 3165221167Sgnn * @devh: Buffer to return HAL device handle. 3166221167Sgnn * @attr: pointer to vxge_hal_device_attr_t structure 3167221167Sgnn * @device_config: Configuration to be _applied_ to the device, 3168221167Sgnn * For the X3100 configuration "knobs" please refer to 3169221167Sgnn * vxge_hal_device_config_t and X3100 User Guide. 3170221167Sgnn * 3171221167Sgnn * Initialize X3100 device. Note that all the arguments of this public API 3172221167Sgnn * are 'IN', except @hldev. Upper-layer driver (ULD) cooperates with 3173221167Sgnn * OS to find new X3100 device, locate its PCI and memory spaces. 3174221167Sgnn * 3175221167Sgnn * When done, the ULD allocates sizeof(vxge_hal_device_t) bytes for HAL 3176221167Sgnn * to enable the latter to perform X3100 hardware initialization. 3177221167Sgnn * 3178221167Sgnn * Returns: VXGE_HAL_OK - success. 3179221167Sgnn * VXGE_HAL_ERR_DRIVER_NOT_INITIALIZED - Driver is not initialized. 3180221167Sgnn * VXGE_HAL_ERR_BAD_DEVICE_CONFIG - Device configuration params are not 3181221167Sgnn * valid. 3182221167Sgnn * VXGE_HAL_ERR_OUT_OF_MEMORY - Memory allocation failed. 3183221167Sgnn * VXGE_HAL_ERR_BAD_SUBSYSTEM_ID - Device subsystem id is invalid. 3184221167Sgnn * VXGE_HAL_ERR_INVALID_MAC_ADDRESS - Device mac address in not valid. 3185221167Sgnn * VXGE_HAL_INF_MEM_STROBE_CMD_EXECUTING - Failed to retrieve the mac 3186221167Sgnn * address within the time(timeout) or TTI/RTI initialization failed. 3187221167Sgnn * VXGE_HAL_ERR_SWAPPER_CTRL - Failed to configure swapper control. 3188221167Sgnn * 3189221167Sgnn * See also: vxge_hal_device_terminate(), vxge_hal_status_e {} 3190221167Sgnn * vxge_hal_device_attr_t {}. 3191221167Sgnn */ 3192221167Sgnnvxge_hal_status_e 3193221167Sgnnvxge_hal_device_initialize( 3194221167Sgnn vxge_hal_device_h *devh, 3195221167Sgnn vxge_hal_device_attr_t *attr, 3196221167Sgnn vxge_hal_device_config_t *device_config); 3197221167Sgnn 3198221167Sgnn/* 3199221167Sgnn * vxge_hal_device_check_id - Verify device ID. 3200221167Sgnn * @devh: HAL device handle. 3201221167Sgnn * 3202221167Sgnn * Verify device ID. 3203221167Sgnn * Returns: one of the vxge_hal_card_e {} enumerated types. 3204221167Sgnn * See also: vxge_hal_card_e {}. 3205221167Sgnn */ 3206221167Sgnnstatic inline 3207221167Sgnn/* LINTED */ 3208221167Sgnnvxge_hal_card_e vxge_hal_device_check_id( 3209221167Sgnn vxge_hal_device_h devh) 3210221167Sgnn{ 3211221167Sgnn vxge_hal_device_t *hldev = (vxge_hal_device_t *) devh; 3212221167Sgnn switch (hldev->device_id) { 3213221167Sgnn case VXGE_PCI_DEVICE_ID_TITAN_1: 3214221167Sgnn if (hldev->revision == VXGE_PCI_REVISION_TITAN_1) 3215221167Sgnn return (VXGE_HAL_CARD_TITAN_1); 3216221167Sgnn else if (hldev->revision == VXGE_PCI_REVISION_TITAN_1A) 3217221167Sgnn return (VXGE_HAL_CARD_TITAN_1A); 3218221167Sgnn else 3219221167Sgnn break; 3220221167Sgnn 3221221167Sgnn case VXGE_PCI_DEVICE_ID_TITAN_2: 3222221167Sgnn if (hldev->revision == VXGE_PCI_REVISION_TITAN_2) 3223221167Sgnn return (VXGE_HAL_CARD_TITAN_2); 3224221167Sgnn else 3225221167Sgnn break; 3226221167Sgnn default: 3227221167Sgnn break; 3228221167Sgnn } 3229221167Sgnn 3230221167Sgnn return (VXGE_HAL_CARD_UNKNOWN); 3231221167Sgnn} 3232221167Sgnn 3233221167Sgnn/* 3234221167Sgnn * vxge_hal_device_revision_get - Get Device revision number. 3235221167Sgnn * @devh: HAL device handle. 3236221167Sgnn * 3237221167Sgnn * Returns: Device revision number 3238221167Sgnn */ 3239221167Sgnnstatic inline 3240221167Sgnn/* LINTED */ 3241221167Sgnnu32 vxge_hal_device_revision_get( 3242221167Sgnn vxge_hal_device_h devh) 3243221167Sgnn{ 3244221167Sgnn return (((vxge_hal_device_t *) devh)->revision); 3245221167Sgnn} 3246221167Sgnn 3247221167Sgnn/* 3248221167Sgnn * vxge_hal_device_pciconfig_get - Read the content of given address 3249221167Sgnn * in pci config space. 3250221167Sgnn * @devh: Device handle. 3251221167Sgnn * @offset: Configuration address(offset)to read from 3252221167Sgnn * @length: Length of the data (1, 2 or 4 bytes) 3253221167Sgnn * @val: Pointer to a buffer to return the content of the address 3254221167Sgnn * 3255221167Sgnn * Read from the pci config space. 3256221167Sgnn * 3257221167Sgnn */ 3258221167Sgnnvxge_hal_status_e 3259221167Sgnnvxge_hal_device_pciconfig_get( 3260221167Sgnn vxge_hal_device_h devh, 3261221167Sgnn u32 offset, 3262221167Sgnn u32 length, 3263221167Sgnn void *val); 3264221167Sgnn 3265221167Sgnn/* 3266221167Sgnn * vxge_hal_device_bar0_get - Get BAR0 mapped address. 3267221167Sgnn * @devh: HAL device handle. 3268221167Sgnn * 3269221167Sgnn * Returns: BAR0 address of the specified device. 3270221167Sgnn */ 3271221167Sgnnstatic inline 3272221167Sgnn/* LINTED */ 3273221167Sgnnu8 *vxge_hal_device_bar0_get( 3274221167Sgnn vxge_hal_device_h devh) 3275221167Sgnn{ 3276221167Sgnn return (((vxge_hal_device_t *) devh)->bar0); 3277221167Sgnn} 3278221167Sgnn 3279221167Sgnn/* 3280221167Sgnn * vxge_hal_device_bar1_get - Get BAR1 mapped address. 3281221167Sgnn * @devh: HAL device handle. 3282221167Sgnn * 3283221167Sgnn * Returns: BAR1 address of the specified device. 3284221167Sgnn */ 3285221167Sgnnstatic inline 3286221167Sgnn/* LINTED */ 3287221167Sgnnu8 *vxge_hal_device_bar1_get( 3288221167Sgnn vxge_hal_device_h devh) 3289221167Sgnn{ 3290221167Sgnn return (((vxge_hal_device_t *) devh)->bar1); 3291221167Sgnn} 3292221167Sgnn 3293221167Sgnn/* 3294221167Sgnn * vxge_hal_device_bar2_get - Get BAR2 mapped address. 3295221167Sgnn * @devh: HAL device handle. 3296221167Sgnn * 3297221167Sgnn * Returns: BAR2 address of the specified device. 3298221167Sgnn */ 3299221167Sgnnstatic inline 3300221167Sgnn/* LINTED */ 3301221167Sgnnu8 *vxge_hal_device_bar2_get( 3302221167Sgnn vxge_hal_device_h devh) 3303221167Sgnn{ 3304221167Sgnn return (((vxge_hal_device_t *) devh)->bar2); 3305221167Sgnn} 3306221167Sgnn 3307221167Sgnn/* 3308221167Sgnn * vxge_hal_device_bar0_set - Set BAR0 mapped address. 3309221167Sgnn * @devh: HAL device handle. 3310221167Sgnn * @bar0: BAR0 mapped address. 3311221167Sgnn * * Set BAR0 address in the HAL device object. 3312221167Sgnn */ 3313221167Sgnnstatic inline 3314221167Sgnn/* LINTED */ 3315221167Sgnnvoid 3316221167Sgnnvxge_hal_device_bar0_set( 3317221167Sgnn vxge_hal_device_h devh, 3318221167Sgnn u8 *bar0) 3319221167Sgnn{ 3320221167Sgnn ((vxge_hal_device_t *) devh)->bar0 = bar0; 3321221167Sgnn} 3322221167Sgnn 3323221167Sgnn/* 3324221167Sgnn * vxge_hal_device_bar1_set - Set BAR1 mapped address. 3325221167Sgnn * @devh: HAL device handle. 3326221167Sgnn * @bar1: BAR1 mapped address. 3327221167Sgnn * 3328221167Sgnn * Set BAR1 address in the HAL Device Object. 3329221167Sgnn */ 3330221167Sgnnstatic inline 3331221167Sgnn/* LINTED */ 3332221167Sgnnvoid 3333221167Sgnnvxge_hal_device_bar1_set( 3334221167Sgnn vxge_hal_device_h devh, 3335221167Sgnn u8 *bar1) 3336221167Sgnn{ 3337221167Sgnn ((vxge_hal_device_t *) devh)->bar1 = bar1; 3338221167Sgnn} 3339221167Sgnn 3340221167Sgnn/* 3341221167Sgnn * vxge_hal_device_bar2_set - Set BAR2 mapped address. 3342221167Sgnn * @devh: HAL device handle. 3343221167Sgnn * @bar2: BAR2 mapped address. 3344221167Sgnn * 3345221167Sgnn * Set BAR2 address in the HAL Device Object. 3346221167Sgnn */ 3347221167Sgnnstatic inline 3348221167Sgnn/* LINTED */ 3349221167Sgnnvoid 3350221167Sgnnvxge_hal_device_bar2_set( 3351221167Sgnn vxge_hal_device_h devh, 3352221167Sgnn u8 *bar2) 3353221167Sgnn{ 3354221167Sgnn ((vxge_hal_device_t *) devh)->bar2 = bar2; 3355221167Sgnn} 3356221167Sgnn 3357221167Sgnn/* 3358221167Sgnn * vxge_hal_device_enable - Enable device. 3359221167Sgnn * @devh: HAL device handle. 3360221167Sgnn * 3361221167Sgnn * Enable the specified device: bring up the link/interface. 3362221167Sgnn * 3363221167Sgnn */ 3364221167Sgnnvxge_hal_status_e 3365221167Sgnnvxge_hal_device_enable( 3366221167Sgnn vxge_hal_device_h devh); 3367221167Sgnn 3368221167Sgnn/* 3369221167Sgnn * vxge_hal_device_disable - Disable X3100 adapter. 3370221167Sgnn * @devh: HAL device handle. 3371221167Sgnn * 3372221167Sgnn * Disable this device. To gracefully reset the adapter, the host should: 3373221167Sgnn * 3374221167Sgnn * - call vxge_hal_device_disable(); 3375221167Sgnn * 3376221167Sgnn * - call vxge_hal_device_intr_disable(); 3377221167Sgnn * 3378221167Sgnn * - do some work (error recovery, change mtu, reset, etc); 3379221167Sgnn * 3380221167Sgnn * - call vxge_hal_device_enable(); 3381221167Sgnn * 3382221167Sgnn * - call vxge_hal_device_intr_enable(). 3383221167Sgnn * 3384221167Sgnn * Note: Disabling the device does _not_ include disabling of interrupts. 3385221167Sgnn * After disabling the device stops receiving new frames but those frames 3386221167Sgnn * that were already in the pipe will keep coming for some few milliseconds. 3387221167Sgnn * 3388221167Sgnn * 3389221167Sgnn */ 3390221167Sgnnvxge_hal_status_e 3391221167Sgnnvxge_hal_device_disable( 3392221167Sgnn vxge_hal_device_h devh); 3393221167Sgnn 3394221167Sgnn/* 3395221167Sgnn * vxge_hal_device_pci_info_get - Get PCI bus informations such as width, 3396221167Sgnn * frequency, and mode from previously stored values. 3397221167Sgnn * @devh: HAL device handle. 3398221167Sgnn * @signalling_rate: pointer to a variable of enumerated type 3399221167Sgnn * vxge_hal_pci_e_signalling_rate_e {}. 3400221167Sgnn * @link_width: pointer to a variable of enumerated type 3401221167Sgnn * vxge_hal_pci_e_link_width_e {}. 3402221167Sgnn * 3403221167Sgnn * Get pci-e signalling rate and link width. 3404221167Sgnn * 3405221167Sgnn * Returns: one of the vxge_hal_status_e {} enumerated types. 3406221167Sgnn * VXGE_HAL_OK - for success. 3407221167Sgnn * VXGE_HAL_ERR_INVALID_DEVICE - for invalid device handle. 3408221167Sgnn */ 3409221167Sgnnstatic inline 3410221167Sgnn/* LINTED */ 3411221167Sgnnvxge_hal_status_e vxge_hal_device_pci_info_get( 3412221167Sgnn vxge_hal_device_h devh, 3413221167Sgnn vxge_hal_pci_e_signalling_rate_e *signalling_rate, 3414221167Sgnn vxge_hal_pci_e_link_width_e *link_width) 3415221167Sgnn{ 3416221167Sgnn vxge_hal_device_t *hldev = (vxge_hal_device_t *) devh; 3417221167Sgnn 3418221167Sgnn if (!hldev || !hldev->is_initialized || 3419221167Sgnn (hldev->magic != VXGE_HAL_DEVICE_MAGIC)) { 3420221167Sgnn return (VXGE_HAL_ERR_INVALID_DEVICE); 3421221167Sgnn } 3422221167Sgnn *signalling_rate = hldev->signalling_rate; 3423221167Sgnn *link_width = hldev->link_width; 3424221167Sgnn 3425221167Sgnn return (VXGE_HAL_OK); 3426221167Sgnn} 3427221167Sgnn 3428221167Sgnn/* 3429221167Sgnn * vxge_hal_device_link_state_test - Test the link state. 3430221167Sgnn * @devh: HAL device handle. 3431221167Sgnn * 3432221167Sgnn * Test link state. 3433221167Sgnn * Returns: link state. 3434221167Sgnn */ 3435221167Sgnnvxge_hal_device_link_state_e 3436221167Sgnnvxge_hal_device_link_state_test( 3437221167Sgnn vxge_hal_device_h devh); 3438221167Sgnn 3439221167Sgnn/* 3440221167Sgnn * vxge_hal_device_link_state_get - Get link state. 3441221167Sgnn * @devh: HAL device handle. 3442221167Sgnn * 3443221167Sgnn * Get link state. 3444221167Sgnn * Returns: link state. 3445221167Sgnn */ 3446221167Sgnnstatic inline 3447221167Sgnn/* LINTED */ 3448221167Sgnnvxge_hal_device_link_state_e vxge_hal_device_link_state_get( 3449221167Sgnn vxge_hal_device_h devh) 3450221167Sgnn{ 3451221167Sgnn return (((vxge_hal_device_t *) devh)->link_state); 3452221167Sgnn} 3453221167Sgnn 3454221167Sgnn/* 3455221167Sgnn * vxge_hal_device_link_state_poll - Poll for the link state. 3456221167Sgnn * @devh: HAL device handle. 3457221167Sgnn * 3458221167Sgnn * Get link state. 3459221167Sgnn * Returns: link state. 3460221167Sgnn */ 3461221167Sgnnvxge_hal_device_link_state_e 3462221167Sgnnvxge_hal_device_link_state_poll( 3463221167Sgnn vxge_hal_device_h devh); 3464221167Sgnn 3465221167Sgnn/* 3466221167Sgnn * vxge_hal_device_data_rate_get - Get data rate. 3467221167Sgnn * @devh: HAL device handle. 3468221167Sgnn * 3469221167Sgnn * Get data rate. 3470221167Sgnn * Returns: data rate(1G or 10G). 3471221167Sgnn */ 3472221167Sgnnstatic inline 3473221167Sgnn/* LINTED */ 3474221167Sgnnvxge_hal_device_data_rate_e vxge_hal_device_data_rate_get( 3475221167Sgnn vxge_hal_device_h devh) 3476221167Sgnn{ 3477221167Sgnn return (((vxge_hal_device_t *) devh)->data_rate); 3478221167Sgnn} 3479221167Sgnn 3480221167Sgnn/* 3481221167Sgnn * vxge_hal_device_data_rate_poll - Poll for the data rate. 3482221167Sgnn * @devh: HAL device handle. 3483221167Sgnn * 3484221167Sgnn * Get data rate. 3485221167Sgnn * Returns: data rate. 3486221167Sgnn */ 3487221167Sgnnvxge_hal_device_data_rate_e 3488221167Sgnnvxge_hal_device_data_rate_poll( 3489221167Sgnn vxge_hal_device_h devh); 3490221167Sgnn 3491221167Sgnn/* 3492221167Sgnn * vxge_hal_device_lag_mode_get - Get Current LAG Mode 3493221167Sgnn * @devh: HAL device handle. 3494221167Sgnn * 3495221167Sgnn * Get Current LAG Mode 3496221167Sgnn */ 3497221167Sgnnvxge_hal_device_lag_mode_e 3498221167Sgnnvxge_hal_device_lag_mode_get( 3499221167Sgnn vxge_hal_device_h devh); 3500221167Sgnn 3501221167Sgnn/* 3502221167Sgnn * vxge_hal_device_reset - Reset device. 3503221167Sgnn * @devh: HAL device handle. 3504221167Sgnn * 3505221167Sgnn * Soft-reset the device, reset the device stats except reset_cnt. 3506221167Sgnn * 3507221167Sgnn * After reset is done, will try to re-initialize HW. 3508221167Sgnn * 3509221167Sgnn * Returns: VXGE_HAL_PENDING - successfully sent reset to device. 3510221167Sgnn * VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED - Device is not initialized. 3511221167Sgnn * VXGE_HAL_ERR_RESET_FAILED - Reset failed. 3512221167Sgnn * 3513221167Sgnn */ 3514221167Sgnnvxge_hal_status_e 3515221167Sgnnvxge_hal_device_reset( 3516221167Sgnn vxge_hal_device_h devh); 3517221167Sgnn 3518221167Sgnn/* 3519221167Sgnn * vxge_hal_device_reset_poll - Poll the device for reset complete. 3520221167Sgnn * @devh: HAL device handle. 3521221167Sgnn * 3522221167Sgnn * Poll the device for reset complete 3523221167Sgnn * 3524221167Sgnn * Returns: VXGE_HAL_OK - success. 3525221167Sgnn * VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED - Device is not initialized. 3526221167Sgnn * VXGE_HAL_ERR_RESET_FAILED - Reset failed. 3527221167Sgnn * 3528221167Sgnn * See also: vxge_hal_status_e {}. 3529221167Sgnn */ 3530221167Sgnnvxge_hal_status_e 3531221167Sgnnvxge_hal_device_reset_poll(vxge_hal_device_h devh); 3532221167Sgnn 3533221167Sgnn/* 3534221167Sgnn * vxge_hal_device_mrpcim_reset_poll - Poll the device for mrpcim reset 3535221167Sgnn * complete. 3536221167Sgnn * @devh: HAL device handle. 3537221167Sgnn * 3538221167Sgnn * Poll the device for mrpcim reset complete 3539221167Sgnn * 3540221167Sgnn * Returns: VXGE_HAL_OK - success. 3541221167Sgnn * VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED - Device is not initialized. 3542221167Sgnn * VXGE_HAL_ERR_RESET_FAILED - Reset failed. 3543221167Sgnn * VXGE_HAL_ERR_MANAGER_NOT_FOUND - MRPCIM/SRPCIM manager not found 3544221167Sgnn * VXGE_HAL_ERR_TIME_OUT - Device Reset timed out 3545221167Sgnn * 3546221167Sgnn * See also: vxge_hal_status_e {}. 3547221167Sgnn */ 3548221167Sgnnvxge_hal_status_e 3549221167Sgnnvxge_hal_device_mrpcim_reset_poll(vxge_hal_device_h devh); 3550221167Sgnn 3551221167Sgnn/* 3552221167Sgnn * vxge_hal_device_terminating - Mark the device as 'terminating'. 3553221167Sgnn * @devh: HAL device handle. 3554221167Sgnn * 3555221167Sgnn * Mark the device as 'terminating', going to terminate. Can be used 3556221167Sgnn * to serialize termination with other running processes/contexts. 3557221167Sgnn * 3558221167Sgnn * See also: vxge_hal_device_terminate(). 3559221167Sgnn */ 3560221167Sgnnstatic inline void 3561221167Sgnn/* LINTED */ 3562221167Sgnnvxge_hal_device_terminating(vxge_hal_device_h devh) 3563221167Sgnn{ 3564221167Sgnn ((vxge_hal_device_t *) devh)->terminating = 1; 3565221167Sgnn} 3566221167Sgnn 3567221167Sgnn/* 3568221167Sgnn * vxge_hal_device_terminate - Terminate X3100 device. 3569221167Sgnn * @devh: HAL device handle. 3570221167Sgnn * 3571221167Sgnn * Terminate HAL device. 3572221167Sgnn * 3573221167Sgnn * See also: vxge_hal_device_initialize(). 3574221167Sgnn */ 3575221167Sgnnvoid 3576221167Sgnnvxge_hal_device_terminate( 3577221167Sgnn vxge_hal_device_h devh); 3578221167Sgnn 3579221167Sgnn/* 3580221167Sgnn * vxge_hal_device_private_set - Set ULD context. 3581221167Sgnn * @devh: HAL device handle. 3582221167Sgnn * @data: pointer to ULD context 3583221167Sgnn * 3584221167Sgnn * Use HAL device to set upper-layer driver (ULD) context. 3585221167Sgnn * 3586221167Sgnn * See also: vxge_hal_device_private_get() 3587221167Sgnn */ 3588221167Sgnnstatic inline 3589221167Sgnn/* LINTED */ 3590221167Sgnnvoid vxge_hal_device_private_set( 3591221167Sgnn vxge_hal_device_h devh, 3592221167Sgnn void *data) 3593221167Sgnn{ 3594221167Sgnn ((vxge_hal_device_t *) devh)->upper_layer_data = data; 3595221167Sgnn} 3596221167Sgnn 3597221167Sgnn/* 3598221167Sgnn * vxge_hal_device_private_get - Get ULD context. 3599221167Sgnn * @devh: HAL device handle. 3600221167Sgnn * 3601221167Sgnn * Use HAL device to set upper-layer driver (ULD) context. 3602221167Sgnn * 3603221167Sgnn * See also: vxge_hal_device_private_get() 3604221167Sgnn */ 3605221167Sgnnstatic inline 3606221167Sgnn/* LINTED */ 3607221167Sgnnvoid *vxge_hal_device_private_get( 3608221167Sgnn vxge_hal_device_h devh) 3609221167Sgnn{ 3610221167Sgnn return (((vxge_hal_device_t *) devh)->upper_layer_data); 3611221167Sgnn} 3612221167Sgnn 3613221167Sgnn/* 3614221167Sgnn * vxge_hal_device_status - Check whether X3100 hardware is ready for 3615221167Sgnn * operation. 3616221167Sgnn * @devh: HAL device handle. 3617221167Sgnn * @hw_status: X3100 status register. Returned by HAL. 3618221167Sgnn * 3619221167Sgnn * Check whether X3100 hardware is ready for operation. 3620221167Sgnn * The checking includes TDMA, RDMA, PFC, PIC, MC_DRAM, and the rest 3621221167Sgnn * hardware functional blocks. 3622221167Sgnn * 3623221167Sgnn * Returns: VXGE_HAL_OK if the device is ready for operation. Otherwise 3624221167Sgnn * returns VXGE_HAL_FAIL. Also, fills in adapter status (in @hw_status). 3625221167Sgnn * 3626221167Sgnn * See also: vxge_hal_status_e {}. 3627221167Sgnn * Usage: See ex_open {}. 3628221167Sgnn */ 3629221167Sgnnvxge_hal_status_e 3630221167Sgnnvxge_hal_device_status(vxge_hal_device_h devh, u64 *hw_status); 3631221167Sgnn 3632221167Sgnn/* 3633221167Sgnn * vxge_hal_device_is_slot_freeze 3634221167Sgnn * @devh: the device 3635221167Sgnn * 3636221167Sgnn * Returns non-zero if the slot is freezed. 3637221167Sgnn * The determination is made based on the adapter_status 3638221167Sgnn * register which will never give all FFs, unless PCI read 3639221167Sgnn * cannot go through. 3640221167Sgnn */ 3641221167Sgnnint 3642221167Sgnnvxge_hal_device_is_slot_freeze(vxge_hal_device_h devh); 3643221167Sgnn 3644221167Sgnn/* 3645221167Sgnn * vxge_hal_device_is_traffic_interrupt 3646221167Sgnn * @reason: The reason returned by the vxge)hal_device_begin_irq 3647221167Sgnn * @vp_id: Id of vpath for which to check the interrupt 3648221167Sgnn * 3649221167Sgnn * Returns non-zero if traffic interrupt raised, 0 otherwise 3650221167Sgnn */ 3651221167Sgnnstatic inline u64 3652221167Sgnn/* LINTED */ 3653221167Sgnnvxge_hal_device_is_traffic_interrupt(u64 reason, u32 vp_id) 3654221167Sgnn{ 3655221167Sgnn return (reason & mBIT(vp_id + 3)); 3656221167Sgnn} 3657221167Sgnn 3658221167Sgnn/* 3659221167Sgnn * vxge_hal_device_intr_enable - Enable X3100 interrupts. 3660221167Sgnn * @devh: HAL device handle. 3661221167Sgnn * @op: One of the vxge_hal_device_intr_e enumerated values specifying 3662221167Sgnn * the type(s) of interrupts to enable. 3663221167Sgnn * 3664221167Sgnn * Enable X3100 interrupts. The function is to be executed the last in 3665221167Sgnn * X3100 initialization sequence. 3666221167Sgnn * 3667221167Sgnn * See also: vxge_hal_device_intr_disable() 3668221167Sgnn */ 3669221167Sgnnvoid 3670221167Sgnnvxge_hal_device_intr_enable( 3671221167Sgnn vxge_hal_device_h devh); 3672221167Sgnn 3673221167Sgnn/* 3674221167Sgnn * vxge_hal_device_intr_disable - Disable X3100 interrupts. 3675221167Sgnn * @devh: HAL device handle. 3676221167Sgnn * @op: One of the vxge_hal_device_intr_e enumerated values specifying 3677221167Sgnn * the type(s) of interrupts to disable. 3678221167Sgnn * 3679221167Sgnn * Disable X3100 interrupts. 3680221167Sgnn * 3681221167Sgnn * See also: vxge_hal_device_intr_enable() 3682221167Sgnn */ 3683221167Sgnnvoid 3684221167Sgnnvxge_hal_device_intr_disable( 3685221167Sgnn vxge_hal_device_h devh); 3686221167Sgnn 3687221167Sgnn/* 3688221167Sgnn * vxge_hal_device_mask_all - Mask all device interrupts. 3689221167Sgnn * @devh: HAL device handle. 3690221167Sgnn * 3691221167Sgnn * Mask all device interrupts. 3692221167Sgnn * 3693221167Sgnn * See also: vxge_hal_device_unmask_all() 3694221167Sgnn */ 3695221167Sgnnvoid 3696221167Sgnnvxge_hal_device_mask_all( 3697221167Sgnn vxge_hal_device_h devh); 3698221167Sgnn 3699221167Sgnn/* 3700221167Sgnn * vxge_hal_device_unmask_all - Unmask all device interrupts. 3701221167Sgnn * @devh: HAL device handle. 3702221167Sgnn * 3703221167Sgnn * Unmask all device interrupts. 3704221167Sgnn * 3705221167Sgnn * See also: vxge_hal_device_mask_all() 3706221167Sgnn */ 3707221167Sgnnvoid 3708221167Sgnnvxge_hal_device_unmask_all( 3709221167Sgnn vxge_hal_device_h devh); 3710221167Sgnn 3711221167Sgnn/* 3712221167Sgnn * vxge_hal_device_begin_irq - Begin IRQ processing. 3713221167Sgnn * @devh: HAL device handle. 3714221167Sgnn * @skip_alarms: Do not clear the alarms 3715221167Sgnn * @reason: "Reason" for the interrupt, the value of X3100's 3716221167Sgnn * general_int_status register. 3717221167Sgnn * 3718221167Sgnn * The function performs two actions, It first checks whether (shared IRQ) the 3719221167Sgnn * interrupt was raised by the device. Next, it masks the device interrupts. 3720221167Sgnn * 3721221167Sgnn * Note: 3722221167Sgnn * vxge_hal_device_begin_irq() does not flush MMIO writes through the 3723221167Sgnn * bridge. Therefore, two back-to-back interrupts are potentially possible. 3724221167Sgnn * It is the responsibility of the ULD to make sure that only one 3725221167Sgnn * vxge_hal_device_continue_irq() runs at a time. 3726221167Sgnn * 3727221167Sgnn * Returns: 0, if the interrupt is not "ours" (note that in this case the 3728221167Sgnn * device remain enabled). 3729221167Sgnn * Otherwise, vxge_hal_device_begin_irq() returns 64bit general adapter 3730221167Sgnn * status. 3731221167Sgnn * See also: vxge_hal_device_handle_irq() 3732221167Sgnn */ 3733221167Sgnnvxge_hal_status_e 3734221167Sgnnvxge_hal_device_begin_irq( 3735221167Sgnn vxge_hal_device_h devh, 3736221167Sgnn u32 skip_alarms, 3737221167Sgnn u64 *reason); 3738221167Sgnn 3739221167Sgnn/* 3740221167Sgnn * vxge_hal_device_continue_irq - Continue handling IRQ: process all 3741221167Sgnn * completed descriptors. 3742221167Sgnn * @devh: HAL device handle. 3743221167Sgnn * 3744221167Sgnn * Process completed descriptors and unmask the device interrupts. 3745221167Sgnn * 3746221167Sgnn * The vxge_hal_device_continue_irq() walks all open virtual paths 3747221167Sgnn * and calls upper-layer driver (ULD) via supplied completion 3748221167Sgnn * callback. 3749221167Sgnn * 3750221167Sgnn * Note that the vxge_hal_device_continue_irq is part of the _fast_ path. 3751221167Sgnn * To optimize the processing, the function does _not_ check for 3752221167Sgnn * errors and alarms. 3753221167Sgnn * 3754221167Sgnn * Returns: VXGE_HAL_OK. 3755221167Sgnn * 3756221167Sgnn * See also: vxge_hal_device_handle_irq(), 3757221167Sgnn * vxge_hal_ring_rxd_next_completed(), 3758221167Sgnn * vxge_hal_fifo_txdl_next_completed(), vxge_hal_ring_callback_f {}, 3759221167Sgnn * vxge_hal_fifo_callback_f {}. 3760221167Sgnn */ 3761221167Sgnnvxge_hal_status_e 3762221167Sgnnvxge_hal_device_continue_irq( 3763221167Sgnn vxge_hal_device_h devh); 3764221167Sgnn 3765221167Sgnn/* 3766221167Sgnn * vxge_hal_device_handle_irq - Handle device IRQ. 3767221167Sgnn * @devh: HAL device handle. 3768221167Sgnn * @skip_alarms: Do not clear the alarms 3769221167Sgnn * 3770221167Sgnn * Perform the complete handling of the line interrupt. The function 3771221167Sgnn * performs two calls. 3772221167Sgnn * First it uses vxge_hal_device_begin_irq() to check the reason for 3773221167Sgnn * the interrupt and mask the device interrupts. 3774221167Sgnn * Second, it calls vxge_hal_device_continue_irq() to process all 3775221167Sgnn * completed descriptors and re-enable the interrupts. 3776221167Sgnn * 3777221167Sgnn * Returns: VXGE_HAL_OK - success; 3778221167Sgnn * VXGE_HAL_ERR_WRONG_IRQ - (shared) IRQ produced by other device. 3779221167Sgnn * 3780221167Sgnn * See also: vxge_hal_device_begin_irq(), vxge_hal_device_continue_irq(). 3781221167Sgnn */ 3782221167Sgnnvxge_hal_status_e 3783221167Sgnnvxge_hal_device_handle_irq( 3784221167Sgnn vxge_hal_device_h devh, 3785221167Sgnn u32 skip_alarms); 3786221167Sgnn 3787221167Sgnn/* 3788221167Sgnn * vxge_hal_device_mask_tx - Mask Tx interrupts. 3789221167Sgnn * @devh: HAL device. 3790221167Sgnn * 3791221167Sgnn * Mask Tx device interrupts. 3792221167Sgnn * 3793221167Sgnn * See also: vxge_hal_device_unmask_tx(), vxge_hal_device_mask_rx(), 3794221167Sgnn * vxge_hal_device_clear_tx(). 3795221167Sgnn */ 3796221167Sgnnvoid 3797221167Sgnnvxge_hal_device_mask_tx( 3798221167Sgnn vxge_hal_device_h devh); 3799221167Sgnn 3800221167Sgnn/* 3801221167Sgnn * vxge_hal_device_clear_tx - Acknowledge (that is, clear) the 3802221167Sgnn * condition that has caused the TX interrupt. 3803221167Sgnn * @devh: HAL device. 3804221167Sgnn * 3805221167Sgnn * Acknowledge (that is, clear) the condition that has caused 3806221167Sgnn * the Tx interrupt. 3807221167Sgnn * See also: vxge_hal_device_begin_irq(), vxge_hal_device_continue_irq(), 3808221167Sgnn * vxge_hal_device_clear_rx(), vxge_hal_device_mask_tx(). 3809221167Sgnn */ 3810221167Sgnnvoid 3811221167Sgnnvxge_hal_device_clear_tx( 3812221167Sgnn vxge_hal_device_h devh); 3813221167Sgnn 3814221167Sgnn 3815221167Sgnn/* 3816221167Sgnn * vxge_hal_device_unmask_tx - Unmask Tx interrupts. 3817221167Sgnn * @devh: HAL device. 3818221167Sgnn * 3819221167Sgnn * Unmask Tx device interrupts. 3820221167Sgnn * 3821221167Sgnn * See also: vxge_hal_device_mask_tx(), vxge_hal_device_clear_tx(). 3822221167Sgnn */ 3823221167Sgnnvoid 3824221167Sgnnvxge_hal_device_unmask_tx( 3825221167Sgnn vxge_hal_device_h devh); 3826221167Sgnn 3827221167Sgnn/* 3828221167Sgnn * vxge_hal_device_mask_rx - Mask Rx interrupts. 3829221167Sgnn * @devh: HAL device. 3830221167Sgnn * 3831221167Sgnn * Mask Rx device interrupts. 3832221167Sgnn * 3833221167Sgnn * See also: vxge_hal_device_unmask_rx(), vxge_hal_device_mask_tx(), 3834221167Sgnn * vxge_hal_device_clear_rx(). 3835221167Sgnn */ 3836221167Sgnnvoid 3837221167Sgnnvxge_hal_device_mask_rx( 3838221167Sgnn vxge_hal_device_h devh); 3839221167Sgnn 3840221167Sgnn 3841221167Sgnn/* 3842221167Sgnn * vxge_hal_device_clear_rx - Acknowledge (that is, clear) the 3843221167Sgnn * condition that has caused the RX interrupt. 3844221167Sgnn * @devh: HAL device. 3845221167Sgnn * 3846221167Sgnn * Acknowledge (that is, clear) the condition that has caused 3847221167Sgnn * the Rx interrupt. 3848221167Sgnn * See also: vxge_hal_device_begin_irq(), vxge_hal_device_continue_irq(), 3849221167Sgnn * vxge_hal_device_clear_tx(), vxge_hal_device_mask_rx(). 3850221167Sgnn */ 3851221167Sgnnvoid 3852221167Sgnnvxge_hal_device_clear_rx( 3853221167Sgnn vxge_hal_device_h devh); 3854221167Sgnn 3855221167Sgnn/* 3856221167Sgnn * vxge_hal_device_unmask_rx - Unmask Rx interrupts. 3857221167Sgnn * @devh: HAL device. 3858221167Sgnn * 3859221167Sgnn * Unmask Rx device interrupts. 3860221167Sgnn * 3861221167Sgnn * See also: vxge_hal_device_mask_rx(), vxge_hal_device_clear_rx(). 3862221167Sgnn */ 3863221167Sgnnvoid 3864221167Sgnnvxge_hal_device_unmask_rx( 3865221167Sgnn vxge_hal_device_h devh); 3866221167Sgnn 3867221167Sgnn/* 3868221167Sgnn * vxge_hal_device_mask_tx_rx - Mask Tx and Rx interrupts. 3869221167Sgnn * @devh: HAL device. 3870221167Sgnn * 3871221167Sgnn * Mask Tx and Rx device interrupts. 3872221167Sgnn * 3873221167Sgnn * See also: vxge_hal_device_unmask_tx_rx(), vxge_hal_device_clear_tx_rx(). 3874221167Sgnn */ 3875221167Sgnnvoid 3876221167Sgnnvxge_hal_device_mask_tx_rx( 3877221167Sgnn vxge_hal_device_h devh); 3878221167Sgnn 3879221167Sgnn/* 3880221167Sgnn * vxge_hal_device_clear_tx_rx - Acknowledge (that is, clear) the 3881221167Sgnn * condition that has caused the Tx and RX interrupt. 3882221167Sgnn * @devh: HAL device. 3883221167Sgnn * 3884221167Sgnn * Acknowledge (that is, clear) the condition that has caused 3885221167Sgnn * the Tx and Rx interrupt. 3886221167Sgnn * See also: vxge_hal_device_begin_irq(), vxge_hal_device_continue_irq(), 3887221167Sgnn * vxge_hal_device_mask_tx_rx(), vxge_hal_device_unmask_tx_rx(). 3888221167Sgnn */ 3889221167Sgnnvoid 3890221167Sgnnvxge_hal_device_clear_tx_rx( 3891221167Sgnn vxge_hal_device_h devh); 3892221167Sgnn 3893221167Sgnn/* 3894221167Sgnn * vxge_hal_device_unmask_tx_rx - Unmask Tx and Rx interrupts. 3895221167Sgnn * @devh: HAL device. 3896221167Sgnn * 3897221167Sgnn * Unmask Tx and Rx device interrupts. 3898221167Sgnn * 3899221167Sgnn * See also: vxge_hal_device_mask_tx_rx(), vxge_hal_device_clear_tx_rx(). 3900221167Sgnn */ 3901221167Sgnnvoid 3902221167Sgnnvxge_hal_device_unmask_tx_rx( 3903221167Sgnn vxge_hal_device_h devh); 3904221167Sgnn 3905221167Sgnn/* 3906221167Sgnn * vxge_hal_device_msix_mode - Is MSIX enabled? 3907221167Sgnn * @devh: HAL device handle. 3908221167Sgnn * 3909221167Sgnn * Returns 0 if MSIX is enabled for the specified device, 3910221167Sgnn * non-zero otherwise. 3911221167Sgnn */ 3912221167Sgnnstatic inline int 3913221167Sgnn/* LINTED */ 3914221167Sgnnvxge_hal_device_msix_mode(vxge_hal_device_h devh) 3915221167Sgnn{ 3916221167Sgnn return (((vxge_hal_device_t *) devh)->msix_enabled); 3917221167Sgnn} 3918221167Sgnn 3919221167Sgnn#if defined(VXGE_TRACE_INTO_CIRCULAR_ARR) 3920221167Sgnn 3921221167Sgnn/* 3922221167Sgnn * vxge_hal_device_trace_write - Write the trace from the given buffer into 3923221167Sgnn * circular trace buffer 3924221167Sgnn * @devh: HAL device handle. 3925221167Sgnn * @trace_buf: Buffer containing the trace. 3926221167Sgnn * @trace_len: Length of the trace in the buffer 3927221167Sgnn * 3928221167Sgnn * Writes the trace from the given buffer into the circular trace buffer 3929221167Sgnn * 3930221167Sgnn */ 3931221167Sgnnvoid 3932221167Sgnnvxge_hal_device_trace_write(vxge_hal_device_h devh, 3933221167Sgnn u8 *trace_buf, 3934221167Sgnn u32 trace_len); 3935221167Sgnn 3936221167Sgnn/* 3937221167Sgnn * vxge_hal_device_trace_dump - Dump the trace buffer. 3938221167Sgnn * @devh: HAL device handle. 3939221167Sgnn * 3940221167Sgnn * Dump the trace buffer contents. 3941221167Sgnn */ 3942221167Sgnnvoid 3943221167Sgnn vxge_hal_device_trace_dump(vxge_hal_device_h devh); 3944221167Sgnn 3945221167Sgnn/* 3946221167Sgnn * vxge_hal_device_trace_read - Read trace buffer contents. 3947221167Sgnn * @devh: HAL device handle. 3948221167Sgnn * @buffer: Buffer to store the trace buffer contents. 3949221167Sgnn * @buf_size: Size of the buffer. 3950221167Sgnn * @read_length: Size of the valid data in the buffer. 3951221167Sgnn * 3952221167Sgnn * Read HAL trace buffer contents starting from the offset 3953221167Sgnn * upto the size of the buffer or till EOF is reached. 3954221167Sgnn * 3955221167Sgnn * Returns: VXGE_HAL_OK - success. 3956221167Sgnn * VXGE_HAL_EOF_TRACE_BUF - No more data in the trace buffer. 3957221167Sgnn * 3958221167Sgnn */ 3959221167Sgnnvxge_hal_status_e 3960221167Sgnnvxge_hal_device_trace_read(vxge_hal_device_h devh, 3961221167Sgnn char *buffer, 3962221167Sgnn unsigned buf_size, 3963221167Sgnn unsigned *read_length); 3964221167Sgnn 3965221167Sgnn#endif 3966221167Sgnn 3967221167Sgnn/* 3968221167Sgnn * vxge_hal_device_debug_set - Set the debug module, level and timestamp 3969221167Sgnn * @devh: Hal device object 3970221167Sgnn * @level: Debug level as defined in enum vxge_debug_level_e 3971221167Sgnn * @mask: An or value of component masks as defined in vxge_debug.h 3972221167Sgnn * 3973221167Sgnn * This routine is used to dynamically change the debug output 3974221167Sgnn */ 3975221167Sgnnvoid 3976221167Sgnnvxge_hal_device_debug_set( 3977221167Sgnn vxge_hal_device_h devh, 3978221167Sgnn vxge_debug_level_e level, 3979221167Sgnn u32 mask); 3980221167Sgnn 3981221167Sgnn/* 3982221167Sgnn * vxge_hal_device_debug_level_get - Get the debug level 3983221167Sgnn * @devh: Hal device object 3984221167Sgnn * 3985221167Sgnn * This routine returns the current debug level set 3986221167Sgnn */ 3987221167Sgnnstatic inline u32 3988221167Sgnn/* LINTED */ 3989221167Sgnnvxge_hal_device_debug_level_get(vxge_hal_device_h devh) 3990221167Sgnn{ 3991221167Sgnn return (((vxge_hal_device_t *) devh)->debug_level); 3992221167Sgnn} 3993221167Sgnn 3994221167Sgnn/* 3995221167Sgnn * vxge_hal_device_debug_mask_get - Get the debug mask 3996221167Sgnn * @devh: Hal device object 3997221167Sgnn * 3998221167Sgnn * This routine returns the current debug mask set 3999221167Sgnn */ 4000221167Sgnnstatic inline u32 4001221167Sgnn/* LINTED */ 4002221167Sgnnvxge_hal_device_debug_mask_get(vxge_hal_device_h devh) 4003221167Sgnn{ 4004221167Sgnn return (((vxge_hal_device_t *) devh)->debug_module_mask); 4005221167Sgnn} 4006221167Sgnn 4007221167Sgnn/* 4008221167Sgnn * vxge_hal_device_flick_link_led - Flick (blink) link LED. 4009221167Sgnn * @devh: HAL device handle. 4010221167Sgnn * @port : Port number 0, or 1 4011221167Sgnn * @on_off: TRUE if flickering to be on, FALSE to be off 4012221167Sgnn * 4013221167Sgnn * Flicker the link LED. 4014221167Sgnn */ 4015221167Sgnnvxge_hal_status_e 4016221167Sgnnvxge_hal_device_flick_link_led( 4017221167Sgnn vxge_hal_device_h devh, 4018221167Sgnn u32 port, 4019221167Sgnn u32 on_off); 4020221167Sgnn 4021221167Sgnn/* 4022221167Sgnn * vxge_hal_device_getpause_data -Pause frame frame generation and reception. 4023221167Sgnn * @devh: HAL device handle. 4024221167Sgnn * @port : Port number 0, 1, or 2 4025221167Sgnn * @tx : A field to return the pause generation capability of the NIC. 4026221167Sgnn * @rx : A field to return the pause reception capability of the NIC. 4027221167Sgnn * 4028221167Sgnn * Returns the Pause frame generation and reception capability of the NIC. 4029221167Sgnn * Return value: 4030221167Sgnn * status 4031221167Sgnn */ 4032221167Sgnnvxge_hal_status_e 4033221167Sgnnvxge_hal_device_getpause_data( 4034221167Sgnn vxge_hal_device_h devh, 4035221167Sgnn u32 port, 4036221167Sgnn u32 *tx, 4037221167Sgnn u32 *rx); 4038221167Sgnn 4039221167Sgnn/* 4040221167Sgnn * Privileged operations 4041221167Sgnn */ 4042221167Sgnn 4043221167Sgnn/* 4044221167Sgnn * enum vxge_hal_pcie_function_mode_e - PCIE Function modes 4045221167Sgnn * @VXGE_HAL_PCIE_FUNC_MODE_SF1_VP17: Single Function 4046221167Sgnn * - 1 function with 17 VPATHs 4047221167Sgnn * @VXGE_HAL_PCIE_FUNC_MODE_MF8_VP2: Multi Function 4048221167Sgnn * - 8 functions with 2 VPATHs per function 4049221167Sgnn * @VXGE_HAL_PCIE_FUNC_MODE_SR17_VP1: SRIOV 4050221167Sgnn * - 17 VFs with 1 VPATH per VF 4051221167Sgnn * @VXGE_HAL_PCIE_FUNC_MODE_MR17_VP1: MRIOV 4052221167Sgnn * - 17 Virtual Hierarchies, 1 Path/Function/Hierarchy 4053221167Sgnn * @VXGE_HAL_PCIE_FUNC_MODE_MR8_VP2: MRIOV 4054221167Sgnn * - 8 Virtual Hierarchies, 2 Path/Function/Hierarchy 4055221167Sgnn * @VXGE_HAL_PCIE_FUNC_MODE_MF17_VP1: Multi Function 4056221167Sgnn * - 17 functions, 1 Path/Function (PCIe ARI) 4057221167Sgnn * @VXGE_HAL_PCIE_FUNC_MODE_SR8_VP2: SRIOV 4058221167Sgnn * - 1 PF, 7 VF, 2 Paths/Function 4059221167Sgnn * @VXGE_HAL_PCIE_FUNC_MODE_SR4_VP4: SRIOV 4060221167Sgnn * - 1 PF, 3 VF, 4 Paths/Function 4061221167Sgnn * @VXGE_HAL_PCIE_FUNC_MODE_MF2_VP8: Multi Function 4062221167Sgnn * - 2 functions, 8 Paths/Function (funcs 2-7 have no resources) 4063221167Sgnn */ 4064221167Sgnntypedef enum vxge_hal_pcie_function_mode_e { 4065221167Sgnn VXGE_HAL_PCIE_FUNC_MODE_SF1_VP17, 4066221167Sgnn VXGE_HAL_PCIE_FUNC_MODE_MF8_VP2, 4067221167Sgnn VXGE_HAL_PCIE_FUNC_MODE_SR17_VP1, 4068221167Sgnn VXGE_HAL_PCIE_FUNC_MODE_MR17_VP1, 4069221167Sgnn VXGE_HAL_PCIE_FUNC_MODE_MR8_VP2, 4070221167Sgnn VXGE_HAL_PCIE_FUNC_MODE_MF17_VP1, 4071221167Sgnn VXGE_HAL_PCIE_FUNC_MODE_SR8_VP2, 4072221167Sgnn VXGE_HAL_PCIE_FUNC_MODE_SR4_VP4, 4073221167Sgnn VXGE_HAL_PCIE_FUNC_MODE_MF2_VP8, 4074221167Sgnn VXGE_HAL_PCIE_FUNC_MODE_MF4_VP4, 4075221167Sgnn VXGE_HAL_PCIE_FUNC_MODE_MR4_VP4, 4076221167Sgnn VXGE_HAL_PCIE_FUNC_MODE_MF8P_VP2 4077221167Sgnn 4078221167Sgnn} vxge_hal_pcie_function_mode_e; 4079221167Sgnn 4080221167Sgnn/* Behavior on failure */ 4081221167Sgnntypedef enum vxge_hal_xmac_nwif_behavior_on_failure { 4082221167Sgnn VXGE_HAL_XMAC_NWIF_OnFailure_NoMove, 4083221167Sgnn VXGE_HAL_XMAC_NWIF_OnFailure_OtherPort, 4084221167Sgnn VXGE_HAL_XMAC_NWIF_OnFailure_OtherPortBackOnRestore 4085221167Sgnn} vxge_hal_xmac_nwif_behavior_on_failure; 4086221167Sgnn 4087221167Sgnn/* 4088221167Sgnn * Network Port configuration cmds 4089221167Sgnn */ 4090221167Sgnntypedef enum vxge_hal_nwif_cmds { 4091221167Sgnn VXGE_HAL_XMAC_NWIF_Cmd_Version = 0x0, 4092221167Sgnn VXGE_HAL_XMAC_NWIF_Cmd_SetMode = 0x1, 4093221167Sgnn VXGE_HAL_XMAC_NWIF_Cmd_CfgSnglPort = 0x4, 4094221167Sgnn VXGE_HAL_XMAC_NWIF_Cmd_Avail = 0x6, 4095221167Sgnn VXGE_HAL_XMAC_NWIF_Cmd_CfgSetActPassPreferredPort = 0x7, 4096221167Sgnn VXGE_HAL_XMAC_NWIF_Cmd_CfgSetBehaviourOnFailure = 0x8, 4097221167Sgnn VXGE_HAL_XMAC_NWIF_Cmd_CfgDualPort_L2SwitchEnable = 0x9, 4098221167Sgnn VXGE_HAL_XMAC_NWIF_Cmd_CfgDualPort_VPathVector = 0xa, 4099221167Sgnn VXGE_HAL_XMAC_NWIF_Cmd_Get_Active_Config = 0xb 4100221167Sgnn} vxge_hal_nwif_cmds; 4101221167Sgnn 4102221167Sgnn/* Network port get active config options */ 4103221167Sgnntypedef enum vxge_hal_xmac_nwif_actconfig { 4104221167Sgnn VXGE_HAL_XMAC_NWIF_ActConfig_Avail = 0, 4105221167Sgnn VXGE_HAL_XMAC_NWIF_ActConfig_NWPortMode = 1, 4106221167Sgnn VXGE_HAL_XMAC_NWIF_ActConfig_PreferredPort = 2, 4107221167Sgnn VXGE_HAL_XMAC_NWIF_ActConfig_BehaviourOnFail = 3, 4108221167Sgnn VXGE_HAL_XMAC_NWIF_ActConfig_ActivePort = 4, 4109221167Sgnn VXGE_HAL_XMAC_NWIF_ActConfig_L2SwitchEnabled = 5, 4110221167Sgnn VXGE_HAL_XMAC_NWIF_ActConfig_DualPortPath = 6 4111221167Sgnn} vxge_hal_xmac_nwif_actconfig; 4112221167Sgnn 4113221167Sgnn/* Dual port modes */ 4114221167Sgnntypedef enum vxge_hal_xmac_nwif_dp_mode { 4115221167Sgnn VXGE_HAL_DP_NP_MODE_DEFAULT, 4116221167Sgnn VXGE_HAL_DP_NP_MODE_LINK_AGGR, 4117221167Sgnn VXGE_HAL_DP_NP_MODE_ACTIVE_PASSIVE, 4118221167Sgnn VXGE_HAL_DP_NP_MODE_SINGLE_PORT, 4119221167Sgnn VXGE_HAL_DP_NP_MODE_DUAL_PORT, 4120221167Sgnn VXGE_HAL_DP_NP_MODE_DISABLE_PORT_MGMT 4121221167Sgnn} vxge_hal_xmac_nwif_dp_mode; 4122221167Sgnn 4123221167Sgnn/* L2 switch status */ 4124221167Sgnntypedef enum vxge_hal_xmac_nwif_l2_switch_status { 4125221167Sgnn VXGE_HAL_XMAC_NWIF_L2_SWITCH_DISABLE, 4126221167Sgnn VXGE_HAL_XMAC_NWIF_L2_SWITCH_ENABLE 4127221167Sgnn} vxge_hal_xmac_nwif_l2_switch_status; 4128221167Sgnn 4129221167Sgnn/* 4130221167Sgnn * vxge_hal_srpcim_alarm_process - Process srpcim Alarms. 4131221167Sgnn * @devh: Device Handle. 4132221167Sgnn * @skip_alarms: Flasg to indicate not to clear alarms 4133221167Sgnn * 4134221167Sgnn * Process srpcim alarms. 4135221167Sgnn * 4136221167Sgnn */ 4137221167Sgnnvxge_hal_status_e 4138221167Sgnnvxge_hal_srpcim_alarm_process(vxge_hal_device_h devh, u32 skip_alarms); 4139221167Sgnn 4140221167Sgnn/* 4141221167Sgnn * vxge_hal_srpcim_intr_enable - Enable srpcim interrupts. 4142221167Sgnn * @devh: Device Handle. 4143221167Sgnn * 4144221167Sgnn * Enable srpcim interrupts. 4145221167Sgnn * 4146221167Sgnn * See also: vxge_hal_srpcim_intr_disable() 4147221167Sgnn */ 4148221167Sgnnvxge_hal_status_e 4149221167Sgnnvxge_hal_srpcim_intr_enable(vxge_hal_device_h devh); 4150221167Sgnn 4151221167Sgnn/* 4152221167Sgnn * vxge_hal_srpcim_intr_disable - Disable srpcim interrupts. 4153221167Sgnn * @devh: Device Handle. 4154221167Sgnn * 4155221167Sgnn * Disable srpcim interrupts. 4156221167Sgnn * 4157221167Sgnn * See also: vxge_hal_srpcim_intr_enable() 4158221167Sgnn */ 4159221167Sgnnvxge_hal_status_e 4160221167Sgnnvxge_hal_srpcim_intr_disable(vxge_hal_device_h devh); 4161221167Sgnn 4162221167Sgnn/* 4163221167Sgnn * vxge_hal_srpcim_msix_set - Associate MSIX vector with srpcim alarm 4164221167Sgnn * @devh: Device Handle. 4165221167Sgnn * @alarm_msix_id: MSIX vector for alarm. 4166221167Sgnn * 4167221167Sgnn * This API will associate a given MSIX vector numbers with srpcim alarm 4168221167Sgnn */ 4169221167Sgnnvxge_hal_status_e 4170221167Sgnnvxge_hal_srpcim_msix_set(vxge_hal_device_h devh, int alarm_msix_id); 4171221167Sgnn 4172221167Sgnn/* 4173221167Sgnn * vxge_hal_srpcim_msix_mask - Mask MSIX Vector. 4174221167Sgnn * @devh: Device Handle. 4175221167Sgnn * 4176221167Sgnn * The function masks the srpcim msix interrupt 4177221167Sgnn * 4178221167Sgnn */ 4179221167Sgnnvoid 4180221167Sgnnvxge_hal_srpcim_msix_mask(vxge_hal_device_h devh); 4181221167Sgnn 4182221167Sgnn/* 4183221167Sgnn * vxge_hal_srpcim_msix_clear - Clear MSIX Vector. 4184221167Sgnn * @devh: Device Handle. 4185221167Sgnn * 4186221167Sgnn * The function clears the srpcim msix interrupt 4187221167Sgnn * 4188221167Sgnn */ 4189221167Sgnnvoid 4190221167Sgnnvxge_hal_srpcim_msix_clear(vxge_hal_device_h devh); 4191221167Sgnn 4192221167Sgnn 4193221167Sgnn/* 4194221167Sgnn * vxge_hal_srpcim_msix_unmask - Unmask MSIX Vector. 4195221167Sgnn * @devh: Device Handle. 4196221167Sgnn * 4197221167Sgnn * The function unmasks the srpcim msix interrupt 4198221167Sgnn * 4199221167Sgnn */ 4200221167Sgnnvoid 4201221167Sgnnvxge_hal_srpcim_msix_unmask(vxge_hal_device_h devh); 4202221167Sgnn 4203221167Sgnnvxge_hal_status_e 4204221167Sgnnvxge_hal_func_mode_count(vxge_hal_device_h devh, 4205221167Sgnn u32 func_mode, u32 *num_funcs); 4206221167Sgnn 4207221167Sgnnvxge_hal_status_e 4208221167Sgnnvxge_hal_send_message(vxge_hal_device_h devh, u64 vp_id, u8 msg_type, 4209221167Sgnn u8 msg_dst, u32 msg_data, u64 *msg_sent_to_vpaths); 4210221167Sgnn 4211221167Sgnn/* 4212221167Sgnn * vxge_hal_func_mode_set - Set PCI-E function mode 4213221167Sgnn * @devh: Device Handle. 4214221167Sgnn * @func_mode: PCI-E func mode. Please see vxge_hal_pcie_function_mode_e{} 4215221167Sgnn * 4216221167Sgnn * Set PCI-E function mode. 4217221167Sgnn * 4218221167Sgnn */ 4219221167Sgnnvxge_hal_status_e 4220221167Sgnnvxge_hal_func_mode_get(vxge_hal_device_h devh, u32 *func_mode); 4221221167Sgnn/* 4222221167Sgnn * vxge_hal_func_mode_set - Set PCI-E function mode 4223221167Sgnn * @devh: Device Handle. 4224221167Sgnn * @func_mode: PCI-E func mode. Please see vxge_hal_pcie_function_mode_e{} 4225221167Sgnn * 4226221167Sgnn * Set PCI-E function mode. 4227221167Sgnn * 4228221167Sgnn */ 4229221167Sgnnvxge_hal_status_e 4230221167Sgnnvxge_hal_mrpcim_pcie_func_mode_set(vxge_hal_device_h devh, 4231221167Sgnn vxge_hal_pcie_function_mode_e func_mode); 4232221167Sgnn 4233221167Sgnn/* 4234221167Sgnn * vxge_hal_get_active_config - Get active configuration 4235221167Sgnn * @devh: Device Handle. 4236221167Sgnn * 4237221167Sgnn */ 4238221167Sgnnvxge_hal_status_e 4239221167Sgnnvxge_hal_get_active_config(vxge_hal_device_h devh, 4240221167Sgnn vxge_hal_xmac_nwif_actconfig req_config, u64 *cur_config); 4241221167Sgnn 4242221167Sgnn/* 4243221167Sgnn * vxge_hw_set_port_mode - Set dual port mode 4244221167Sgnn * override the default dual port mode 4245221167Sgnn * @devh: Device Handle. 4246221167Sgnn * 4247221167Sgnn */ 4248221167Sgnn 4249221167Sgnnvxge_hal_status_e 4250221167Sgnnvxge_hal_set_port_mode(vxge_hal_device_h devh, 4251221167Sgnn vxge_hal_xmac_nwif_dp_mode port_mode); 4252221167Sgnn 4253221167Sgnn/* 4254221167Sgnn * vxge_hal_set_behavior_on_failure - Set port behaviour 4255221167Sgnn * change port behavior on failure 4256221167Sgnn * @devh: Device Handle. 4257221167Sgnn */ 4258221167Sgnnvxge_hal_status_e 4259221167Sgnnvxge_hal_set_behavior_on_failure(vxge_hal_device_h devh, 4260221167Sgnn vxge_hal_xmac_nwif_behavior_on_failure behave_on_failure); 4261221167Sgnn 4262221167Sgnn 4263221167Sgnn/* 4264221167Sgnn * vxge_hal_set_l2switch_mode - Set port behaviour 4265221167Sgnn * set l2switch mode 4266221167Sgnn * @devh: Device Handle. 4267221167Sgnn */ 4268221167Sgnnvxge_hal_status_e 4269221167Sgnnvxge_hal_set_l2switch_mode(vxge_hal_device_h devh, 4270221167Sgnn enum vxge_hal_xmac_nwif_l2_switch_status l2_switch); 4271221167Sgnn/* 4272221167Sgnn * vxge_hal_set_fw_api - Setup FW api 4273221167Sgnn * @devh: Device Handle. 4274221167Sgnn * 4275221167Sgnn */ 4276221167Sgnnvxge_hal_status_e 4277221167Sgnnvxge_hal_set_fw_api(vxge_hal_device_h devh, u64 vp_id, u32 action, 4278221167Sgnn u32 offset, u64 data0, u64 data1); 4279221167Sgnn 4280221167Sgnnvxge_hal_status_e 4281221167Sgnnvxge_hal_config_vpath_map(vxge_hal_device_h devh, u64 port_map); 4282221167Sgnn 4283221167Sgnnvxge_hal_status_e 4284221167Sgnnvxge_hal_get_vpath_mask(vxge_hal_device_h devh, u32 vf_id, 4285221167Sgnn u32 *no_of_vpath, u64 *vpath_mask); 4286221167Sgnn 4287221167Sgnnvxge_hal_status_e 4288221167Sgnnvxge_hal_get_vpath_list(vxge_hal_device_h devh, u32 vf_id, 4289221167Sgnn u64 *vpath_list, u32 *vpath_count); 4290221167Sgnn 4291221167Sgnnvxge_hal_status_e 4292221167Sgnnvxge_hal_rx_bw_priority_set(vxge_hal_device_h devh, u64 vp_id); 4293221167Sgnn 4294221167Sgnnvxge_hal_status_e 4295221167Sgnnvxge_hal_tx_bw_priority_set(vxge_hal_device_h devh, u64 vp_id); 4296221167Sgnn 4297221167Sgnnvxge_hal_status_e 4298221167Sgnnvxge_hal_bw_priority_get(vxge_hal_device_h devh, u64 vp_id, 4299221167Sgnn u32 *bandwidth, u32 *priority); 4300221167Sgnn 4301221167Sgnnvxge_hal_status_e 4302221167Sgnnvxge_hal_vf_rx_bw_get(vxge_hal_device_h devh, u64 func_id, 4303221167Sgnn u32 *bandwidth, u32 *priority); 4304221167Sgnn/* 4305221167Sgnn * vxge_hal_mrpcim_serial_number_get - Returns the serial number 4306221167Sgnn * @devh: Device Handle. 4307221167Sgnn * 4308221167Sgnn * Return the serial number 4309221167Sgnn */ 4310221167Sgnnconst u8 * 4311221167Sgnnvxge_hal_mrpcim_serial_number_get(vxge_hal_device_h devh); 4312221167Sgnn 4313221167Sgnn/* 4314221167Sgnn * vxge_hal_mrpcim_fw_upgrade - Upgrade firmware 4315221167Sgnn * @pdev: PCI device object. 4316221167Sgnn * @regh0: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev 4317221167Sgnn * (Linux and the rest.) 4318221167Sgnn * @bar0: Address of BAR0 in PCI config 4319221167Sgnn * @buffer: Buffer containing F/W image 4320221167Sgnn * @length: F/W image length 4321221167Sgnn * 4322221167Sgnn * Upgrade firmware 4323221167Sgnn */ 4324221167Sgnnvxge_hal_status_e 4325221167Sgnnvxge_hal_mrpcim_fw_upgrade( 4326221167Sgnn pci_dev_h pdev, 4327221167Sgnn pci_reg_h regh0, 4328221167Sgnn u8 *bar0, 4329221167Sgnn u8 *buffer, 4330221167Sgnn u32 length); 4331221167Sgnn 4332221167Sgnn/* 4333221167Sgnn * vxge_hal_mrpcim_vpath_map_get - Returns the assigned vpaths map 4334221167Sgnn * @pdev: PCI device object. 4335221167Sgnn * @regh0: BAR0 mapped memory handle (Solaris), or simply PCI device @pdev 4336221167Sgnn * (Linux and the rest.) 4337221167Sgnn * @bar0: Address of BAR0 in PCI config 4338221167Sgnn * @func: Function Number 4339221167Sgnn * 4340221167Sgnn * Returns the assigned vpaths map 4341221167Sgnn */ 4342221167Sgnnu64 4343221167Sgnnvxge_hal_mrpcim_vpath_map_get( 4344221167Sgnn pci_dev_h pdev, 4345221167Sgnn pci_reg_h regh0, 4346221167Sgnn u8 *bar0, 4347221167Sgnn u32 func); 4348221167Sgnn 4349221167Sgnn/* 4350221167Sgnn * vxge_hal_mrpcim_vpath_qos_set - Set the priority, Guaranteed and maximum 4351221167Sgnn * bandwidth for a vpath. 4352221167Sgnn * @devh: HAL device handle. 4353221167Sgnn * @vp_id: Vpath Id. 4354221167Sgnn * @priority: Priority 4355221167Sgnn * @min_bandwidth: Minimum Bandwidth 4356221167Sgnn * @max_bandwidth: Maximum Bandwidth 4357221167Sgnn * 4358221167Sgnn * Set the Priority, Guaranteed and maximum bandwidth for a given vpath 4359221167Sgnn * 4360221167Sgnn */ 4361221167Sgnnvxge_hal_status_e 4362221167Sgnnvxge_hal_mrpcim_vpath_qos_set( 4363221167Sgnn vxge_hal_device_h devh, 4364221167Sgnn u32 vp_id, 4365221167Sgnn u32 priority, 4366221167Sgnn u32 min_bandwidth, 4367221167Sgnn u32 max_bandwidth); 4368221167Sgnn 4369221167Sgnn/* 4370221167Sgnn * vxge_hal_mrpcim_vpath_qos_get - Get the priority, Guaranteed and maximum 4371221167Sgnn * bandwidth for a vpath. 4372221167Sgnn * @devh: HAL device handle. 4373221167Sgnn * @vp_id: Vpath Id. 4374221167Sgnn * @priority: Buffer to return Priority 4375221167Sgnn * @min_bandwidth: Buffer to return Minimum Bandwidth 4376221167Sgnn * @max_bandwidth: Buffer to return Maximum Bandwidth 4377221167Sgnn * 4378221167Sgnn * Get the Priority, Guaranteed and maximum bandwidth for a given vpath 4379221167Sgnn * 4380221167Sgnn */ 4381221167Sgnnvxge_hal_status_e 4382221167Sgnnvxge_hal_mrpcim_vpath_qos_get( 4383221167Sgnn vxge_hal_device_h devh, 4384221167Sgnn u32 vp_id, 4385221167Sgnn u32 *priority, 4386221167Sgnn u32 *min_bandwidth, 4387221167Sgnn u32 *max_bandwidth); 4388221167Sgnn 4389221167Sgnn/* 4390221167Sgnn * vxge_hal_mrpcim_mac_addr_add - Add the mac address entry 4391221167Sgnn * into MAC address table. 4392221167Sgnn * @devh: Device handle. 4393221167Sgnn * @offset: Index into the DA table to add the mac address. 4394221167Sgnn * @macaddr: MAC address to be added for this vpath into the list 4395221167Sgnn * @macaddr_mask: MAC address mask for macaddr 4396221167Sgnn * @vpath_vector: Bit mask specifying the vpaths to which the mac address 4397221167Sgnn * applies 4398221167Sgnn * @duplicate_mode: Duplicate MAC address add mode. Please see 4399221167Sgnn * vxge_hal_vpath_mac_addr_add_mode_e {} 4400221167Sgnn * 4401221167Sgnn * Adds the given mac address, mac address mask and vpath vector into the list 4402221167Sgnn * 4403221167Sgnn * see also: vxge_hal_vpath_mac_addr_delete, vxge_hal_vpath_mac_addr_get and 4404221167Sgnn * vxge_hal_vpath_mac_addr_get_next 4405221167Sgnn * 4406221167Sgnn */ 4407221167Sgnnvxge_hal_status_e 4408221167Sgnnvxge_hal_mrpcim_mac_addr_add( 4409221167Sgnn vxge_hal_device_h devh, 4410221167Sgnn u32 offset, 4411221167Sgnn macaddr_t macaddr, 4412221167Sgnn macaddr_t macaddr_mask, 4413221167Sgnn u64 vpath_vector, 4414221167Sgnn u32 duplicate_mode); 4415221167Sgnn 4416221167Sgnn/* 4417221167Sgnn * vxge_hal_mrpcim_mac_addr_get - Read the mac address entry 4418221167Sgnn * into MAC address table. 4419221167Sgnn * @devh: Device handle. 4420221167Sgnn * @offset: Index into the DA table to execute the command on. 4421221167Sgnn * @macaddr: Buffer to return MAC address to be added for this vpath 4422221167Sgnn * @macaddr_mask: Buffer to return MAC address mask for macaddr 4423221167Sgnn * @vpath_vector: Buffer to return Bit mask specifying the vpaths to which 4424221167Sgnn * the mac address applies 4425221167Sgnn * 4426221167Sgnn * Reads the mac address,mac address mask and vpath vector from the given offset 4427221167Sgnn * 4428221167Sgnn * see also: vxge_hal_mrpcim_mac_addr_add 4429221167Sgnn * 4430221167Sgnn */ 4431221167Sgnnvxge_hal_status_e 4432221167Sgnnvxge_hal_mrpcim_mac_addr_get( 4433221167Sgnn vxge_hal_device_h devh, 4434221167Sgnn u32 offset, 4435221167Sgnn macaddr_t macaddr, 4436221167Sgnn macaddr_t macaddr_mask, 4437221167Sgnn u64 *vpath_vector); 4438221167Sgnn 4439221167Sgnn/* 4440221167Sgnn * vxge_hal_mrpcim_reset - Reset the entire device. 4441221167Sgnn * @devh: HAL device handle. 4442221167Sgnn * 4443221167Sgnn * Soft-reset the device, reset the device stats except reset_cnt. 4444221167Sgnn * 4445221167Sgnn * 4446221167Sgnn * Returns: VXGE_HAL_OK - success. 4447221167Sgnn * VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED - Device is not initialized. 4448221167Sgnn * VXGE_HAL_ERR_RESET_FAILED - Reset failed. 4449221167Sgnn * 4450221167Sgnn * See also: vxge_hal_status_e {}. 4451221167Sgnn */ 4452221167Sgnnvxge_hal_status_e 4453221167Sgnnvxge_hal_mrpcim_reset(vxge_hal_device_h devh); 4454221167Sgnn 4455221167Sgnn/* 4456221167Sgnn * vxge_hal_mrpcim_reset_poll - Poll the device for reset complete. 4457221167Sgnn * @devh: HAL device handle. 4458221167Sgnn * 4459221167Sgnn * Soft-reset the device, reset the device stats except reset_cnt. 4460221167Sgnn * 4461221167Sgnn * After reset is done, will try to re-initialize HW. 4462221167Sgnn * 4463221167Sgnn * Returns: VXGE_HAL_OK - success. 4464221167Sgnn * VXGE_HAL_ERR_DEVICE_NOT_INITIALIZED - Device is not initialized. 4465221167Sgnn * VXGE_HAL_ERR_RESET_FAILED - Reset failed. 4466221167Sgnn * 4467221167Sgnn * See also: vxge_hal_status_e {}. 4468221167Sgnn */ 4469221167Sgnnvxge_hal_status_e 4470221167Sgnnvxge_hal_mrpcim_reset_poll(vxge_hal_device_h devh); 4471221167Sgnn 4472221167Sgnn/* 4473221167Sgnn * vxge_hal_mrpcim_strip_repl_vlan_tag_enable - Enable strip Repl vlan tag. 4474221167Sgnn * @devh: Device handle. 4475221167Sgnn * 4476221167Sgnn * Enable X3100 strip Repl vlan tag. 4477221167Sgnn * Returns: VXGE_HAL_OK on success. 4478221167Sgnn * 4479221167Sgnn */ 4480221167Sgnnvxge_hal_status_e 4481221167Sgnnvxge_hal_mrpcim_strip_repl_vlan_tag_enable( 4482221167Sgnn vxge_hal_device_h devh); 4483221167Sgnn 4484221167Sgnn/* 4485221167Sgnn * vxge_hal_mrpcim_strip_repl_vlan_tag_disable - Disable strip Repl vlan tag. 4486221167Sgnn * @devh: Device handle. 4487221167Sgnn * 4488221167Sgnn * Disable X3100 strip Repl vlan tag. 4489221167Sgnn * Returns: VXGE_HAL_OK on success. 4490221167Sgnn * 4491221167Sgnn */ 4492221167Sgnnvxge_hal_status_e 4493221167Sgnnvxge_hal_mrpcim_strip_repl_vlan_tag_disable( 4494221167Sgnn vxge_hal_device_h devh); 4495221167Sgnn 4496221167Sgnn/* 4497221167Sgnn * vxge_hal_mrpcim_intr_enable - Enable the interrupts on mrpcim. 4498221167Sgnn * @devh: HAL device handle. 4499221167Sgnn * 4500221167Sgnn * Enable mrpcim interrupts 4501221167Sgnn * 4502221167Sgnn * See also: vxge_hal_mrpcim_intr_disable(). 4503221167Sgnn */ 4504221167Sgnnvxge_hal_status_e 4505221167Sgnnvxge_hal_mrpcim_intr_enable(vxge_hal_device_h devh); 4506221167Sgnn 4507221167Sgnn/* 4508221167Sgnn * vxge_hal_mrpcim_intr_disable - Disable the interrupts on mrpcim. 4509221167Sgnn * @devh: HAL device handle. 4510221167Sgnn * 4511221167Sgnn * Disable mrpcim interrupts 4512221167Sgnn * 4513221167Sgnn * See also: vxge_hal_mrpcim_intr_enable(). 4514221167Sgnn */ 4515221167Sgnnvxge_hal_status_e 4516221167Sgnnvxge_hal_mrpcim_intr_disable(vxge_hal_device_h devh); 4517221167Sgnn 4518221167Sgnn/* 4519221167Sgnn * vxge_hal_mrpcim_lag_config_get - Get the LAG config. 4520221167Sgnn * @devh: Device handle. 4521221167Sgnn * @lconfig: LAG Configuration 4522221167Sgnn * 4523221167Sgnn * Returns the current LAG configuration. 4524221167Sgnn * Returns: VXGE_HAL_OK on success. 4525221167Sgnn * 4526221167Sgnn */ 4527221167Sgnnvxge_hal_status_e 4528221167Sgnnvxge_hal_mrpcim_lag_config_get( 4529221167Sgnn vxge_hal_device_h devh, 4530221167Sgnn vxge_hal_lag_config_t *lconfig); 4531221167Sgnn 4532221167Sgnn/* 4533221167Sgnn * vxge_hal_mrpcim_lag_config_set - Set the LAG config. 4534221167Sgnn * @devh: Device handle. 4535221167Sgnn * @lconfig: LAG Configuration 4536221167Sgnn * 4537221167Sgnn * Sets the LAG configuration. 4538221167Sgnn * Returns: VXGE_HAL_OK on success. 4539221167Sgnn * 4540221167Sgnn */ 4541221167Sgnnvxge_hal_status_e 4542221167Sgnnvxge_hal_mrpcim_lag_config_set( 4543221167Sgnn vxge_hal_device_h devh, 4544221167Sgnn vxge_hal_lag_config_t *lconfig); 4545221167Sgnn 4546221167Sgnn/* 4547221167Sgnn * vxge_hal_mrpcim_getpause_data -Pause frame frame generation and reception. 4548221167Sgnn * @devh: HAL device handle. 4549221167Sgnn * @port : Port number 0, 1, or 2 4550221167Sgnn * @tx : A field to return the pause generation capability of the NIC. 4551221167Sgnn * @rx : A field to return the pause reception capability of the NIC. 4552221167Sgnn * 4553221167Sgnn * Returns the Pause frame generation and reception capability of the NIC. 4554221167Sgnn * Return value: 4555221167Sgnn * status 4556221167Sgnn */ 4557221167Sgnnvxge_hal_status_e 4558221167Sgnnvxge_hal_mrpcim_getpause_data(vxge_hal_device_h devh, 4559221167Sgnn u32 port, 4560221167Sgnn u32 *tx, 4561221167Sgnn u32 *rx); 4562221167Sgnn 4563221167Sgnn/* 4564221167Sgnn * vxge_hal_mrpcim_setpause_data - set/reset pause frame generation. 4565221167Sgnn * @devh: HAL device handle. 4566221167Sgnn * @port : Port number 0, 1, or 2 4567221167Sgnn * @tx: A field that indicates the pause generation capability to be 4568221167Sgnn * set on the NIC. 4569221167Sgnn * @rx: A field that indicates the pause reception capability to be 4570221167Sgnn * set on the NIC. 4571221167Sgnn * 4572221167Sgnn * It can be used to set or reset Pause frame generation or reception 4573221167Sgnn * support of the NIC. 4574221167Sgnn * Return value: 4575221167Sgnn * int, returns 0 on Success 4576221167Sgnn */ 4577221167Sgnn 4578221167Sgnnvxge_hal_status_e 4579221167Sgnnvxge_hal_mrpcim_setpause_data( 4580221167Sgnn vxge_hal_device_h devh, 4581221167Sgnn u32 port, 4582221167Sgnn u32 tx, 4583221167Sgnn u32 rx); 4584221167Sgnn 4585221167Sgnn/* 4586221167Sgnn * vxge_hal_mrpcim_bist_test - invokes the MemBist test of the card . 4587221167Sgnn * @devh: HAL device handle. 4588221167Sgnn * @data:variable that returns the result of each of the test conducted by 4589221167Sgnn * the driver. 4590221167Sgnn * 4591221167Sgnn * This invokes the MemBist test of the card. We give around 4592221167Sgnn * 2 secs time for the Test to complete. If it's still not complete 4593221167Sgnn * within this peiod, we consider that the test failed. 4594221167Sgnn * Return value: 4595221167Sgnn * 0 on success and -1 on failure. 4596221167Sgnn */ 4597221167Sgnnvxge_hal_status_e 4598221167Sgnnvxge_hal_mrpcim_bist_test(vxge_hal_device_h devh, u64 *data); 4599221167Sgnn 4600221167Sgnn/* 4601221167Sgnn * vxge_hal_mrpcim_udp_rth_enable - Enable UDP/RTH. 4602221167Sgnn * @devh: HAL device handle. 4603221167Sgnn * 4604221167Sgnn * enable udp rth 4605221167Sgnn * 4606221167Sgnn */ 4607221167Sgnnvxge_hal_status_e 4608221167Sgnnvxge_hal_mrpcim_udp_rth_enable( 4609221167Sgnn vxge_hal_device_h devh); 4610221167Sgnn 4611221167Sgnn/* 4612221167Sgnn * Virtual Paths 4613221167Sgnn */ 4614221167Sgnn 4615221167Sgnn/* 4616221167Sgnn * struct vxge_hal_vpath_attr_t - Attributes of virtual path 4617221167Sgnn * @vp_id: Identifier of Virtual Path 4618221167Sgnn * @ring_attr: Attributes of ring for non-offload receive 4619221167Sgnn * @fifo_attr: Attributes of fifo for non-offload transmit 4620221167Sgnn * 4621221167Sgnn * Attributes of virtual path. This structure is passed as parameter 4622221167Sgnn * to the vxge_hal_vpath_open() routine to set the attributes of DMQ, UMQ, 4623221167Sgnn * ring and fifo. After virtual path is open, iWARP/RDMA module can attach 4624221167Sgnn * to virtual path. 4625221167Sgnn */ 4626221167Sgnntypedef struct vxge_hal_vpath_attr_t { 4627221167Sgnn u32 vp_id; 4628221167Sgnn vxge_hal_ring_attr_t ring_attr; 4629221167Sgnn vxge_hal_fifo_attr_t fifo_attr; 4630221167Sgnn} vxge_hal_vpath_attr_t; 4631221167Sgnn 4632221167Sgnn/* 4633221167Sgnn * vxge_hal_vpath_open - Open a virtual path on a given adapter 4634221167Sgnn * @devh: handle to device object 4635221167Sgnn * @attr: Virtual path attributes 4636221167Sgnn * @cb_fn: Call back to be called to complete an asynchronous function call 4637221167Sgnn * @client_handle: handle to be returned in the callback 4638221167Sgnn * @vpath_handle: Buffer to return a handle to the vpath 4639221167Sgnn * 4640221167Sgnn * This function is used to open access to virtual path of an 4641221167Sgnn * adapter for offload, LRO and SPDM operations. This function returns 4642221167Sgnn * synchronously. 4643221167Sgnn */ 4644221167Sgnnvxge_hal_status_e 4645221167Sgnnvxge_hal_vpath_open( 4646221167Sgnn vxge_hal_device_h devh, 4647221167Sgnn vxge_hal_vpath_attr_t *attr, 4648221167Sgnn vxge_hal_vpath_callback_f cb_fn, 4649221167Sgnn vxge_hal_client_h client_handle, 4650221167Sgnn vxge_hal_vpath_h *vpath_handle); 4651221167Sgnn 4652221167Sgnn/* 4653221167Sgnn * vxge_hal_vpath_enable 4654221167Sgnn * @vpath_handle: Handle to the vpath object 4655221167Sgnn * 4656221167Sgnn * This routine clears the vpath reset and puts vpath in service 4657221167Sgnn */ 4658221167Sgnnvxge_hal_status_e 4659221167Sgnnvxge_hal_vpath_enable( 4660221167Sgnn vxge_hal_vpath_h vpath_handle); 4661221167Sgnn 4662221167Sgnn/* 4663221167Sgnn * vxge_hal_vpath_id - Get virtual path ID 4664221167Sgnn * @vpath_handle: Handle got from previous vpath open 4665221167Sgnn * 4666221167Sgnn * This function returns virtual path id 4667221167Sgnn */ 4668221167Sgnnu32 4669221167Sgnnvxge_hal_vpath_id(vxge_hal_vpath_h vpath_handle); 4670221167Sgnn 4671221167Sgnn/* 4672221167Sgnn * vxge_hal_vpath_close - Close the handle got from previous vpath (vpath) open 4673221167Sgnn * @vpath_handle: Handle got from previous vpath open 4674221167Sgnn * 4675221167Sgnn * This function is used to close access to virtual path opened 4676221167Sgnn * earlier. This function returns synchronously. 4677221167Sgnn */ 4678221167Sgnnvxge_hal_status_e 4679221167Sgnnvxge_hal_vpath_close(vxge_hal_vpath_h vpath_handle); 4680221167Sgnn 4681221167Sgnn/* 4682221167Sgnn * vxge_hal_vpath_reset - Resets vpath 4683221167Sgnn * @vpath_handle: Handle got from previous vpath open 4684221167Sgnn * 4685221167Sgnn * This function is used to request a reset of vpath 4686221167Sgnn */ 4687221167Sgnnvxge_hal_status_e 4688221167Sgnnvxge_hal_vpath_reset(vxge_hal_vpath_h vpath_handle); 4689221167Sgnn 4690221167Sgnn/* 4691221167Sgnn * vxge_hal_vpath_reset_poll - Poll for reset complete 4692221167Sgnn * @vpath_handle: Handle got from previous vpath open 4693221167Sgnn * 4694221167Sgnn * This function is used to poll for the vpath reset completion 4695221167Sgnn */ 4696221167Sgnnvxge_hal_status_e 4697221167Sgnnvxge_hal_vpath_reset_poll(vxge_hal_vpath_h vpath_handle); 4698221167Sgnn 4699221167Sgnn/* 4700221167Sgnn * vxge_hal_vpath_obj_count_get - Get the Object usage count for a given 4701221167Sgnn * virtual path 4702221167Sgnn * @vpath_handle: Virtal path handle 4703221167Sgnn * @obj_counts: Buffer to return object counts 4704221167Sgnn * 4705221167Sgnn * This function returns the object counts for virtual path. This function 4706221167Sgnn * returns synchronously. 4707221167Sgnn */ 4708221167Sgnnvxge_hal_status_e 4709221167Sgnnvxge_hal_vpath_obj_count_get(vxge_hal_vpath_h vpath_handle, 4710221167Sgnn vxge_hal_vpath_sw_obj_count_t *obj_counts); 4711221167Sgnn 4712221167Sgnn/* 4713221167Sgnn * vxge_hal_vpath_mtu_check - check MTU value for ranges 4714221167Sgnn * @vpath_handle: Virtal path handle 4715221167Sgnn * @new_mtu: new MTU value to check 4716221167Sgnn * 4717221167Sgnn * Will do sanity check for new MTU value. 4718221167Sgnn * 4719221167Sgnn * Returns: VXGE_HAL_OK - success. 4720221167Sgnn * VXGE_HAL_ERR_INVALID_MTU_SIZE - MTU is invalid. 4721221167Sgnn * 4722221167Sgnn * See also: vxge_hal_vpath_mtu_set() 4723221167Sgnn */ 4724221167Sgnnvxge_hal_status_e 4725221167Sgnnvxge_hal_device_mtu_check(vxge_hal_vpath_h vpath_handle, 4726221167Sgnn unsigned long new_mtu); 4727221167Sgnn 4728221167Sgnn/* 4729221167Sgnn * vxge_hal_vpath_mtu_set - Set MTU. 4730221167Sgnn * @vpath_handle: Virtal path handle 4731221167Sgnn * @new_mtu: New MTU size to configure. 4732221167Sgnn * 4733221167Sgnn * Set new MTU value. Example, to use jumbo frames: 4734221167Sgnn * vxge_hal_vpath_mtu_set(my_device, 9600); 4735221167Sgnn * 4736221167Sgnn */ 4737221167Sgnnvxge_hal_status_e 4738221167Sgnnvxge_hal_vpath_mtu_set(vxge_hal_vpath_h vpath_handle, 4739221167Sgnn unsigned long new_mtu); 4740221167Sgnn 4741221167Sgnntypedef enum vxge_hal_vpath_mac_addr_add_mode_e { 4742221167Sgnn VXGE_HAL_VPATH_MAC_ADDR_ADD_DUPLICATE = 0, 4743221167Sgnn VXGE_HAL_VPATH_MAC_ADDR_DISCARD_DUPLICATE = 1, 4744221167Sgnn VXGE_HAL_VPATH_MAC_ADDR_REPLACE_DUPLICATE = 2 4745221167Sgnn} vxge_hal_vpath_mac_addr_add_mode_e; 4746221167Sgnn 4747221167Sgnn/* 4748221167Sgnn * vxge_hal_vpath_mac_addr_add - Add the mac address entry for this vpath 4749221167Sgnn * to MAC address table. 4750221167Sgnn * @vpath_handle: Vpath handle. 4751221167Sgnn * @macaddr: MAC address to be added for this vpath into the list 4752221167Sgnn * @macaddr_mask: MAC address mask for mac_addr 4753221167Sgnn * @duplicate_mode: Duplicate MAC address add mode. Please see 4754221167Sgnn * vxge_hal_vpath_mac_addr_add_mode_e {} 4755221167Sgnn * 4756221167Sgnn * Adds the given mac address and mac address mask into the list for this 4757221167Sgnn * vpath. 4758221167Sgnn * see also: vxge_hal_vpath_mac_addr_delete, vxge_hal_vpath_mac_addr_get and 4759221167Sgnn * vxge_hal_vpath_mac_addr_get_next 4760221167Sgnn * 4761221167Sgnn */ 4762221167Sgnnvxge_hal_status_e 4763221167Sgnnvxge_hal_vpath_mac_addr_add( 4764221167Sgnn vxge_hal_vpath_h vpath_handle, 4765221167Sgnn macaddr_t macaddr, 4766221167Sgnn macaddr_t macaddr_mask, 4767221167Sgnn vxge_hal_vpath_mac_addr_add_mode_e duplicate_mode); 4768221167Sgnn 4769221167Sgnn/* 4770221167Sgnn * vxge_hal_vpath_mac_addr_get - Get the first mac address entry for this vpath 4771221167Sgnn * from MAC address table. 4772221167Sgnn * @vpath_handle: Vpath handle. 4773221167Sgnn * @macaddr: First MAC address entry for this vpath in the list 4774221167Sgnn * @macaddr_mask: MAC address mask for mac_addr 4775221167Sgnn * 4776221167Sgnn * Returns the first mac address and mac address mask in the list for this 4777221167Sgnn * vpath. 4778221167Sgnn * see also: vxge_hal_vpath_mac_addr_get_next 4779221167Sgnn * 4780221167Sgnn */ 4781221167Sgnnvxge_hal_status_e 4782221167Sgnnvxge_hal_vpath_mac_addr_get( 4783221167Sgnn vxge_hal_vpath_h vpath_handle, 4784221167Sgnn macaddr_t macaddr, 4785221167Sgnn macaddr_t macaddr_mask); 4786221167Sgnn 4787221167Sgnn/* 4788221167Sgnn * vxge_hal_vpath_mac_addr_get_next - Get the next mac address entry for this 4789221167Sgnn * vpath from MAC address table. 4790221167Sgnn * @vpath_handle: Vpath handle. 4791221167Sgnn * @macaddr: Next MAC address entry for this vpath in the list 4792221167Sgnn * @macaddr_mask: MAC address mask for mac_addr 4793221167Sgnn * 4794221167Sgnn * Returns the next mac address and mac address mask in the list for this 4795221167Sgnn * vpath. 4796221167Sgnn * see also: vxge_hal_vpath_mac_addr_get 4797221167Sgnn * 4798221167Sgnn */ 4799221167Sgnnvxge_hal_status_e 4800221167Sgnnvxge_hal_vpath_mac_addr_get_next( 4801221167Sgnn vxge_hal_vpath_h vpath_handle, 4802221167Sgnn macaddr_t macaddr, 4803221167Sgnn macaddr_t macaddr_mask); 4804221167Sgnn 4805221167Sgnn/* 4806221167Sgnn * vxge_hal_vpath_mac_addr_delete - Delete the mac address entry for this vpath 4807221167Sgnn * to MAC address table. 4808221167Sgnn * @vpath_handle: Vpath handle. 4809221167Sgnn * @macaddr: MAC address to be added for this vpath into the list 4810221167Sgnn * @macaddr_mask: MAC address mask for macaddr 4811221167Sgnn * 4812221167Sgnn * Delete the given mac address and mac address mask into the list for this 4813221167Sgnn * vpath. 4814221167Sgnn * see also: vxge_hal_vpath_mac_addr_add, vxge_hal_vpath_mac_addr_get and 4815221167Sgnn * vxge_hal_vpath_mac_addr_get_next 4816221167Sgnn * 4817221167Sgnn */ 4818221167Sgnnvxge_hal_status_e 4819221167Sgnnvxge_hal_vpath_mac_addr_delete( 4820221167Sgnn vxge_hal_vpath_h vpath_handle, 4821221167Sgnn macaddr_t macaddr, 4822221167Sgnn macaddr_t macaddr_mask); 4823221167Sgnn 4824221167Sgnn/* 4825221167Sgnn * vxge_hal_vpath_vid_add - Add the vlan id entry for this vpath 4826221167Sgnn * to vlan id table. 4827221167Sgnn * @vpath_handle: Vpath handle. 4828221167Sgnn * @vid: vlan id to be added for this vpath into the list 4829221167Sgnn * 4830221167Sgnn * Adds the given vlan id into the list for this vpath. 4831221167Sgnn * see also: vxge_hal_vpath_vid_delete, vxge_hal_vpath_vid_get and 4832221167Sgnn * vxge_hal_vpath_vid_get_next 4833221167Sgnn * 4834221167Sgnn */ 4835221167Sgnnvxge_hal_status_e 4836221167Sgnnvxge_hal_vpath_vid_add( 4837221167Sgnn vxge_hal_vpath_h vpath_handle, 4838221167Sgnn u64 vid); 4839221167Sgnn 4840221167Sgnn/* 4841221167Sgnn * vxge_hal_vpath_vid_get - Get the first vid entry for this vpath 4842221167Sgnn * from vlan id table. 4843221167Sgnn * @vpath_handle: Vpath handle. 4844221167Sgnn * @vid: Buffer to return vlan id 4845221167Sgnn * 4846221167Sgnn * Returns the first vlan id in the list for this vpath. 4847221167Sgnn * see also: vxge_hal_vpath_vid_get_next 4848221167Sgnn * 4849221167Sgnn */ 4850221167Sgnnvxge_hal_status_e 4851221167Sgnnvxge_hal_vpath_vid_get( 4852221167Sgnn vxge_hal_vpath_h vpath_handle, 4853221167Sgnn u64 *vid); 4854221167Sgnn 4855221167Sgnn/* 4856221167Sgnn * vxge_hal_vpath_vid_get_next - Get the next vid entry for this vpath 4857221167Sgnn * from vlan id table. 4858221167Sgnn * @vpath_handle: Vpath handle. 4859221167Sgnn * @vid: Buffer to return vlan id 4860221167Sgnn * 4861221167Sgnn * Returns the next vlan id in the list for this vpath. 4862221167Sgnn * see also: vxge_hal_vpath_vid_get 4863221167Sgnn * 4864221167Sgnn */ 4865221167Sgnnvxge_hal_status_e 4866221167Sgnnvxge_hal_vpath_vid_get_next( 4867221167Sgnn vxge_hal_vpath_h vpath_handle, 4868221167Sgnn u64 *vid); 4869221167Sgnn 4870221167Sgnn/* 4871221167Sgnn * vxge_hal_vpath_vid_delete - Delete the vlan id entry for this vpath 4872221167Sgnn * to vlan id table. 4873221167Sgnn * @vpath_handle: Vpath handle. 4874221167Sgnn * @vid: vlan id to be added for this vpath into the list 4875221167Sgnn * 4876221167Sgnn * Adds the given vlan id into the list for this vpath. 4877221167Sgnn * see also: vxge_hal_vpath_vid_add, vxge_hal_vpath_vid_get and 4878221167Sgnn * vxge_hal_vpath_vid_get_next 4879221167Sgnn * 4880221167Sgnn */ 4881221167Sgnnvxge_hal_status_e 4882221167Sgnnvxge_hal_vpath_vid_delete( 4883221167Sgnn vxge_hal_vpath_h vpath_handle, 4884221167Sgnn u64 vid); 4885221167Sgnn 4886221167Sgnn/* 4887221167Sgnn * vxge_hal_vpath_etype_add - Add the Ethertype entry for this vpath 4888221167Sgnn * to Ethertype table. 4889221167Sgnn * @vpath_handle: Vpath handle. 4890221167Sgnn * @etype: ethertype to be added for this vpath into the list 4891221167Sgnn * 4892221167Sgnn * Adds the given Ethertype into the list for this vpath. 4893221167Sgnn * see also: vxge_hal_vpath_etype_delete, vxge_hal_vpath_etype_get and 4894221167Sgnn * vxge_hal_vpath_etype_get_next 4895221167Sgnn * 4896221167Sgnn */ 4897221167Sgnnvxge_hal_status_e 4898221167Sgnnvxge_hal_vpath_etype_add( 4899221167Sgnn vxge_hal_vpath_h vpath_handle, 4900221167Sgnn u64 etype); 4901221167Sgnn 4902221167Sgnn/* 4903221167Sgnn * vxge_hal_vpath_etype_get - Get the first ethertype entry for this vpath 4904221167Sgnn * from Ethertype table. 4905221167Sgnn * @vpath_handle: Vpath handle. 4906221167Sgnn * @etype: Buffer to return Ethertype 4907221167Sgnn * 4908221167Sgnn * Returns the first ethype entry in the list for this vpath. 4909221167Sgnn * see also: vxge_hal_vpath_etype_get_next 4910221167Sgnn * 4911221167Sgnn */ 4912221167Sgnnvxge_hal_status_e 4913221167Sgnnvxge_hal_vpath_etype_get( 4914221167Sgnn vxge_hal_vpath_h vpath_handle, 4915221167Sgnn u64 *etype); 4916221167Sgnn 4917221167Sgnn/* 4918221167Sgnn * vxge_hal_vpath_etype_get_next - Get the next Ethertype entry for this vpath 4919221167Sgnn * from Ethertype table. 4920221167Sgnn * @vpath_handle: Vpath handle. 4921221167Sgnn * @etype: Buffer to return Ethwrtype 4922221167Sgnn * 4923221167Sgnn * Returns the next Ethwrtype in the list for this vpath. 4924221167Sgnn * see also: vxge_hal_vpath_etype_get 4925221167Sgnn * 4926221167Sgnn */ 4927221167Sgnnvxge_hal_status_e 4928221167Sgnnvxge_hal_vpath_etype_get_next( 4929221167Sgnn vxge_hal_vpath_h vpath_handle, 4930221167Sgnn u64 *etype); 4931221167Sgnn 4932221167Sgnn/* 4933221167Sgnn * vxge_hal_vpath_etype_delete - Delete the Ethertype entry for this vpath 4934221167Sgnn * to Ethertype table. 4935221167Sgnn * @vpath_handle: Vpath handle. 4936221167Sgnn * @etype: ethertype to be added for this vpath into the list 4937221167Sgnn * 4938221167Sgnn * Adds the given Ethertype into the list for this vpath. 4939221167Sgnn * see also: vxge_hal_vpath_etype_add, vxge_hal_vpath_etype_get and 4940221167Sgnn * vxge_hal_vpath_etype_get_next 4941221167Sgnn * 4942221167Sgnn */ 4943221167Sgnnvxge_hal_status_e 4944221167Sgnnvxge_hal_vpath_etype_delete( 4945221167Sgnn vxge_hal_vpath_h vpath_handle, 4946221167Sgnn u64 etype); 4947221167Sgnn 4948221167Sgnn/* 4949221167Sgnn * vxge_hal_vpath_port_add - Add the port entry for this vpath 4950221167Sgnn * to port number table. 4951221167Sgnn * @vpath_handle: Vpath handle. 4952221167Sgnn * @port_type: if 0 - Src port or 1 - Dest port 4953221167Sgnn * @protocol: if 0 - TCP or 1 - UDP 4954221167Sgnn * @port: port to be added for this vpath into the list 4955221167Sgnn * 4956221167Sgnn * Adds the given port into the list for this vpath. 4957221167Sgnn * see also: vxge_hal_vpath_port_delete, vxge_hal_vpath_port_get and 4958221167Sgnn * vxge_hal_vpath_port_get_next 4959221167Sgnn * 4960221167Sgnn */ 4961221167Sgnnvxge_hal_status_e 4962221167Sgnnvxge_hal_vpath_port_add( 4963221167Sgnn vxge_hal_vpath_h vpath_handle, 4964221167Sgnn u32 port_type, 4965221167Sgnn u32 protocol, 4966221167Sgnn u32 port); 4967221167Sgnn 4968221167Sgnn/* 4969221167Sgnn * vxge_hal_vpath_port_get - Get the first port number entry for this vpath 4970221167Sgnn * from port number table. 4971221167Sgnn * @vpath_handle: Vpath handle. 4972221167Sgnn * @port_type: Buffer to return if 0 - Src port or 1 - Dest port 4973221167Sgnn * @protocol: Buffer to return if 0 - TCP or 1 - UDP 4974221167Sgnn * @port: Buffer to return port number 4975221167Sgnn * 4976221167Sgnn * Returns the first port number entry in the list for this vpath. 4977221167Sgnn * see also: vxge_hal_vpath_port_get_next 4978221167Sgnn * 4979221167Sgnn */ 4980221167Sgnnvxge_hal_status_e 4981221167Sgnnvxge_hal_vpath_port_get( 4982221167Sgnn vxge_hal_vpath_h vpath_handle, 4983221167Sgnn u32 *port_type, 4984221167Sgnn u32 *protocol, 4985221167Sgnn u32 *port); 4986221167Sgnn 4987221167Sgnn/* 4988221167Sgnn * vxge_hal_vpath_port_get_next - Get the next port number entry for this vpath 4989221167Sgnn * from port number table. 4990221167Sgnn * @vpath_handle: Vpath handle. 4991221167Sgnn * @port_type: Buffer to return if 0 - Src port or 1 - Dest port 4992221167Sgnn * @protocol: Buffer to return if 0 - TCP or 1 - UDP 4993221167Sgnn * @port: Buffer to return port number 4994221167Sgnn * 4995221167Sgnn * Returns the next port number entry in the list for this vpath. 4996221167Sgnn * see also: vxge_hal_vpath_port_get 4997221167Sgnn * 4998221167Sgnn */ 4999221167Sgnnvxge_hal_status_e 5000221167Sgnnvxge_hal_vpath_port_get_next( 5001221167Sgnn vxge_hal_vpath_h vpath_handle, 5002221167Sgnn u32 *port_type, 5003221167Sgnn u32 *protocol, 5004221167Sgnn u32 *port); 5005221167Sgnn 5006221167Sgnn/* 5007221167Sgnn * vxge_hal_vpath_port_delete - Delete the port entry for this vpath 5008221167Sgnn * to port number table. 5009221167Sgnn * @vpath_handle: Vpath handle. 5010221167Sgnn * @port_type: if 0 - Src port or 1 - Dest port 5011221167Sgnn * @protocol: if 0 - TCP or 1 - UDP 5012221167Sgnn * @port: port to be added for this vpath into the list 5013221167Sgnn * 5014221167Sgnn * Adds the given port into the list for this vpath. 5015221167Sgnn * see also: vxge_hal_vpath_port_add, vxge_hal_vpath_port_get and 5016221167Sgnn * vxge_hal_vpath_port_get_next 5017221167Sgnn * 5018221167Sgnn */ 5019221167Sgnnvxge_hal_status_e 5020221167Sgnnvxge_hal_vpath_port_delete( 5021221167Sgnn vxge_hal_vpath_h vpath_handle, 5022221167Sgnn u32 port_type, 5023221167Sgnn u32 protocol, 5024221167Sgnn u32 port); 5025221167Sgnn 5026221167Sgnntypedef enum vxge_hal_rth_algoritms_t { 5027221167Sgnn RTH_ALG_NONE = -1, 5028221167Sgnn RTH_ALG_JENKINS = 0, 5029221167Sgnn RTH_ALG_MS_RSS = 1, 5030221167Sgnn RTH_ALG_CRC32C = 2 5031221167Sgnn} vxge_hal_rth_algoritms_t; 5032221167Sgnn 5033221167Sgnn/* 5034221167Sgnn * struct vxge_hal_rth_hash_types_t - RTH hash types. 5035221167Sgnn * @hash_type_tcpipv4_en: Enables RTH field type HashTypeTcpIPv4 5036221167Sgnn * @hash_type_ipv4_en: Enables RTH field type HashTypeIPv4 5037221167Sgnn * @hash_type_tcpipv6_en: Enables RTH field type HashTypeTcpIPv6 5038221167Sgnn * @hash_type_ipv6_en: Enables RTH field type HashTypeIPv6 5039221167Sgnn * @hash_type_tcpipv6ex_en: Enables RTH field type HashTypeTcpIPv6Ex 5040221167Sgnn * @hash_type_ipv6ex_en: Enables RTH field type HashTypeIPv6Ex 5041221167Sgnn * 5042221167Sgnn * Used to pass RTH hash types to rts_rts_set. 5043221167Sgnn * 5044221167Sgnn * See also: vxge_hal_vpath_rts_rth_set(), vxge_hal_vpath_rts_rth_get(). 5045221167Sgnn */ 5046221167Sgnntypedef struct vxge_hal_rth_hash_types_t { 5047221167Sgnn u8 hash_type_tcpipv4_en; 5048221167Sgnn u8 hash_type_ipv4_en; 5049221167Sgnn u8 hash_type_tcpipv6_en; 5050221167Sgnn u8 hash_type_ipv6_en; 5051221167Sgnn u8 hash_type_tcpipv6ex_en; 5052221167Sgnn u8 hash_type_ipv6ex_en; 5053221167Sgnn} vxge_hal_rth_hash_types_t; 5054221167Sgnn 5055221167Sgnn/* 5056221167Sgnn * vxge_hal_vpath_udp_rth_disable - Disable UDP/RTH. 5057221167Sgnn * @vpath_handle: Vpath handle. 5058221167Sgnn * 5059221167Sgnn * Disable udp rth 5060221167Sgnn * 5061221167Sgnn */ 5062221167Sgnnvxge_hal_status_e 5063221167Sgnnvxge_hal_vpath_udp_rth_disable( 5064221167Sgnn vxge_hal_vpath_h vpath_handle); 5065221167Sgnn 5066221167Sgnn/* 5067221167Sgnn * vxge_hal_vpath_rts_rth_set - Set/configure RTS hashing. 5068221167Sgnn * @vpath_handle: Virtual Path handle. 5069221167Sgnn * @algorithm: Algorithm Select 5070221167Sgnn * @hash_type: Hash Type 5071221167Sgnn * @bucket_size: no of least significant bits to be used for hashing. 5072221167Sgnn * @it_switch: Itable switch required 5073221167Sgnn * 5074221167Sgnn * Used to set/configure all RTS hashing related stuff. 5075221167Sgnn * 5076221167Sgnn * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_itable_set(). 5077221167Sgnn */ 5078221167Sgnnvxge_hal_status_e 5079221167Sgnnvxge_hal_vpath_rts_rth_set( 5080221167Sgnn vxge_hal_vpath_h vpath_handle, 5081221167Sgnn vxge_hal_rth_algoritms_t algorithm, 5082221167Sgnn vxge_hal_rth_hash_types_t *hash_type, 5083221167Sgnn u16 bucket_size, 5084221167Sgnn u16 it_switch); 5085221167Sgnn 5086221167Sgnn/* 5087221167Sgnn * vxge_hal_vpath_rts_rth_get - Read RTS hashing. 5088221167Sgnn * @vpath_handle: Virtual Path handle. 5089221167Sgnn * @algorithm: Buffer to return Algorithm Select 5090221167Sgnn * @hash_type: Buffer to return Hash Type 5091221167Sgnn * @table_select: Buffer to return active Table 5092221167Sgnn * @bucket_size: Buffer to return no of least significant bits used for hashing. 5093221167Sgnn * 5094221167Sgnn * Used to read all RTS hashing related stuff. 5095221167Sgnn * 5096221167Sgnn * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_itable_set(), 5097221167Sgnn * vxge_hal_vpath_rts_rth_set(). 5098221167Sgnn */ 5099221167Sgnnvxge_hal_status_e 5100221167Sgnnvxge_hal_vpath_rts_rth_get( 5101221167Sgnn vxge_hal_vpath_h vpath_handle, 5102221167Sgnn vxge_hal_rth_algoritms_t *algorithm, 5103221167Sgnn vxge_hal_rth_hash_types_t *hash_type, 5104221167Sgnn u8 *table_select, 5105221167Sgnn u16 *bucket_size); 5106221167Sgnn 5107221167Sgnn/* 5108221167Sgnn * vxge_hal_vpath_rts_rth_key_set - Configure 40byte secret for hash calc. 5109221167Sgnn * 5110221167Sgnn * @vpath_handle: Virtual Path ahandle. 5111221167Sgnn * @KeySize: Number of 64-bit words 5112221167Sgnn * @Key: upto 40-byte array of 64-bit values 5113221167Sgnn * This function configures the 40-byte secret which is used for hash 5114221167Sgnn * calculation. 5115221167Sgnn * 5116221167Sgnn * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set(). 5117221167Sgnn */ 5118221167Sgnnvxge_hal_status_e 5119221167Sgnnvxge_hal_vpath_rts_rth_key_set( 5120221167Sgnn vxge_hal_vpath_h vpath_handle, 5121221167Sgnn u8 KeySize, 5122221167Sgnn u64 *Key); 5123221167Sgnn 5124221167Sgnn/* 5125221167Sgnn * vxge_hal_vpath_rts_rth_key_get - Read 40byte secret for hash calc. 5126221167Sgnn * 5127221167Sgnn * @vpath_handle: Virtual Path ahandle. 5128221167Sgnn * @KeySize: Number of 64-bit words 5129221167Sgnn * @Key: Buffer to return the key 5130221167Sgnn * This function reads the 40-byte secret which is used for hash 5131221167Sgnn * calculation. 5132221167Sgnn * 5133221167Sgnn * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set(), 5134221167Sgnn * vxge_hal_vpath_rts_rth_key_set(). 5135221167Sgnn */ 5136221167Sgnnvxge_hal_status_e 5137221167Sgnnvxge_hal_vpath_rts_rth_key_get( 5138221167Sgnn vxge_hal_vpath_h vpath_handle, 5139221167Sgnn u8 KeySize, 5140221167Sgnn u64 *Key); 5141221167Sgnn 5142221167Sgnn/* 5143221167Sgnn * vxge_hal_vpath_rts_rth_jhash_cfg_set - Configure JHASH algorithm 5144221167Sgnn * 5145221167Sgnn * @vpath_handle: Virtual Path ahandle. 5146221167Sgnn * @golden_ratio: Golden ratio 5147221167Sgnn * @init_value: Initial value 5148221167Sgnn * This function configures JENKIN's HASH algorithm 5149221167Sgnn * 5150221167Sgnn * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set(). 5151221167Sgnn */ 5152221167Sgnnvxge_hal_status_e 5153221167Sgnnvxge_hal_vpath_rts_rth_jhash_cfg_set( 5154221167Sgnn vxge_hal_vpath_h vpath_handle, 5155221167Sgnn u32 golden_ratio, 5156221167Sgnn u32 init_value); 5157221167Sgnn 5158221167Sgnn/* 5159221167Sgnn * vxge_hal_vpath_rts_rth_jhash_cfg_get - Read JHASH algorithm 5160221167Sgnn * 5161221167Sgnn * @vpath_handle: Virtual Path ahandle. 5162221167Sgnn * @golden_ratio: Buffer to return Golden ratio 5163221167Sgnn * @init_value: Buffer to return Initial value 5164221167Sgnn * This function reads JENKIN's HASH algorithm 5165221167Sgnn * 5166221167Sgnn * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set(), 5167221167Sgnn * vxge_hal_vpath_rts_rth_jhash_cfg_set(). 5168221167Sgnn */ 5169221167Sgnnvxge_hal_status_e 5170221167Sgnnvxge_hal_vpath_rts_rth_jhash_cfg_get( 5171221167Sgnn vxge_hal_vpath_h vpath_handle, 5172221167Sgnn u32 *golden_ratio, 5173221167Sgnn u32 *init_value); 5174221167Sgnn 5175221167Sgnn/* 5176221167Sgnn * vxge_hal_vpath_rts_rth_mask_set - Set/configure JHASH mask. 5177221167Sgnn * @vpath_handle: Virtual Path ahandle. 5178221167Sgnn * @table_size: Size of the mask table 5179221167Sgnn * @hash_mask_ipv6sa: IPv6SA Hash Mask 5180221167Sgnn * @hash_mask_ipv6da: IPv6DA Hash Mask 5181221167Sgnn * @hash_mask_ipv4sa: IPv4SA Hash Mask 5182221167Sgnn * @hash_mask_ipv4da: IPv4DA Hash Mask 5183221167Sgnn * @hash_mask_l4sp: L4SP Hash Mask 5184221167Sgnn * @hash_mask_l4dp: L4DP Hash Mask 5185221167Sgnn * 5186221167Sgnn * Used to set/configure indirection table masks. 5187221167Sgnn * 5188221167Sgnn * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set(). 5189221167Sgnn */ 5190221167Sgnnvxge_hal_status_e 5191221167Sgnnvxge_hal_vpath_rts_rth_mask_set( 5192221167Sgnn vxge_hal_vpath_h vpath_handle, 5193221167Sgnn u32 table_size, 5194221167Sgnn u32 *hash_mask_ipv6sa, 5195221167Sgnn u32 *hash_mask_ipv6da, 5196221167Sgnn u32 *hash_mask_ipv4sa, 5197221167Sgnn u32 *hash_mask_ipv4da, 5198221167Sgnn u32 *hash_mask_l4sp, 5199221167Sgnn u32 *hash_mask_l4dp); 5200221167Sgnn 5201221167Sgnn/* 5202221167Sgnn * vxge_hal_vpath_rts_rth_mask_get - Read JHASH mask. 5203221167Sgnn * @vpath_handle: Virtual Path ahandle. 5204221167Sgnn * @table_size: Size of the mask table 5205221167Sgnn * @hash_mask_ipv6sa: Buffer to return IPv6SA Hash Mask 5206221167Sgnn * @hash_mask_ipv6da: Buffer to return IPv6DA Hash Mask 5207221167Sgnn * @hash_mask_ipv4sa: Buffer to return IPv4SA Hash Mask 5208221167Sgnn * @hash_mask_ipv4da: Buffer to return IPv4DA Hash Mask 5209221167Sgnn * @hash_mask_l4sp: Buffer to return L4SP Hash Mask 5210221167Sgnn * @hash_mask_l4dp: Buffer to return L4DP Hash Mask 5211221167Sgnn * 5212221167Sgnn * Used to read rth mask. 5213221167Sgnn * 5214221167Sgnn * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set(), 5215221167Sgnn * vxge_hal_vpath_rts_rth_mask_set(). 5216221167Sgnn */ 5217221167Sgnnvxge_hal_status_e 5218221167Sgnnvxge_hal_vpath_rts_rth_mask_get( 5219221167Sgnn vxge_hal_vpath_h vpath_handle, 5220221167Sgnn u32 table_size, 5221221167Sgnn u32 *hash_mask_ipv6sa, 5222221167Sgnn u32 *hash_mask_ipv6da, 5223221167Sgnn u32 *hash_mask_ipv4sa, 5224221167Sgnn u32 *hash_mask_ipv4da, 5225221167Sgnn u32 *hash_mask_l4sp, 5226221167Sgnn u32 *hash_mask_l4dp); 5227221167Sgnn 5228221167Sgnn/* 5229221167Sgnn * vxge_hal_vpath_rts_rth_itable_set - Set/configure indirection table (IT). 5230221167Sgnn * @vpath_handles: Virtual Path handles. 5231221167Sgnn * @vpath_count: Number of vpath handles passed in vpath_handles 5232221167Sgnn * @itable: Pointer to indirection table 5233221167Sgnn * @itable_size: Number of entries in itable 5234221167Sgnn * 5235221167Sgnn * Used to set/configure indirection table. 5236221167Sgnn * It enables the required no of entries in the IT. 5237221167Sgnn * It adds entries to the IT. 5238221167Sgnn * 5239221167Sgnn * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set(). 5240221167Sgnn */ 5241221167Sgnnvxge_hal_status_e 5242221167Sgnnvxge_hal_vpath_rts_rth_itable_set( 5243221167Sgnn vxge_hal_vpath_h *vpath_handles, 5244221167Sgnn u32 vpath_count, 5245221167Sgnn u8 *itable, 5246221167Sgnn u32 itable_size); 5247221167Sgnn 5248221167Sgnn/* 5249221167Sgnn * vxge_hal_vpath_rts_rth_itable_get - Read indirection table (IT). 5250221167Sgnn * @vpath_handles: Virtual Path handles. 5251221167Sgnn * @vpath_count: Number of vpath handles passed in vpath_handles 5252221167Sgnn * @itable: Pointer to the buffer to return indirection table 5253221167Sgnn * @itable_size: pointer to buffer to return Number of entries in itable 5254221167Sgnn * 5255221167Sgnn * Used to read indirection table. 5256221167Sgnn * 5257221167Sgnn * See also: vxge_hal_vpath_rts_rth_clr(), vxge_hal_vpath_rts_rth_set(), 5258221167Sgnn * vxge_hal_vpath_rts_rth_itable_set(). 5259221167Sgnn */ 5260221167Sgnnvxge_hal_status_e 5261221167Sgnnvxge_hal_vpath_rts_rth_itable_get( 5262221167Sgnn vxge_hal_vpath_h *vpath_handles, 5263221167Sgnn u32 vpath_count, 5264221167Sgnn u8 *itable, 5265221167Sgnn u32 itable_size); 5266221167Sgnn 5267221167Sgnn/* 5268221167Sgnn * vxge_hal_vpath_rts_rth_clr - Clear RTS hashing. 5269221167Sgnn * @vpath_handles: Virtual Path handles. 5270221167Sgnn * @vpath_count: Number of vpath handles passed in vpath_handles 5271221167Sgnn * 5272221167Sgnn * This function is used to clear all RTS hashing related stuff. 5273221167Sgnn * 5274221167Sgnn * See also: vxge_hal_vpath_rts_rth_set(), vxge_hal_vpath_rts_rth_itable_set(). 5275221167Sgnn */ 5276221167Sgnnvxge_hal_status_e 5277221167Sgnnvxge_hal_vpath_rts_rth_clr( 5278221167Sgnn vxge_hal_vpath_h *vpath_handles, 5279221167Sgnn u32 vpath_count); 5280221167Sgnn 5281221167Sgnn/* 5282221167Sgnn * vxge_hal_vpath_promisc_enable - Enable promiscuous mode. 5283221167Sgnn * @vpath_handle: Vpath handle. 5284221167Sgnn * 5285221167Sgnn * Enable promiscuous mode of X3100 operation. 5286221167Sgnn * 5287221167Sgnn * See also: vxge_hal_vpath_promisc_disable(). 5288221167Sgnn */ 5289221167Sgnnvxge_hal_status_e 5290221167Sgnnvxge_hal_vpath_promisc_enable( 5291221167Sgnn vxge_hal_vpath_h vpath_handle); 5292221167Sgnn 5293221167Sgnn/* 5294221167Sgnn * vxge_hal_vpath_promisc_disable - Disable promiscuous mode. 5295221167Sgnn * @vpath_handle: Vpath handle. 5296221167Sgnn * 5297221167Sgnn * Disable promiscuous mode of X3100 operation. 5298221167Sgnn * 5299221167Sgnn * See also: vxge_hal_vpath_promisc_enable(). 5300221167Sgnn */ 5301221167Sgnnvxge_hal_status_e 5302221167Sgnnvxge_hal_vpath_promisc_disable( 5303221167Sgnn vxge_hal_vpath_h vpath_handle); 5304221167Sgnn 5305221167Sgnn/* 5306221167Sgnn * vxge_hal_vpath_bcast_enable - Enable broadcast 5307221167Sgnn * @vpath_handle: Vpath handle. 5308221167Sgnn * 5309221167Sgnn * Enable receiving broadcasts. 5310221167Sgnn */ 5311221167Sgnnvxge_hal_status_e 5312221167Sgnnvxge_hal_vpath_bcast_enable( 5313221167Sgnn vxge_hal_vpath_h vpath_handle); 5314221167Sgnn 5315221167Sgnn/* 5316221167Sgnn * vxge_hal_vpath_bcast_disable - Disable broadcast 5317221167Sgnn * @vpath_handle: Vpath handle. 5318221167Sgnn * 5319221167Sgnn * Disable receiving broadcasts. 5320221167Sgnn */ 5321221167Sgnnvxge_hal_status_e 5322221167Sgnnvxge_hal_vpath_bcast_disable( 5323221167Sgnn vxge_hal_vpath_h vpath_handle); 5324221167Sgnn 5325221167Sgnn/* 5326221167Sgnn * vxge_hal_vpath_mcast_enable - Enable multicast addresses. 5327221167Sgnn * @vpath_handle: Vpath handle. 5328221167Sgnn * 5329221167Sgnn * Enable X3100 multicast addresses. 5330221167Sgnn * Returns: VXGE_HAL_OK on success. 5331221167Sgnn * 5332221167Sgnn */ 5333221167Sgnnvxge_hal_status_e 5334221167Sgnnvxge_hal_vpath_mcast_enable( 5335221167Sgnn vxge_hal_vpath_h vpath_handle); 5336221167Sgnn 5337221167Sgnn/* 5338221167Sgnn * vxge_hal_vpath_mcast_disable - Disable multicast addresses. 5339221167Sgnn * @vpath_handle: Vpath handle. 5340221167Sgnn * 5341221167Sgnn * Disable X3100 multicast addresses. 5342221167Sgnn * Returns: VXGE_HAL_OK - success. 5343221167Sgnn * 5344221167Sgnn */ 5345221167Sgnnvxge_hal_status_e 5346221167Sgnnvxge_hal_vpath_mcast_disable( 5347221167Sgnn vxge_hal_vpath_h vpath_handle); 5348221167Sgnn 5349221167Sgnn/* 5350221167Sgnn * vxge_hal_vpath_ucast_enable - Enable unicast addresses. 5351221167Sgnn * @vpath_handle: Vpath handle. 5352221167Sgnn * 5353221167Sgnn * Enable X3100 unicast addresses. 5354221167Sgnn * Returns: VXGE_HAL_OK on success. 5355221167Sgnn * 5356221167Sgnn */ 5357221167Sgnnvxge_hal_status_e 5358221167Sgnnvxge_hal_vpath_ucast_enable( 5359221167Sgnn vxge_hal_vpath_h vpath_handle); 5360221167Sgnn 5361221167Sgnn/* 5362221167Sgnn * vxge_hal_vpath_ucast_disable - Disable unicast addresses. 5363221167Sgnn * @vpath_handle: Vpath handle. 5364221167Sgnn * 5365221167Sgnn * Disable X3100 unicast addresses. 5366221167Sgnn * Returns: VXGE_HAL_OK - success. 5367221167Sgnn * 5368221167Sgnn */ 5369221167Sgnnvxge_hal_status_e 5370221167Sgnnvxge_hal_vpath_ucast_disable( 5371221167Sgnn vxge_hal_vpath_h vpath_handle); 5372221167Sgnn 5373221167Sgnn/* 5374221167Sgnn * vxge_hal_vpath_all_vid_enable - Enable all Vlan Ids. 5375221167Sgnn * @vpath_handle: Vpath handle. 5376221167Sgnn * 5377221167Sgnn * Enable X3100 vlan ids. 5378221167Sgnn * Returns: VXGE_HAL_OK on success. 5379221167Sgnn * 5380221167Sgnn */ 5381221167Sgnnvxge_hal_status_e 5382221167Sgnnvxge_hal_vpath_all_vid_enable( 5383221167Sgnn vxge_hal_vpath_h vpath_handle); 5384221167Sgnn 5385221167Sgnn/* 5386221167Sgnn * vxge_hal_vpath_all_vid_disable - Disable all Vlan Ids. 5387221167Sgnn * @vpath_handle: Vpath handle. 5388221167Sgnn * 5389221167Sgnn * Disable X3100 vlan ids. 5390221167Sgnn * Returns: VXGE_HAL_OK - success. 5391221167Sgnn * 5392221167Sgnn */ 5393221167Sgnnvxge_hal_status_e 5394221167Sgnnvxge_hal_vpath_all_vid_disable( 5395221167Sgnn vxge_hal_vpath_h vpath_handle); 5396221167Sgnn 5397221167Sgnn/* 5398221167Sgnn * vxge_hal_vpath_strip_vlan_tag_enable - Enable strip vlan tag. 5399221167Sgnn * @vpath_handle: Vpath handle. 5400221167Sgnn * 5401221167Sgnn * Enable X3100 strip vlan tag. 5402221167Sgnn * Returns: VXGE_HAL_OK on success. 5403221167Sgnn * 5404221167Sgnn */ 5405221167Sgnnvxge_hal_status_e 5406221167Sgnnvxge_hal_vpath_strip_vlan_tag_enable( 5407221167Sgnn vxge_hal_vpath_h vpath_handle); 5408221167Sgnn 5409221167Sgnn/* 5410221167Sgnn * vxge_hal_vpath_strip_vlan_tag_disable - Disable strip vlan tag. 5411221167Sgnn * @vpath_handle: Vpath handle. 5412221167Sgnn * 5413221167Sgnn * Disable X3100 strip vlan tag. 5414221167Sgnn * Returns: VXGE_HAL_OK on success. 5415221167Sgnn * 5416221167Sgnn */ 5417221167Sgnnvxge_hal_status_e 5418221167Sgnnvxge_hal_vpath_strip_vlan_tag_disable( 5419221167Sgnn vxge_hal_vpath_h vpath_handle); 5420221167Sgnn 5421221167Sgnnvoid 5422221167Sgnnvxge_hal_vpath_dynamic_tti_rtimer_set(vxge_hal_vpath_h vpath_handle, 5423221167Sgnn u32 timer_val); 5424221167Sgnn 5425221167Sgnnvoid 5426221167Sgnnvxge_hal_vpath_dynamic_rti_rtimer_set(vxge_hal_vpath_h vpath_handle, 5427221167Sgnn u32 timer_val); 5428221167Sgnn 5429221167Sgnnvoid 5430221167Sgnnvxge_hal_vpath_tti_ci_set(vxge_hal_vpath_h vpath_handle); 5431221167Sgnn 5432221167Sgnnvoid 5433221167Sgnnvxge_hal_vpath_tti_ci_reset(vxge_hal_vpath_h vpath_handle); 5434221167Sgnn 5435221167Sgnnvoid 5436221167Sgnnvxge_hal_vpath_rti_ci_set(vxge_hal_vpath_h vpath_handle); 5437221167Sgnn 5438221167Sgnnvoid 5439221167Sgnnvxge_hal_vpath_rti_ci_reset(vxge_hal_vpath_h vpath_handle); 5440221167Sgnn 5441221167Sgnn/* 5442221167Sgnn * struct vxge_hal_vpath_tpa_params - Vpath TPA Parameters. 5443221167Sgnn * @tpa_lsov2_en: LSOv2 Behaviour for IP ID roll-over 5444221167Sgnn * 1 - enable, 0 - disable, 5445221167Sgnn * VXGE_HAL_DEFAULT_32 - don't change current setting 5446221167Sgnn * @tpa_ignore_frame_error: Ignore Frame Error. TPA may detect frame integrity 5447221167Sgnn * errors as it processes each frame. If this bit is set to '0', 5448221167Sgnn * the TPA will tag such frames as invalid and they will be dropped 5449221167Sgnn * by the transmit MAC. If the bit is set to '1',the frame will not 5450221167Sgnn * be tagged as "errored". Detectable errors include: 5451221167Sgnn * 1) early end-of-frame error, which occurs when the frame ends 5452221167Sgnn * before the number of bytes predicted by the IP "total length" 5453221167Sgnn * field have been received; 5454221167Sgnn * 2) IP version mismatches; 5455221167Sgnn * 3) IPv6 packets that include routing headers that are not type 0 5456221167Sgnn * 4) Frames which contain IP packets but have an illegal SNAP-OUI 5457221167Sgnn * or LLC-CTRL fields, unless IGNORE_SNAP_OUI or IGNORE_LLC_CTRL 5458221167Sgnn * are set (see below). 5459221167Sgnn * setting the value of this field to VXGE_HAL_DEFAULT_32 - don't 5460221167Sgnn * change current setting 5461221167Sgnn * @tpa_ipv6_keep_searching: If unknown IPv6 header is found, 5462221167Sgnn * 0 - stop searching for TCP 5463221167Sgnn * 1 - keep searching for TCP 5464221167Sgnn * VXGE_HAL_DEFAULT_32 - don't change current setting 5465221167Sgnn * @tpa_l4_pshdr_present: If asserted true, indicates the host has provided a 5466221167Sgnn * valid pseudo header for TCP or UDP running over IPv4 or IPv6 5467221167Sgnn * if set to VXGE_HAL_DEFAULT_32 - don't change current setting 5468221167Sgnn * @tpa_support_mobile_ipv6_hdrs: This register is somewhat equivalent to 5469221167Sgnn * asserting both Hercules register fields LSO_RT2_EN and 5470221167Sgnn * LSO_IPV6_HAO_EN. Enable/disable support for Type 2 Routing 5471221167Sgnn * Headers, and for Mobile-IPv6 Home Address Option (HAO), as 5472221167Sgnn * defined by mobile-ipv6. if set to VXGE_HAL_DEFAULT_32 - 5473221167Sgnn * don't change current setting 5474221167Sgnn * 5475221167Sgnn * See also: vxge_hal_vpath_tpa_set() 5476221167Sgnn */ 5477221167Sgnntypedef struct vxge_hal_vpath_tpa_params { 5478221167Sgnn u32 tpa_lsov2_en; 5479221167Sgnn u32 tpa_ignore_frame_error; 5480221167Sgnn u32 tpa_ipv6_keep_searching; 5481221167Sgnn u32 tpa_l4_pshdr_present; 5482221167Sgnn u32 tpa_support_mobile_ipv6_hdrs; 5483221167Sgnn} vxge_hal_vpath_tpa_params; 5484221167Sgnn 5485221167Sgnn/* 5486221167Sgnn * vxge_hal_vpath_tpa_set - Set tpa parameters. 5487221167Sgnn * @vpath_handle: Virtual Path ahandle. 5488221167Sgnn * @params: vxge_hal_vpath_tpa_params {} structure with parameters 5489221167Sgnn * 5490221167Sgnn * The function sets the tpa parametrs for the vpath. 5491221167Sgnn * 5492221167Sgnn * See also: vxge_hal_vpath_tpa_params {} 5493221167Sgnn */ 5494221167Sgnnvxge_hal_status_e 5495221167Sgnnvxge_hal_vpath_tpa_set( 5496221167Sgnn vxge_hal_vpath_h vpath_handle, 5497221167Sgnn vxge_hal_vpath_tpa_params *params); 5498221167Sgnn 5499221167Sgnn/* 5500221167Sgnn * struct vxge_hal_vpath_rpa_params - Vpath RPA Parameters. 5501221167Sgnn * 5502221167Sgnn * @rpa_ipv4_tcp_incl_ph: Determines if the pseudo-header is included in the 5503221167Sgnn * calculation of the L4 checksum that is passed to the host. This 5504221167Sgnn * field applies to TCP/IPv4 packets only. This field affects both 5505221167Sgnn * non-offload and LRO traffic. Note that the RPA always includes 5506221167Sgnn * the pseudo-header in the "Checksum Ok" L4 checksum calculation 5507221167Sgnn * i.e. the checksum that decides whether a frame is a candidate to 5508221167Sgnn * be offloaded. 5509221167Sgnn * 0 - Do not include the pseudo-header in L4 checksum calculation. 5510221167Sgnn * This setting should be used if the adapter is incorrectly 5511221167Sgnn * calculating the pseudo-header. 5512221167Sgnn * 1 - Include the pseudo-header in L4 checksum calculation 5513221167Sgnn * VXGE_HAL_DEFAULT_32 - don't change current setting 5514221167Sgnn * @rpa_ipv6_tcp_incl_ph: Determines whether the pseudo-header is included in 5515221167Sgnn * the calculation of the L4 checksum that is passed to the host. 5516221167Sgnn * This field applies to TCP/IPv6 packets only. This field affects 5517221167Sgnn * both non-offload and LRO traffic. Note that the RPA always 5518221167Sgnn * includes the pseudo-header in the "Checksum Ok" L4 checksum 5519221167Sgnn * calculation. i.e. the checksum that decides whether a frame 5520221167Sgnn * is a candidate to be offloaded. 5521221167Sgnn * 0 - Do not include the pseudo-header in L4 checksum calculation. 5522221167Sgnn * This setting should be used if the adapter is incorrectly 5523221167Sgnn * calculating the pseudo-header. 5524221167Sgnn * 1 - Include the pseudo-header in L4 checksum calculation 5525221167Sgnn * VXGE_HAL_DEFAULT_32 - don't change current setting 5526221167Sgnn * @rpa_ipv4_udp_incl_ph: Determines whether the pseudo-header is included in 5527221167Sgnn * the calculation of the L4 checksum that is passed to the host. 5528221167Sgnn * This field applies to UDP/IPv4 packets only. It only affects 5529221167Sgnn * non-offload traffic(since UDP frames are not candidates for LRO) 5530221167Sgnn * 0 - Do not include the pseudo-header in L4 checksum calculation. 5531221167Sgnn * This setting should be used if the adapter is incorrectly 5532221167Sgnn * calculating the pseudo-header. 5533221167Sgnn * 1 - Include the pseudo-header in L4 checksum calculation 5534221167Sgnn * VXGE_HAL_DEFAULT_32 - don't change current setting 5535221167Sgnn * @rpa_ipv6_udp_incl_ph: Determines if the pseudo-header is included in the 5536221167Sgnn * calculation of the L4 checksum that is passed to the host. This 5537221167Sgnn * field applies to UDP/IPv6 packets only. It only affects 5538221167Sgnn * non-offload traffic(since UDP frames are not candidates for LRO) 5539221167Sgnn * 0 - Do not include the pseudo-header in L4 checksum calculation. 5540221167Sgnn * This setting should be used if the adapter is incorrectly 5541221167Sgnn * calculating the pseudo-header. 5542221167Sgnn * 1 - Include the pseudo-header in L4 checksum calculation 5543221167Sgnn * VXGE_HAL_DEFAULT_32 - don't change current setting 5544221167Sgnn * @rpa_l4_incl_cf: Determines whether the checksum field (CF) of the received 5545221167Sgnn * frame is included in the calculation of the L4 checksum that is 5546221167Sgnn * passed to the host. This field affects both non-offload and LRO 5547221167Sgnn * traffic. Note that the RPA always includes the checksum field in 5548221167Sgnn * the "Checksum Ok" L4 checksum calculation -- i.e. the checksum 5549221167Sgnn * that decides whether a frame is a candidate to be offloaded. 5550221167Sgnn * 0 - Do not include the checksum field in L4 checksum calculation 5551221167Sgnn * 1 - Include the checksum field in L4 checksum calculation 5552221167Sgnn * VXGE_HAL_DEFAULT_32 - don't change current setting 5553221167Sgnn * @rpa_strip_vlan_tag: Strip VLAN Tag enable/disable. Instructs the device to 5554221167Sgnn * remove the VLAN tag from all received tagged frames that are not 5555221167Sgnn * replicated at the internal L2 switch. 5556221167Sgnn * 0 - Do not strip the VLAN tag. 5557221167Sgnn * 1 - Strip the VLAN tag. Regardless of this setting,VLAN tags are 5558221167Sgnn * always placed into the RxDMA descriptor. 5559221167Sgnn * VXGE_HAL_DEFAULT_32 - don't change current setting 5560221167Sgnn * @rpa_l4_comp_csum: Determines whether the calculated L4 checksum should be 5561221167Sgnn * complemented before it is passed to the host This field affects 5562221167Sgnn * both non-offload and LRO traffic. 5563221167Sgnn * 0 - Do not complement the calculated L4 checksum. 5564221167Sgnn * 1 - Complement the calculated L4 checksum 5565221167Sgnn * VXGE_HAL_DEFAULT_32 - don't change current setting 5566221167Sgnn * @rpa_l3_incl_cf: Determines whether the checksum field (CF) of the received 5567221167Sgnn * frame is included in the calculation of the L3 checksum that is 5568221167Sgnn * passed to the host. This field affects both non-offload and LRO 5569221167Sgnn * traffic. Note that the RPA always includes the checksum field in 5570221167Sgnn * the "Checksum Ok" L3 checksum calculation -- i.e. the checksum 5571221167Sgnn * that decides whether a frame is a candidate to be offloaded. 5572221167Sgnn * 0 - Do not include the checksum field in L3 checksum calculation 5573221167Sgnn * 1 - Include the checksum field in L3 checksum calculation 5574221167Sgnn * VXGE_HAL_DEFAULT_32 - don't change current setting 5575221167Sgnn * @rpa_l3_comp_csum: Determines whether the calculated L3 checksum should be 5576221167Sgnn * complemented before it is passed to the host This field affects 5577221167Sgnn * both non-offload and LRO traffic. 5578221167Sgnn * 0 - Do not complement the calculated L3 checksum. 5579221167Sgnn * 1 - Complement the calculated L3 checksum 5580221167Sgnn * VXGE_HAL_DEFAULT_32 - don't change current setting 5581221167Sgnn * @rpa_ucast_all_addr_en: Enables frames with any unicast address (as its 5582221167Sgnn * destination address) to be passed to the host. 5583221167Sgnn * Setting this field to VXGE_HAL_DEFAULT_32 - don't change current 5584221167Sgnn * setting 5585221167Sgnn * @rpa_mcast_all_addr_en: Enables frames with any multicast address (as its 5586221167Sgnn * destination address) to be passed to the host. 5587221167Sgnn * Setting this field to VXGE_HAL_DEFAULT_32 - don't change current 5588221167Sgnn * setting 5589221167Sgnn * @rpa_bcast_en: Enables frames with any broadicast address (as its 5590221167Sgnn * destination address) to be passed to the host. 5591221167Sgnn * Setting this field to VXGE_HAL_DEFAULT_32 - don't change current 5592221167Sgnn * setting 5593221167Sgnn * @rpa_all_vid_en: romiscuous mode, it overrides the value held in this field. 5594221167Sgnn * 0 - Disable; 5595221167Sgnn * 1 - Enable 5596221167Sgnn * VXGE_HAL_DEFAULT_32 - don't change current setting 5597221167Sgnn * Note: RXMAC_GLOBAL_CFG.AUTHORIZE_VP_ALL_VID must be set to 5598221167Sgnn * allow this. 5599221167Sgnn * 5600221167Sgnn * See also: vxge_hal_vpath_rpa_set() 5601221167Sgnn */ 5602221167Sgnntypedef struct vxge_hal_vpath_rpa_params { 5603221167Sgnn u32 rpa_ipv4_tcp_incl_ph; 5604221167Sgnn u32 rpa_ipv6_tcp_incl_ph; 5605221167Sgnn u32 rpa_ipv4_udp_incl_ph; 5606221167Sgnn u32 rpa_ipv6_udp_incl_ph; 5607221167Sgnn u32 rpa_l4_incl_cf; 5608221167Sgnn u32 rpa_strip_vlan_tag; 5609221167Sgnn u32 rpa_l4_comp_csum; 5610221167Sgnn u32 rpa_l3_incl_cf; 5611221167Sgnn u32 rpa_l3_comp_csum; 5612221167Sgnn u32 rpa_ucast_all_addr_en; 5613221167Sgnn u32 rpa_mcast_all_addr_en; 5614221167Sgnn u32 rpa_bcast_en; 5615221167Sgnn u32 rpa_all_vid_en; 5616221167Sgnn} vxge_hal_vpath_rpa_params; 5617221167Sgnn 5618221167Sgnn/* 5619221167Sgnn * vxge_hal_vpath_rpa_set - Set rpa parameters. 5620221167Sgnn * @vpath_handle: Virtual Path ahandle. 5621221167Sgnn * @params: vxge_hal_vpath_rpa_params {} structure with parameters 5622221167Sgnn * 5623221167Sgnn * The function sets the rpa parametrs for the vpath. 5624221167Sgnn * 5625221167Sgnn * See also: vxge_hal_vpath_rpa_params {} 5626221167Sgnn */ 5627221167Sgnnvxge_hal_status_e 5628221167Sgnnvxge_hal_vpath_rpa_set( 5629221167Sgnn vxge_hal_vpath_h vpath_handle, 5630221167Sgnn vxge_hal_vpath_rpa_params *params); 5631221167Sgnn 5632221167Sgnn/* 5633221167Sgnn * vxge_hal_vpath_poll_rx - Poll Rx od Virtual Path for completed 5634221167Sgnn * descriptors and process the same. 5635221167Sgnn * @vpath_handle: Virtual Path ahandle. 5636221167Sgnn * @got_rx: Buffer to return the flag set if receive interrupt is occured 5637221167Sgnn * 5638221167Sgnn * The function polls the Rx for the completed descriptors and calls 5639221167Sgnn * the upper-layer driver (ULD) via supplied completion callback. 5640221167Sgnn * 5641221167Sgnn * Returns: VXGE_HAL_OK, if the polling is completed successful. 5642221167Sgnn * VXGE_HAL_COMPLETIONS_REMAIN: There are still more completed 5643221167Sgnn * descriptors available which are yet to be processed. 5644221167Sgnn * 5645221167Sgnn * See also: vxge_hal_vpath_poll_tx() 5646221167Sgnn */ 5647221167Sgnnvxge_hal_status_e 5648221167Sgnnvxge_hal_vpath_poll_rx( 5649221167Sgnn vxge_hal_vpath_h vpath_handle, 5650221167Sgnn u32 *got_rx); 5651221167Sgnn 5652221167Sgnn/* 5653221167Sgnn * vxge_hal_vpath_poll_tx - Poll Tx for completed descriptors and process 5654221167Sgnn * the same. 5655221167Sgnn * @vpath_handle: Virtual Path ahandle. 5656221167Sgnn * @got_tx: Buffer to return the flag set if transmit interrupt is occured 5657221167Sgnn * 5658221167Sgnn * The function polls the Tx for the completed descriptors and calls 5659221167Sgnn * the upper-layer driver (ULD) via supplied completion callback. 5660221167Sgnn * 5661221167Sgnn * Returns: VXGE_HAL_OK, if the polling is completed successful. 5662221167Sgnn * VXGE_HAL_COMPLETIONS_REMAIN: There are still more completed 5663221167Sgnn * descriptors available which are yet to be processed. 5664221167Sgnn * 5665221167Sgnn * See also: vxge_hal_vpath_poll_rx(). 5666221167Sgnn */ 5667221167Sgnnvxge_hal_status_e 5668221167Sgnnvxge_hal_vpath_poll_tx( 5669221167Sgnn vxge_hal_vpath_h vpath_handle, 5670221167Sgnn u32 *got_tx); 5671221167Sgnn 5672221167Sgnn 5673221167Sgnn/* 5674221167Sgnn * vxge_hal_vpath_intr_enable - Enable vpath interrupts. 5675221167Sgnn * @vpath_handle: Virtual Path handle. 5676221167Sgnn * @op: One of the vxge_hal_vpath_intr_e enumerated values specifying 5677221167Sgnn * the type(s) of interrupts to enable. 5678221167Sgnn * 5679221167Sgnn * Enable vpath interrupts. The function is to be executed the last in 5680221167Sgnn * vpath initialization sequence. 5681221167Sgnn * 5682221167Sgnn * See also: vxge_hal_vpath_intr_disable() 5683221167Sgnn */ 5684221167Sgnnvxge_hal_status_e 5685221167Sgnnvxge_hal_vpath_intr_enable( 5686221167Sgnn vxge_hal_vpath_h vpath_handle); 5687221167Sgnn 5688221167Sgnn/* 5689221167Sgnn * vxge_hal_vpath_intr_disable - Disable vpath interrupts. 5690221167Sgnn * @vpath_handle: Virtual Path handle. 5691221167Sgnn * @op: One of the vxge_hal_vpath_intr_e enumerated values specifying 5692221167Sgnn * the type(s) of interrupts to disable. 5693221167Sgnn * 5694221167Sgnn * Disable vpath interrupts. 5695221167Sgnn * 5696221167Sgnn * See also: vxge_hal_vpath_intr_enable() 5697221167Sgnn */ 5698221167Sgnnvxge_hal_status_e 5699221167Sgnnvxge_hal_vpath_intr_disable( 5700221167Sgnn vxge_hal_vpath_h vpath_handle); 5701221167Sgnn 5702221167Sgnn/* 5703221167Sgnn * vxge_hal_vpath_mask_all - Mask all vpath interrupts. 5704221167Sgnn * @vpath_handle: Virtual Path handle. 5705221167Sgnn * 5706221167Sgnn * Mask all vpath interrupts. 5707221167Sgnn * 5708221167Sgnn * See also: vxge_hal_vpath_unmask_all() 5709221167Sgnn */ 5710221167Sgnnvoid 5711221167Sgnnvxge_hal_vpath_mask_all( 5712221167Sgnn vxge_hal_vpath_h vpath_handle); 5713221167Sgnn 5714221167Sgnn/* 5715221167Sgnn * vxge_hal_vpath_unmask_all - Unmask all vpath interrupts. 5716221167Sgnn * @vpath_handle: Virtual Path handle. 5717221167Sgnn * 5718221167Sgnn * Unmask all vpath interrupts. 5719221167Sgnn * 5720221167Sgnn * See also: vxge_hal_vpath_mask_all() 5721221167Sgnn */ 5722221167Sgnnvoid 5723221167Sgnnvxge_hal_vpath_unmask_all( 5724221167Sgnn vxge_hal_vpath_h vpath_handle); 5725221167Sgnn 5726221167Sgnn/* 5727221167Sgnn * vxge_hal_vpath_begin_irq - Begin IRQ processing. 5728221167Sgnn * @vpath_handle: Virtual Path handle. 5729221167Sgnn * @skip_alarms: Do not clear the alarms 5730221167Sgnn * @reason: "Reason" for the interrupt, the value of vpath's 5731221167Sgnn * general_int_status register. 5732221167Sgnn * 5733221167Sgnn * The function performs two actions, It first checks whether (shared IRQ) the 5734221167Sgnn * interrupt was raised by the device. Next, it masks the device interrupts. 5735221167Sgnn * 5736221167Sgnn * Note: 5737221167Sgnn * vxge_hal_vpath_begin_irq() does not flush MMIO writes through the 5738221167Sgnn * bridge. Therefore, two back-to-back interrupts are potentially possible. 5739221167Sgnn * It is the responsibility of the ULD to make sure that only one 5740221167Sgnn * vxge_hal_vpath_continue_irq() runs at a time. 5741221167Sgnn * 5742221167Sgnn * Returns: 0, if the interrupt is not "ours" (note that in this case the 5743221167Sgnn * vpath remain enabled). 5744221167Sgnn * Otherwise, vxge_hal_vpath_begin_irq() returns 64bit general adapter 5745221167Sgnn * status. 5746221167Sgnn * See also: vxge_hal_vpath_handle_irq() 5747221167Sgnn */ 5748221167Sgnnvxge_hal_status_e 5749221167Sgnnvxge_hal_vpath_begin_irq( 5750221167Sgnn vxge_hal_vpath_h vpath_handle, 5751221167Sgnn u32 skip_alarms, 5752221167Sgnn u64 *reason); 5753221167Sgnn 5754221167Sgnn/* 5755221167Sgnn * vxge_hal_vpath_continue_irq - Continue handling IRQ: process all 5756221167Sgnn * completed descriptors. 5757221167Sgnn * @vpath_handle: Virtual Path handle. 5758221167Sgnn * 5759221167Sgnn * Process completed descriptors and unmask the vpath interrupts. 5760221167Sgnn * 5761221167Sgnn * The vxge_hal_vpath_continue_irq() calls upper-layer driver (ULD) 5762221167Sgnn * via supplied completion callback. 5763221167Sgnn * 5764221167Sgnn * Note that the vxge_hal_vpath_continue_irq is part of the _fast_ path. 5765221167Sgnn * To optimize the processing, the function does _not_ check for 5766221167Sgnn * errors and alarms. 5767221167Sgnn * 5768221167Sgnn * Returns: VXGE_HAL_OK. 5769221167Sgnn * 5770221167Sgnn * See also: vxge_hal_vpath_handle_irq(), 5771221167Sgnn * vxge_hal_ring_rxd_next_completed(), 5772221167Sgnn * vxge_hal_fifo_txdl_next_completed(), vxge_hal_ring_callback_f {}, 5773221167Sgnn * vxge_hal_fifo_callback_f {}. 5774221167Sgnn */ 5775221167Sgnnvxge_hal_status_e 5776221167Sgnnvxge_hal_vpath_continue_irq( 5777221167Sgnn vxge_hal_vpath_h vpath_handle); 5778221167Sgnn 5779221167Sgnn/* 5780221167Sgnn * vxge_hal_vpathe_handle_irq - Handle vpath IRQ. 5781221167Sgnn * @vpath_handle: Virtual Path handle. 5782221167Sgnn * @skip_alarms: Do not clear the alarms 5783221167Sgnn * 5784221167Sgnn * Perform the complete handling of the line interrupt. The function 5785221167Sgnn * performs two calls. 5786221167Sgnn * First it uses vxge_hal_vpath_begin_irq() to check the reason for 5787221167Sgnn * the interrupt and mask the vpath interrupts. 5788221167Sgnn * Second, it calls vxge_hal_vpath_continue_irq() to process all 5789221167Sgnn * completed descriptors and re-enable the interrupts. 5790221167Sgnn * 5791221167Sgnn * Returns: VXGE_HAL_OK - success; 5792221167Sgnn * VXGE_HAL_ERR_WRONG_IRQ - (shared) IRQ produced by other device. 5793221167Sgnn * 5794221167Sgnn * See also: vxge_hal_vpath_begin_irq(), vxge_hal_vpath_continue_irq(). 5795221167Sgnn */ 5796221167Sgnnvxge_hal_status_e 5797221167Sgnnvxge_hal_vpath_handle_irq( 5798221167Sgnn vxge_hal_vpath_h vpath_handle, 5799221167Sgnn u32 skip_alarms); 5800221167Sgnn 5801221167Sgnn/* 5802221167Sgnn * vxge_hal_vpath_mask_tx - Mask Tx interrupts. 5803221167Sgnn * @vpath_handle: Virtual Path handle. 5804221167Sgnn * 5805221167Sgnn * Mask Tx device interrupts. 5806221167Sgnn * 5807221167Sgnn * See also: vxge_hal_vpath_unmask_tx(), vxge_hal_vpath_mask_rx(), 5808221167Sgnn * vxge_hal_vpath_clear_tx(). 5809221167Sgnn */ 5810221167Sgnnvoid 5811221167Sgnnvxge_hal_vpath_mask_tx( 5812221167Sgnn vxge_hal_vpath_h vpath_handle); 5813221167Sgnn 5814221167Sgnn/* 5815221167Sgnn * vxge_hal_vpath_clear_tx - Acknowledge (that is, clear) the 5816221167Sgnn * condition that has caused the TX interrupt. 5817221167Sgnn * @vpath_handle: Virtual Path handle. 5818221167Sgnn * 5819221167Sgnn * Acknowledge (that is, clear) the condition that has caused 5820221167Sgnn * the Tx interrupt. 5821221167Sgnn * See also: vxge_hal_vpath_begin_irq(), vxge_hal_vpath_continue_irq(), 5822221167Sgnn * vxge_hal_vpath_clear_rx(), vxge_hal_vpath_mask_tx(). 5823221167Sgnn */ 5824221167Sgnnvoid 5825221167Sgnnvxge_hal_vpath_clear_tx( 5826221167Sgnn vxge_hal_vpath_h vpath_handle); 5827221167Sgnn 5828221167Sgnn 5829221167Sgnn/* 5830221167Sgnn * vxge_hal_vpath_unmask_tx - Unmask Tx interrupts. 5831221167Sgnn * @vpath_handle: Virtual Path handle. 5832221167Sgnn * 5833221167Sgnn * Unmask Tx vpath interrupts. 5834221167Sgnn * 5835221167Sgnn * See also: vxge_hal_vpath_mask_tx(), vxge_hal_vpath_clear_tx(). 5836221167Sgnn */ 5837221167Sgnnvoid 5838221167Sgnnvxge_hal_vpath_unmask_tx( 5839221167Sgnn vxge_hal_vpath_h vpath_handle); 5840221167Sgnn 5841221167Sgnn/* 5842221167Sgnn * vxge_hal_vpath_mask_rx - Mask Rx interrupts. 5843221167Sgnn * @vpath_handle: Virtual Path handle. 5844221167Sgnn * 5845221167Sgnn * Mask Rx vpath interrupts. 5846221167Sgnn * 5847221167Sgnn * See also: vxge_hal_vpath_unmask_rx(), vxge_hal_vpath_mask_tx(), 5848221167Sgnn * vxge_hal_vpath_clear_rx(). 5849221167Sgnn */ 5850221167Sgnnvoid 5851221167Sgnnvxge_hal_vpath_mask_rx( 5852221167Sgnn vxge_hal_vpath_h vpath_handle); 5853221167Sgnn 5854221167Sgnn 5855221167Sgnn/* 5856221167Sgnn * vxge_hal_vpath_clear_rx - Acknowledge (that is, clear) the 5857221167Sgnn * condition that has caused the RX interrupt. 5858221167Sgnn * @vpath_handle: Virtual Path handle. 5859221167Sgnn * 5860221167Sgnn * Acknowledge (that is, clear) the condition that has caused 5861221167Sgnn * the Rx interrupt. 5862221167Sgnn * See also: vxge_hal_vpath_begin_irq(), vxge_hal_vpath_continue_irq(), 5863221167Sgnn * vxge_hal_vpath_clear_tx(), vxge_hal_vpath_mask_rx(). 5864221167Sgnn */ 5865221167Sgnnvoid 5866221167Sgnnvxge_hal_vpath_clear_rx( 5867221167Sgnn vxge_hal_vpath_h vpath_handle); 5868221167Sgnn 5869221167Sgnn/* 5870221167Sgnn * vxge_hal_vpath_unmask_rx - Unmask Rx interrupts. 5871221167Sgnn * @vpath_handle: Virtual Path handle. 5872221167Sgnn * 5873221167Sgnn * Unmask Rx vpath interrupts. 5874221167Sgnn * 5875221167Sgnn * See also: vxge_hal_vpath_mask_rx(), vxge_hal_vpath_clear_rx(). 5876221167Sgnn */ 5877221167Sgnnvoid 5878221167Sgnnvxge_hal_vpath_unmask_rx( 5879221167Sgnn vxge_hal_vpath_h vpath_handle); 5880221167Sgnn 5881221167Sgnn/* 5882221167Sgnn * vxge_hal_vpath_mask_tx_rx - Mask Tx and Rx interrupts. 5883221167Sgnn * @vpath_handle: Virtual Path handle. 5884221167Sgnn * 5885221167Sgnn * Mask Tx and Rx vpath interrupts. 5886221167Sgnn * 5887221167Sgnn * See also: vxge_hal_vpath_unmask_tx_rx(), vxge_hal_vpath_clear_tx_rx(). 5888221167Sgnn */ 5889221167Sgnnvoid 5890221167Sgnnvxge_hal_vpath_mask_tx_rx( 5891221167Sgnn vxge_hal_vpath_h vpath_handle); 5892221167Sgnn 5893221167Sgnn/* 5894221167Sgnn * vxge_hal_vpath_clear_tx_rx - Acknowledge (that is, clear) the 5895221167Sgnn * condition that has caused the Tx and RX interrupt. 5896221167Sgnn * @vpath_handle: Virtual Path handle. 5897221167Sgnn * 5898221167Sgnn * Acknowledge (that is, clear) the condition that has caused 5899221167Sgnn * the Tx and Rx interrupt. 5900221167Sgnn * See also: vxge_hal_vpath_begin_irq(), vxge_hal_vpath_continue_irq(), 5901221167Sgnn * vxge_hal_vpath_clear_tx_rx(), vxge_hal_vpath_mask_tx_rx(). 5902221167Sgnn */ 5903221167Sgnnvoid 5904221167Sgnnvxge_hal_vpath_clear_tx_rx( 5905221167Sgnn vxge_hal_vpath_h vpath_handle); 5906221167Sgnn 5907221167Sgnn/* 5908221167Sgnn * vxge_hal_vpath_unmask_tx_rx - Unmask Tx and Rx interrupts. 5909221167Sgnn * @vpath_handle: Virtual Path handle. 5910221167Sgnn * 5911221167Sgnn * Unmask Tx and Rx vpath interrupts. 5912221167Sgnn * 5913221167Sgnn * See also: vxge_hal_vpath_mask_tx_rx(), vxge_hal_vpath_clear_tx_rx(). 5914221167Sgnn */ 5915221167Sgnnvoid 5916221167Sgnnvxge_hal_vpath_unmask_tx_rx( 5917221167Sgnn vxge_hal_vpath_h vpath_handle); 5918221167Sgnn 5919221167Sgnn/* 5920221167Sgnn * vxge_hal_vpath_alarm_process - Process Alarms. 5921221167Sgnn * @vpath: Virtual Path. 5922221167Sgnn * @skip_alarms: Do not clear the alarms 5923221167Sgnn * 5924221167Sgnn * Process vpath alarms. 5925221167Sgnn * 5926221167Sgnn */ 5927221167Sgnnvxge_hal_status_e 5928221167Sgnnvxge_hal_vpath_alarm_process( 5929221167Sgnn vxge_hal_vpath_h vpath_handle, 5930221167Sgnn u32 skip_alarms); 5931221167Sgnn 5932221167Sgnn/* NEWCODE */ 5933221167Sgnn 5934221167Sgnnvxge_hal_status_e 5935221167Sgnnvxge_hal_vpath_mf_msix_set(vxge_hal_vpath_h vpath_handle, 5936221167Sgnn int *tim_msix_id, int alarm_msix_id); 5937221167Sgnnvoid 5938221167Sgnnvxge_hal_vpath_mf_msix_clear(vxge_hal_vpath_h vpath_handle, int msix_id); 5939221167Sgnnvoid 5940221167Sgnnvxge_hal_vpath_mf_msix_mask(vxge_hal_vpath_h vpath_handle, int msix_id); 5941221167Sgnnvoid 5942221167Sgnnvxge_hal_vpath_mf_msix_unmask(vxge_hal_vpath_h vpath_handle, int msix_id); 5943221167Sgnn 5944221167Sgnn/* NEWCODE */ 5945221167Sgnn 5946221167Sgnn/* 5947221167Sgnn * vxge_hal_vpath_msix_mode - Is MSIX enabled? 5948221167Sgnn * @vpath_handle: Virtual Path handle. 5949221167Sgnn * 5950221167Sgnn * Returns 0 if MSI is enabled for the specified device, 5951221167Sgnn * non-zero otherwise. 5952221167Sgnn */ 5953221167Sgnnu32 5954221167Sgnnvxge_hal_vpath_msix_mode(vxge_hal_vpath_h vpath_handle); 5955221167Sgnn 5956221167Sgnn/* 5957221167Sgnn * vxge_hal_vpath_msix_set - Associate MSIX vectors with TIM interrupts and 5958221167Sgnn * alrms 5959221167Sgnn * @vpath_handle: Virtual Path handle. 5960221167Sgnn * @tim_msix_id: MSIX vectors associated with VXGE_HAL_VPATH_MSIX_MAX number of 5961221167Sgnn * interrupts(Valid numbers 0 to 3). 5962221167Sgnn * @alarm_msix_id: MSIX vector for alarm (Valid numbers 0 to 3). 5963221167Sgnn * 5964221167Sgnn * This API will associate a given MSIX vector numbers with the four TIM 5965221167Sgnn * interrupts and alarm interrupt. 5966221167Sgnn */ 5967221167Sgnnvxge_hal_status_e 5968221167Sgnnvxge_hal_vpath_msix_set(vxge_hal_vpath_h vpath_handle, 5969221167Sgnn int *tim_msix_id, 5970221167Sgnn int alarm_msix_id); 5971221167Sgnn 5972221167Sgnn/* 5973221167Sgnn * vxge_hal_vpath_msix_mask - Mask MSIX Vector. 5974221167Sgnn * @vpath_handle: Virtual Path handle. 5975221167Sgnn * @msix_id: MSIX ID 5976221167Sgnn * 5977221167Sgnn * The function masks the msix interrupt for the given msix_id 5978221167Sgnn * 5979221167Sgnn * Note: 5980221167Sgnn * 5981221167Sgnn * Returns: 0, 5982221167Sgnn * Otherwise, VXGE_HAL_ERR_WRONG_IRQ if the msix index is out of range 5983221167Sgnn * status. 5984221167Sgnn * See also: 5985221167Sgnn */ 5986221167Sgnnvoid 5987221167Sgnnvxge_hal_vpath_msix_mask(vxge_hal_vpath_h vpath_handle, int msix_id); 5988221167Sgnn 5989221167Sgnn/* 5990221167Sgnn * vxge_hal_vpath_msix_clear - Clear MSIX Vector. 5991221167Sgnn * @vpath_handle: Virtual Path handle. 5992221167Sgnn * @msix_id: MSI ID 5993221167Sgnn * 5994221167Sgnn * The function clears the msix interrupt for the given msix_id 5995221167Sgnn * 5996221167Sgnn * Note: 5997221167Sgnn * 5998221167Sgnn * Returns: 0, 5999221167Sgnn * Otherwise, VXGE_HAL_ERR_WRONG_IRQ if the msix index is out of range 6000221167Sgnn * status. 6001221167Sgnn * See also: 6002221167Sgnn */ 6003221167Sgnnvoid 6004221167Sgnnvxge_hal_vpath_msix_clear(vxge_hal_vpath_h vpath_handle, int msix_id); 6005221167Sgnn 6006221167Sgnn/* 6007221167Sgnn * vxge_hal_vpath_msix_unmask - Unmask MSIX Vector. 6008221167Sgnn * @vpath_handle: Virtual Path handle. 6009221167Sgnn * @msix_id: MSI ID 6010221167Sgnn * 6011221167Sgnn * The function unmasks the msix interrupt for the given msix_id 6012221167Sgnn * 6013221167Sgnn * Note: 6014221167Sgnn * 6015221167Sgnn * Returns: 0, 6016221167Sgnn * Otherwise, VXGE_HAL_ERR_WRONG_IRQ if the msix index is out of range 6017221167Sgnn * status. 6018221167Sgnn * See also: 6019221167Sgnn */ 6020221167Sgnnvoid 6021221167Sgnnvxge_hal_vpath_msix_unmask(vxge_hal_vpath_h vpath_handle, int msix_id); 6022221167Sgnn 6023221167Sgnn/* 6024221167Sgnn * vxge_hal_vpath_msix_mask_all - Mask all MSIX vectors for the vpath. 6025221167Sgnn * @vpath_handle: Virtual Path handle. 6026221167Sgnn * 6027221167Sgnn * The function masks the msix interrupt for the given vpath 6028221167Sgnn * 6029221167Sgnn */ 6030221167Sgnnvoid 6031221167Sgnnvxge_hal_vpath_msix_mask_all(vxge_hal_vpath_h vpath_handle); 6032221167Sgnn 6033221167Sgnn/* 6034221167Sgnn * vxge_hal_vpath_msix_unmask_all - Unmask all MSIX vectors for the vpath. 6035221167Sgnn * @vpath_handle: Virtual Path handle. 6036221167Sgnn * 6037221167Sgnn * The function unmasks the msix interrupt for the given vpath 6038221167Sgnn * 6039221167Sgnn */ 6040221167Sgnnvoid 6041221167Sgnnvxge_hal_vpath_msix_unmask_all(vxge_hal_vpath_h vpath_handle); 6042221167Sgnn 6043221167Sgnn/* 6044221167Sgnn * vxge_hal_vpath_is_rxdmem_leak - Check for the rxd memory leak. 6045221167Sgnn * @vpath_handle: Virtual Path handle. 6046221167Sgnn * 6047221167Sgnn * The function checks for the rxd memory leak. 6048221167Sgnn * 6049221167Sgnn */ 6050221167Sgnnu32 6051221167Sgnnvxge_hal_vpath_is_rxdmem_leak(vxge_hal_vpath_h vpath_handle); 6052221167Sgnn 6053221167Sgnn/* 6054221167Sgnn * vxge_hal_rldram_test - offline test for access to the RldRam chip on 6055221167Sgnn * the NIC 6056221167Sgnn * @devh: HAL device handle. 6057221167Sgnn * @data: variable that returns the result of each of the test 6058221167Sgnn * conducted by the driver. 6059221167Sgnn * 6060221167Sgnn * This is one of the offline test that tests the read and write 6061221167Sgnn * access to the RldRam chip on the NIC. 6062221167Sgnn * Return value: 6063221167Sgnn * 0 on success. 6064221167Sgnn */ 6065221167Sgnnvxge_hal_status_e 6066221167Sgnnvxge_hal_rldram_test( 6067221167Sgnn vxge_hal_device_h devh, 6068221167Sgnn u64 *data); 6069221167Sgnn 6070221167Sgnn/* 6071221167Sgnn * vxge_hal_check_alignment - Check buffer alignment and calculate the 6072221167Sgnn * "misaligned" portion. 6073221167Sgnn * @dma_pointer: DMA address of the buffer. 6074221167Sgnn * @size: Buffer size, in bytes. 6075221167Sgnn * @alignment: Alignment "granularity" (see below), in bytes. 6076221167Sgnn * @copy_size: Maximum number of bytes to "extract" from the buffer 6077221167Sgnn * (in order to spost it as a separate scatter-gather entry). See below. 6078221167Sgnn * 6079221167Sgnn * Check buffer alignment and calculate "misaligned" portion, if exists. 6080221167Sgnn * The buffer is considered aligned if its address is multiple of 6081221167Sgnn * the specified @alignment. If this is the case, 6082221167Sgnn * vxge_hal_check_alignment() returns zero. 6083221167Sgnn * Otherwise, vxge_hal_check_alignment() uses the last argument, 6084221167Sgnn * @copy_size, 6085221167Sgnn * to calculate the size to "extract" from the buffer. The @copy_size 6086221167Sgnn * may or may not be equal @alignment. The difference between these two 6087221167Sgnn * arguments is that the @alignment is used to make the decision: aligned 6088221167Sgnn * or not aligned. While the @copy_size is used to calculate the portion 6089221167Sgnn * of the buffer to "extract", i.e. to post as a separate entry in the 6090221167Sgnn * transmit descriptor. For example, the combination 6091221167Sgnn * @alignment=8 and @copy_size=64 will work okay on AMD Opteron boxes. 6092221167Sgnn * 6093221167Sgnn * Note: @copy_size should be a multiple of @alignment. In many practical 6094221167Sgnn * cases @copy_size and @alignment will probably be equal. 6095221167Sgnn * 6096221167Sgnn * See also: vxge_hal_fifo_txdl_buffer_set_aligned(). 6097221167Sgnn */ 6098221167Sgnnu32 6099221167Sgnnvxge_hal_check_alignment( 6100221167Sgnn dma_addr_t dma_pointer, 6101221167Sgnn u32 size, 6102221167Sgnn u32 alignment, 6103221167Sgnn u32 copy_size); 6104221167Sgnn 6105221167Sgnn 6106221167Sgnnvoid 6107221167Sgnnvxge_hw_vpath_set_zero_rx_frm_len(vxge_hal_device_h devh, u32 vp_id); 6108221167Sgnn 6109221167Sgnnvoid 6110221167Sgnnvxge_hw_vpath_wait_receive_idle(vxge_hal_device_h devh, u32 vp_id, 6111221167Sgnn u32 *count, u32 *total_count); 6112221167Sgnn 6113221167Sgnn#define VXGE_HW_MIN_SUCCESSIVE_IDLE_COUNT 5 6114221167Sgnn#define VXGE_HW_MAX_POLLING_COUNT 160 6115221167Sgnn 6116221167Sgnn 6117221167Sgnn__EXTERN_END_DECLS 6118221167Sgnn 6119221167Sgnn#include <dev/vxge/include/vxge-os-debug.h> 6120221167Sgnn 6121221167Sgnn#endif /* VXGE_HAL_LL_H */ 6122