1231437Sluigi/*- 2252869Sdelphij * Copyright (C) 2013 Emulex 3231437Sluigi * All rights reserved. 4231437Sluigi * 5231437Sluigi * Redistribution and use in source and binary forms, with or without 6231437Sluigi * modification, are permitted provided that the following conditions are met: 7231437Sluigi * 8231437Sluigi * 1. Redistributions of source code must retain the above copyright notice, 9231437Sluigi * this list of conditions and the following disclaimer. 10231437Sluigi * 11231437Sluigi * 2. Redistributions in binary form must reproduce the above copyright 12231437Sluigi * notice, this list of conditions and the following disclaimer in the 13231437Sluigi * documentation and/or other materials provided with the distribution. 14231437Sluigi * 15231437Sluigi * 3. Neither the name of the Emulex Corporation nor the names of its 16231437Sluigi * contributors may be used to endorse or promote products derived from 17231437Sluigi * this software without specific prior written permission. 18231437Sluigi * 19231437Sluigi * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20231437Sluigi * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21231437Sluigi * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22231437Sluigi * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23231437Sluigi * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24231437Sluigi * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25231437Sluigi * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26231437Sluigi * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27231437Sluigi * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28231437Sluigi * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29231437Sluigi * POSSIBILITY OF SUCH DAMAGE. 30231437Sluigi * 31231437Sluigi * Contact Information: 32231437Sluigi * freebsd-drivers@emulex.com 33231437Sluigi * 34231437Sluigi * Emulex 35231437Sluigi * 3333 Susan Street 36231437Sluigi * Costa Mesa, CA 92626 37231437Sluigi */ 38231437Sluigi 39231437Sluigi/* $FreeBSD$ */ 40231437Sluigi 41231437Sluigi#include <sys/types.h> 42231437Sluigi 43231437Sluigi#undef _BIG_ENDIAN /* TODO */ 44231437Sluigi#pragma pack(1) 45231437Sluigi 46231437Sluigi#define OC_CNA_GEN2 0x2 47231437Sluigi#define OC_CNA_GEN3 0x3 48231437Sluigi#define DEVID_TIGERSHARK 0x700 49231437Sluigi#define DEVID_TOMCAT 0x710 50231437Sluigi 51231437Sluigi/* PCI CSR offsets */ 52231437Sluigi#define PCICFG_F1_CSR 0x0 /* F1 for NIC */ 53231437Sluigi#define PCICFG_SEMAPHORE 0xbc 54231437Sluigi#define PCICFG_SOFT_RESET 0x5c 55231437Sluigi#define PCICFG_UE_STATUS_HI_MASK 0xac 56231437Sluigi#define PCICFG_UE_STATUS_LO_MASK 0xa8 57231437Sluigi#define PCICFG_ONLINE0 0xb0 58231437Sluigi#define PCICFG_ONLINE1 0xb4 59231437Sluigi#define INTR_EN 0x20000000 60231437Sluigi#define IMAGE_TRANSFER_SIZE (32 * 1024) /* 32K at a time */ 61231437Sluigi 62257187Sdelphij 63257187Sdelphij/********* UE Status and Mask Registers ***/ 64257187Sdelphij#define PCICFG_UE_STATUS_LOW 0xA0 65257187Sdelphij#define PCICFG_UE_STATUS_HIGH 0xA4 66257187Sdelphij#define PCICFG_UE_STATUS_LOW_MASK 0xA8 67257187Sdelphij 68257187Sdelphij/* Lancer SLIPORT registers */ 69257187Sdelphij#define SLIPORT_STATUS_OFFSET 0x404 70257187Sdelphij#define SLIPORT_CONTROL_OFFSET 0x408 71257187Sdelphij#define SLIPORT_ERROR1_OFFSET 0x40C 72257187Sdelphij#define SLIPORT_ERROR2_OFFSET 0x410 73257187Sdelphij#define PHYSDEV_CONTROL_OFFSET 0x414 74257187Sdelphij 75257187Sdelphij#define SLIPORT_STATUS_ERR_MASK 0x80000000 76257187Sdelphij#define SLIPORT_STATUS_DIP_MASK 0x02000000 77257187Sdelphij#define SLIPORT_STATUS_RN_MASK 0x01000000 78257187Sdelphij#define SLIPORT_STATUS_RDY_MASK 0x00800000 79257187Sdelphij#define SLI_PORT_CONTROL_IP_MASK 0x08000000 80257187Sdelphij#define PHYSDEV_CONTROL_FW_RESET_MASK 0x00000002 81257187Sdelphij#define PHYSDEV_CONTROL_DD_MASK 0x00000004 82257187Sdelphij#define PHYSDEV_CONTROL_INP_MASK 0x40000000 83257187Sdelphij 84257187Sdelphij#define SLIPORT_ERROR_NO_RESOURCE1 0x2 85257187Sdelphij#define SLIPORT_ERROR_NO_RESOURCE2 0x9 86231437Sluigi/* CSR register offsets */ 87231437Sluigi#define MPU_EP_CONTROL 0 88231437Sluigi#define MPU_EP_SEMAPHORE_BE3 0xac 89231437Sluigi#define MPU_EP_SEMAPHORE_XE201 0x400 90252869Sdelphij#define MPU_EP_SEMAPHORE_SH 0x94 91231437Sluigi#define PCICFG_INTR_CTRL 0xfc 92231437Sluigi#define HOSTINTR_MASK (1 << 29) 93231437Sluigi#define HOSTINTR_PFUNC_SHIFT 26 94231437Sluigi#define HOSTINTR_PFUNC_MASK 7 95231437Sluigi 96231437Sluigi/* POST status reg struct */ 97231437Sluigi#define POST_STAGE_POWER_ON_RESET 0x00 98231437Sluigi#define POST_STAGE_AWAITING_HOST_RDY 0x01 99231437Sluigi#define POST_STAGE_HOST_RDY 0x02 100231437Sluigi#define POST_STAGE_CHIP_RESET 0x03 101231437Sluigi#define POST_STAGE_ARMFW_READY 0xc000 102231437Sluigi#define POST_STAGE_ARMFW_UE 0xf000 103231437Sluigi 104231437Sluigi/* DOORBELL registers */ 105231437Sluigi#define PD_RXULP_DB 0x0100 106231437Sluigi#define PD_TXULP_DB 0x0060 107231437Sluigi#define DB_RQ_ID_MASK 0x3FF 108231437Sluigi 109231437Sluigi#define PD_CQ_DB 0x0120 110231437Sluigi#define PD_EQ_DB PD_CQ_DB 111231437Sluigi#define PD_MPU_MBOX_DB 0x0160 112231437Sluigi#define PD_MQ_DB 0x0140 113231437Sluigi 114231437Sluigi/* EQE completion types */ 115231437Sluigi#define EQ_MINOR_CODE_COMPLETION 0x00 116231437Sluigi#define EQ_MINOR_CODE_OTHER 0x01 117231437Sluigi#define EQ_MAJOR_CODE_COMPLETION 0x00 118231437Sluigi 119231437Sluigi/* Link Status field values */ 120231437Sluigi#define PHY_LINK_FAULT_NONE 0x0 121231437Sluigi#define PHY_LINK_FAULT_LOCAL 0x01 122231437Sluigi#define PHY_LINK_FAULT_REMOTE 0x02 123231437Sluigi 124231437Sluigi#define PHY_LINK_SPEED_ZERO 0x0 /* No link */ 125231437Sluigi#define PHY_LINK_SPEED_10MBPS 0x1 /* (10 Mbps) */ 126231437Sluigi#define PHY_LINK_SPEED_100MBPS 0x2 /* (100 Mbps) */ 127231437Sluigi#define PHY_LINK_SPEED_1GBPS 0x3 /* (1 Gbps) */ 128231437Sluigi#define PHY_LINK_SPEED_10GBPS 0x4 /* (10 Gbps) */ 129231437Sluigi 130231437Sluigi#define PHY_LINK_DUPLEX_NONE 0x0 131231437Sluigi#define PHY_LINK_DUPLEX_HALF 0x1 132231437Sluigi#define PHY_LINK_DUPLEX_FULL 0x2 133231437Sluigi 134231437Sluigi#define NTWK_PORT_A 0x0 /* (Port A) */ 135231437Sluigi#define NTWK_PORT_B 0x1 /* (Port B) */ 136231437Sluigi 137231437Sluigi#define PHY_LINK_SPEED_ZERO 0x0 /* (No link.) */ 138231437Sluigi#define PHY_LINK_SPEED_10MBPS 0x1 /* (10 Mbps) */ 139231437Sluigi#define PHY_LINK_SPEED_100MBPS 0x2 /* (100 Mbps) */ 140231437Sluigi#define PHY_LINK_SPEED_1GBPS 0x3 /* (1 Gbps) */ 141231437Sluigi#define PHY_LINK_SPEED_10GBPS 0x4 /* (10 Gbps) */ 142231437Sluigi 143231437Sluigi/* Hardware Address types */ 144231437Sluigi#define MAC_ADDRESS_TYPE_STORAGE 0x0 /* (Storage MAC Address) */ 145231437Sluigi#define MAC_ADDRESS_TYPE_NETWORK 0x1 /* (Network MAC Address) */ 146231437Sluigi#define MAC_ADDRESS_TYPE_PD 0x2 /* (Protection Domain MAC Addr) */ 147231437Sluigi#define MAC_ADDRESS_TYPE_MANAGEMENT 0x3 /* (Management MAC Address) */ 148231437Sluigi#define MAC_ADDRESS_TYPE_FCOE 0x4 /* (FCoE MAC Address) */ 149231437Sluigi 150231437Sluigi/* CREATE_IFACE capability and cap_en flags */ 151231437Sluigi#define MBX_RX_IFACE_FLAGS_RSS 0x4 152231437Sluigi#define MBX_RX_IFACE_FLAGS_PROMISCUOUS 0x8 153231437Sluigi#define MBX_RX_IFACE_FLAGS_BROADCAST 0x10 154231437Sluigi#define MBX_RX_IFACE_FLAGS_UNTAGGED 0x20 155231437Sluigi#define MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS 0x80 156231437Sluigi#define MBX_RX_IFACE_FLAGS_VLAN 0x100 157231437Sluigi#define MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS 0x200 158231437Sluigi#define MBX_RX_IFACE_FLAGS_PASS_L2_ERR 0x400 159231437Sluigi#define MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR 0x800 160231437Sluigi#define MBX_RX_IFACE_FLAGS_MULTICAST 0x1000 161231437Sluigi#define MBX_RX_IFACE_RX_FILTER_IF_MULTICAST_HASH 0x2000 162231437Sluigi#define MBX_RX_IFACE_FLAGS_HDS 0x4000 163231437Sluigi#define MBX_RX_IFACE_FLAGS_DIRECTED 0x8000 164231437Sluigi#define MBX_RX_IFACE_FLAGS_VMQ 0x10000 165231437Sluigi#define MBX_RX_IFACE_FLAGS_NETQ 0x20000 166231437Sluigi#define MBX_RX_IFACE_FLAGS_QGROUPS 0x40000 167231437Sluigi#define MBX_RX_IFACE_FLAGS_LSO 0x80000 168231437Sluigi#define MBX_RX_IFACE_FLAGS_LRO 0x100000 169231437Sluigi 170231437Sluigi#define MQ_RING_CONTEXT_SIZE_16 0x5 /* (16 entries) */ 171231437Sluigi#define MQ_RING_CONTEXT_SIZE_32 0x6 /* (32 entries) */ 172231437Sluigi#define MQ_RING_CONTEXT_SIZE_64 0x7 /* (64 entries) */ 173231437Sluigi#define MQ_RING_CONTEXT_SIZE_128 0x8 /* (128 entries) */ 174231437Sluigi 175231437Sluigi#define MBX_DB_READY_BIT 0x1 176231437Sluigi#define MBX_DB_HI_BIT 0x2 177231437Sluigi#define ASYNC_EVENT_CODE_LINK_STATE 0x1 178231437Sluigi#define ASYNC_EVENT_LINK_UP 0x1 179231437Sluigi#define ASYNC_EVENT_LINK_DOWN 0x0 180231879Sluigi#define ASYNC_EVENT_GRP5 0x5 181247880Sdelphij#define ASYNC_EVENT_CODE_DEBUG 0x6 182231879Sluigi#define ASYNC_EVENT_PVID_STATE 0x3 183247880Sdelphij#define ASYNC_EVENT_DEBUG_QNQ 0x1 184247880Sdelphij#define ASYNC_EVENT_CODE_SLIPORT 0x11 185231879Sluigi#define VLAN_VID_MASK 0x0FFF 186231437Sluigi 187231437Sluigi/* port link_status */ 188231437Sluigi#define ASYNC_EVENT_LOGICAL 0x02 189231437Sluigi 190231437Sluigi/* Logical Link Status */ 191231437Sluigi#define NTWK_LOGICAL_LINK_DOWN 0 192231437Sluigi#define NTWK_LOGICAL_LINK_UP 1 193231437Sluigi 194231437Sluigi/* Rx filter bits */ 195231437Sluigi#define NTWK_RX_FILTER_IP_CKSUM 0x1 196231437Sluigi#define NTWK_RX_FILTER_TCP_CKSUM 0x2 197231437Sluigi#define NTWK_RX_FILTER_UDP_CKSUM 0x4 198231437Sluigi#define NTWK_RX_FILTER_STRIP_CRC 0x8 199231437Sluigi 200231437Sluigi/* max SGE per mbx */ 201231437Sluigi#define MAX_MBX_SGE 19 202231437Sluigi 203231437Sluigi/* Max multicast filter size*/ 204231437Sluigi#define OCE_MAX_MC_FILTER_SIZE 64 205231437Sluigi 206231437Sluigi/* PCI SLI (Service Level Interface) capabilities register */ 207231437Sluigi#define OCE_INTF_REG_OFFSET 0x58 208231437Sluigi#define OCE_INTF_VALID_SIG 6 /* register's signature */ 209231437Sluigi#define OCE_INTF_FUNC_RESET_REQD 1 210231437Sluigi#define OCE_INTF_HINT1_NOHINT 0 211231437Sluigi#define OCE_INTF_HINT1_SEMAINIT 1 212231437Sluigi#define OCE_INTF_HINT1_STATCTRL 2 213231437Sluigi#define OCE_INTF_IF_TYPE_0 0 214231437Sluigi#define OCE_INTF_IF_TYPE_1 1 215231437Sluigi#define OCE_INTF_IF_TYPE_2 2 216231437Sluigi#define OCE_INTF_IF_TYPE_3 3 217231437Sluigi#define OCE_INTF_SLI_REV3 3 /* not supported by driver */ 218231437Sluigi#define OCE_INTF_SLI_REV4 4 /* driver supports SLI-4 */ 219231437Sluigi#define OCE_INTF_PHYS_FUNC 0 220231437Sluigi#define OCE_INTF_VIRT_FUNC 1 221231437Sluigi#define OCE_INTF_FAMILY_BE2 0 /* not supported by driver */ 222231437Sluigi#define OCE_INTF_FAMILY_BE3 1 /* driver supports BE3 */ 223231437Sluigi#define OCE_INTF_FAMILY_A0_CHIP 0xA /* Lancer A0 chip (supported) */ 224231437Sluigi#define OCE_INTF_FAMILY_B0_CHIP 0xB /* Lancer B0 chip (future) */ 225231437Sluigi 226231437Sluigi#define NIC_WQE_SIZE 16 227231437Sluigi#define NIC_UNICAST 0x00 228231437Sluigi#define NIC_MULTICAST 0x01 229231437Sluigi#define NIC_BROADCAST 0x02 230231437Sluigi 231231437Sluigi#define NIC_HDS_NO_SPLIT 0x00 232231437Sluigi#define NIC_HDS_SPLIT_L3PL 0x01 233231437Sluigi#define NIC_HDS_SPLIT_L4PL 0x02 234231437Sluigi 235231437Sluigi#define NIC_WQ_TYPE_FORWARDING 0x01 236231437Sluigi#define NIC_WQ_TYPE_STANDARD 0x02 237231437Sluigi#define NIC_WQ_TYPE_LOW_LATENCY 0x04 238231437Sluigi 239231437Sluigi#define OCE_RESET_STATS 1 240231437Sluigi#define OCE_RETAIN_STATS 0 241231437Sluigi#define OCE_TXP_SW_SZ 48 242231437Sluigi 243231437Sluigitypedef union pci_sli_intf_u { 244231437Sluigi uint32_t dw0; 245231437Sluigi struct { 246231437Sluigi#ifdef _BIG_ENDIAN 247231437Sluigi uint32_t sli_valid:3; 248231437Sluigi uint32_t sli_hint2:5; 249231437Sluigi uint32_t sli_hint1:8; 250231437Sluigi uint32_t sli_if_type:4; 251231437Sluigi uint32_t sli_family:4; 252231437Sluigi uint32_t sli_rev:4; 253231437Sluigi uint32_t rsv0:3; 254231437Sluigi uint32_t sli_func_type:1; 255231437Sluigi#else 256231437Sluigi uint32_t sli_func_type:1; 257231437Sluigi uint32_t rsv0:3; 258231437Sluigi uint32_t sli_rev:4; 259231437Sluigi uint32_t sli_family:4; 260231437Sluigi uint32_t sli_if_type:4; 261231437Sluigi uint32_t sli_hint1:8; 262231437Sluigi uint32_t sli_hint2:5; 263231437Sluigi uint32_t sli_valid:3; 264231437Sluigi#endif 265231437Sluigi } bits; 266231437Sluigi} pci_sli_intf_t; 267231437Sluigi 268231437Sluigi 269231437Sluigi 270231437Sluigi/* physical address structure to be used in MBX */ 271231437Sluigistruct phys_addr { 272231437Sluigi /* dw0 */ 273231437Sluigi uint32_t lo; 274231437Sluigi /* dw1 */ 275231437Sluigi uint32_t hi; 276231437Sluigi}; 277231437Sluigi 278231437Sluigi 279231437Sluigi 280231437Sluigitypedef union pcicfg_intr_ctl_u { 281231437Sluigi uint32_t dw0; 282231437Sluigi struct { 283231437Sluigi#ifdef _BIG_ENDIAN 284231437Sluigi uint32_t winselect:2; 285231437Sluigi uint32_t hostintr:1; 286231437Sluigi uint32_t pfnum:3; 287231437Sluigi uint32_t vf_cev_int_line_en:1; 288231437Sluigi uint32_t winaddr:23; 289231437Sluigi uint32_t membarwinen:1; 290231437Sluigi#else 291231437Sluigi uint32_t membarwinen:1; 292231437Sluigi uint32_t winaddr:23; 293231437Sluigi uint32_t vf_cev_int_line_en:1; 294231437Sluigi uint32_t pfnum:3; 295231437Sluigi uint32_t hostintr:1; 296231437Sluigi uint32_t winselect:2; 297231437Sluigi#endif 298231437Sluigi } bits; 299231437Sluigi} pcicfg_intr_ctl_t; 300231437Sluigi 301231437Sluigi 302231437Sluigi 303231437Sluigi 304231437Sluigitypedef union pcicfg_semaphore_u { 305231437Sluigi uint32_t dw0; 306231437Sluigi struct { 307231437Sluigi#ifdef _BIG_ENDIAN 308231437Sluigi uint32_t rsvd:31; 309231437Sluigi uint32_t lock:1; 310231437Sluigi#else 311231437Sluigi uint32_t lock:1; 312231437Sluigi uint32_t rsvd:31; 313231437Sluigi#endif 314231437Sluigi } bits; 315231437Sluigi} pcicfg_semaphore_t; 316231437Sluigi 317231437Sluigi 318231437Sluigi 319231437Sluigi 320231437Sluigitypedef union pcicfg_soft_reset_u { 321231437Sluigi uint32_t dw0; 322231437Sluigi struct { 323231437Sluigi#ifdef _BIG_ENDIAN 324231437Sluigi uint32_t nec_ll_rcvdetect:8; 325231437Sluigi uint32_t dbg_all_reqs_62_49:14; 326231437Sluigi uint32_t scratchpad0:1; 327231437Sluigi uint32_t exception_oe:1; 328231437Sluigi uint32_t soft_reset:1; 329231437Sluigi uint32_t rsvd0:7; 330231437Sluigi#else 331231437Sluigi uint32_t rsvd0:7; 332231437Sluigi uint32_t soft_reset:1; 333231437Sluigi uint32_t exception_oe:1; 334231437Sluigi uint32_t scratchpad0:1; 335231437Sluigi uint32_t dbg_all_reqs_62_49:14; 336231437Sluigi uint32_t nec_ll_rcvdetect:8; 337231437Sluigi#endif 338231437Sluigi } bits; 339231437Sluigi} pcicfg_soft_reset_t; 340231437Sluigi 341231437Sluigi 342231437Sluigi 343231437Sluigi 344231437Sluigitypedef union pcicfg_online1_u { 345231437Sluigi uint32_t dw0; 346231437Sluigi struct { 347231437Sluigi#ifdef _BIG_ENDIAN 348231437Sluigi uint32_t host8_online:1; 349231437Sluigi uint32_t host7_online:1; 350231437Sluigi uint32_t host6_online:1; 351231437Sluigi uint32_t host5_online:1; 352231437Sluigi uint32_t host4_online:1; 353231437Sluigi uint32_t host3_online:1; 354231437Sluigi uint32_t host2_online:1; 355231437Sluigi uint32_t ipc_online:1; 356231437Sluigi uint32_t arm_online:1; 357231437Sluigi uint32_t txp_online:1; 358231437Sluigi uint32_t xaui_online:1; 359231437Sluigi uint32_t rxpp_online:1; 360231437Sluigi uint32_t txpb_online:1; 361231437Sluigi uint32_t rr_online:1; 362231437Sluigi uint32_t pmem_online:1; 363231437Sluigi uint32_t pctl1_online:1; 364231437Sluigi uint32_t pctl0_online:1; 365231437Sluigi uint32_t pcs1online_online:1; 366231437Sluigi uint32_t mpu_iram_online:1; 367231437Sluigi uint32_t pcs0online_online:1; 368231437Sluigi uint32_t mgmt_mac_online:1; 369231437Sluigi uint32_t lpcmemhost_online:1; 370231437Sluigi#else 371231437Sluigi uint32_t lpcmemhost_online:1; 372231437Sluigi uint32_t mgmt_mac_online:1; 373231437Sluigi uint32_t pcs0online_online:1; 374231437Sluigi uint32_t mpu_iram_online:1; 375231437Sluigi uint32_t pcs1online_online:1; 376231437Sluigi uint32_t pctl0_online:1; 377231437Sluigi uint32_t pctl1_online:1; 378231437Sluigi uint32_t pmem_online:1; 379231437Sluigi uint32_t rr_online:1; 380231437Sluigi uint32_t txpb_online:1; 381231437Sluigi uint32_t rxpp_online:1; 382231437Sluigi uint32_t xaui_online:1; 383231437Sluigi uint32_t txp_online:1; 384231437Sluigi uint32_t arm_online:1; 385231437Sluigi uint32_t ipc_online:1; 386231437Sluigi uint32_t host2_online:1; 387231437Sluigi uint32_t host3_online:1; 388231437Sluigi uint32_t host4_online:1; 389231437Sluigi uint32_t host5_online:1; 390231437Sluigi uint32_t host6_online:1; 391231437Sluigi uint32_t host7_online:1; 392231437Sluigi uint32_t host8_online:1; 393231437Sluigi#endif 394231437Sluigi } bits; 395231437Sluigi} pcicfg_online1_t; 396231437Sluigi 397231437Sluigi 398231437Sluigi 399231437Sluigitypedef union mpu_ep_semaphore_u { 400231437Sluigi uint32_t dw0; 401231437Sluigi struct { 402231437Sluigi#ifdef _BIG_ENDIAN 403231437Sluigi uint32_t error:1; 404231437Sluigi uint32_t backup_fw:1; 405231437Sluigi uint32_t iscsi_no_ip:1; 406231437Sluigi uint32_t iscsi_ip_conflict:1; 407231437Sluigi uint32_t option_rom_installed:1; 408231437Sluigi uint32_t iscsi_drv_loaded:1; 409231437Sluigi uint32_t rsvd0:10; 410231437Sluigi uint32_t stage:16; 411231437Sluigi#else 412231437Sluigi uint32_t stage:16; 413231437Sluigi uint32_t rsvd0:10; 414231437Sluigi uint32_t iscsi_drv_loaded:1; 415231437Sluigi uint32_t option_rom_installed:1; 416231437Sluigi uint32_t iscsi_ip_conflict:1; 417231437Sluigi uint32_t iscsi_no_ip:1; 418231437Sluigi uint32_t backup_fw:1; 419231437Sluigi uint32_t error:1; 420231437Sluigi#endif 421231437Sluigi } bits; 422231437Sluigi} mpu_ep_semaphore_t; 423231437Sluigi 424231437Sluigi 425231437Sluigi 426231437Sluigi 427231437Sluigitypedef union mpu_ep_control_u { 428231437Sluigi uint32_t dw0; 429231437Sluigi struct { 430231437Sluigi#ifdef _BIG_ENDIAN 431231437Sluigi uint32_t cpu_reset:1; 432231437Sluigi uint32_t rsvd1:15; 433231437Sluigi uint32_t ep_ram_init_status:1; 434231437Sluigi uint32_t rsvd0:12; 435231437Sluigi uint32_t m2_rxpbuf:1; 436231437Sluigi uint32_t m1_rxpbuf:1; 437231437Sluigi uint32_t m0_rxpbuf:1; 438231437Sluigi#else 439231437Sluigi uint32_t m0_rxpbuf:1; 440231437Sluigi uint32_t m1_rxpbuf:1; 441231437Sluigi uint32_t m2_rxpbuf:1; 442231437Sluigi uint32_t rsvd0:12; 443231437Sluigi uint32_t ep_ram_init_status:1; 444231437Sluigi uint32_t rsvd1:15; 445231437Sluigi uint32_t cpu_reset:1; 446231437Sluigi#endif 447231437Sluigi } bits; 448231437Sluigi} mpu_ep_control_t; 449231437Sluigi 450231437Sluigi 451231437Sluigi 452231437Sluigi 453231437Sluigi/* RX doorbell */ 454231437Sluigitypedef union pd_rxulp_db_u { 455231437Sluigi uint32_t dw0; 456231437Sluigi struct { 457231437Sluigi#ifdef _BIG_ENDIAN 458231437Sluigi uint32_t num_posted:8; 459231437Sluigi uint32_t invalidate:1; 460231437Sluigi uint32_t rsvd1:13; 461231437Sluigi uint32_t qid:10; 462231437Sluigi#else 463231437Sluigi uint32_t qid:10; 464231437Sluigi uint32_t rsvd1:13; 465231437Sluigi uint32_t invalidate:1; 466231437Sluigi uint32_t num_posted:8; 467231437Sluigi#endif 468231437Sluigi } bits; 469231437Sluigi} pd_rxulp_db_t; 470231437Sluigi 471231437Sluigi 472231437Sluigi/* TX doorbell */ 473231437Sluigitypedef union pd_txulp_db_u { 474231437Sluigi uint32_t dw0; 475231437Sluigi struct { 476231437Sluigi#ifdef _BIG_ENDIAN 477231437Sluigi uint32_t rsvd1:2; 478231437Sluigi uint32_t num_posted:14; 479231437Sluigi uint32_t rsvd0:6; 480231437Sluigi uint32_t qid:10; 481231437Sluigi#else 482231437Sluigi uint32_t qid:10; 483231437Sluigi uint32_t rsvd0:6; 484231437Sluigi uint32_t num_posted:14; 485231437Sluigi uint32_t rsvd1:2; 486231437Sluigi#endif 487231437Sluigi } bits; 488231437Sluigi} pd_txulp_db_t; 489231437Sluigi 490231437Sluigi/* CQ doorbell */ 491231437Sluigitypedef union cq_db_u { 492231437Sluigi uint32_t dw0; 493231437Sluigi struct { 494231437Sluigi#ifdef _BIG_ENDIAN 495231437Sluigi uint32_t rsvd1:2; 496231437Sluigi uint32_t rearm:1; 497231437Sluigi uint32_t num_popped:13; 498231437Sluigi uint32_t rsvd0:5; 499231437Sluigi uint32_t event:1; 500231437Sluigi uint32_t qid:10; 501231437Sluigi#else 502231437Sluigi uint32_t qid:10; 503231437Sluigi uint32_t event:1; 504231437Sluigi uint32_t rsvd0:5; 505231437Sluigi uint32_t num_popped:13; 506231437Sluigi uint32_t rearm:1; 507231437Sluigi uint32_t rsvd1:2; 508231437Sluigi#endif 509231437Sluigi } bits; 510231437Sluigi} cq_db_t; 511231437Sluigi 512231437Sluigi/* EQ doorbell */ 513231437Sluigitypedef union eq_db_u { 514231437Sluigi uint32_t dw0; 515231437Sluigi struct { 516231437Sluigi#ifdef _BIG_ENDIAN 517231437Sluigi uint32_t rsvd1:2; 518231437Sluigi uint32_t rearm:1; 519231437Sluigi uint32_t num_popped:13; 520231437Sluigi uint32_t rsvd0:5; 521231437Sluigi uint32_t event:1; 522231437Sluigi uint32_t clrint:1; 523231437Sluigi uint32_t qid:9; 524231437Sluigi#else 525231437Sluigi uint32_t qid:9; 526231437Sluigi uint32_t clrint:1; 527231437Sluigi uint32_t event:1; 528231437Sluigi uint32_t rsvd0:5; 529231437Sluigi uint32_t num_popped:13; 530231437Sluigi uint32_t rearm:1; 531231437Sluigi uint32_t rsvd1:2; 532231437Sluigi#endif 533231437Sluigi } bits; 534231437Sluigi} eq_db_t; 535231437Sluigi 536231437Sluigi/* bootstrap mbox doorbell */ 537231437Sluigitypedef union pd_mpu_mbox_db_u { 538231437Sluigi uint32_t dw0; 539231437Sluigi struct { 540231437Sluigi#ifdef _BIG_ENDIAN 541231437Sluigi uint32_t address:30; 542231437Sluigi uint32_t hi:1; 543231437Sluigi uint32_t ready:1; 544231437Sluigi#else 545231437Sluigi uint32_t ready:1; 546231437Sluigi uint32_t hi:1; 547231437Sluigi uint32_t address:30; 548231437Sluigi#endif 549231437Sluigi } bits; 550231437Sluigi} pd_mpu_mbox_db_t; 551231437Sluigi 552231437Sluigi/* MQ ring doorbell */ 553231437Sluigitypedef union pd_mq_db_u { 554231437Sluigi uint32_t dw0; 555231437Sluigi struct { 556231437Sluigi#ifdef _BIG_ENDIAN 557231437Sluigi uint32_t rsvd1:2; 558231437Sluigi uint32_t num_posted:14; 559231437Sluigi uint32_t rsvd0:5; 560231437Sluigi uint32_t mq_id:11; 561231437Sluigi#else 562231437Sluigi uint32_t mq_id:11; 563231437Sluigi uint32_t rsvd0:5; 564231437Sluigi uint32_t num_posted:14; 565231437Sluigi uint32_t rsvd1:2; 566231437Sluigi#endif 567231437Sluigi } bits; 568231437Sluigi} pd_mq_db_t; 569231437Sluigi 570231437Sluigi/* 571231437Sluigi * Event Queue Entry 572231437Sluigi */ 573231437Sluigistruct oce_eqe { 574231437Sluigi uint32_t evnt; 575231437Sluigi}; 576231437Sluigi 577231437Sluigi/* MQ scatter gather entry. Array of these make an SGL */ 578231437Sluigistruct oce_mq_sge { 579231437Sluigi uint32_t pa_lo; 580231437Sluigi uint32_t pa_hi; 581231437Sluigi uint32_t length; 582231437Sluigi}; 583231437Sluigi 584231437Sluigi/* 585231437Sluigi * payload can contain an SGL or an embedded array of upto 59 dwords 586231437Sluigi */ 587231437Sluigistruct oce_mbx_payload { 588231437Sluigi union { 589231437Sluigi union { 590231437Sluigi struct oce_mq_sge sgl[MAX_MBX_SGE]; 591231437Sluigi uint32_t embedded[59]; 592231437Sluigi } u1; 593231437Sluigi uint32_t dw[59]; 594231437Sluigi } u0; 595231437Sluigi}; 596231437Sluigi 597231437Sluigi/* 598231437Sluigi * MQ MBX structure 599231437Sluigi */ 600231437Sluigistruct oce_mbx { 601231437Sluigi union { 602231437Sluigi struct { 603231437Sluigi#ifdef _BIG_ENDIAN 604231437Sluigi uint32_t special:8; 605231437Sluigi uint32_t rsvd1:16; 606231437Sluigi uint32_t sge_count:5; 607231437Sluigi uint32_t rsvd0:2; 608231437Sluigi uint32_t embedded:1; 609231437Sluigi#else 610231437Sluigi uint32_t embedded:1; 611231437Sluigi uint32_t rsvd0:2; 612231437Sluigi uint32_t sge_count:5; 613231437Sluigi uint32_t rsvd1:16; 614231437Sluigi uint32_t special:8; 615231437Sluigi#endif 616231437Sluigi } s; 617231437Sluigi uint32_t dw0; 618231437Sluigi } u0; 619231437Sluigi 620231437Sluigi uint32_t payload_length; 621231437Sluigi uint32_t tag[2]; 622231437Sluigi uint32_t rsvd2[1]; 623231437Sluigi struct oce_mbx_payload payload; 624231437Sluigi}; 625231437Sluigi 626231437Sluigi/* completion queue entry for MQ */ 627231437Sluigistruct oce_mq_cqe { 628231437Sluigi union { 629231437Sluigi struct { 630231437Sluigi#ifdef _BIG_ENDIAN 631231437Sluigi /* dw0 */ 632231437Sluigi uint32_t extended_status:16; 633231437Sluigi uint32_t completion_status:16; 634231437Sluigi /* dw1 dw2 */ 635231437Sluigi uint32_t mq_tag[2]; 636231437Sluigi /* dw3 */ 637231437Sluigi uint32_t valid:1; 638231437Sluigi uint32_t async_event:1; 639231437Sluigi uint32_t hpi_buffer_cmpl:1; 640231437Sluigi uint32_t completed:1; 641231437Sluigi uint32_t consumed:1; 642231879Sluigi uint32_t rsvd0:3; 643231879Sluigi uint32_t async_type:8; 644231879Sluigi uint32_t event_type:8; 645231879Sluigi uint32_t rsvd1:8; 646231437Sluigi#else 647231437Sluigi /* dw0 */ 648231437Sluigi uint32_t completion_status:16; 649231437Sluigi uint32_t extended_status:16; 650231437Sluigi /* dw1 dw2 */ 651231437Sluigi uint32_t mq_tag[2]; 652231437Sluigi /* dw3 */ 653231879Sluigi uint32_t rsvd1:8; 654231879Sluigi uint32_t event_type:8; 655231879Sluigi uint32_t async_type:8; 656231879Sluigi uint32_t rsvd0:3; 657231437Sluigi uint32_t consumed:1; 658231437Sluigi uint32_t completed:1; 659231437Sluigi uint32_t hpi_buffer_cmpl:1; 660231437Sluigi uint32_t async_event:1; 661231437Sluigi uint32_t valid:1; 662231437Sluigi#endif 663231437Sluigi } s; 664231437Sluigi uint32_t dw[4]; 665231437Sluigi } u0; 666231437Sluigi}; 667231437Sluigi 668231437Sluigi/* Mailbox Completion Status Codes */ 669231437Sluigienum MBX_COMPLETION_STATUS { 670231437Sluigi MBX_CQE_STATUS_SUCCESS = 0x00, 671231437Sluigi MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES = 0x01, 672231437Sluigi MBX_CQE_STATUS_INVALID_PARAMETER = 0x02, 673231437Sluigi MBX_CQE_STATUS_INSUFFICIENT_RESOURCES = 0x03, 674231437Sluigi MBX_CQE_STATUS_QUEUE_FLUSHING = 0x04, 675231437Sluigi MBX_CQE_STATUS_DMA_FAILED = 0x05 676231437Sluigi}; 677231437Sluigi 678231437Sluigistruct oce_async_cqe_link_state { 679231437Sluigi union { 680231437Sluigi struct { 681231437Sluigi#ifdef _BIG_ENDIAN 682231437Sluigi /* dw0 */ 683231437Sluigi uint8_t speed; 684231437Sluigi uint8_t duplex; 685231437Sluigi uint8_t link_status; 686231437Sluigi uint8_t phy_port; 687231437Sluigi /* dw1 */ 688231437Sluigi uint16_t qos_link_speed; 689231437Sluigi uint8_t rsvd0; 690231437Sluigi uint8_t fault; 691231437Sluigi /* dw2 */ 692231437Sluigi uint32_t event_tag; 693231437Sluigi /* dw3 */ 694231437Sluigi uint32_t valid:1; 695231437Sluigi uint32_t async_event:1; 696231437Sluigi uint32_t rsvd2:6; 697231437Sluigi uint32_t event_type:8; 698231437Sluigi uint32_t event_code:8; 699231437Sluigi uint32_t rsvd1:8; 700231437Sluigi#else 701231437Sluigi /* dw0 */ 702231437Sluigi uint8_t phy_port; 703231437Sluigi uint8_t link_status; 704231437Sluigi uint8_t duplex; 705231437Sluigi uint8_t speed; 706231437Sluigi /* dw1 */ 707231437Sluigi uint8_t fault; 708231437Sluigi uint8_t rsvd0; 709231437Sluigi uint16_t qos_link_speed; 710231437Sluigi /* dw2 */ 711231437Sluigi uint32_t event_tag; 712231437Sluigi /* dw3 */ 713231437Sluigi uint32_t rsvd1:8; 714231437Sluigi uint32_t event_code:8; 715231437Sluigi uint32_t event_type:8; 716231437Sluigi uint32_t rsvd2:6; 717231437Sluigi uint32_t async_event:1; 718231437Sluigi uint32_t valid:1; 719231437Sluigi#endif 720231437Sluigi } s; 721231437Sluigi uint32_t dw[4]; 722231437Sluigi } u0; 723231437Sluigi}; 724231437Sluigi 725231879Sluigi 726231879Sluigi/* PVID aync event */ 727231879Sluigistruct oce_async_event_grp5_pvid_state { 728231879Sluigi uint8_t enabled; 729231879Sluigi uint8_t rsvd0; 730231879Sluigi uint16_t tag; 731231879Sluigi uint32_t event_tag; 732231879Sluigi uint32_t rsvd1; 733231879Sluigi uint32_t code; 734231879Sluigi}; 735231879Sluigi 736247880Sdelphij/* async event indicating outer VLAN tag in QnQ */ 737247880Sdelphijstruct oce_async_event_qnq { 738247880Sdelphij uint8_t valid; /* Indicates if outer VLAN is valid */ 739247880Sdelphij uint8_t rsvd0; 740247880Sdelphij uint16_t vlan_tag; 741247880Sdelphij uint32_t event_tag; 742247880Sdelphij uint8_t rsvd1[4]; 743247880Sdelphij uint32_t code; 744247880Sdelphij} ; 745247880Sdelphij 746247880Sdelphij 747231879Sluigitypedef union oce_mq_ext_ctx_u { 748231879Sluigi uint32_t dw[6]; 749231879Sluigi struct { 750231879Sluigi #ifdef _BIG_ENDIAN 751231879Sluigi /* dw0 */ 752231879Sluigi uint32_t dw4rsvd1:16; 753231879Sluigi uint32_t num_pages:16; 754231879Sluigi /* dw1 */ 755231879Sluigi uint32_t async_evt_bitmap; 756231879Sluigi /* dw2 */ 757231879Sluigi uint32_t cq_id:10; 758231879Sluigi uint32_t dw5rsvd2:2; 759231879Sluigi uint32_t ring_size:4; 760231879Sluigi uint32_t dw5rsvd1:16; 761231879Sluigi /* dw3 */ 762231879Sluigi uint32_t valid:1; 763231879Sluigi uint32_t dw6rsvd1:31; 764231879Sluigi /* dw4 */ 765231879Sluigi uint32_t dw7rsvd1:21; 766231879Sluigi uint32_t async_cq_id:10; 767231879Sluigi uint32_t async_cq_valid:1; 768231879Sluigi #else 769231879Sluigi /* dw0 */ 770231879Sluigi uint32_t num_pages:16; 771231879Sluigi uint32_t dw4rsvd1:16; 772231879Sluigi /* dw1 */ 773231879Sluigi uint32_t async_evt_bitmap; 774231879Sluigi /* dw2 */ 775231879Sluigi uint32_t dw5rsvd1:16; 776231879Sluigi uint32_t ring_size:4; 777231879Sluigi uint32_t dw5rsvd2:2; 778231879Sluigi uint32_t cq_id:10; 779231879Sluigi /* dw3 */ 780231879Sluigi uint32_t dw6rsvd1:31; 781231879Sluigi uint32_t valid:1; 782231879Sluigi /* dw4 */ 783231879Sluigi uint32_t async_cq_valid:1; 784231879Sluigi uint32_t async_cq_id:10; 785231879Sluigi uint32_t dw7rsvd1:21; 786231879Sluigi #endif 787231879Sluigi /* dw5 */ 788231879Sluigi uint32_t dw8rsvd1; 789231879Sluigi } v0; 790247880Sdelphij struct { 791247880Sdelphij #ifdef _BIG_ENDIAN 792247880Sdelphij /* dw0 */ 793247880Sdelphij uint32_t cq_id:16; 794247880Sdelphij uint32_t num_pages:16; 795247880Sdelphij /* dw1 */ 796247880Sdelphij uint32_t async_evt_bitmap; 797247880Sdelphij /* dw2 */ 798247880Sdelphij uint32_t dw5rsvd2:12; 799247880Sdelphij uint32_t ring_size:4; 800247880Sdelphij uint32_t async_cq_id:16; 801247880Sdelphij /* dw3 */ 802247880Sdelphij uint32_t valid:1; 803247880Sdelphij uint32_t dw6rsvd1:31; 804247880Sdelphij /* dw4 */ 805247880Sdelphij uint32_t dw7rsvd1:31; 806247880Sdelphij uint32_t async_cq_valid:1; 807247880Sdelphij #else 808247880Sdelphij /* dw0 */ 809247880Sdelphij uint32_t num_pages:16; 810247880Sdelphij uint32_t cq_id:16; 811247880Sdelphij /* dw1 */ 812247880Sdelphij uint32_t async_evt_bitmap; 813247880Sdelphij /* dw2 */ 814247880Sdelphij uint32_t async_cq_id:16; 815247880Sdelphij uint32_t ring_size:4; 816247880Sdelphij uint32_t dw5rsvd2:12; 817247880Sdelphij /* dw3 */ 818247880Sdelphij uint32_t dw6rsvd1:31; 819247880Sdelphij uint32_t valid:1; 820247880Sdelphij /* dw4 */ 821247880Sdelphij uint32_t async_cq_valid:1; 822247880Sdelphij uint32_t dw7rsvd1:31; 823247880Sdelphij #endif 824247880Sdelphij /* dw5 */ 825247880Sdelphij uint32_t dw8rsvd1; 826247880Sdelphij } v1; 827247880Sdelphij 828231879Sluigi} oce_mq_ext_ctx_t; 829231879Sluigi 830231879Sluigi 831231437Sluigi/* MQ mailbox structure */ 832231437Sluigistruct oce_bmbx { 833231437Sluigi struct oce_mbx mbx; 834231437Sluigi struct oce_mq_cqe cqe; 835231437Sluigi}; 836231437Sluigi 837231437Sluigi/* ---[ MBXs start here ]---------------------------------------------- */ 838231437Sluigi/* MBXs sub system codes */ 839231437Sluigienum MBX_SUBSYSTEM_CODES { 840231437Sluigi MBX_SUBSYSTEM_RSVD = 0, 841231437Sluigi MBX_SUBSYSTEM_COMMON = 1, 842231437Sluigi MBX_SUBSYSTEM_COMMON_ISCSI = 2, 843231437Sluigi MBX_SUBSYSTEM_NIC = 3, 844231437Sluigi MBX_SUBSYSTEM_TOE = 4, 845231437Sluigi MBX_SUBSYSTEM_PXE_UNDI = 5, 846231437Sluigi MBX_SUBSYSTEM_ISCSI_INI = 6, 847231437Sluigi MBX_SUBSYSTEM_ISCSI_TGT = 7, 848231437Sluigi MBX_SUBSYSTEM_MILI_PTL = 8, 849231437Sluigi MBX_SUBSYSTEM_MILI_TMD = 9, 850231437Sluigi MBX_SUBSYSTEM_RDMA = 10, 851231437Sluigi MBX_SUBSYSTEM_LOWLEVEL = 11, 852231437Sluigi MBX_SUBSYSTEM_LRO = 13, 853231437Sluigi IOCBMBX_SUBSYSTEM_DCBX = 15, 854231437Sluigi IOCBMBX_SUBSYSTEM_DIAG = 16, 855231437Sluigi IOCBMBX_SUBSYSTEM_VENDOR = 17 856231437Sluigi}; 857231437Sluigi 858231437Sluigi/* common ioctl opcodes */ 859231437Sluigienum COMMON_SUBSYSTEM_OPCODES { 860231437Sluigi/* These opcodes are common to both networking and storage PCI functions 861231437Sluigi * They are used to reserve resources and configure CNA. These opcodes 862231437Sluigi * all use the MBX_SUBSYSTEM_COMMON subsystem code. 863231437Sluigi */ 864231437Sluigi OPCODE_COMMON_QUERY_IFACE_MAC = 1, 865231437Sluigi OPCODE_COMMON_SET_IFACE_MAC = 2, 866231437Sluigi OPCODE_COMMON_SET_IFACE_MULTICAST = 3, 867231437Sluigi OPCODE_COMMON_CONFIG_IFACE_VLAN = 4, 868231437Sluigi OPCODE_COMMON_QUERY_LINK_CONFIG = 5, 869231437Sluigi OPCODE_COMMON_READ_FLASHROM = 6, 870231437Sluigi OPCODE_COMMON_WRITE_FLASHROM = 7, 871231437Sluigi OPCODE_COMMON_QUERY_MAX_MBX_BUFFER_SIZE = 8, 872231437Sluigi OPCODE_COMMON_CREATE_CQ = 12, 873231437Sluigi OPCODE_COMMON_CREATE_EQ = 13, 874231437Sluigi OPCODE_COMMON_CREATE_MQ = 21, 875231437Sluigi OPCODE_COMMON_GET_QOS = 27, 876231437Sluigi OPCODE_COMMON_SET_QOS = 28, 877231437Sluigi OPCODE_COMMON_READ_EPROM = 30, 878231437Sluigi OPCODE_COMMON_GET_CNTL_ATTRIBUTES = 32, 879231437Sluigi OPCODE_COMMON_NOP = 33, 880231437Sluigi OPCODE_COMMON_SET_IFACE_RX_FILTER = 34, 881231437Sluigi OPCODE_COMMON_GET_FW_VERSION = 35, 882231437Sluigi OPCODE_COMMON_SET_FLOW_CONTROL = 36, 883231437Sluigi OPCODE_COMMON_GET_FLOW_CONTROL = 37, 884231437Sluigi OPCODE_COMMON_SET_FRAME_SIZE = 39, 885231437Sluigi OPCODE_COMMON_MODIFY_EQ_DELAY = 41, 886231437Sluigi OPCODE_COMMON_CREATE_IFACE = 50, 887231437Sluigi OPCODE_COMMON_DESTROY_IFACE = 51, 888231437Sluigi OPCODE_COMMON_MODIFY_MSI_MESSAGES = 52, 889231437Sluigi OPCODE_COMMON_DESTROY_MQ = 53, 890231437Sluigi OPCODE_COMMON_DESTROY_CQ = 54, 891231437Sluigi OPCODE_COMMON_DESTROY_EQ = 55, 892231437Sluigi OPCODE_COMMON_UPLOAD_TCP = 56, 893231437Sluigi OPCODE_COMMON_SET_NTWK_LINK_SPEED = 57, 894231437Sluigi OPCODE_COMMON_QUERY_FIRMWARE_CONFIG = 58, 895231437Sluigi OPCODE_COMMON_ADD_IFACE_MAC = 59, 896231437Sluigi OPCODE_COMMON_DEL_IFACE_MAC = 60, 897231437Sluigi OPCODE_COMMON_FUNCTION_RESET = 61, 898231437Sluigi OPCODE_COMMON_SET_PHYSICAL_LINK_CONFIG = 62, 899231437Sluigi OPCODE_COMMON_GET_BOOT_CONFIG = 66, 900231437Sluigi OPCPDE_COMMON_SET_BOOT_CONFIG = 67, 901231437Sluigi OPCODE_COMMON_SET_BEACON_CONFIG = 69, 902231437Sluigi OPCODE_COMMON_GET_BEACON_CONFIG = 70, 903231437Sluigi OPCODE_COMMON_GET_PHYSICAL_LINK_CONFIG = 71, 904247880Sdelphij OPCODE_COMMON_READ_TRANSRECEIVER_DATA = 73, 905231437Sluigi OPCODE_COMMON_GET_OEM_ATTRIBUTES = 76, 906231437Sluigi OPCODE_COMMON_GET_PORT_NAME = 77, 907231437Sluigi OPCODE_COMMON_GET_CONFIG_SIGNATURE = 78, 908231437Sluigi OPCODE_COMMON_SET_CONFIG_SIGNATURE = 79, 909231437Sluigi OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG = 80, 910231437Sluigi OPCODE_COMMON_GET_BE_CONFIGURATION_RESOURCES = 81, 911231437Sluigi OPCODE_COMMON_SET_BE_CONFIGURATION_RESOURCES = 82, 912231437Sluigi OPCODE_COMMON_GET_RESET_NEEDED = 84, 913231437Sluigi OPCODE_COMMON_GET_SERIAL_NUMBER = 85, 914231437Sluigi OPCODE_COMMON_GET_NCSI_CONFIG = 86, 915231437Sluigi OPCODE_COMMON_SET_NCSI_CONFIG = 87, 916231437Sluigi OPCODE_COMMON_CREATE_MQ_EXT = 90, 917231437Sluigi OPCODE_COMMON_SET_FUNCTION_PRIVILEGES = 100, 918231437Sluigi OPCODE_COMMON_SET_VF_PORT_TYPE = 101, 919231437Sluigi OPCODE_COMMON_GET_PHY_CONFIG = 102, 920231437Sluigi OPCODE_COMMON_SET_FUNCTIONAL_CAPS = 103, 921231437Sluigi OPCODE_COMMON_GET_ADAPTER_ID = 110, 922231437Sluigi OPCODE_COMMON_GET_UPGRADE_FEATURES = 111, 923231437Sluigi OPCODE_COMMON_GET_INSTALLED_FEATURES = 112, 924231437Sluigi OPCODE_COMMON_GET_AVAIL_PERSONALITIES = 113, 925231437Sluigi OPCODE_COMMON_GET_CONFIG_PERSONALITIES = 114, 926231437Sluigi OPCODE_COMMON_SEND_ACTIVATION = 115, 927231437Sluigi OPCODE_COMMON_RESET_LICENSES = 116, 928231437Sluigi OPCODE_COMMON_GET_CNTL_ADDL_ATTRIBUTES = 121, 929231437Sluigi OPCODE_COMMON_QUERY_TCB = 144, 930231437Sluigi OPCODE_COMMON_ADD_IFACE_QUEUE_FILTER = 145, 931231437Sluigi OPCODE_COMMON_DEL_IFACE_QUEUE_FILTER = 146, 932231437Sluigi OPCODE_COMMON_GET_IFACE_MAC_LIST = 147, 933231437Sluigi OPCODE_COMMON_SET_IFACE_MAC_LIST = 148, 934231437Sluigi OPCODE_COMMON_MODIFY_CQ = 149, 935231437Sluigi OPCODE_COMMON_GET_IFACE_VLAN_LIST = 150, 936231437Sluigi OPCODE_COMMON_SET_IFACE_VLAN_LIST = 151, 937231437Sluigi OPCODE_COMMON_GET_HSW_CONFIG = 152, 938231437Sluigi OPCODE_COMMON_SET_HSW_CONFIG = 153, 939231437Sluigi OPCODE_COMMON_GET_RESOURCE_EXTENT_INFO = 154, 940231437Sluigi OPCODE_COMMON_GET_ALLOCATED_RESOURCE_EXTENTS = 155, 941231437Sluigi OPCODE_COMMON_ALLOC_RESOURCE_EXTENTS = 156, 942231437Sluigi OPCODE_COMMON_DEALLOC_RESOURCE_EXTENTS = 157, 943231437Sluigi OPCODE_COMMON_SET_DIAG_REGISTERS = 158, 944231437Sluigi OPCODE_COMMON_GET_FUNCTION_CONFIG = 160, 945231437Sluigi OPCODE_COMMON_GET_PROFILE_CAPACITIES = 161, 946231437Sluigi OPCODE_COMMON_GET_MR_PROFILE_CAPACITIES = 162, 947231437Sluigi OPCODE_COMMON_SET_MR_PROFILE_CAPACITIES = 163, 948231437Sluigi OPCODE_COMMON_GET_PROFILE_CONFIG = 164, 949231437Sluigi OPCODE_COMMON_SET_PROFILE_CONFIG = 165, 950231437Sluigi OPCODE_COMMON_GET_PROFILE_LIST = 166, 951231437Sluigi OPCODE_COMMON_GET_ACTIVE_PROFILE = 167, 952231437Sluigi OPCODE_COMMON_SET_ACTIVE_PROFILE = 168, 953231437Sluigi OPCODE_COMMON_GET_FUNCTION_PRIVILEGES = 170, 954231437Sluigi OPCODE_COMMON_READ_OBJECT = 171, 955231437Sluigi OPCODE_COMMON_WRITE_OBJECT = 172 956231437Sluigi}; 957231437Sluigi 958231437Sluigi/* common ioctl header */ 959231437Sluigi#define OCE_MBX_VER_V2 0x0002 /* Version V2 mailbox command */ 960231437Sluigi#define OCE_MBX_VER_V1 0x0001 /* Version V1 mailbox command */ 961231437Sluigi#define OCE_MBX_VER_V0 0x0000 /* Version V0 mailbox command */ 962231437Sluigistruct mbx_hdr { 963231437Sluigi union { 964231437Sluigi uint32_t dw[4]; 965231437Sluigi struct { 966231437Sluigi #ifdef _BIG_ENDIAN 967231437Sluigi /* dw 0 */ 968231437Sluigi uint32_t domain:8; 969231437Sluigi uint32_t port_number:8; 970231437Sluigi uint32_t subsystem:8; 971231437Sluigi uint32_t opcode:8; 972231437Sluigi /* dw 1 */ 973231437Sluigi uint32_t timeout; 974231437Sluigi /* dw 2 */ 975231437Sluigi uint32_t request_length; 976231437Sluigi /* dw 3 */ 977231437Sluigi uint32_t rsvd0:24; 978231437Sluigi uint32_t version:8; 979231437Sluigi #else 980231437Sluigi /* dw 0 */ 981231437Sluigi uint32_t opcode:8; 982231437Sluigi uint32_t subsystem:8; 983231437Sluigi uint32_t port_number:8; 984231437Sluigi uint32_t domain:8; 985231437Sluigi /* dw 1 */ 986231437Sluigi uint32_t timeout; 987231437Sluigi /* dw 2 */ 988231437Sluigi uint32_t request_length; 989231437Sluigi /* dw 3 */ 990231437Sluigi uint32_t version:8; 991231437Sluigi uint32_t rsvd0:24; 992231437Sluigi #endif 993231437Sluigi } req; 994231437Sluigi struct { 995231437Sluigi #ifdef _BIG_ENDIAN 996231437Sluigi /* dw 0 */ 997231437Sluigi uint32_t domain:8; 998231437Sluigi uint32_t rsvd0:8; 999231437Sluigi uint32_t subsystem:8; 1000231437Sluigi uint32_t opcode:8; 1001231437Sluigi /* dw 1 */ 1002231437Sluigi uint32_t rsvd1:16; 1003231437Sluigi uint32_t additional_status:8; 1004231437Sluigi uint32_t status:8; 1005231437Sluigi #else 1006231437Sluigi /* dw 0 */ 1007231437Sluigi uint32_t opcode:8; 1008231437Sluigi uint32_t subsystem:8; 1009231437Sluigi uint32_t rsvd0:8; 1010231437Sluigi uint32_t domain:8; 1011231437Sluigi /* dw 1 */ 1012231437Sluigi uint32_t status:8; 1013231437Sluigi uint32_t additional_status:8; 1014231437Sluigi uint32_t rsvd1:16; 1015231437Sluigi #endif 1016231437Sluigi uint32_t rsp_length; 1017231437Sluigi uint32_t actual_rsp_length; 1018231437Sluigi } rsp; 1019231437Sluigi } u0; 1020231437Sluigi}; 1021231437Sluigi#define OCE_BMBX_RHDR_SZ 20 1022231437Sluigi#define OCE_MBX_RRHDR_SZ sizeof (struct mbx_hdr) 1023231437Sluigi#define OCE_MBX_ADDL_STATUS(_MHDR) ((_MHDR)->u0.rsp.additional_status) 1024231437Sluigi#define OCE_MBX_STATUS(_MHDR) ((_MHDR)->u0.rsp.status) 1025231437Sluigi 1026268046Sdelphij/* [05] OPCODE_COMMON_QUERY_LINK_CONFIG_V1 */ 1027231437Sluigistruct mbx_query_common_link_config { 1028231437Sluigi struct mbx_hdr hdr; 1029231437Sluigi union { 1030231437Sluigi struct { 1031231437Sluigi uint32_t rsvd0; 1032231437Sluigi } req; 1033231437Sluigi 1034231437Sluigi struct { 1035268046Sdelphij #ifdef _BIG_ENDIAN 1036268046Sdelphij uint32_t physical_port_fault:8; 1037268046Sdelphij uint32_t physical_port_speed:8; 1038268046Sdelphij uint32_t link_duplex:8; 1039268046Sdelphij uint32_t pt:2; 1040268046Sdelphij uint32_t port_number:6; 1041268046Sdelphij 1042231437Sluigi uint16_t qos_link_speed; 1043268046Sdelphij uint16_t rsvd0; 1044268046Sdelphij 1045268046Sdelphij uint32_t rsvd1:21; 1046268046Sdelphij uint32_t phys_fcv:1; 1047268046Sdelphij uint32_t phys_rxf:1; 1048268046Sdelphij uint32_t phys_txf:1; 1049268046Sdelphij uint32_t logical_link_status:8; 1050268046Sdelphij #else 1051268046Sdelphij uint32_t port_number:6; 1052268046Sdelphij uint32_t pt:2; 1053268046Sdelphij uint32_t link_duplex:8; 1054268046Sdelphij uint32_t physical_port_speed:8; 1055268046Sdelphij uint32_t physical_port_fault:8; 1056268046Sdelphij 1057268046Sdelphij uint16_t rsvd0; 1058268046Sdelphij uint16_t qos_link_speed; 1059268046Sdelphij 1060268046Sdelphij uint32_t logical_link_status:8; 1061268046Sdelphij uint32_t phys_txf:1; 1062268046Sdelphij uint32_t phys_rxf:1; 1063268046Sdelphij uint32_t phys_fcv:1; 1064268046Sdelphij uint32_t rsvd1:21; 1065268046Sdelphij #endif 1066231437Sluigi } rsp; 1067231437Sluigi } params; 1068231437Sluigi}; 1069231437Sluigi 1070231437Sluigi/* [57] OPCODE_COMMON_SET_LINK_SPEED */ 1071231437Sluigistruct mbx_set_common_link_speed { 1072231437Sluigi struct mbx_hdr hdr; 1073231437Sluigi union { 1074231437Sluigi struct { 1075231437Sluigi#ifdef _BIG_ENDIAN 1076231437Sluigi uint8_t rsvd0; 1077231437Sluigi uint8_t mac_speed; 1078231437Sluigi uint8_t virtual_port; 1079231437Sluigi uint8_t physical_port; 1080231437Sluigi#else 1081231437Sluigi uint8_t physical_port; 1082231437Sluigi uint8_t virtual_port; 1083231437Sluigi uint8_t mac_speed; 1084231437Sluigi uint8_t rsvd0; 1085231437Sluigi#endif 1086231437Sluigi } req; 1087231437Sluigi 1088231437Sluigi struct { 1089231437Sluigi uint32_t rsvd0; 1090231437Sluigi } rsp; 1091231437Sluigi 1092231437Sluigi uint32_t dw; 1093231437Sluigi } params; 1094231437Sluigi}; 1095231437Sluigi 1096231437Sluigistruct mac_address_format { 1097231437Sluigi uint16_t size_of_struct; 1098231437Sluigi uint8_t mac_addr[6]; 1099231437Sluigi}; 1100231437Sluigi 1101231437Sluigi/* [01] OPCODE_COMMON_QUERY_IFACE_MAC */ 1102231437Sluigistruct mbx_query_common_iface_mac { 1103231437Sluigi struct mbx_hdr hdr; 1104231437Sluigi union { 1105231437Sluigi struct { 1106231437Sluigi#ifdef _BIG_ENDIAN 1107231437Sluigi uint16_t if_id; 1108231437Sluigi uint8_t permanent; 1109231437Sluigi uint8_t type; 1110231437Sluigi#else 1111231437Sluigi uint8_t type; 1112231437Sluigi uint8_t permanent; 1113231437Sluigi uint16_t if_id; 1114231437Sluigi#endif 1115231437Sluigi 1116231437Sluigi } req; 1117231437Sluigi 1118231437Sluigi struct { 1119231437Sluigi struct mac_address_format mac; 1120231437Sluigi } rsp; 1121231437Sluigi } params; 1122231437Sluigi}; 1123231437Sluigi 1124231437Sluigi/* [02] OPCODE_COMMON_SET_IFACE_MAC */ 1125231437Sluigistruct mbx_set_common_iface_mac { 1126231437Sluigi struct mbx_hdr hdr; 1127231437Sluigi union { 1128231437Sluigi struct { 1129231437Sluigi#ifdef _BIG_ENDIAN 1130231437Sluigi /* dw 0 */ 1131231437Sluigi uint16_t if_id; 1132231437Sluigi uint8_t invalidate; 1133231437Sluigi uint8_t type; 1134231437Sluigi#else 1135231437Sluigi /* dw 0 */ 1136231437Sluigi uint8_t type; 1137231437Sluigi uint8_t invalidate; 1138231437Sluigi uint16_t if_id; 1139231437Sluigi#endif 1140231437Sluigi /* dw 1 */ 1141231437Sluigi struct mac_address_format mac; 1142231437Sluigi } req; 1143231437Sluigi 1144231437Sluigi struct { 1145231437Sluigi uint32_t rsvd0; 1146231437Sluigi } rsp; 1147231437Sluigi 1148231437Sluigi uint32_t dw[2]; 1149231437Sluigi } params; 1150231437Sluigi}; 1151231437Sluigi 1152231437Sluigi/* [03] OPCODE_COMMON_SET_IFACE_MULTICAST */ 1153231437Sluigistruct mbx_set_common_iface_multicast { 1154231437Sluigi struct mbx_hdr hdr; 1155231437Sluigi union { 1156231437Sluigi struct { 1157231437Sluigi /* dw 0 */ 1158231437Sluigi uint16_t num_mac; 1159231437Sluigi uint8_t promiscuous; 1160231437Sluigi uint8_t if_id; 1161231437Sluigi /* dw 1-48 */ 1162231437Sluigi struct { 1163231437Sluigi uint8_t byte[6]; 1164231437Sluigi } mac[32]; 1165231437Sluigi 1166231437Sluigi } req; 1167231437Sluigi 1168231437Sluigi struct { 1169231437Sluigi uint32_t rsvd0; 1170231437Sluigi } rsp; 1171231437Sluigi 1172231437Sluigi uint32_t dw[49]; 1173231437Sluigi } params; 1174231437Sluigi}; 1175231437Sluigi 1176231437Sluigistruct qinq_vlan { 1177231437Sluigi#ifdef _BIG_ENDIAN 1178231437Sluigi uint16_t inner; 1179231437Sluigi uint16_t outer; 1180231437Sluigi#else 1181231437Sluigi uint16_t outer; 1182231437Sluigi uint16_t inner; 1183231437Sluigi#endif 1184231437Sluigi}; 1185231437Sluigi 1186231437Sluigistruct normal_vlan { 1187231437Sluigi uint16_t vtag; 1188231437Sluigi}; 1189231437Sluigi 1190231437Sluigistruct ntwk_if_vlan_tag { 1191231437Sluigi union { 1192231437Sluigi struct normal_vlan normal; 1193231437Sluigi struct qinq_vlan qinq; 1194231437Sluigi } u0; 1195231437Sluigi}; 1196231437Sluigi 1197231437Sluigi/* [50] OPCODE_COMMON_CREATE_IFACE */ 1198231437Sluigistruct mbx_create_common_iface { 1199231437Sluigi struct mbx_hdr hdr; 1200231437Sluigi union { 1201231437Sluigi struct { 1202231437Sluigi uint32_t version; 1203231437Sluigi uint32_t cap_flags; 1204231437Sluigi uint32_t enable_flags; 1205231437Sluigi uint8_t mac_addr[6]; 1206231437Sluigi uint8_t rsvd0; 1207231437Sluigi uint8_t mac_invalid; 1208231437Sluigi struct ntwk_if_vlan_tag vlan_tag; 1209231437Sluigi } req; 1210231437Sluigi 1211231437Sluigi struct { 1212231437Sluigi uint32_t if_id; 1213231437Sluigi uint32_t pmac_id; 1214231437Sluigi } rsp; 1215231437Sluigi uint32_t dw[4]; 1216231437Sluigi } params; 1217231437Sluigi}; 1218231437Sluigi 1219231437Sluigi/* [51] OPCODE_COMMON_DESTROY_IFACE */ 1220231437Sluigistruct mbx_destroy_common_iface { 1221231437Sluigi struct mbx_hdr hdr; 1222231437Sluigi union { 1223231437Sluigi struct { 1224231437Sluigi uint32_t if_id; 1225231437Sluigi } req; 1226231437Sluigi 1227231437Sluigi struct { 1228231437Sluigi uint32_t rsvd0; 1229231437Sluigi } rsp; 1230231437Sluigi 1231231437Sluigi uint32_t dw; 1232231437Sluigi } params; 1233231437Sluigi}; 1234231437Sluigi 1235231437Sluigi/* event queue context structure */ 1236231437Sluigistruct oce_eq_ctx { 1237231437Sluigi#ifdef _BIG_ENDIAN 1238231437Sluigi uint32_t dw4rsvd1:16; 1239231437Sluigi uint32_t num_pages:16; 1240231437Sluigi 1241231437Sluigi uint32_t size:1; 1242231437Sluigi uint32_t dw5rsvd2:1; 1243231437Sluigi uint32_t valid:1; 1244231437Sluigi uint32_t dw5rsvd1:29; 1245231437Sluigi 1246231437Sluigi uint32_t armed:1; 1247231437Sluigi uint32_t dw6rsvd2:2; 1248231437Sluigi uint32_t count:3; 1249231437Sluigi uint32_t dw6rsvd1:26; 1250231437Sluigi 1251231437Sluigi uint32_t dw7rsvd2:9; 1252231437Sluigi uint32_t delay_mult:10; 1253231437Sluigi uint32_t dw7rsvd1:13; 1254231437Sluigi 1255231437Sluigi uint32_t dw8rsvd1; 1256231437Sluigi#else 1257231437Sluigi uint32_t num_pages:16; 1258231437Sluigi uint32_t dw4rsvd1:16; 1259231437Sluigi 1260231437Sluigi uint32_t dw5rsvd1:29; 1261231437Sluigi uint32_t valid:1; 1262231437Sluigi uint32_t dw5rsvd2:1; 1263231437Sluigi uint32_t size:1; 1264231437Sluigi 1265231437Sluigi uint32_t dw6rsvd1:26; 1266231437Sluigi uint32_t count:3; 1267231437Sluigi uint32_t dw6rsvd2:2; 1268231437Sluigi uint32_t armed:1; 1269231437Sluigi 1270231437Sluigi uint32_t dw7rsvd1:13; 1271231437Sluigi uint32_t delay_mult:10; 1272231437Sluigi uint32_t dw7rsvd2:9; 1273231437Sluigi 1274231437Sluigi uint32_t dw8rsvd1; 1275231437Sluigi#endif 1276231437Sluigi}; 1277231437Sluigi 1278231437Sluigi/* [13] OPCODE_COMMON_CREATE_EQ */ 1279231437Sluigistruct mbx_create_common_eq { 1280231437Sluigi struct mbx_hdr hdr; 1281231437Sluigi union { 1282231437Sluigi struct { 1283231437Sluigi struct oce_eq_ctx ctx; 1284231437Sluigi struct phys_addr pages[8]; 1285231437Sluigi } req; 1286231437Sluigi 1287231437Sluigi struct { 1288231437Sluigi uint16_t eq_id; 1289231437Sluigi uint16_t rsvd0; 1290231437Sluigi } rsp; 1291231437Sluigi } params; 1292231437Sluigi}; 1293231437Sluigi 1294231437Sluigi/* [55] OPCODE_COMMON_DESTROY_EQ */ 1295231437Sluigistruct mbx_destroy_common_eq { 1296231437Sluigi struct mbx_hdr hdr; 1297231437Sluigi union { 1298231437Sluigi struct { 1299231437Sluigi#ifdef _BIG_ENDIAN 1300231437Sluigi uint16_t rsvd0; 1301231437Sluigi uint16_t id; 1302231437Sluigi#else 1303231437Sluigi uint16_t id; 1304231437Sluigi uint16_t rsvd0; 1305231437Sluigi#endif 1306231437Sluigi } req; 1307231437Sluigi 1308231437Sluigi struct { 1309231437Sluigi uint32_t rsvd0; 1310231437Sluigi } rsp; 1311231437Sluigi } params; 1312231437Sluigi}; 1313231437Sluigi 1314231437Sluigi/* SLI-4 CQ context - use version V0 for B3, version V2 for Lancer */ 1315231437Sluigitypedef union oce_cq_ctx_u { 1316231437Sluigi uint32_t dw[5]; 1317231437Sluigi struct { 1318231437Sluigi #ifdef _BIG_ENDIAN 1319231437Sluigi /* dw4 */ 1320231437Sluigi uint32_t dw4rsvd1:16; 1321231437Sluigi uint32_t num_pages:16; 1322231437Sluigi /* dw5 */ 1323231437Sluigi uint32_t eventable:1; 1324231437Sluigi uint32_t dw5rsvd3:1; 1325231437Sluigi uint32_t valid:1; 1326231437Sluigi uint32_t count:2; 1327231437Sluigi uint32_t dw5rsvd2:12; 1328231437Sluigi uint32_t nodelay:1; 1329231437Sluigi uint32_t coalesce_wm:2; 1330231437Sluigi uint32_t dw5rsvd1:12; 1331231437Sluigi /* dw6 */ 1332231437Sluigi uint32_t armed:1; 1333231437Sluigi uint32_t dw6rsvd2:1; 1334231437Sluigi uint32_t eq_id:8; 1335231437Sluigi uint32_t dw6rsvd1:22; 1336231437Sluigi #else 1337231437Sluigi /* dw4 */ 1338231437Sluigi uint32_t num_pages:16; 1339231437Sluigi uint32_t dw4rsvd1:16; 1340231437Sluigi /* dw5 */ 1341231437Sluigi uint32_t dw5rsvd1:12; 1342231437Sluigi uint32_t coalesce_wm:2; 1343231437Sluigi uint32_t nodelay:1; 1344231437Sluigi uint32_t dw5rsvd2:12; 1345231437Sluigi uint32_t count:2; 1346231437Sluigi uint32_t valid:1; 1347231437Sluigi uint32_t dw5rsvd3:1; 1348231437Sluigi uint32_t eventable:1; 1349231437Sluigi /* dw6 */ 1350231437Sluigi uint32_t dw6rsvd1:22; 1351231437Sluigi uint32_t eq_id:8; 1352231437Sluigi uint32_t dw6rsvd2:1; 1353231437Sluigi uint32_t armed:1; 1354231437Sluigi #endif 1355231437Sluigi /* dw7 */ 1356231437Sluigi uint32_t dw7rsvd1; 1357231437Sluigi /* dw8 */ 1358231437Sluigi uint32_t dw8rsvd1; 1359231437Sluigi } v0; 1360231437Sluigi struct { 1361231437Sluigi #ifdef _BIG_ENDIAN 1362231437Sluigi /* dw4 */ 1363231437Sluigi uint32_t dw4rsvd1:8; 1364231437Sluigi uint32_t page_size:8; 1365231437Sluigi uint32_t num_pages:16; 1366231437Sluigi /* dw5 */ 1367231437Sluigi uint32_t eventable:1; 1368231437Sluigi uint32_t dw5rsvd3:1; 1369231437Sluigi uint32_t valid:1; 1370231437Sluigi uint32_t count:2; 1371231437Sluigi uint32_t dw5rsvd2:11; 1372231437Sluigi uint32_t autovalid:1; 1373231437Sluigi uint32_t nodelay:1; 1374231437Sluigi uint32_t coalesce_wm:2; 1375231437Sluigi uint32_t dw5rsvd1:12; 1376231437Sluigi /* dw6 */ 1377231437Sluigi uint32_t armed:1; 1378231437Sluigi uint32_t dw6rsvd1:15; 1379231437Sluigi uint32_t eq_id:16; 1380231437Sluigi /* dw7 */ 1381231437Sluigi uint32_t dw7rsvd1:16; 1382231437Sluigi uint32_t cqe_count:16; 1383231437Sluigi #else 1384231437Sluigi /* dw4 */ 1385231437Sluigi uint32_t num_pages:16; 1386231437Sluigi uint32_t page_size:8; 1387231437Sluigi uint32_t dw4rsvd1:8; 1388231437Sluigi /* dw5 */ 1389231437Sluigi uint32_t dw5rsvd1:12; 1390231437Sluigi uint32_t coalesce_wm:2; 1391231437Sluigi uint32_t nodelay:1; 1392231437Sluigi uint32_t autovalid:1; 1393231437Sluigi uint32_t dw5rsvd2:11; 1394231437Sluigi uint32_t count:2; 1395231437Sluigi uint32_t valid:1; 1396231437Sluigi uint32_t dw5rsvd3:1; 1397231437Sluigi uint32_t eventable:1; 1398231437Sluigi /* dw6 */ 1399231437Sluigi uint32_t eq_id:8; 1400231437Sluigi uint32_t dw6rsvd1:15; 1401231437Sluigi uint32_t armed:1; 1402231437Sluigi /* dw7 */ 1403231437Sluigi uint32_t cqe_count:16; 1404231437Sluigi uint32_t dw7rsvd1:16; 1405231437Sluigi #endif 1406231437Sluigi /* dw8 */ 1407231437Sluigi uint32_t dw8rsvd1; 1408231437Sluigi } v2; 1409231437Sluigi} oce_cq_ctx_t; 1410231437Sluigi 1411231437Sluigi/* [12] OPCODE_COMMON_CREATE_CQ */ 1412231437Sluigistruct mbx_create_common_cq { 1413231437Sluigi struct mbx_hdr hdr; 1414231437Sluigi union { 1415231437Sluigi struct { 1416231437Sluigi oce_cq_ctx_t cq_ctx; 1417231437Sluigi struct phys_addr pages[4]; 1418231437Sluigi } req; 1419231437Sluigi 1420231437Sluigi struct { 1421231437Sluigi uint16_t cq_id; 1422231437Sluigi uint16_t rsvd0; 1423231437Sluigi } rsp; 1424231437Sluigi } params; 1425231437Sluigi}; 1426231437Sluigi 1427231437Sluigi/* [54] OPCODE_COMMON_DESTROY_CQ */ 1428231437Sluigistruct mbx_destroy_common_cq { 1429231437Sluigi struct mbx_hdr hdr; 1430231437Sluigi union { 1431231437Sluigi struct { 1432231437Sluigi#ifdef _BIG_ENDIAN 1433231437Sluigi uint16_t rsvd0; 1434231437Sluigi uint16_t id; 1435231437Sluigi#else 1436231437Sluigi uint16_t id; 1437231437Sluigi uint16_t rsvd0; 1438231437Sluigi#endif 1439231437Sluigi } req; 1440231437Sluigi 1441231437Sluigi struct { 1442231437Sluigi uint32_t rsvd0; 1443231437Sluigi } rsp; 1444231437Sluigi } params; 1445231437Sluigi}; 1446231437Sluigi 1447231437Sluigitypedef union oce_mq_ctx_u { 1448231437Sluigi uint32_t dw[5]; 1449231437Sluigi struct { 1450231437Sluigi #ifdef _BIG_ENDIAN 1451231437Sluigi /* dw4 */ 1452231437Sluigi uint32_t dw4rsvd1:16; 1453231437Sluigi uint32_t num_pages:16; 1454231437Sluigi /* dw5 */ 1455231437Sluigi uint32_t cq_id:10; 1456231437Sluigi uint32_t dw5rsvd2:2; 1457231437Sluigi uint32_t ring_size:4; 1458231437Sluigi uint32_t dw5rsvd1:16; 1459231437Sluigi /* dw6 */ 1460231437Sluigi uint32_t valid:1; 1461231437Sluigi uint32_t dw6rsvd1:31; 1462231437Sluigi /* dw7 */ 1463231437Sluigi uint32_t dw7rsvd1:21; 1464231437Sluigi uint32_t async_cq_id:10; 1465231437Sluigi uint32_t async_cq_valid:1; 1466231437Sluigi #else 1467231437Sluigi /* dw4 */ 1468231437Sluigi uint32_t num_pages:16; 1469231437Sluigi uint32_t dw4rsvd1:16; 1470231437Sluigi /* dw5 */ 1471231437Sluigi uint32_t dw5rsvd1:16; 1472231437Sluigi uint32_t ring_size:4; 1473231437Sluigi uint32_t dw5rsvd2:2; 1474231437Sluigi uint32_t cq_id:10; 1475231437Sluigi /* dw6 */ 1476231437Sluigi uint32_t dw6rsvd1:31; 1477231437Sluigi uint32_t valid:1; 1478231437Sluigi /* dw7 */ 1479231437Sluigi uint32_t async_cq_valid:1; 1480231437Sluigi uint32_t async_cq_id:10; 1481231437Sluigi uint32_t dw7rsvd1:21; 1482231437Sluigi #endif 1483231437Sluigi /* dw8 */ 1484231437Sluigi uint32_t dw8rsvd1; 1485231437Sluigi } v0; 1486231437Sluigi} oce_mq_ctx_t; 1487231437Sluigi 1488231437Sluigi/** 1489231437Sluigi * @brief [21] OPCODE_COMMON_CREATE_MQ 1490231437Sluigi * A MQ must be at least 16 entries deep (corresponding to 1 page) and 1491231437Sluigi * at most 128 entries deep (corresponding to 8 pages). 1492231437Sluigi */ 1493231437Sluigistruct mbx_create_common_mq { 1494231437Sluigi struct mbx_hdr hdr; 1495231437Sluigi union { 1496231437Sluigi struct { 1497231437Sluigi oce_mq_ctx_t context; 1498231437Sluigi struct phys_addr pages[8]; 1499231437Sluigi } req; 1500231437Sluigi 1501231437Sluigi struct { 1502231437Sluigi uint32_t mq_id:16; 1503231437Sluigi uint32_t rsvd0:16; 1504231437Sluigi } rsp; 1505231437Sluigi } params; 1506231437Sluigi}; 1507231437Sluigi 1508231879Sluigistruct mbx_create_common_mq_ex { 1509231879Sluigi struct mbx_hdr hdr; 1510231879Sluigi union { 1511231879Sluigi struct { 1512231879Sluigi oce_mq_ext_ctx_t context; 1513231879Sluigi struct phys_addr pages[8]; 1514231879Sluigi } req; 1515231879Sluigi 1516231879Sluigi struct { 1517231879Sluigi uint32_t mq_id:16; 1518231879Sluigi uint32_t rsvd0:16; 1519231879Sluigi } rsp; 1520231879Sluigi } params; 1521231879Sluigi}; 1522231879Sluigi 1523231879Sluigi 1524231879Sluigi 1525231437Sluigi/* [53] OPCODE_COMMON_DESTROY_MQ */ 1526231437Sluigistruct mbx_destroy_common_mq { 1527231437Sluigi struct mbx_hdr hdr; 1528231437Sluigi union { 1529231437Sluigi struct { 1530231437Sluigi#ifdef _BIG_ENDIAN 1531231437Sluigi uint16_t rsvd0; 1532231437Sluigi uint16_t id; 1533231437Sluigi#else 1534231437Sluigi uint16_t id; 1535231437Sluigi uint16_t rsvd0; 1536231437Sluigi#endif 1537231437Sluigi } req; 1538231437Sluigi 1539231437Sluigi struct { 1540231437Sluigi uint32_t rsvd0; 1541231437Sluigi } rsp; 1542231437Sluigi } params; 1543231437Sluigi}; 1544231437Sluigi 1545231437Sluigi/* [35] OPCODE_COMMON_GET_ FW_VERSION */ 1546231437Sluigistruct mbx_get_common_fw_version { 1547231437Sluigi struct mbx_hdr hdr; 1548231437Sluigi union { 1549231437Sluigi struct { 1550231437Sluigi uint32_t rsvd0; 1551231437Sluigi } req; 1552231437Sluigi 1553231437Sluigi struct { 1554231437Sluigi uint8_t fw_ver_str[32]; 1555231437Sluigi uint8_t fw_on_flash_ver_str[32]; 1556231437Sluigi } rsp; 1557231437Sluigi } params; 1558231437Sluigi}; 1559231437Sluigi 1560231437Sluigi/* [52] OPCODE_COMMON_CEV_MODIFY_MSI_MESSAGES */ 1561231437Sluigistruct mbx_common_cev_modify_msi_messages { 1562231437Sluigi struct mbx_hdr hdr; 1563231437Sluigi union { 1564231437Sluigi struct { 1565231437Sluigi uint32_t num_msi_msgs; 1566231437Sluigi } req; 1567231437Sluigi 1568231437Sluigi struct { 1569231437Sluigi uint32_t rsvd0; 1570231437Sluigi } rsp; 1571231437Sluigi } params; 1572231437Sluigi}; 1573231437Sluigi 1574231437Sluigi/* [36] OPCODE_COMMON_SET_FLOW_CONTROL */ 1575231437Sluigi/* [37] OPCODE_COMMON_GET_FLOW_CONTROL */ 1576231437Sluigistruct mbx_common_get_set_flow_control { 1577231437Sluigi struct mbx_hdr hdr; 1578231437Sluigi#ifdef _BIG_ENDIAN 1579231437Sluigi uint16_t tx_flow_control; 1580231437Sluigi uint16_t rx_flow_control; 1581231437Sluigi#else 1582231437Sluigi uint16_t rx_flow_control; 1583231437Sluigi uint16_t tx_flow_control; 1584231437Sluigi#endif 1585231437Sluigi}; 1586231437Sluigi 1587231437Sluigienum e_flash_opcode { 1588231437Sluigi MGMT_FLASHROM_OPCODE_FLASH = 1, 1589231437Sluigi MGMT_FLASHROM_OPCODE_SAVE = 2 1590231437Sluigi}; 1591231437Sluigi 1592231437Sluigi/* [06] OPCODE_READ_COMMON_FLASHROM */ 1593231437Sluigi/* [07] OPCODE_WRITE_COMMON_FLASHROM */ 1594231437Sluigi 1595231437Sluigistruct mbx_common_read_write_flashrom { 1596231437Sluigi struct mbx_hdr hdr; 1597231437Sluigi uint32_t flash_op_code; 1598231437Sluigi uint32_t flash_op_type; 1599231437Sluigi uint32_t data_buffer_size; 1600231437Sluigi uint32_t data_offset; 1601231437Sluigi uint8_t data_buffer[4]; /* + IMAGE_TRANSFER_SIZE */ 1602231437Sluigi}; 1603231437Sluigi 1604231437Sluigistruct oce_phy_info { 1605231437Sluigi uint16_t phy_type; 1606231437Sluigi uint16_t interface_type; 1607231437Sluigi uint32_t misc_params; 1608231437Sluigi uint16_t ext_phy_details; 1609231437Sluigi uint16_t rsvd; 1610231437Sluigi uint16_t auto_speeds_supported; 1611231437Sluigi uint16_t fixed_speeds_supported; 1612231437Sluigi uint32_t future_use[2]; 1613231437Sluigi}; 1614231437Sluigi 1615231437Sluigistruct mbx_common_phy_info { 1616231437Sluigi struct mbx_hdr hdr; 1617231437Sluigi union { 1618231437Sluigi struct { 1619231437Sluigi uint32_t rsvd0[4]; 1620231437Sluigi } req; 1621231437Sluigi struct { 1622231437Sluigi struct oce_phy_info phy_info; 1623231437Sluigi } rsp; 1624231437Sluigi } params; 1625231437Sluigi}; 1626231437Sluigi 1627231437Sluigi/*Lancer firmware*/ 1628231437Sluigi 1629231437Sluigistruct mbx_lancer_common_write_object { 1630231437Sluigi union { 1631231437Sluigi struct { 1632231437Sluigi struct mbx_hdr hdr; 1633231437Sluigi uint32_t write_length: 24; 1634231437Sluigi uint32_t rsvd: 7; 1635231437Sluigi uint32_t eof: 1; 1636231437Sluigi uint32_t write_offset; 1637231437Sluigi uint8_t object_name[104]; 1638231437Sluigi uint32_t descriptor_count; 1639231437Sluigi uint32_t buffer_length; 1640231437Sluigi uint32_t address_lower; 1641231437Sluigi uint32_t address_upper; 1642231437Sluigi } req; 1643231437Sluigi struct { 1644231437Sluigi uint8_t opcode; 1645231437Sluigi uint8_t subsystem; 1646231437Sluigi uint8_t rsvd1[2]; 1647231437Sluigi uint8_t status; 1648231437Sluigi uint8_t additional_status; 1649231437Sluigi uint8_t rsvd2[2]; 1650231437Sluigi uint32_t response_length; 1651231437Sluigi uint32_t actual_response_length; 1652231437Sluigi uint32_t actual_write_length; 1653231437Sluigi } rsp; 1654231437Sluigi } params; 1655231437Sluigi}; 1656231437Sluigi 1657231437Sluigi/** 1658231437Sluigi * @brief MBX Common Quiery Firmaware Config 1659231437Sluigi * This command retrieves firmware configuration parameters and adapter 1660231437Sluigi * resources available to the driver originating the request. The firmware 1661231437Sluigi * configuration defines supported protocols by the installed adapter firmware. 1662231437Sluigi * This includes which ULP processors support the specified protocols and 1663231437Sluigi * the number of TCP connections allowed for that protocol. 1664231437Sluigi */ 1665231437Sluigistruct mbx_common_query_fw_config { 1666231437Sluigi struct mbx_hdr hdr; 1667231437Sluigi union { 1668231437Sluigi struct { 1669231437Sluigi uint32_t rsvd0[30]; 1670231437Sluigi } req; 1671231437Sluigi 1672231437Sluigi struct { 1673231437Sluigi uint32_t config_number; 1674231437Sluigi uint32_t asic_revision; 1675231437Sluigi uint32_t port_id; /* used for stats retrieval */ 1676231437Sluigi uint32_t function_mode; 1677231437Sluigi struct { 1678231437Sluigi 1679231437Sluigi uint32_t ulp_mode; 1680231437Sluigi uint32_t nic_wqid_base; 1681231437Sluigi uint32_t nic_wq_tot; 1682231437Sluigi uint32_t toe_wqid_base; 1683231437Sluigi uint32_t toe_wq_tot; 1684231437Sluigi uint32_t toe_rqid_base; 1685231437Sluigi uint32_t toe_rqid_tot; 1686231437Sluigi uint32_t toe_defrqid_base; 1687231437Sluigi uint32_t toe_defrqid_count; 1688231437Sluigi uint32_t lro_rqid_base; 1689231437Sluigi uint32_t lro_rqid_tot; 1690231437Sluigi uint32_t iscsi_icd_base; 1691231437Sluigi uint32_t iscsi_icd_count; 1692231437Sluigi } ulp[2]; 1693231437Sluigi uint32_t function_caps; 1694231437Sluigi uint32_t cqid_base; 1695231437Sluigi uint32_t cqid_tot; 1696231437Sluigi uint32_t eqid_base; 1697231437Sluigi uint32_t eqid_tot; 1698231437Sluigi } rsp; 1699231437Sluigi } params; 1700231437Sluigi}; 1701231437Sluigi 1702231437Sluigienum CQFW_CONFIG_NUMBER { 1703231437Sluigi FCN_NIC_ISCSI_Initiator = 0x0, 1704231437Sluigi FCN_ISCSI_Target = 0x3, 1705231437Sluigi FCN_FCoE = 0x7, 1706231437Sluigi FCN_ISCSI_Initiator_Target = 0x9, 1707231437Sluigi FCN_NIC_RDMA_TOE = 0xA, 1708231437Sluigi FCN_NIC_RDMA_FCoE = 0xB, 1709231437Sluigi FCN_NIC_RDMA_iSCSI = 0xC, 1710231437Sluigi FCN_NIC_iSCSI_FCoE = 0xD 1711231437Sluigi}; 1712231437Sluigi 1713231437Sluigi/** 1714231437Sluigi * @brief Function Capabilites 1715231437Sluigi * This field contains the flags indicating the capabilities of 1716231437Sluigi * the SLI Host���s PCI function. 1717231437Sluigi */ 1718231437Sluigienum CQFW_FUNCTION_CAPABILITIES { 1719231437Sluigi FNC_UNCLASSIFIED_STATS = 0x1, 1720231437Sluigi FNC_RSS = 0x2, 1721231437Sluigi FNC_PROMISCUOUS = 0x4, 1722231437Sluigi FNC_LEGACY_MODE = 0x8, 1723231437Sluigi FNC_HDS = 0x4000, 1724231437Sluigi FNC_VMQ = 0x10000, 1725231437Sluigi FNC_NETQ = 0x20000, 1726231437Sluigi FNC_QGROUPS = 0x40000, 1727231437Sluigi FNC_LRO = 0x100000, 1728231437Sluigi FNC_VLAN_OFFLOAD = 0x800000 1729231437Sluigi}; 1730231437Sluigi 1731231437Sluigienum CQFW_ULP_MODES_SUPPORTED { 1732231437Sluigi ULP_TOE_MODE = 0x1, 1733231437Sluigi ULP_NIC_MODE = 0x2, 1734231437Sluigi ULP_RDMA_MODE = 0x4, 1735231437Sluigi ULP_ISCSI_INI_MODE = 0x10, 1736231437Sluigi ULP_ISCSI_TGT_MODE = 0x20, 1737231437Sluigi ULP_FCOE_INI_MODE = 0x40, 1738231437Sluigi ULP_FCOE_TGT_MODE = 0x80, 1739231437Sluigi ULP_DAL_MODE = 0x100, 1740231437Sluigi ULP_LRO_MODE = 0x200 1741231437Sluigi}; 1742231437Sluigi 1743231437Sluigi/** 1744231437Sluigi * @brief Function Modes Supported 1745231437Sluigi * Valid function modes (or protocol-types) supported on the SLI-Host���s 1746231437Sluigi * PCIe function. This field is a logical OR of the following values: 1747231437Sluigi */ 1748231437Sluigienum CQFW_FUNCTION_MODES_SUPPORTED { 1749231437Sluigi FNM_TOE_MODE = 0x1, /* TCP offload supported */ 1750231437Sluigi FNM_NIC_MODE = 0x2, /* Raw Ethernet supported */ 1751231437Sluigi FNM_RDMA_MODE = 0x4, /* RDMA protocol supported */ 1752231437Sluigi FNM_VM_MODE = 0x8, /* Virtual Machines supported */ 1753231437Sluigi FNM_ISCSI_INI_MODE = 0x10, /* iSCSI initiator supported */ 1754231437Sluigi FNM_ISCSI_TGT_MODE = 0x20, /* iSCSI target plus initiator */ 1755231437Sluigi FNM_FCOE_INI_MODE = 0x40, /* FCoE Initiator supported */ 1756231437Sluigi FNM_FCOE_TGT_MODE = 0x80, /* FCoE target supported */ 1757231437Sluigi FNM_DAL_MODE = 0x100, /* DAL supported */ 1758231437Sluigi FNM_LRO_MODE = 0x200, /* LRO supported */ 1759231437Sluigi FNM_FLEX10_MODE = 0x400, /* QinQ, FLEX-10 or VNIC */ 1760231437Sluigi FNM_NCSI_MODE = 0x800, /* NCSI supported */ 1761231437Sluigi FNM_IPV6_MODE = 0x1000, /* IPV6 stack enabled */ 1762231437Sluigi FNM_BE2_COMPAT_MODE = 0x2000, /* BE2 compatibility (BE3 disable)*/ 1763231437Sluigi FNM_INVALID_MODE = 0x8000, /* Invalid */ 1764231437Sluigi FNM_BE3_COMPAT_MODE = 0x10000, /* BE3 features */ 1765231437Sluigi FNM_VNIC_MODE = 0x20000, /* Set when IBM vNIC mode is set */ 1766231437Sluigi FNM_VNTAG_MODE = 0x40000, /* Set when VNTAG mode is set */ 1767231879Sluigi FNM_UMC_MODE = 0x1000000, /* Set when UMC mode is set */ 1768231437Sluigi FNM_UMC_DEF_EN = 0x100000, /* Set when UMC Default is set */ 1769231437Sluigi FNM_ONE_GB_EN = 0x200000, /* Set when 1GB Default is set */ 1770231437Sluigi FNM_VNIC_DEF_VALID = 0x400000, /* Set when VNIC_DEF_EN is valid */ 1771231437Sluigi FNM_VNIC_DEF_EN = 0x800000 /* Set when VNIC Default enabled */ 1772231437Sluigi}; 1773231437Sluigi 1774231437Sluigi 1775231437Sluigistruct mbx_common_config_vlan { 1776231437Sluigi struct mbx_hdr hdr; 1777231437Sluigi union { 1778231437Sluigi struct { 1779231437Sluigi#ifdef _BIG_ENDIAN 1780231437Sluigi uint8_t num_vlans; 1781231437Sluigi uint8_t untagged; 1782231437Sluigi uint8_t promisc; 1783231437Sluigi uint8_t if_id; 1784231437Sluigi#else 1785231437Sluigi uint8_t if_id; 1786231437Sluigi uint8_t promisc; 1787231437Sluigi uint8_t untagged; 1788231437Sluigi uint8_t num_vlans; 1789231437Sluigi#endif 1790231437Sluigi union { 1791231437Sluigi struct normal_vlan normal_vlans[64]; 1792231437Sluigi struct qinq_vlan qinq_vlans[32]; 1793231437Sluigi } tags; 1794231437Sluigi } req; 1795231437Sluigi 1796231437Sluigi struct { 1797231437Sluigi uint32_t rsvd; 1798231437Sluigi } rsp; 1799231437Sluigi } params; 1800231437Sluigi}; 1801231437Sluigi 1802231437Sluigitypedef struct iface_rx_filter_ctx { 1803231437Sluigi uint32_t global_flags_mask; 1804231437Sluigi uint32_t global_flags; 1805231437Sluigi uint32_t iface_flags_mask; 1806231437Sluigi uint32_t iface_flags; 1807231437Sluigi uint32_t if_id; 1808231437Sluigi #define IFACE_RX_NUM_MCAST_MAX 64 1809231437Sluigi uint32_t num_mcast; 1810231437Sluigi struct mbx_mcast_addr { 1811231437Sluigi uint8_t byte[6]; 1812231437Sluigi } mac[IFACE_RX_NUM_MCAST_MAX]; 1813231437Sluigi} iface_rx_filter_ctx_t; 1814231437Sluigi 1815231437Sluigi/* [34] OPCODE_COMMON_SET_IFACE_RX_FILTER */ 1816231437Sluigistruct mbx_set_common_iface_rx_filter { 1817231437Sluigi struct mbx_hdr hdr; 1818231437Sluigi union { 1819231437Sluigi iface_rx_filter_ctx_t req; 1820231437Sluigi iface_rx_filter_ctx_t rsp; 1821231437Sluigi } params; 1822231437Sluigi}; 1823231437Sluigi 1824247880Sdelphijstruct be_set_eqd { 1825247880Sdelphij uint32_t eq_id; 1826247880Sdelphij uint32_t phase; 1827247880Sdelphij uint32_t dm; 1828247880Sdelphij}; 1829247880Sdelphij 1830231437Sluigi/* [41] OPCODE_COMMON_MODIFY_EQ_DELAY */ 1831231437Sluigistruct mbx_modify_common_eq_delay { 1832231437Sluigi struct mbx_hdr hdr; 1833231437Sluigi union { 1834231437Sluigi struct { 1835231437Sluigi uint32_t num_eq; 1836231437Sluigi struct { 1837231437Sluigi uint32_t eq_id; 1838231437Sluigi uint32_t phase; 1839231437Sluigi uint32_t dm; 1840231437Sluigi } delay[8]; 1841231437Sluigi } req; 1842231437Sluigi 1843231437Sluigi struct { 1844231437Sluigi uint32_t rsvd0; 1845231437Sluigi } rsp; 1846231437Sluigi } params; 1847231437Sluigi}; 1848231437Sluigi 1849247880Sdelphij/* [32] OPCODE_COMMON_GET_CNTL_ATTRIBUTES */ 1850247880Sdelphij 1851247880Sdelphijstruct mgmt_hba_attr { 1852247880Sdelphij int8_t flashrom_ver_str[32]; 1853247880Sdelphij int8_t manufac_name[32]; 1854247880Sdelphij uint32_t supp_modes; 1855247880Sdelphij int8_t seeprom_ver_lo; 1856247880Sdelphij int8_t seeprom_ver_hi; 1857247880Sdelphij int8_t rsvd0[2]; 1858247880Sdelphij uint32_t ioctl_data_struct_ver; 1859247880Sdelphij uint32_t ep_fw_data_struct_ver; 1860247880Sdelphij uint8_t ncsi_ver_str[12]; 1861247880Sdelphij uint32_t def_ext_to; 1862247880Sdelphij int8_t cntl_mod_num[32]; 1863247880Sdelphij int8_t cntl_desc[64]; 1864247880Sdelphij int8_t cntl_ser_num[32]; 1865247880Sdelphij int8_t ip_ver_str[32]; 1866247880Sdelphij int8_t fw_ver_str[32]; 1867247880Sdelphij int8_t bios_ver_str[32]; 1868247880Sdelphij int8_t redboot_ver_str[32]; 1869247880Sdelphij int8_t drv_ver_str[32]; 1870247880Sdelphij int8_t fw_on_flash_ver_str[32]; 1871247880Sdelphij uint32_t funcs_supp; 1872247880Sdelphij uint16_t max_cdblen; 1873247880Sdelphij uint8_t asic_rev; 1874247880Sdelphij uint8_t gen_guid[16]; 1875247880Sdelphij uint8_t hba_port_count; 1876247880Sdelphij uint16_t default_link_down_timeout; 1877247880Sdelphij uint8_t iscsi_ver_min_max; 1878247880Sdelphij uint8_t multifunc_dev; 1879247880Sdelphij uint8_t cache_valid; 1880247880Sdelphij uint8_t hba_status; 1881247880Sdelphij uint8_t max_domains_supp; 1882247880Sdelphij uint8_t phy_port; 1883247880Sdelphij uint32_t fw_post_status; 1884247880Sdelphij uint32_t hba_mtu[8]; 1885247880Sdelphij uint8_t iSCSI_feat; 1886247880Sdelphij uint8_t asic_gen; 1887247880Sdelphij uint8_t future_u8[2]; 1888247880Sdelphij uint32_t future_u32[3]; 1889247880Sdelphij}; 1890247880Sdelphij 1891247880Sdelphijstruct mgmt_cntl_attr { 1892247880Sdelphij struct mgmt_hba_attr hba_attr; 1893247880Sdelphij uint16_t pci_vendor_id; 1894247880Sdelphij uint16_t pci_device_id; 1895247880Sdelphij uint16_t pci_sub_vendor_id; 1896247880Sdelphij uint16_t pci_sub_system_id; 1897247880Sdelphij uint8_t pci_bus_num; 1898247880Sdelphij uint8_t pci_dev_num; 1899247880Sdelphij uint8_t pci_func_num; 1900247880Sdelphij uint8_t interface_type; 1901247880Sdelphij uint64_t unique_id; 1902247880Sdelphij uint8_t netfilters; 1903247880Sdelphij uint8_t rsvd0[3]; 1904247880Sdelphij uint32_t future_u32[4]; 1905247880Sdelphij}; 1906247880Sdelphij 1907247880Sdelphijstruct mbx_common_get_cntl_attr { 1908247880Sdelphij struct mbx_hdr hdr; 1909247880Sdelphij union { 1910247880Sdelphij struct { 1911247880Sdelphij uint32_t rsvd0; 1912247880Sdelphij } req; 1913247880Sdelphij struct { 1914247880Sdelphij struct mgmt_cntl_attr cntl_attr_info; 1915247880Sdelphij } rsp; 1916247880Sdelphij } params; 1917247880Sdelphij}; 1918247880Sdelphij 1919231437Sluigi/* [59] OPCODE_ADD_COMMON_IFACE_MAC */ 1920231437Sluigistruct mbx_add_common_iface_mac { 1921231437Sluigi struct mbx_hdr hdr; 1922231437Sluigi union { 1923231437Sluigi struct { 1924231437Sluigi uint32_t if_id; 1925231437Sluigi uint8_t mac_address[6]; 1926231437Sluigi uint8_t rsvd0[2]; 1927231437Sluigi } req; 1928231437Sluigi struct { 1929231437Sluigi uint32_t pmac_id; 1930231437Sluigi } rsp; 1931231437Sluigi } params; 1932231437Sluigi}; 1933231437Sluigi 1934231437Sluigi/* [60] OPCODE_DEL_COMMON_IFACE_MAC */ 1935231437Sluigistruct mbx_del_common_iface_mac { 1936231437Sluigi struct mbx_hdr hdr; 1937231437Sluigi union { 1938231437Sluigi struct { 1939231437Sluigi uint32_t if_id; 1940231437Sluigi uint32_t pmac_id; 1941231437Sluigi } req; 1942231437Sluigi struct { 1943231437Sluigi uint32_t rsvd0; 1944231437Sluigi } rsp; 1945231437Sluigi } params; 1946231437Sluigi}; 1947231437Sluigi 1948231437Sluigi/* [8] OPCODE_QUERY_COMMON_MAX_MBX_BUFFER_SIZE */ 1949231437Sluigistruct mbx_query_common_max_mbx_buffer_size { 1950231437Sluigi struct mbx_hdr hdr; 1951231437Sluigi struct { 1952231437Sluigi uint32_t max_ioctl_bufsz; 1953231437Sluigi } rsp; 1954231437Sluigi}; 1955231437Sluigi 1956231437Sluigi/* [61] OPCODE_COMMON_FUNCTION_RESET */ 1957231437Sluigistruct ioctl_common_function_reset { 1958231437Sluigi struct mbx_hdr hdr; 1959231437Sluigi}; 1960231437Sluigi 1961247880Sdelphij/* [73] OPCODE_COMMON_READ_TRANSRECEIVER_DATA */ 1962247880Sdelphijstruct mbx_read_common_transrecv_data { 1963247880Sdelphij struct mbx_hdr hdr; 1964247880Sdelphij union { 1965247880Sdelphij struct { 1966247880Sdelphij uint32_t page_num; 1967247880Sdelphij uint32_t port; 1968247880Sdelphij } req; 1969247880Sdelphij struct { 1970247880Sdelphij uint32_t page_num; 1971247880Sdelphij uint32_t port; 1972247880Sdelphij uint32_t page_data[32]; 1973247880Sdelphij } rsp; 1974247880Sdelphij } params; 1975247880Sdelphij 1976247880Sdelphij}; 1977247880Sdelphij 1978231437Sluigi/* [80] OPCODE_COMMON_FUNCTION_LINK_CONFIG */ 1979231437Sluigistruct mbx_common_func_link_cfg { 1980231437Sluigi struct mbx_hdr hdr; 1981231437Sluigi union { 1982231437Sluigi struct { 1983231437Sluigi uint32_t enable; 1984231437Sluigi } req; 1985231437Sluigi struct { 1986231437Sluigi uint32_t rsvd0; 1987231437Sluigi } rsp; 1988231437Sluigi } params; 1989231437Sluigi}; 1990231437Sluigi 1991231437Sluigi/* [103] OPCODE_COMMON_SET_FUNCTIONAL_CAPS */ 1992231437Sluigi#define CAP_SW_TIMESTAMPS 2 1993231437Sluigi#define CAP_BE3_NATIVE_ERX_API 4 1994231437Sluigi 1995231437Sluigistruct mbx_common_set_function_cap { 1996231437Sluigi struct mbx_hdr hdr; 1997231437Sluigi union { 1998231437Sluigi struct { 1999231437Sluigi uint32_t valid_capability_flags; 2000231437Sluigi uint32_t capability_flags; 2001231437Sluigi uint8_t sbz[212]; 2002231437Sluigi } req; 2003231437Sluigi struct { 2004231437Sluigi uint32_t valid_capability_flags; 2005231437Sluigi uint32_t capability_flags; 2006231437Sluigi uint8_t sbz[212]; 2007231437Sluigi } rsp; 2008231437Sluigi } params; 2009231437Sluigi}; 2010231437Sluigistruct mbx_lowlevel_test_loopback_mode { 2011231437Sluigi struct mbx_hdr hdr; 2012231437Sluigi union { 2013231437Sluigi struct { 2014231437Sluigi uint32_t loopback_type; 2015231437Sluigi uint32_t num_pkts; 2016231437Sluigi uint64_t pattern; 2017231437Sluigi uint32_t src_port; 2018231437Sluigi uint32_t dest_port; 2019231437Sluigi uint32_t pkt_size; 2020231437Sluigi }req; 2021231437Sluigi struct { 2022231437Sluigi uint32_t status; 2023231437Sluigi uint32_t num_txfer; 2024231437Sluigi uint32_t num_rx; 2025231437Sluigi uint32_t miscomp_off; 2026231437Sluigi uint32_t ticks_compl; 2027231437Sluigi }rsp; 2028231437Sluigi } params; 2029231437Sluigi}; 2030231437Sluigi 2031231437Sluigistruct mbx_lowlevel_set_loopback_mode { 2032231437Sluigi struct mbx_hdr hdr; 2033231437Sluigi union { 2034231437Sluigi struct { 2035231437Sluigi uint8_t src_port; 2036231437Sluigi uint8_t dest_port; 2037231437Sluigi uint8_t loopback_type; 2038231437Sluigi uint8_t loopback_state; 2039231437Sluigi } req; 2040231437Sluigi struct { 2041231437Sluigi uint8_t rsvd0[4]; 2042231437Sluigi } rsp; 2043231437Sluigi } params; 2044231437Sluigi}; 2045252869Sdelphij#define MAX_RESC_DESC 256 2046252869Sdelphij#define RESC_DESC_SIZE 88 2047252869Sdelphij#define ACTIVE_PROFILE 2 2048252869Sdelphij#define NIC_RESC_DESC_TYPE_V0 0x41 2049252869Sdelphij#define NIC_RESC_DESC_TYPE_V1 0x51 2050252869Sdelphij/* OPCODE_COMMON_GET_FUNCTION_CONFIG */ 2051252869Sdelphijstruct mbx_common_get_func_config { 2052252869Sdelphij struct mbx_hdr hdr; 2053252869Sdelphij union { 2054252869Sdelphij struct { 2055252869Sdelphij uint8_t rsvd; 2056252869Sdelphij uint8_t type; 2057252869Sdelphij uint16_t rsvd1; 2058252869Sdelphij } req; 2059252869Sdelphij struct { 2060252869Sdelphij uint32_t desc_count; 2061252869Sdelphij uint8_t resources[MAX_RESC_DESC * RESC_DESC_SIZE]; 2062252869Sdelphij } rsp; 2063252869Sdelphij } params; 2064252869Sdelphij}; 2065231437Sluigi 2066252869Sdelphij 2067252869Sdelphij/* OPCODE_COMMON_GET_PROFILE_CONFIG */ 2068252869Sdelphij 2069252869Sdelphijstruct mbx_common_get_profile_config { 2070252869Sdelphij struct mbx_hdr hdr; 2071252869Sdelphij union { 2072252869Sdelphij struct { 2073252869Sdelphij uint8_t rsvd; 2074252869Sdelphij uint8_t type; 2075252869Sdelphij uint16_t rsvd1; 2076252869Sdelphij } req; 2077252869Sdelphij struct { 2078252869Sdelphij uint32_t desc_count; 2079252869Sdelphij uint8_t resources[MAX_RESC_DESC * RESC_DESC_SIZE]; 2080252869Sdelphij } rsp; 2081252869Sdelphij } params; 2082252869Sdelphij}; 2083252869Sdelphij 2084252869Sdelphijstruct oce_nic_resc_desc { 2085252869Sdelphij uint8_t desc_type; 2086252869Sdelphij uint8_t desc_len; 2087252869Sdelphij uint8_t rsvd1; 2088252869Sdelphij uint8_t flags; 2089252869Sdelphij uint8_t vf_num; 2090252869Sdelphij uint8_t rsvd2; 2091252869Sdelphij uint8_t pf_num; 2092252869Sdelphij uint8_t rsvd3; 2093252869Sdelphij uint16_t unicast_mac_count; 2094252869Sdelphij uint8_t rsvd4[6]; 2095252869Sdelphij uint16_t mcc_count; 2096252869Sdelphij uint16_t vlan_count; 2097252869Sdelphij uint16_t mcast_mac_count; 2098252869Sdelphij uint16_t txq_count; 2099252869Sdelphij uint16_t rq_count; 2100252869Sdelphij uint16_t rssq_count; 2101252869Sdelphij uint16_t lro_count; 2102252869Sdelphij uint16_t cq_count; 2103252869Sdelphij uint16_t toe_conn_count; 2104252869Sdelphij uint16_t eq_count; 2105252869Sdelphij uint32_t rsvd5; 2106252869Sdelphij uint32_t cap_flags; 2107252869Sdelphij uint8_t link_param; 2108252869Sdelphij uint8_t rsvd6[3]; 2109252869Sdelphij uint32_t bw_min; 2110252869Sdelphij uint32_t bw_max; 2111252869Sdelphij uint8_t acpi_params; 2112252869Sdelphij uint8_t wol_param; 2113252869Sdelphij uint16_t rsvd7; 2114252869Sdelphij uint32_t rsvd8[7]; 2115252869Sdelphij 2116252869Sdelphij}; 2117252869Sdelphij 2118252869Sdelphij 2119231437Sluigistruct flash_file_hdr { 2120231437Sluigi uint8_t sign[52]; 2121231437Sluigi uint8_t ufi_version[4]; 2122231437Sluigi uint32_t file_len; 2123231437Sluigi uint32_t cksum; 2124231437Sluigi uint32_t antidote; 2125231437Sluigi uint32_t num_imgs; 2126231437Sluigi uint8_t build[24]; 2127257187Sdelphij uint8_t asic_type_rev; 2128257187Sdelphij uint8_t rsvd[31]; 2129231437Sluigi}; 2130231437Sluigi 2131231437Sluigistruct image_hdr { 2132231437Sluigi uint32_t imageid; 2133231437Sluigi uint32_t imageoffset; 2134231437Sluigi uint32_t imagelength; 2135231437Sluigi uint32_t image_checksum; 2136231437Sluigi uint8_t image_version[32]; 2137231437Sluigi}; 2138231437Sluigi 2139231437Sluigistruct flash_section_hdr { 2140231437Sluigi uint32_t format_rev; 2141231437Sluigi uint32_t cksum; 2142231437Sluigi uint32_t antidote; 2143231437Sluigi uint32_t num_images; 2144231437Sluigi uint8_t id_string[128]; 2145231437Sluigi uint32_t rsvd[4]; 2146231437Sluigi}; 2147231437Sluigi 2148231437Sluigistruct flash_section_entry { 2149231437Sluigi uint32_t type; 2150231437Sluigi uint32_t offset; 2151231437Sluigi uint32_t pad_size; 2152231437Sluigi uint32_t image_size; 2153231437Sluigi uint32_t cksum; 2154231437Sluigi uint32_t entry_point; 2155231437Sluigi uint32_t rsvd0; 2156231437Sluigi uint32_t rsvd1; 2157231437Sluigi uint8_t ver_data[32]; 2158231437Sluigi}; 2159231437Sluigi 2160231437Sluigistruct flash_sec_info { 2161231437Sluigi uint8_t cookie[32]; 2162231437Sluigi struct flash_section_hdr fsec_hdr; 2163231437Sluigi struct flash_section_entry fsec_entry[32]; 2164231437Sluigi}; 2165231437Sluigi 2166231437Sluigi 2167231437Sluigienum LOWLEVEL_SUBSYSTEM_OPCODES { 2168231437Sluigi/* Opcodes used for lowlevel functions common to many subystems. 2169231437Sluigi * Some of these opcodes are used for diagnostic functions only. 2170231437Sluigi * These opcodes use the MBX_SUBSYSTEM_LOWLEVEL subsystem code. 2171231437Sluigi */ 2172231437Sluigi OPCODE_LOWLEVEL_TEST_LOOPBACK = 18, 2173231437Sluigi OPCODE_LOWLEVEL_SET_LOOPBACK_MODE = 19, 2174231437Sluigi OPCODE_LOWLEVEL_GET_LOOPBACK_MODE = 20 2175231437Sluigi}; 2176231437Sluigi 2177231437Sluigienum LLDP_SUBSYSTEM_OPCODES { 2178231437Sluigi/* Opcodes used for LLDP susbsytem for configuring the LLDP state machines. */ 2179231437Sluigi OPCODE_LLDP_GET_CFG = 1, 2180231437Sluigi OPCODE_LLDP_SET_CFG = 2, 2181231437Sluigi OPCODE_LLDP_GET_STATS = 3 2182231437Sluigi}; 2183231437Sluigi 2184231437Sluigienum DCBX_SUBSYSTEM_OPCODES { 2185231437Sluigi/* Opcodes used for DCBX. */ 2186231437Sluigi OPCODE_DCBX_GET_CFG = 1, 2187231437Sluigi OPCODE_DCBX_SET_CFG = 2, 2188231437Sluigi OPCODE_DCBX_GET_MIB_INFO = 3, 2189231437Sluigi OPCODE_DCBX_GET_DCBX_MODE = 4, 2190231437Sluigi OPCODE_DCBX_SET_MODE = 5 2191231437Sluigi}; 2192231437Sluigi 2193231437Sluigienum DMTF_SUBSYSTEM_OPCODES { 2194231437Sluigi/* Opcodes used for DCBX subsystem. */ 2195231437Sluigi OPCODE_DMTF_EXEC_CLP_CMD = 1 2196231437Sluigi}; 2197231437Sluigi 2198231437Sluigienum DIAG_SUBSYSTEM_OPCODES { 2199231437Sluigi/* Opcodes used for diag functions common to many subsystems. */ 2200231437Sluigi OPCODE_DIAG_RUN_DMA_TEST = 1, 2201231437Sluigi OPCODE_DIAG_RUN_MDIO_TEST = 2, 2202231437Sluigi OPCODE_DIAG_RUN_NLB_TEST = 3, 2203231437Sluigi OPCODE_DIAG_RUN_ARM_TIMER_TEST = 4, 2204231437Sluigi OPCODE_DIAG_GET_MAC = 5 2205231437Sluigi}; 2206231437Sluigi 2207231437Sluigienum VENDOR_SUBSYSTEM_OPCODES { 2208231437Sluigi/* Opcodes used for Vendor subsystem. */ 2209231437Sluigi OPCODE_VENDOR_SLI = 1 2210231437Sluigi}; 2211231437Sluigi 2212231437Sluigi/* Management Status Codes */ 2213231437Sluigienum MGMT_STATUS_SUCCESS { 2214231437Sluigi MGMT_SUCCESS = 0, 2215231437Sluigi MGMT_FAILED = 1, 2216231437Sluigi MGMT_ILLEGAL_REQUEST = 2, 2217231437Sluigi MGMT_ILLEGAL_FIELD = 3, 2218231437Sluigi MGMT_INSUFFICIENT_BUFFER = 4, 2219231437Sluigi MGMT_UNAUTHORIZED_REQUEST = 5, 2220231437Sluigi MGMT_INVALID_ISNS_ADDRESS = 10, 2221231437Sluigi MGMT_INVALID_IPADDR = 11, 2222231437Sluigi MGMT_INVALID_GATEWAY = 12, 2223231437Sluigi MGMT_INVALID_SUBNETMASK = 13, 2224231437Sluigi MGMT_INVALID_TARGET_IPADDR = 16, 2225231437Sluigi MGMT_TGTTBL_FULL = 20, 2226231437Sluigi MGMT_FLASHROM_SAVE_FAILED = 23, 2227231437Sluigi MGMT_IOCTLHANDLE_ALLOC_FAILED = 27, 2228231437Sluigi MGMT_INVALID_SESSION = 31, 2229231437Sluigi MGMT_INVALID_CONNECTION = 32, 2230231437Sluigi MGMT_BTL_PATH_EXCEEDS_OSM_LIMIT = 33, 2231231437Sluigi MGMT_BTL_TGTID_EXCEEDS_OSM_LIMIT = 34, 2232231437Sluigi MGMT_BTL_PATH_TGTID_OCCUPIED = 35, 2233231437Sluigi MGMT_BTL_NO_FREE_SLOT_PATH = 36, 2234231437Sluigi MGMT_BTL_NO_FREE_SLOT_TGTID = 37, 2235231437Sluigi MGMT_POLL_IOCTL_TIMEOUT = 40, 2236231437Sluigi MGMT_ERROR_ACITISCSI = 41, 2237231437Sluigi MGMT_BUFFER_SIZE_EXCEED_OSM_OR_OS_LIMIT = 43, 2238231437Sluigi MGMT_REBOOT_REQUIRED = 44, 2239231437Sluigi MGMT_INSUFFICIENT_TIMEOUT = 45, 2240231437Sluigi MGMT_IPADDR_NOT_SET = 46, 2241231437Sluigi MGMT_IPADDR_DUP_DETECTED = 47, 2242231437Sluigi MGMT_CANT_REMOVE_LAST_CONNECTION = 48, 2243231437Sluigi MGMT_TARGET_BUSY = 49, 2244231437Sluigi MGMT_TGT_ERR_LISTEN_SOCKET = 50, 2245231437Sluigi MGMT_TGT_ERR_BIND_SOCKET = 51, 2246231437Sluigi MGMT_TGT_ERR_NO_SOCKET = 52, 2247231437Sluigi MGMT_TGT_ERR_ISNS_COMM_FAILED = 55, 2248231437Sluigi MGMT_CANNOT_DELETE_BOOT_TARGET = 56, 2249231437Sluigi MGMT_TGT_PORTAL_MODE_IN_LISTEN = 57, 2250231437Sluigi MGMT_FCF_IN_USE = 58 , 2251231437Sluigi MGMT_NO_CQE = 59, 2252231437Sluigi MGMT_TARGET_NOT_FOUND = 65, 2253231437Sluigi MGMT_NOT_SUPPORTED = 66, 2254231437Sluigi MGMT_NO_FCF_RECORDS = 67, 2255231437Sluigi MGMT_FEATURE_NOT_SUPPORTED = 68, 2256231437Sluigi MGMT_VPD_FUNCTION_OUT_OF_RANGE = 69, 2257231437Sluigi MGMT_VPD_FUNCTION_TYPE_INCORRECT = 70, 2258231437Sluigi MGMT_INVALID_NON_EMBEDDED_WRB = 71, 2259231437Sluigi MGMT_OOR = 100, 2260231437Sluigi MGMT_INVALID_PD = 101, 2261231437Sluigi MGMT_STATUS_PD_INUSE = 102, 2262231437Sluigi MGMT_INVALID_CQ = 103, 2263231437Sluigi MGMT_INVALID_QP = 104, 2264231437Sluigi MGMT_INVALID_STAG = 105, 2265231437Sluigi MGMT_ORD_EXCEEDS = 106, 2266231437Sluigi MGMT_IRD_EXCEEDS = 107, 2267231437Sluigi MGMT_SENDQ_WQE_EXCEEDS = 108, 2268231437Sluigi MGMT_RECVQ_RQE_EXCEEDS = 109, 2269231437Sluigi MGMT_SGE_SEND_EXCEEDS = 110, 2270231437Sluigi MGMT_SGE_WRITE_EXCEEDS = 111, 2271231437Sluigi MGMT_SGE_RECV_EXCEEDS = 112, 2272231437Sluigi MGMT_INVALID_STATE_CHANGE = 113, 2273231437Sluigi MGMT_MW_BOUND = 114, 2274231437Sluigi MGMT_INVALID_VA = 115, 2275231437Sluigi MGMT_INVALID_LENGTH = 116, 2276231437Sluigi MGMT_INVALID_FBO = 117, 2277231437Sluigi MGMT_INVALID_ACC_RIGHTS = 118, 2278231437Sluigi MGMT_INVALID_PBE_SIZE = 119, 2279231437Sluigi MGMT_INVALID_PBL_ENTRY = 120, 2280231437Sluigi MGMT_INVALID_PBL_OFFSET = 121, 2281231437Sluigi MGMT_ADDR_NON_EXIST = 122, 2282231437Sluigi MGMT_INVALID_VLANID = 123, 2283231437Sluigi MGMT_INVALID_MTU = 124, 2284231437Sluigi MGMT_INVALID_BACKLOG = 125, 2285231437Sluigi MGMT_CONNECTION_INPROGRESS = 126, 2286231437Sluigi MGMT_INVALID_RQE_SIZE = 127, 2287231437Sluigi MGMT_INVALID_RQE_ENTRY = 128 2288231437Sluigi}; 2289231437Sluigi 2290231437Sluigi/* Additional Management Status Codes */ 2291231437Sluigienum MGMT_ADDI_STATUS { 2292231437Sluigi MGMT_ADDI_NO_STATUS = 0, 2293231437Sluigi MGMT_ADDI_INVALID_IPTYPE = 1, 2294231437Sluigi MGMT_ADDI_TARGET_HANDLE_NOT_FOUND = 9, 2295231437Sluigi MGMT_ADDI_SESSION_HANDLE_NOT_FOUND = 10, 2296231437Sluigi MGMT_ADDI_CONNECTION_HANDLE_NOT_FOUND = 11, 2297231437Sluigi MGMT_ADDI_ACTIVE_SESSIONS_PRESENT = 16, 2298231437Sluigi MGMT_ADDI_SESSION_ALREADY_OPENED = 17, 2299231437Sluigi MGMT_ADDI_SESSION_ALREADY_CLOSED = 18, 2300231437Sluigi MGMT_ADDI_DEST_HOST_UNREACHABLE = 19, 2301231437Sluigi MGMT_ADDI_LOGIN_IN_PROGRESS = 20, 2302231437Sluigi MGMT_ADDI_TCP_CONNECT_FAILED = 21, 2303231437Sluigi MGMT_ADDI_INSUFFICIENT_RESOURCES = 22, 2304231437Sluigi MGMT_ADDI_LINK_DOWN = 23, 2305231437Sluigi MGMT_ADDI_DHCP_ERROR = 24, 2306231437Sluigi MGMT_ADDI_CONNECTION_OFFLOADED = 25, 2307231437Sluigi MGMT_ADDI_CONNECTION_NOT_OFFLOADED = 26, 2308231437Sluigi MGMT_ADDI_CONNECTION_UPLOAD_IN_PROGRESS = 27, 2309231437Sluigi MGMT_ADDI_REQUEST_REJECTED = 28, 2310231437Sluigi MGMT_ADDI_INVALID_SUBSYSTEM = 29, 2311231437Sluigi MGMT_ADDI_INVALID_OPCODE = 30, 2312231437Sluigi MGMT_ADDI_INVALID_MAXCONNECTION_PARAM = 31, 2313231437Sluigi MGMT_ADDI_INVALID_KEY = 32, 2314231437Sluigi MGMT_ADDI_INVALID_DOMAIN = 35, 2315231437Sluigi MGMT_ADDI_LOGIN_INITIATOR_ERROR = 43, 2316231437Sluigi MGMT_ADDI_LOGIN_AUTHENTICATION_ERROR = 44, 2317231437Sluigi MGMT_ADDI_LOGIN_AUTHORIZATION_ERROR = 45, 2318231437Sluigi MGMT_ADDI_LOGIN_NOT_FOUND = 46, 2319231437Sluigi MGMT_ADDI_LOGIN_TARGET_REMOVED = 47, 2320231437Sluigi MGMT_ADDI_LOGIN_UNSUPPORTED_VERSION = 48, 2321231437Sluigi MGMT_ADDI_LOGIN_TOO_MANY_CONNECTIONS = 49, 2322231437Sluigi MGMT_ADDI_LOGIN_MISSING_PARAMETER = 50, 2323231437Sluigi MGMT_ADDI_LOGIN_NO_SESSION_SPANNING = 51, 2324231437Sluigi MGMT_ADDI_LOGIN_SESSION_TYPE_NOT_SUPPORTED = 52, 2325231437Sluigi MGMT_ADDI_LOGIN_SESSION_DOES_NOT_EXIST = 53, 2326231437Sluigi MGMT_ADDI_LOGIN_INVALID_DURING_LOGIN = 54, 2327231437Sluigi MGMT_ADDI_LOGIN_TARGET_ERROR = 55, 2328231437Sluigi MGMT_ADDI_LOGIN_SERVICE_UNAVAILABLE = 56, 2329231437Sluigi MGMT_ADDI_LOGIN_OUT_OF_RESOURCES = 57, 2330231437Sluigi MGMT_ADDI_SAME_CHAP_SECRET = 58, 2331231437Sluigi MGMT_ADDI_INVALID_SECRET_LENGTH = 59, 2332231437Sluigi MGMT_ADDI_DUPLICATE_ENTRY = 60, 2333231437Sluigi MGMT_ADDI_SETTINGS_MODIFIED_REBOOT_REQD = 63, 2334231437Sluigi MGMT_ADDI_INVALID_EXTENDED_TIMEOUT = 64, 2335231437Sluigi MGMT_ADDI_INVALID_INTERFACE_HANDLE = 65, 2336231437Sluigi MGMT_ADDI_ERR_VLAN_ON_DEF_INTERFACE = 66, 2337231437Sluigi MGMT_ADDI_INTERFACE_DOES_NOT_EXIST = 67, 2338231437Sluigi MGMT_ADDI_INTERFACE_ALREADY_EXISTS = 68, 2339231437Sluigi MGMT_ADDI_INVALID_VLAN_RANGE = 69, 2340231437Sluigi MGMT_ADDI_ERR_SET_VLAN = 70, 2341231437Sluigi MGMT_ADDI_ERR_DEL_VLAN = 71, 2342231437Sluigi MGMT_ADDI_CANNOT_DEL_DEF_INTERFACE = 72, 2343231437Sluigi MGMT_ADDI_DHCP_REQ_ALREADY_PENDING = 73, 2344231437Sluigi MGMT_ADDI_TOO_MANY_INTERFACES = 74, 2345231437Sluigi MGMT_ADDI_INVALID_REQUEST = 75 2346231437Sluigi}; 2347231437Sluigi 2348231437Sluigienum NIC_SUBSYSTEM_OPCODES { 2349231437Sluigi/** 2350231437Sluigi * @brief NIC Subsystem Opcodes (see Network SLI-4 manual >= Rev4, v21-2) 2351231437Sluigi * These opcodes are used for configuring the Ethernet interfaces. 2352231437Sluigi * These opcodes all use the MBX_SUBSYSTEM_NIC subsystem code. 2353231437Sluigi */ 2354231437Sluigi NIC_CONFIG_RSS = 1, 2355231437Sluigi NIC_CONFIG_ACPI = 2, 2356231437Sluigi NIC_CONFIG_PROMISCUOUS = 3, 2357231437Sluigi NIC_GET_STATS = 4, 2358231437Sluigi NIC_CREATE_WQ = 7, 2359231437Sluigi NIC_CREATE_RQ = 8, 2360231437Sluigi NIC_DELETE_WQ = 9, 2361231437Sluigi NIC_DELETE_RQ = 10, 2362231437Sluigi NIC_CONFIG_ACPI_WOL_MAGIC = 12, 2363231437Sluigi NIC_GET_NETWORK_STATS = 13, 2364231437Sluigi NIC_CREATE_HDS_RQ = 16, 2365231437Sluigi NIC_DELETE_HDS_RQ = 17, 2366231437Sluigi NIC_GET_PPORT_STATS = 18, 2367231437Sluigi NIC_GET_VPORT_STATS = 19, 2368231437Sluigi NIC_GET_QUEUE_STATS = 20 2369231437Sluigi}; 2370231437Sluigi 2371231437Sluigi/* Hash option flags for RSS enable */ 2372231437Sluigienum RSS_ENABLE_FLAGS { 2373231437Sluigi RSS_ENABLE_NONE = 0x0, /* (No RSS) */ 2374231437Sluigi RSS_ENABLE_IPV4 = 0x1, /* (IPV4 HASH enabled ) */ 2375231437Sluigi RSS_ENABLE_TCP_IPV4 = 0x2, /* (TCP IPV4 Hash enabled) */ 2376231437Sluigi RSS_ENABLE_IPV6 = 0x4, /* (IPV6 HASH enabled) */ 2377247880Sdelphij RSS_ENABLE_TCP_IPV6 = 0x8, /* (TCP IPV6 HASH */ 2378247880Sdelphij RSS_ENABLE_UDP_IPV4 = 0x10, /* UDP IPV4 HASH */ 2379247880Sdelphij RSS_ENABLE_UDP_IPV6 = 0x20 /* UDP IPV6 HASH */ 2380231437Sluigi}; 2381231437Sluigi#define RSS_ENABLE (RSS_ENABLE_IPV4 | RSS_ENABLE_TCP_IPV4) 2382231437Sluigi#define RSS_DISABLE RSS_ENABLE_NONE 2383231437Sluigi 2384231437Sluigi/* NIC header WQE */ 2385231437Sluigistruct oce_nic_hdr_wqe { 2386231437Sluigi union { 2387231437Sluigi struct { 2388231437Sluigi#ifdef _BIG_ENDIAN 2389231437Sluigi /* dw0 */ 2390231437Sluigi uint32_t rsvd0; 2391231437Sluigi 2392231437Sluigi /* dw1 */ 2393231437Sluigi uint32_t last_seg_udp_len:14; 2394231437Sluigi uint32_t rsvd1:18; 2395231437Sluigi 2396231437Sluigi /* dw2 */ 2397231437Sluigi uint32_t lso_mss:14; 2398231437Sluigi uint32_t num_wqe:5; 2399231437Sluigi uint32_t rsvd4:2; 2400231437Sluigi uint32_t vlan:1; 2401231437Sluigi uint32_t lso:1; 2402231437Sluigi uint32_t tcpcs:1; 2403231437Sluigi uint32_t udpcs:1; 2404231437Sluigi uint32_t ipcs:1; 2405231437Sluigi uint32_t rsvd3:1; 2406231437Sluigi uint32_t rsvd2:1; 2407231437Sluigi uint32_t forward:1; 2408231437Sluigi uint32_t crc:1; 2409231437Sluigi uint32_t event:1; 2410231437Sluigi uint32_t complete:1; 2411231437Sluigi 2412231437Sluigi /* dw3 */ 2413231437Sluigi uint32_t vlan_tag:16; 2414231437Sluigi uint32_t total_length:16; 2415231437Sluigi#else 2416231437Sluigi /* dw0 */ 2417231437Sluigi uint32_t rsvd0; 2418231437Sluigi 2419231437Sluigi /* dw1 */ 2420231437Sluigi uint32_t rsvd1:18; 2421231437Sluigi uint32_t last_seg_udp_len:14; 2422231437Sluigi 2423231437Sluigi /* dw2 */ 2424231437Sluigi uint32_t complete:1; 2425231437Sluigi uint32_t event:1; 2426231437Sluigi uint32_t crc:1; 2427231437Sluigi uint32_t forward:1; 2428231437Sluigi uint32_t rsvd2:1; 2429231437Sluigi uint32_t rsvd3:1; 2430231437Sluigi uint32_t ipcs:1; 2431231437Sluigi uint32_t udpcs:1; 2432231437Sluigi uint32_t tcpcs:1; 2433231437Sluigi uint32_t lso:1; 2434231437Sluigi uint32_t vlan:1; 2435231437Sluigi uint32_t rsvd4:2; 2436231437Sluigi uint32_t num_wqe:5; 2437231437Sluigi uint32_t lso_mss:14; 2438231437Sluigi 2439231437Sluigi /* dw3 */ 2440231437Sluigi uint32_t total_length:16; 2441231437Sluigi uint32_t vlan_tag:16; 2442231437Sluigi#endif 2443231437Sluigi } s; 2444231437Sluigi uint32_t dw[4]; 2445231437Sluigi } u0; 2446231437Sluigi}; 2447231437Sluigi 2448231437Sluigi/* NIC fragment WQE */ 2449231437Sluigistruct oce_nic_frag_wqe { 2450231437Sluigi union { 2451231437Sluigi struct { 2452231437Sluigi /* dw0 */ 2453231437Sluigi uint32_t frag_pa_hi; 2454231437Sluigi /* dw1 */ 2455231437Sluigi uint32_t frag_pa_lo; 2456231437Sluigi /* dw2 */ 2457231437Sluigi uint32_t rsvd0; 2458231437Sluigi uint32_t frag_len; 2459231437Sluigi } s; 2460231437Sluigi uint32_t dw[4]; 2461231437Sluigi } u0; 2462231437Sluigi}; 2463231437Sluigi 2464231437Sluigi/* Ethernet Tx Completion Descriptor */ 2465231437Sluigistruct oce_nic_tx_cqe { 2466231437Sluigi union { 2467231437Sluigi struct { 2468231437Sluigi#ifdef _BIG_ENDIAN 2469231437Sluigi /* dw 0 */ 2470231437Sluigi uint32_t status:4; 2471231437Sluigi uint32_t rsvd0:8; 2472231437Sluigi uint32_t port:2; 2473231437Sluigi uint32_t ct:2; 2474231437Sluigi uint32_t wqe_index:16; 2475231437Sluigi 2476231437Sluigi /* dw 1 */ 2477231437Sluigi uint32_t rsvd1:5; 2478231437Sluigi uint32_t cast_enc:2; 2479231437Sluigi uint32_t lso:1; 2480231437Sluigi uint32_t nwh_bytes:8; 2481231437Sluigi uint32_t user_bytes:16; 2482231437Sluigi 2483231437Sluigi /* dw 2 */ 2484231437Sluigi uint32_t rsvd2; 2485231437Sluigi 2486231437Sluigi /* dw 3 */ 2487231437Sluigi uint32_t valid:1; 2488231437Sluigi uint32_t rsvd3:4; 2489231437Sluigi uint32_t wq_id:11; 2490231437Sluigi uint32_t num_pkts:16; 2491231437Sluigi#else 2492231437Sluigi /* dw 0 */ 2493231437Sluigi uint32_t wqe_index:16; 2494231437Sluigi uint32_t ct:2; 2495231437Sluigi uint32_t port:2; 2496231437Sluigi uint32_t rsvd0:8; 2497231437Sluigi uint32_t status:4; 2498231437Sluigi 2499231437Sluigi /* dw 1 */ 2500231437Sluigi uint32_t user_bytes:16; 2501231437Sluigi uint32_t nwh_bytes:8; 2502231437Sluigi uint32_t lso:1; 2503231437Sluigi uint32_t cast_enc:2; 2504231437Sluigi uint32_t rsvd1:5; 2505231437Sluigi /* dw 2 */ 2506231437Sluigi uint32_t rsvd2; 2507231437Sluigi 2508231437Sluigi /* dw 3 */ 2509231437Sluigi uint32_t num_pkts:16; 2510231437Sluigi uint32_t wq_id:11; 2511231437Sluigi uint32_t rsvd3:4; 2512231437Sluigi uint32_t valid:1; 2513231437Sluigi#endif 2514231437Sluigi } s; 2515231437Sluigi uint32_t dw[4]; 2516231437Sluigi } u0; 2517231437Sluigi}; 2518231437Sluigi#define WQ_CQE_VALID(_cqe) (_cqe->u0.dw[3]) 2519231437Sluigi#define WQ_CQE_INVALIDATE(_cqe) (_cqe->u0.dw[3] = 0) 2520231437Sluigi 2521231437Sluigi/* Receive Queue Entry (RQE) */ 2522231437Sluigistruct oce_nic_rqe { 2523231437Sluigi union { 2524231437Sluigi struct { 2525231437Sluigi uint32_t frag_pa_hi; 2526231437Sluigi uint32_t frag_pa_lo; 2527231437Sluigi } s; 2528231437Sluigi uint32_t dw[2]; 2529231437Sluigi } u0; 2530231437Sluigi}; 2531231437Sluigi 2532231437Sluigi/* NIC Receive CQE */ 2533231437Sluigistruct oce_nic_rx_cqe { 2534231437Sluigi union { 2535231437Sluigi struct { 2536231437Sluigi#ifdef _BIG_ENDIAN 2537231437Sluigi /* dw 0 */ 2538231437Sluigi uint32_t ip_options:1; 2539231437Sluigi uint32_t port:1; 2540231437Sluigi uint32_t pkt_size:14; 2541231437Sluigi uint32_t vlan_tag:16; 2542231437Sluigi 2543231437Sluigi /* dw 1 */ 2544231437Sluigi uint32_t num_fragments:3; 2545231437Sluigi uint32_t switched:1; 2546231437Sluigi uint32_t ct:2; 2547231437Sluigi uint32_t frag_index:10; 2548231437Sluigi uint32_t rsvd0:1; 2549231437Sluigi uint32_t vlan_tag_present:1; 2550231437Sluigi uint32_t mac_dst:6; 2551231437Sluigi uint32_t ip_ver:1; 2552231437Sluigi uint32_t l4_cksum_pass:1; 2553231437Sluigi uint32_t ip_cksum_pass:1; 2554231437Sluigi uint32_t udpframe:1; 2555231437Sluigi uint32_t tcpframe:1; 2556231437Sluigi uint32_t ipframe:1; 2557231437Sluigi uint32_t rss_hp:1; 2558231437Sluigi uint32_t error:1; 2559231437Sluigi 2560231437Sluigi /* dw 2 */ 2561231437Sluigi uint32_t valid:1; 2562231437Sluigi uint32_t hds_type:2; 2563231437Sluigi uint32_t lro_pkt:1; 2564231437Sluigi uint32_t rsvd4:1; 2565231437Sluigi uint32_t hds_hdr_size:12; 2566231437Sluigi uint32_t hds_hdr_frag_index:10; 2567231437Sluigi uint32_t rss_bank:1; 2568231437Sluigi uint32_t qnq:1; 2569231437Sluigi uint32_t pkt_type:2; 2570231437Sluigi uint32_t rss_flush:1; 2571231437Sluigi 2572231437Sluigi /* dw 3 */ 2573231437Sluigi uint32_t rss_hash_value; 2574231437Sluigi#else 2575231437Sluigi /* dw 0 */ 2576231437Sluigi uint32_t vlan_tag:16; 2577231437Sluigi uint32_t pkt_size:14; 2578231437Sluigi uint32_t port:1; 2579231437Sluigi uint32_t ip_options:1; 2580231437Sluigi /* dw 1 */ 2581231437Sluigi uint32_t error:1; 2582231437Sluigi uint32_t rss_hp:1; 2583231437Sluigi uint32_t ipframe:1; 2584231437Sluigi uint32_t tcpframe:1; 2585231437Sluigi uint32_t udpframe:1; 2586231437Sluigi uint32_t ip_cksum_pass:1; 2587231437Sluigi uint32_t l4_cksum_pass:1; 2588231437Sluigi uint32_t ip_ver:1; 2589231437Sluigi uint32_t mac_dst:6; 2590231437Sluigi uint32_t vlan_tag_present:1; 2591231437Sluigi uint32_t rsvd0:1; 2592231437Sluigi uint32_t frag_index:10; 2593231437Sluigi uint32_t ct:2; 2594231437Sluigi uint32_t switched:1; 2595231437Sluigi uint32_t num_fragments:3; 2596231437Sluigi 2597231437Sluigi /* dw 2 */ 2598231437Sluigi uint32_t rss_flush:1; 2599231437Sluigi uint32_t pkt_type:2; 2600231437Sluigi uint32_t qnq:1; 2601231437Sluigi uint32_t rss_bank:1; 2602231437Sluigi uint32_t hds_hdr_frag_index:10; 2603231437Sluigi uint32_t hds_hdr_size:12; 2604231437Sluigi uint32_t rsvd4:1; 2605231437Sluigi uint32_t lro_pkt:1; 2606231437Sluigi uint32_t hds_type:2; 2607231437Sluigi uint32_t valid:1; 2608231437Sluigi /* dw 3 */ 2609231437Sluigi uint32_t rss_hash_value; 2610231437Sluigi#endif 2611231437Sluigi } s; 2612231437Sluigi uint32_t dw[4]; 2613231437Sluigi } u0; 2614231437Sluigi}; 2615231437Sluigi/* NIC Receive CQE_v1 */ 2616231437Sluigistruct oce_nic_rx_cqe_v1 { 2617231437Sluigi union { 2618231437Sluigi struct { 2619231437Sluigi#ifdef _BIG_ENDIAN 2620231437Sluigi /* dw 0 */ 2621231437Sluigi uint32_t ip_options:1; 2622231437Sluigi uint32_t vlan_tag_present:1; 2623231437Sluigi uint32_t pkt_size:14; 2624231437Sluigi uint32_t vlan_tag:16; 2625231437Sluigi 2626231437Sluigi /* dw 1 */ 2627231437Sluigi uint32_t num_fragments:3; 2628231437Sluigi uint32_t switched:1; 2629231437Sluigi uint32_t ct:2; 2630231437Sluigi uint32_t frag_index:10; 2631231437Sluigi uint32_t rsvd0:1; 2632231437Sluigi uint32_t mac_dst:7; 2633231437Sluigi uint32_t ip_ver:1; 2634231437Sluigi uint32_t l4_cksum_pass:1; 2635231437Sluigi uint32_t ip_cksum_pass:1; 2636231437Sluigi uint32_t udpframe:1; 2637231437Sluigi uint32_t tcpframe:1; 2638231437Sluigi uint32_t ipframe:1; 2639231437Sluigi uint32_t rss_hp:1; 2640231437Sluigi uint32_t error:1; 2641231437Sluigi 2642231437Sluigi /* dw 2 */ 2643231437Sluigi uint32_t valid:1; 2644231437Sluigi uint32_t rsvd4:13; 2645231437Sluigi uint32_t hds_hdr_size: 2646231437Sluigi uint32_t hds_hdr_frag_index:8; 2647231437Sluigi uint32_t vlantag:1; 2648231437Sluigi uint32_t port:2; 2649231437Sluigi uint32_t rss_bank:1; 2650231437Sluigi uint32_t qnq:1; 2651231437Sluigi uint32_t pkt_type:2; 2652231437Sluigi uint32_t rss_flush:1; 2653231437Sluigi 2654231437Sluigi /* dw 3 */ 2655231437Sluigi uint32_t rss_hash_value; 2656231437Sluigi #else 2657231437Sluigi /* dw 0 */ 2658231437Sluigi uint32_t vlan_tag:16; 2659231437Sluigi uint32_t pkt_size:14; 2660231437Sluigi uint32_t vlan_tag_present:1; 2661231437Sluigi uint32_t ip_options:1; 2662231437Sluigi /* dw 1 */ 2663231437Sluigi uint32_t error:1; 2664231437Sluigi uint32_t rss_hp:1; 2665231437Sluigi uint32_t ipframe:1; 2666231437Sluigi uint32_t tcpframe:1; 2667231437Sluigi uint32_t udpframe:1; 2668231437Sluigi uint32_t ip_cksum_pass:1; 2669231437Sluigi uint32_t l4_cksum_pass:1; 2670231437Sluigi uint32_t ip_ver:1; 2671231437Sluigi uint32_t mac_dst:7; 2672231437Sluigi uint32_t rsvd0:1; 2673231437Sluigi uint32_t frag_index:10; 2674231437Sluigi uint32_t ct:2; 2675231437Sluigi uint32_t switched:1; 2676231437Sluigi uint32_t num_fragments:3; 2677231437Sluigi 2678231437Sluigi /* dw 2 */ 2679231437Sluigi uint32_t rss_flush:1; 2680231437Sluigi uint32_t pkt_type:2; 2681231437Sluigi uint32_t qnq:1; 2682231437Sluigi uint32_t rss_bank:1; 2683231437Sluigi uint32_t port:2; 2684231437Sluigi uint32_t vlantag:1; 2685231437Sluigi uint32_t hds_hdr_frag_index:8; 2686231437Sluigi uint32_t hds_hdr_size:2; 2687231437Sluigi uint32_t rsvd4:13; 2688231437Sluigi uint32_t valid:1; 2689231437Sluigi /* dw 3 */ 2690231437Sluigi uint32_t rss_hash_value; 2691231437Sluigi#endif 2692231437Sluigi } s; 2693231437Sluigi uint32_t dw[4]; 2694231437Sluigi } u0; 2695231437Sluigi}; 2696231437Sluigi 2697231437Sluigi#define RQ_CQE_VALID_MASK 0x80 2698231437Sluigi#define RQ_CQE_VALID(_cqe) (_cqe->u0.dw[2]) 2699231437Sluigi#define RQ_CQE_INVALIDATE(_cqe) (_cqe->u0.dw[2] = 0) 2700231437Sluigi 2701231437Sluigistruct mbx_config_nic_promiscuous { 2702231437Sluigi struct mbx_hdr hdr; 2703231437Sluigi union { 2704231437Sluigi struct { 2705231437Sluigi#ifdef _BIG_ENDIAN 2706231437Sluigi uint16_t rsvd0; 2707231437Sluigi uint8_t port1_promisc; 2708231437Sluigi uint8_t port0_promisc; 2709231437Sluigi#else 2710231437Sluigi uint8_t port0_promisc; 2711231437Sluigi uint8_t port1_promisc; 2712231437Sluigi uint16_t rsvd0; 2713231437Sluigi#endif 2714231437Sluigi } req; 2715231437Sluigi 2716231437Sluigi struct { 2717231437Sluigi uint32_t rsvd0; 2718231437Sluigi } rsp; 2719231437Sluigi } params; 2720231437Sluigi}; 2721231437Sluigi 2722231437Sluigitypedef union oce_wq_ctx_u { 2723231437Sluigi uint32_t dw[17]; 2724231437Sluigi struct { 2725231437Sluigi#ifdef _BIG_ENDIAN 2726231437Sluigi /* dw4 */ 2727231437Sluigi uint32_t dw4rsvd2:8; 2728231437Sluigi uint32_t nic_wq_type:8; 2729231437Sluigi uint32_t dw4rsvd1:8; 2730231437Sluigi uint32_t num_pages:8; 2731231437Sluigi /* dw5 */ 2732231437Sluigi uint32_t dw5rsvd2:12; 2733231437Sluigi uint32_t wq_size:4; 2734231437Sluigi uint32_t dw5rsvd1:16; 2735231437Sluigi /* dw6 */ 2736231437Sluigi uint32_t valid:1; 2737231437Sluigi uint32_t dw6rsvd1:31; 2738231437Sluigi /* dw7 */ 2739231437Sluigi uint32_t dw7rsvd1:16; 2740231437Sluigi uint32_t cq_id:16; 2741231437Sluigi#else 2742231437Sluigi /* dw4 */ 2743231437Sluigi uint32_t num_pages:8; 2744231437Sluigi#if 0 2745231437Sluigi uint32_t dw4rsvd1:8; 2746231437Sluigi#else 2747231437Sluigi/* PSP: this workaround is not documented: fill 0x01 for ulp_mask */ 2748231437Sluigi uint32_t ulp_mask:8; 2749231437Sluigi#endif 2750231437Sluigi uint32_t nic_wq_type:8; 2751231437Sluigi uint32_t dw4rsvd2:8; 2752231437Sluigi /* dw5 */ 2753231437Sluigi uint32_t dw5rsvd1:16; 2754231437Sluigi uint32_t wq_size:4; 2755231437Sluigi uint32_t dw5rsvd2:12; 2756231437Sluigi /* dw6 */ 2757231437Sluigi uint32_t dw6rsvd1:31; 2758231437Sluigi uint32_t valid:1; 2759231437Sluigi /* dw7 */ 2760231437Sluigi uint32_t cq_id:16; 2761231437Sluigi uint32_t dw7rsvd1:16; 2762231437Sluigi#endif 2763231437Sluigi /* dw8 - dw20 */ 2764231437Sluigi uint32_t dw8_20rsvd1[13]; 2765231437Sluigi } v0; 2766231437Sluigi struct { 2767231437Sluigi#ifdef _BIG_ENDIAN 2768231437Sluigi /* dw4 */ 2769231437Sluigi uint32_t dw4rsvd2:8; 2770231437Sluigi uint32_t nic_wq_type:8; 2771231437Sluigi uint32_t dw4rsvd1:8; 2772231437Sluigi uint32_t num_pages:8; 2773231437Sluigi /* dw5 */ 2774231437Sluigi uint32_t dw5rsvd2:12; 2775231437Sluigi uint32_t wq_size:4; 2776231437Sluigi uint32_t iface_id:16; 2777231437Sluigi /* dw6 */ 2778231437Sluigi uint32_t valid:1; 2779231437Sluigi uint32_t dw6rsvd1:31; 2780231437Sluigi /* dw7 */ 2781231437Sluigi uint32_t dw7rsvd1:16; 2782231437Sluigi uint32_t cq_id:16; 2783231437Sluigi#else 2784231437Sluigi /* dw4 */ 2785231437Sluigi uint32_t num_pages:8; 2786231437Sluigi uint32_t dw4rsvd1:8; 2787231437Sluigi uint32_t nic_wq_type:8; 2788231437Sluigi uint32_t dw4rsvd2:8; 2789231437Sluigi /* dw5 */ 2790231437Sluigi uint32_t iface_id:16; 2791231437Sluigi uint32_t wq_size:4; 2792231437Sluigi uint32_t dw5rsvd2:12; 2793231437Sluigi /* dw6 */ 2794231437Sluigi uint32_t dw6rsvd1:31; 2795231437Sluigi uint32_t valid:1; 2796231437Sluigi /* dw7 */ 2797231437Sluigi uint32_t cq_id:16; 2798231437Sluigi uint32_t dw7rsvd1:16; 2799231437Sluigi#endif 2800231437Sluigi /* dw8 - dw20 */ 2801231437Sluigi uint32_t dw8_20rsvd1[13]; 2802231437Sluigi } v1; 2803231437Sluigi} oce_wq_ctx_t; 2804231437Sluigi 2805231437Sluigi/** 2806231437Sluigi * @brief [07] NIC_CREATE_WQ 2807231437Sluigi * @note 2808231437Sluigi * Lancer requires an InterfaceID to be specified with every WQ. This 2809231437Sluigi * is the basis for NIC IOV where the Interface maps to a vPort and maps 2810231437Sluigi * to both Tx and Rx sides. 2811231437Sluigi */ 2812231437Sluigi#define OCE_WQ_TYPE_FORWARDING 0x1 /* wq forwards pkts to TOE */ 2813231437Sluigi#define OCE_WQ_TYPE_STANDARD 0x2 /* wq sends network pkts */ 2814231437Sluigistruct mbx_create_nic_wq { 2815231437Sluigi struct mbx_hdr hdr; 2816231437Sluigi union { 2817231437Sluigi struct { 2818231437Sluigi uint8_t num_pages; 2819231437Sluigi uint8_t ulp_num; 2820231437Sluigi uint16_t nic_wq_type; 2821231437Sluigi uint16_t if_id; 2822231437Sluigi uint8_t wq_size; 2823231437Sluigi uint8_t rsvd1; 2824231437Sluigi uint32_t rsvd2; 2825231437Sluigi uint16_t cq_id; 2826231437Sluigi uint16_t rsvd3; 2827231437Sluigi uint32_t rsvd4[13]; 2828231437Sluigi struct phys_addr pages[8]; 2829231437Sluigi 2830231437Sluigi } req; 2831231437Sluigi 2832231437Sluigi struct { 2833231437Sluigi uint16_t wq_id; 2834231437Sluigi uint16_t rid; 2835231437Sluigi uint32_t db_offset; 2836231437Sluigi uint8_t tc_id; 2837231437Sluigi uint8_t rsvd0[3]; 2838231437Sluigi } rsp; 2839231437Sluigi } params; 2840231437Sluigi}; 2841231437Sluigi 2842231437Sluigi/* [09] NIC_DELETE_WQ */ 2843231437Sluigistruct mbx_delete_nic_wq { 2844231437Sluigi /* dw0 - dw3 */ 2845231437Sluigi struct mbx_hdr hdr; 2846231437Sluigi union { 2847231437Sluigi struct { 2848231437Sluigi#ifdef _BIG_ENDIAN 2849231437Sluigi /* dw4 */ 2850231437Sluigi uint16_t rsvd0; 2851231437Sluigi uint16_t wq_id; 2852231437Sluigi#else 2853231437Sluigi /* dw4 */ 2854231437Sluigi uint16_t wq_id; 2855231437Sluigi uint16_t rsvd0; 2856231437Sluigi#endif 2857231437Sluigi } req; 2858231437Sluigi struct { 2859231437Sluigi uint32_t rsvd0; 2860231437Sluigi } rsp; 2861231437Sluigi } params; 2862231437Sluigi}; 2863231437Sluigi 2864231437Sluigi 2865231437Sluigi 2866231437Sluigistruct mbx_create_nic_rq { 2867231437Sluigi struct mbx_hdr hdr; 2868231437Sluigi union { 2869231437Sluigi struct { 2870231437Sluigi uint16_t cq_id; 2871231437Sluigi uint8_t frag_size; 2872231437Sluigi uint8_t num_pages; 2873231437Sluigi struct phys_addr pages[2]; 2874231437Sluigi uint32_t if_id; 2875231437Sluigi uint16_t max_frame_size; 2876231437Sluigi uint16_t page_size; 2877231437Sluigi uint32_t is_rss_queue; 2878231437Sluigi } req; 2879231437Sluigi 2880231437Sluigi struct { 2881231437Sluigi uint16_t rq_id; 2882231437Sluigi uint8_t rss_cpuid; 2883231437Sluigi uint8_t rsvd0; 2884231437Sluigi } rsp; 2885231437Sluigi 2886231437Sluigi } params; 2887231437Sluigi}; 2888231437Sluigi 2889231437Sluigi 2890231437Sluigi 2891231437Sluigi/* [10] NIC_DELETE_RQ */ 2892231437Sluigistruct mbx_delete_nic_rq { 2893231437Sluigi /* dw0 - dw3 */ 2894231437Sluigi struct mbx_hdr hdr; 2895231437Sluigi union { 2896231437Sluigi struct { 2897231437Sluigi#ifdef _BIG_ENDIAN 2898231437Sluigi /* dw4 */ 2899231437Sluigi uint16_t bypass_flush; 2900231437Sluigi uint16_t rq_id; 2901231437Sluigi#else 2902231437Sluigi /* dw4 */ 2903231437Sluigi uint16_t rq_id; 2904231437Sluigi uint16_t bypass_flush; 2905231437Sluigi#endif 2906231437Sluigi } req; 2907231437Sluigi 2908231437Sluigi struct { 2909231437Sluigi /* dw4 */ 2910231437Sluigi uint32_t rsvd0; 2911231437Sluigi } rsp; 2912231437Sluigi } params; 2913231437Sluigi}; 2914231437Sluigi 2915231437Sluigi 2916231437Sluigi 2917231437Sluigi 2918231437Sluigistruct oce_port_rxf_stats_v0 { 2919231437Sluigi uint32_t rx_bytes_lsd; /* dword 0*/ 2920231437Sluigi uint32_t rx_bytes_msd; /* dword 1*/ 2921231437Sluigi uint32_t rx_total_frames; /* dword 2*/ 2922231437Sluigi uint32_t rx_unicast_frames; /* dword 3*/ 2923231437Sluigi uint32_t rx_multicast_frames; /* dword 4*/ 2924231437Sluigi uint32_t rx_broadcast_frames; /* dword 5*/ 2925231437Sluigi uint32_t rx_crc_errors; /* dword 6*/ 2926231437Sluigi uint32_t rx_alignment_symbol_errors; /* dword 7*/ 2927231437Sluigi uint32_t rx_pause_frames; /* dword 8*/ 2928231437Sluigi uint32_t rx_control_frames; /* dword 9*/ 2929231437Sluigi uint32_t rx_in_range_errors; /* dword 10*/ 2930231437Sluigi uint32_t rx_out_range_errors; /* dword 11*/ 2931231437Sluigi uint32_t rx_frame_too_long; /* dword 12*/ 2932231437Sluigi uint32_t rx_address_match_errors; /* dword 13*/ 2933231437Sluigi uint32_t rx_vlan_mismatch; /* dword 14*/ 2934231437Sluigi uint32_t rx_dropped_too_small; /* dword 15*/ 2935231437Sluigi uint32_t rx_dropped_too_short; /* dword 16*/ 2936231437Sluigi uint32_t rx_dropped_header_too_small; /* dword 17*/ 2937231437Sluigi uint32_t rx_dropped_tcp_length; /* dword 18*/ 2938231437Sluigi uint32_t rx_dropped_runt; /* dword 19*/ 2939231437Sluigi uint32_t rx_64_byte_packets; /* dword 20*/ 2940231437Sluigi uint32_t rx_65_127_byte_packets; /* dword 21*/ 2941231437Sluigi uint32_t rx_128_256_byte_packets; /* dword 22*/ 2942231437Sluigi uint32_t rx_256_511_byte_packets; /* dword 23*/ 2943231437Sluigi uint32_t rx_512_1023_byte_packets; /* dword 24*/ 2944231437Sluigi uint32_t rx_1024_1518_byte_packets; /* dword 25*/ 2945231437Sluigi uint32_t rx_1519_2047_byte_packets; /* dword 26*/ 2946231437Sluigi uint32_t rx_2048_4095_byte_packets; /* dword 27*/ 2947231437Sluigi uint32_t rx_4096_8191_byte_packets; /* dword 28*/ 2948231437Sluigi uint32_t rx_8192_9216_byte_packets; /* dword 29*/ 2949231437Sluigi uint32_t rx_ip_checksum_errs; /* dword 30*/ 2950231437Sluigi uint32_t rx_tcp_checksum_errs; /* dword 31*/ 2951231437Sluigi uint32_t rx_udp_checksum_errs; /* dword 32*/ 2952231437Sluigi uint32_t rx_non_rss_packets; /* dword 33*/ 2953231437Sluigi uint32_t rx_ipv4_packets; /* dword 34*/ 2954231437Sluigi uint32_t rx_ipv6_packets; /* dword 35*/ 2955231437Sluigi uint32_t rx_ipv4_bytes_lsd; /* dword 36*/ 2956231437Sluigi uint32_t rx_ipv4_bytes_msd; /* dword 37*/ 2957231437Sluigi uint32_t rx_ipv6_bytes_lsd; /* dword 38*/ 2958231437Sluigi uint32_t rx_ipv6_bytes_msd; /* dword 39*/ 2959231437Sluigi uint32_t rx_chute1_packets; /* dword 40*/ 2960231437Sluigi uint32_t rx_chute2_packets; /* dword 41*/ 2961231437Sluigi uint32_t rx_chute3_packets; /* dword 42*/ 2962231437Sluigi uint32_t rx_management_packets; /* dword 43*/ 2963231437Sluigi uint32_t rx_switched_unicast_packets; /* dword 44*/ 2964231437Sluigi uint32_t rx_switched_multicast_packets; /* dword 45*/ 2965231437Sluigi uint32_t rx_switched_broadcast_packets; /* dword 46*/ 2966231437Sluigi uint32_t tx_bytes_lsd; /* dword 47*/ 2967231437Sluigi uint32_t tx_bytes_msd; /* dword 48*/ 2968231437Sluigi uint32_t tx_unicastframes; /* dword 49*/ 2969231437Sluigi uint32_t tx_multicastframes; /* dword 50*/ 2970231437Sluigi uint32_t tx_broadcastframes; /* dword 51*/ 2971231437Sluigi uint32_t tx_pauseframes; /* dword 52*/ 2972231437Sluigi uint32_t tx_controlframes; /* dword 53*/ 2973231437Sluigi uint32_t tx_64_byte_packets; /* dword 54*/ 2974231437Sluigi uint32_t tx_65_127_byte_packets; /* dword 55*/ 2975231437Sluigi uint32_t tx_128_256_byte_packets; /* dword 56*/ 2976231437Sluigi uint32_t tx_256_511_byte_packets; /* dword 57*/ 2977231437Sluigi uint32_t tx_512_1023_byte_packets; /* dword 58*/ 2978231437Sluigi uint32_t tx_1024_1518_byte_packets; /* dword 59*/ 2979231437Sluigi uint32_t tx_1519_2047_byte_packets; /* dword 60*/ 2980231437Sluigi uint32_t tx_2048_4095_byte_packets; /* dword 61*/ 2981231437Sluigi uint32_t tx_4096_8191_byte_packets; /* dword 62*/ 2982231437Sluigi uint32_t tx_8192_9216_byte_packets; /* dword 63*/ 2983231437Sluigi uint32_t rxpp_fifo_overflow_drop; /* dword 64*/ 2984231437Sluigi uint32_t rx_input_fifo_overflow_drop; /* dword 65*/ 2985231437Sluigi}; 2986231437Sluigi 2987231437Sluigi 2988231437Sluigistruct oce_rxf_stats_v0 { 2989231437Sluigi struct oce_port_rxf_stats_v0 port[2]; 2990231437Sluigi uint32_t rx_drops_no_pbuf; /* dword 132*/ 2991231437Sluigi uint32_t rx_drops_no_txpb; /* dword 133*/ 2992231437Sluigi uint32_t rx_drops_no_erx_descr; /* dword 134*/ 2993231437Sluigi uint32_t rx_drops_no_tpre_descr; /* dword 135*/ 2994231437Sluigi uint32_t management_rx_port_packets; /* dword 136*/ 2995231437Sluigi uint32_t management_rx_port_bytes; /* dword 137*/ 2996231437Sluigi uint32_t management_rx_port_pause_frames;/* dword 138*/ 2997231437Sluigi uint32_t management_rx_port_errors; /* dword 139*/ 2998231437Sluigi uint32_t management_tx_port_packets; /* dword 140*/ 2999231437Sluigi uint32_t management_tx_port_bytes; /* dword 141*/ 3000231437Sluigi uint32_t management_tx_port_pause; /* dword 142*/ 3001231437Sluigi uint32_t management_rx_port_rxfifo_overflow; /* dword 143*/ 3002231437Sluigi uint32_t rx_drops_too_many_frags; /* dword 144*/ 3003231437Sluigi uint32_t rx_drops_invalid_ring; /* dword 145*/ 3004231437Sluigi uint32_t forwarded_packets; /* dword 146*/ 3005231437Sluigi uint32_t rx_drops_mtu; /* dword 147*/ 3006231437Sluigi uint32_t rsvd0[7]; 3007231437Sluigi uint32_t port0_jabber_events; 3008231437Sluigi uint32_t port1_jabber_events; 3009231437Sluigi uint32_t rsvd1[6]; 3010231437Sluigi}; 3011231437Sluigi 3012231437Sluigistruct oce_port_rxf_stats_v1 { 3013231437Sluigi uint32_t rsvd0[12]; 3014231437Sluigi uint32_t rx_crc_errors; 3015231437Sluigi uint32_t rx_alignment_symbol_errors; 3016231437Sluigi uint32_t rx_pause_frames; 3017231437Sluigi uint32_t rx_priority_pause_frames; 3018231437Sluigi uint32_t rx_control_frames; 3019231437Sluigi uint32_t rx_in_range_errors; 3020231437Sluigi uint32_t rx_out_range_errors; 3021231437Sluigi uint32_t rx_frame_too_long; 3022231437Sluigi uint32_t rx_address_match_errors; 3023231437Sluigi uint32_t rx_dropped_too_small; 3024231437Sluigi uint32_t rx_dropped_too_short; 3025231437Sluigi uint32_t rx_dropped_header_too_small; 3026231437Sluigi uint32_t rx_dropped_tcp_length; 3027231437Sluigi uint32_t rx_dropped_runt; 3028231437Sluigi uint32_t rsvd1[10]; 3029231437Sluigi uint32_t rx_ip_checksum_errs; 3030231437Sluigi uint32_t rx_tcp_checksum_errs; 3031231437Sluigi uint32_t rx_udp_checksum_errs; 3032231437Sluigi uint32_t rsvd2[7]; 3033231437Sluigi uint32_t rx_switched_unicast_packets; 3034231437Sluigi uint32_t rx_switched_multicast_packets; 3035231437Sluigi uint32_t rx_switched_broadcast_packets; 3036231437Sluigi uint32_t rsvd3[3]; 3037231437Sluigi uint32_t tx_pauseframes; 3038231437Sluigi uint32_t tx_priority_pauseframes; 3039231437Sluigi uint32_t tx_controlframes; 3040231437Sluigi uint32_t rsvd4[10]; 3041231437Sluigi uint32_t rxpp_fifo_overflow_drop; 3042231437Sluigi uint32_t rx_input_fifo_overflow_drop; 3043231437Sluigi uint32_t pmem_fifo_overflow_drop; 3044231437Sluigi uint32_t jabber_events; 3045231437Sluigi uint32_t rsvd5[3]; 3046231437Sluigi}; 3047231437Sluigi 3048231437Sluigi 3049231437Sluigistruct oce_rxf_stats_v1 { 3050231437Sluigi struct oce_port_rxf_stats_v1 port[4]; 3051231437Sluigi uint32_t rsvd0[2]; 3052231437Sluigi uint32_t rx_drops_no_pbuf; 3053231437Sluigi uint32_t rx_drops_no_txpb; 3054231437Sluigi uint32_t rx_drops_no_erx_descr; 3055231437Sluigi uint32_t rx_drops_no_tpre_descr; 3056231437Sluigi uint32_t rsvd1[6]; 3057231437Sluigi uint32_t rx_drops_too_many_frags; 3058231437Sluigi uint32_t rx_drops_invalid_ring; 3059231437Sluigi uint32_t forwarded_packets; 3060231437Sluigi uint32_t rx_drops_mtu; 3061231437Sluigi uint32_t rsvd2[14]; 3062231437Sluigi}; 3063231437Sluigi 3064231437Sluigistruct oce_erx_stats_v1 { 3065231437Sluigi uint32_t rx_drops_no_fragments[68]; 3066231437Sluigi uint32_t rsvd[4]; 3067231437Sluigi}; 3068231437Sluigi 3069231437Sluigi 3070231437Sluigistruct oce_erx_stats_v0 { 3071231437Sluigi uint32_t rx_drops_no_fragments[44]; 3072231437Sluigi uint32_t rsvd[4]; 3073231437Sluigi}; 3074231437Sluigi 3075231437Sluigistruct oce_pmem_stats { 3076231437Sluigi uint32_t eth_red_drops; 3077231437Sluigi uint32_t rsvd[5]; 3078231437Sluigi}; 3079231437Sluigi 3080231437Sluigistruct oce_hw_stats_v1 { 3081231437Sluigi struct oce_rxf_stats_v1 rxf; 3082231437Sluigi uint32_t rsvd0[OCE_TXP_SW_SZ]; 3083231437Sluigi struct oce_erx_stats_v1 erx; 3084231437Sluigi struct oce_pmem_stats pmem; 3085231437Sluigi uint32_t rsvd1[18]; 3086231437Sluigi}; 3087231437Sluigi 3088231437Sluigistruct oce_hw_stats_v0 { 3089231437Sluigi struct oce_rxf_stats_v0 rxf; 3090231437Sluigi uint32_t rsvd[48]; 3091231437Sluigi struct oce_erx_stats_v0 erx; 3092231437Sluigi struct oce_pmem_stats pmem; 3093231437Sluigi}; 3094231437Sluigi 3095231437Sluigistruct mbx_get_nic_stats_v0 { 3096231437Sluigi struct mbx_hdr hdr; 3097231437Sluigi union { 3098231437Sluigi struct { 3099231437Sluigi uint32_t rsvd0; 3100231437Sluigi } req; 3101231437Sluigi 3102231437Sluigi union { 3103231437Sluigi struct oce_hw_stats_v0 stats; 3104231437Sluigi } rsp; 3105231437Sluigi } params; 3106231437Sluigi}; 3107231437Sluigi 3108231437Sluigistruct mbx_get_nic_stats { 3109231437Sluigi struct mbx_hdr hdr; 3110231437Sluigi union { 3111231437Sluigi struct { 3112231437Sluigi uint32_t rsvd0; 3113231437Sluigi } req; 3114231437Sluigi 3115231437Sluigi struct { 3116231437Sluigi struct oce_hw_stats_v1 stats; 3117231437Sluigi } rsp; 3118231437Sluigi } params; 3119231437Sluigi}; 3120231437Sluigi 3121231437Sluigi 3122231437Sluigi/* [18(0x12)] NIC_GET_PPORT_STATS */ 3123231437Sluigistruct pport_stats { 3124231437Sluigi uint64_t tx_pkts; 3125231437Sluigi uint64_t tx_unicast_pkts; 3126231437Sluigi uint64_t tx_multicast_pkts; 3127231437Sluigi uint64_t tx_broadcast_pkts; 3128231437Sluigi uint64_t tx_bytes; 3129231437Sluigi uint64_t tx_unicast_bytes; 3130231437Sluigi uint64_t tx_multicast_bytes; 3131231437Sluigi uint64_t tx_broadcast_bytes; 3132231437Sluigi uint64_t tx_discards; 3133231437Sluigi uint64_t tx_errors; 3134231437Sluigi uint64_t tx_pause_frames; 3135231437Sluigi uint64_t tx_pause_on_frames; 3136231437Sluigi uint64_t tx_pause_off_frames; 3137231437Sluigi uint64_t tx_internal_mac_errors; 3138231437Sluigi uint64_t tx_control_frames; 3139231437Sluigi uint64_t tx_pkts_64_bytes; 3140231437Sluigi uint64_t tx_pkts_65_to_127_bytes; 3141231437Sluigi uint64_t tx_pkts_128_to_255_bytes; 3142231437Sluigi uint64_t tx_pkts_256_to_511_bytes; 3143231437Sluigi uint64_t tx_pkts_512_to_1023_bytes; 3144231437Sluigi uint64_t tx_pkts_1024_to_1518_bytes; 3145231437Sluigi uint64_t tx_pkts_1519_to_2047_bytes; 3146231437Sluigi uint64_t tx_pkts_2048_to_4095_bytes; 3147231437Sluigi uint64_t tx_pkts_4096_to_8191_bytes; 3148231437Sluigi uint64_t tx_pkts_8192_to_9216_bytes; 3149231437Sluigi uint64_t tx_lso_pkts; 3150231437Sluigi uint64_t rx_pkts; 3151231437Sluigi uint64_t rx_unicast_pkts; 3152231437Sluigi uint64_t rx_multicast_pkts; 3153231437Sluigi uint64_t rx_broadcast_pkts; 3154231437Sluigi uint64_t rx_bytes; 3155231437Sluigi uint64_t rx_unicast_bytes; 3156231437Sluigi uint64_t rx_multicast_bytes; 3157231437Sluigi uint64_t rx_broadcast_bytes; 3158231437Sluigi uint32_t rx_unknown_protos; 3159231437Sluigi uint32_t reserved_word69; 3160231437Sluigi uint64_t rx_discards; 3161231437Sluigi uint64_t rx_errors; 3162231437Sluigi uint64_t rx_crc_errors; 3163231437Sluigi uint64_t rx_alignment_errors; 3164231437Sluigi uint64_t rx_symbol_errors; 3165231437Sluigi uint64_t rx_pause_frames; 3166231437Sluigi uint64_t rx_pause_on_frames; 3167231437Sluigi uint64_t rx_pause_off_frames; 3168231437Sluigi uint64_t rx_frames_too_long; 3169231437Sluigi uint64_t rx_internal_mac_errors; 3170231437Sluigi uint32_t rx_undersize_pkts; 3171231437Sluigi uint32_t rx_oversize_pkts; 3172231437Sluigi uint32_t rx_fragment_pkts; 3173231437Sluigi uint32_t rx_jabbers; 3174231437Sluigi uint64_t rx_control_frames; 3175231437Sluigi uint64_t rx_control_frames_unknown_opcode; 3176231437Sluigi uint32_t rx_in_range_errors; 3177231437Sluigi uint32_t rx_out_of_range_errors; 3178231437Sluigi uint32_t rx_address_match_errors; 3179231437Sluigi uint32_t rx_vlan_mismatch_errors; 3180231437Sluigi uint32_t rx_dropped_too_small; 3181231437Sluigi uint32_t rx_dropped_too_short; 3182231437Sluigi uint32_t rx_dropped_header_too_small; 3183231437Sluigi uint32_t rx_dropped_invalid_tcp_length; 3184231437Sluigi uint32_t rx_dropped_runt; 3185231437Sluigi uint32_t rx_ip_checksum_errors; 3186231437Sluigi uint32_t rx_tcp_checksum_errors; 3187231437Sluigi uint32_t rx_udp_checksum_errors; 3188231437Sluigi uint32_t rx_non_rss_pkts; 3189231437Sluigi uint64_t reserved_word111; 3190231437Sluigi uint64_t rx_ipv4_pkts; 3191231437Sluigi uint64_t rx_ipv6_pkts; 3192231437Sluigi uint64_t rx_ipv4_bytes; 3193231437Sluigi uint64_t rx_ipv6_bytes; 3194231437Sluigi uint64_t rx_nic_pkts; 3195231437Sluigi uint64_t rx_tcp_pkts; 3196231437Sluigi uint64_t rx_iscsi_pkts; 3197231437Sluigi uint64_t rx_management_pkts; 3198231437Sluigi uint64_t rx_switched_unicast_pkts; 3199231437Sluigi uint64_t rx_switched_multicast_pkts; 3200231437Sluigi uint64_t rx_switched_broadcast_pkts; 3201231437Sluigi uint64_t num_forwards; 3202231437Sluigi uint32_t rx_fifo_overflow; 3203231437Sluigi uint32_t rx_input_fifo_overflow; 3204231437Sluigi uint64_t rx_drops_too_many_frags; 3205231437Sluigi uint32_t rx_drops_invalid_queue; 3206231437Sluigi uint32_t reserved_word141; 3207231437Sluigi uint64_t rx_drops_mtu; 3208231437Sluigi uint64_t rx_pkts_64_bytes; 3209231437Sluigi uint64_t rx_pkts_65_to_127_bytes; 3210231437Sluigi uint64_t rx_pkts_128_to_255_bytes; 3211231437Sluigi uint64_t rx_pkts_256_to_511_bytes; 3212231437Sluigi uint64_t rx_pkts_512_to_1023_bytes; 3213231437Sluigi uint64_t rx_pkts_1024_to_1518_bytes; 3214231437Sluigi uint64_t rx_pkts_1519_to_2047_bytes; 3215231437Sluigi uint64_t rx_pkts_2048_to_4095_bytes; 3216231437Sluigi uint64_t rx_pkts_4096_to_8191_bytes; 3217231437Sluigi uint64_t rx_pkts_8192_to_9216_bytes; 3218231437Sluigi}; 3219231437Sluigi 3220231437Sluigistruct mbx_get_pport_stats { 3221231437Sluigi /* dw0 - dw3 */ 3222231437Sluigi struct mbx_hdr hdr; 3223231437Sluigi union { 3224231437Sluigi struct { 3225231437Sluigi /* dw4 */ 3226231437Sluigi#ifdef _BIG_ENDIAN 3227231437Sluigi uint32_t reset_stats:8; 3228231437Sluigi uint32_t rsvd0:8; 3229231437Sluigi uint32_t port_number:16; 3230231437Sluigi#else 3231231437Sluigi uint32_t port_number:16; 3232231437Sluigi uint32_t rsvd0:8; 3233231437Sluigi uint32_t reset_stats:8; 3234231437Sluigi#endif 3235231437Sluigi } req; 3236231437Sluigi 3237231437Sluigi union { 3238231437Sluigi struct pport_stats pps; 3239231437Sluigi uint32_t pport_stats[164 - 4 + 1]; 3240231437Sluigi } rsp; 3241231437Sluigi } params; 3242231437Sluigi}; 3243231437Sluigi 3244231437Sluigi/* [19(0x13)] NIC_GET_VPORT_STATS */ 3245231437Sluigistruct vport_stats { 3246231437Sluigi uint64_t tx_pkts; 3247231437Sluigi uint64_t tx_unicast_pkts; 3248231437Sluigi uint64_t tx_multicast_pkts; 3249231437Sluigi uint64_t tx_broadcast_pkts; 3250231437Sluigi uint64_t tx_bytes; 3251231437Sluigi uint64_t tx_unicast_bytes; 3252231437Sluigi uint64_t tx_multicast_bytes; 3253231437Sluigi uint64_t tx_broadcast_bytes; 3254231437Sluigi uint64_t tx_discards; 3255231437Sluigi uint64_t tx_errors; 3256231437Sluigi uint64_t tx_pkts_64_bytes; 3257231437Sluigi uint64_t tx_pkts_65_to_127_bytes; 3258231437Sluigi uint64_t tx_pkts_128_to_255_bytes; 3259231437Sluigi uint64_t tx_pkts_256_to_511_bytes; 3260231437Sluigi uint64_t tx_pkts_512_to_1023_bytes; 3261231437Sluigi uint64_t tx_pkts_1024_to_1518_bytes; 3262231437Sluigi uint64_t tx_pkts_1519_to_9699_bytes; 3263231437Sluigi uint64_t tx_pkts_over_9699_bytes; 3264231437Sluigi uint64_t rx_pkts; 3265231437Sluigi uint64_t rx_unicast_pkts; 3266231437Sluigi uint64_t rx_multicast_pkts; 3267231437Sluigi uint64_t rx_broadcast_pkts; 3268231437Sluigi uint64_t rx_bytes; 3269231437Sluigi uint64_t rx_unicast_bytes; 3270231437Sluigi uint64_t rx_multicast_bytes; 3271231437Sluigi uint64_t rx_broadcast_bytes; 3272231437Sluigi uint64_t rx_discards; 3273231437Sluigi uint64_t rx_errors; 3274231437Sluigi uint64_t rx_pkts_64_bytes; 3275231437Sluigi uint64_t rx_pkts_65_to_127_bytes; 3276231437Sluigi uint64_t rx_pkts_128_to_255_bytes; 3277231437Sluigi uint64_t rx_pkts_256_to_511_bytes; 3278231437Sluigi uint64_t rx_pkts_512_to_1023_bytes; 3279231437Sluigi uint64_t rx_pkts_1024_to_1518_bytes; 3280231437Sluigi uint64_t rx_pkts_1519_to_9699_bytes; 3281231437Sluigi uint64_t rx_pkts_gt_9699_bytes; 3282231437Sluigi}; 3283231437Sluigistruct mbx_get_vport_stats { 3284231437Sluigi /* dw0 - dw3 */ 3285231437Sluigi struct mbx_hdr hdr; 3286231437Sluigi union { 3287231437Sluigi struct { 3288231437Sluigi /* dw4 */ 3289231437Sluigi#ifdef _BIG_ENDIAN 3290231437Sluigi uint32_t reset_stats:8; 3291231437Sluigi uint32_t rsvd0:8; 3292231437Sluigi uint32_t vport_number:16; 3293231437Sluigi#else 3294231437Sluigi uint32_t vport_number:16; 3295231437Sluigi uint32_t rsvd0:8; 3296231437Sluigi uint32_t reset_stats:8; 3297231437Sluigi#endif 3298231437Sluigi } req; 3299231437Sluigi 3300231437Sluigi union { 3301231437Sluigi struct vport_stats vps; 3302231437Sluigi uint32_t vport_stats[75 - 4 + 1]; 3303231437Sluigi } rsp; 3304231437Sluigi } params; 3305231437Sluigi}; 3306231437Sluigi 3307231437Sluigi/** 3308231437Sluigi * @brief [20(0x14)] NIC_GET_QUEUE_STATS 3309231437Sluigi * The significant difference between vPort and Queue statistics is 3310231437Sluigi * the packet byte counters. 3311231437Sluigi */ 3312231437Sluigistruct queue_stats { 3313231437Sluigi uint64_t packets; 3314231437Sluigi uint64_t bytes; 3315231437Sluigi uint64_t errors; 3316231437Sluigi uint64_t drops; 3317231437Sluigi uint64_t buffer_errors; /* rsvd when tx */ 3318231437Sluigi}; 3319231437Sluigi 3320231437Sluigi#define QUEUE_TYPE_WQ 0 3321231437Sluigi#define QUEUE_TYPE_RQ 1 3322231437Sluigi#define QUEUE_TYPE_HDS_RQ 1 /* same as RQ */ 3323231437Sluigi 3324231437Sluigistruct mbx_get_queue_stats { 3325231437Sluigi /* dw0 - dw3 */ 3326231437Sluigi struct mbx_hdr hdr; 3327231437Sluigi union { 3328231437Sluigi struct { 3329231437Sluigi /* dw4 */ 3330231437Sluigi#ifdef _BIG_ENDIAN 3331231437Sluigi uint32_t reset_stats:8; 3332231437Sluigi uint32_t queue_type:8; 3333231437Sluigi uint32_t queue_id:16; 3334231437Sluigi#else 3335231437Sluigi uint32_t queue_id:16; 3336231437Sluigi uint32_t queue_type:8; 3337231437Sluigi uint32_t reset_stats:8; 3338231437Sluigi#endif 3339231437Sluigi } req; 3340231437Sluigi 3341231437Sluigi union { 3342231437Sluigi struct queue_stats qs; 3343231437Sluigi uint32_t queue_stats[13 - 4 + 1]; 3344231437Sluigi } rsp; 3345231437Sluigi } params; 3346231437Sluigi}; 3347231437Sluigi 3348231437Sluigi 3349231437Sluigi/* [01] NIC_CONFIG_RSS */ 3350231437Sluigi#define OCE_HASH_TBL_SZ 10 3351231437Sluigi#define OCE_CPU_TBL_SZ 128 3352231437Sluigi#define OCE_FLUSH 1 /* RSS flush completion per CQ port */ 3353231437Sluigistruct mbx_config_nic_rss { 3354231437Sluigi struct mbx_hdr hdr; 3355231437Sluigi union { 3356231437Sluigi struct { 3357231437Sluigi#ifdef _BIG_ENDIAN 3358231437Sluigi uint32_t if_id; 3359231437Sluigi uint16_t cpu_tbl_sz_log2; 3360231437Sluigi uint16_t enable_rss; 3361231437Sluigi uint32_t hash[OCE_HASH_TBL_SZ]; 3362231437Sluigi uint8_t cputable[OCE_CPU_TBL_SZ]; 3363231437Sluigi uint8_t rsvd[3]; 3364231437Sluigi uint8_t flush; 3365231437Sluigi#else 3366231437Sluigi uint32_t if_id; 3367231437Sluigi uint16_t enable_rss; 3368231437Sluigi uint16_t cpu_tbl_sz_log2; 3369231437Sluigi uint32_t hash[OCE_HASH_TBL_SZ]; 3370231437Sluigi uint8_t cputable[OCE_CPU_TBL_SZ]; 3371231437Sluigi uint8_t flush; 3372231437Sluigi uint8_t rsvd[3]; 3373231437Sluigi#endif 3374231437Sluigi } req; 3375231437Sluigi struct { 3376231437Sluigi uint8_t rsvd[3]; 3377231437Sluigi uint8_t rss_bank; 3378231437Sluigi } rsp; 3379231437Sluigi } params; 3380231437Sluigi}; 3381231437Sluigi 3382231437Sluigi 3383231437Sluigi#pragma pack() 3384231437Sluigi 3385231437Sluigi 3386231437Sluigitypedef uint32_t oce_stat_t; /* statistic counter */ 3387231437Sluigi 3388231437Sluigienum OCE_RXF_PORT_STATS { 3389231437Sluigi RXF_RX_BYTES_LSD, 3390231437Sluigi RXF_RX_BYTES_MSD, 3391231437Sluigi RXF_RX_TOTAL_FRAMES, 3392231437Sluigi RXF_RX_UNICAST_FRAMES, 3393231437Sluigi RXF_RX_MULTICAST_FRAMES, 3394231437Sluigi RXF_RX_BROADCAST_FRAMES, 3395231437Sluigi RXF_RX_CRC_ERRORS, 3396231437Sluigi RXF_RX_ALIGNMENT_SYMBOL_ERRORS, 3397231437Sluigi RXF_RX_PAUSE_FRAMES, 3398231437Sluigi RXF_RX_CONTROL_FRAMES, 3399231437Sluigi RXF_RX_IN_RANGE_ERRORS, 3400231437Sluigi RXF_RX_OUT_RANGE_ERRORS, 3401231437Sluigi RXF_RX_FRAME_TOO_LONG, 3402231437Sluigi RXF_RX_ADDRESS_MATCH_ERRORS, 3403231437Sluigi RXF_RX_VLAN_MISMATCH, 3404231437Sluigi RXF_RX_DROPPED_TOO_SMALL, 3405231437Sluigi RXF_RX_DROPPED_TOO_SHORT, 3406231437Sluigi RXF_RX_DROPPED_HEADER_TOO_SMALL, 3407231437Sluigi RXF_RX_DROPPED_TCP_LENGTH, 3408231437Sluigi RXF_RX_DROPPED_RUNT, 3409231437Sluigi RXF_RX_64_BYTE_PACKETS, 3410231437Sluigi RXF_RX_65_127_BYTE_PACKETS, 3411231437Sluigi RXF_RX_128_256_BYTE_PACKETS, 3412231437Sluigi RXF_RX_256_511_BYTE_PACKETS, 3413231437Sluigi RXF_RX_512_1023_BYTE_PACKETS, 3414231437Sluigi RXF_RX_1024_1518_BYTE_PACKETS, 3415231437Sluigi RXF_RX_1519_2047_BYTE_PACKETS, 3416231437Sluigi RXF_RX_2048_4095_BYTE_PACKETS, 3417231437Sluigi RXF_RX_4096_8191_BYTE_PACKETS, 3418231437Sluigi RXF_RX_8192_9216_BYTE_PACKETS, 3419231437Sluigi RXF_RX_IP_CHECKSUM_ERRS, 3420231437Sluigi RXF_RX_TCP_CHECKSUM_ERRS, 3421231437Sluigi RXF_RX_UDP_CHECKSUM_ERRS, 3422231437Sluigi RXF_RX_NON_RSS_PACKETS, 3423231437Sluigi RXF_RX_IPV4_PACKETS, 3424231437Sluigi RXF_RX_IPV6_PACKETS, 3425231437Sluigi RXF_RX_IPV4_BYTES_LSD, 3426231437Sluigi RXF_RX_IPV4_BYTES_MSD, 3427231437Sluigi RXF_RX_IPV6_BYTES_LSD, 3428231437Sluigi RXF_RX_IPV6_BYTES_MSD, 3429231437Sluigi RXF_RX_CHUTE1_PACKETS, 3430231437Sluigi RXF_RX_CHUTE2_PACKETS, 3431231437Sluigi RXF_RX_CHUTE3_PACKETS, 3432231437Sluigi RXF_RX_MANAGEMENT_PACKETS, 3433231437Sluigi RXF_RX_SWITCHED_UNICAST_PACKETS, 3434231437Sluigi RXF_RX_SWITCHED_MULTICAST_PACKETS, 3435231437Sluigi RXF_RX_SWITCHED_BROADCAST_PACKETS, 3436231437Sluigi RXF_TX_BYTES_LSD, 3437231437Sluigi RXF_TX_BYTES_MSD, 3438231437Sluigi RXF_TX_UNICAST_FRAMES, 3439231437Sluigi RXF_TX_MULTICAST_FRAMES, 3440231437Sluigi RXF_TX_BROADCAST_FRAMES, 3441231437Sluigi RXF_TX_PAUSE_FRAMES, 3442231437Sluigi RXF_TX_CONTROL_FRAMES, 3443231437Sluigi RXF_TX_64_BYTE_PACKETS, 3444231437Sluigi RXF_TX_65_127_BYTE_PACKETS, 3445231437Sluigi RXF_TX_128_256_BYTE_PACKETS, 3446231437Sluigi RXF_TX_256_511_BYTE_PACKETS, 3447231437Sluigi RXF_TX_512_1023_BYTE_PACKETS, 3448231437Sluigi RXF_TX_1024_1518_BYTE_PACKETS, 3449231437Sluigi RXF_TX_1519_2047_BYTE_PACKETS, 3450231437Sluigi RXF_TX_2048_4095_BYTE_PACKETS, 3451231437Sluigi RXF_TX_4096_8191_BYTE_PACKETS, 3452231437Sluigi RXF_TX_8192_9216_BYTE_PACKETS, 3453231437Sluigi RXF_RX_FIFO_OVERFLOW, 3454231437Sluigi RXF_RX_INPUT_FIFO_OVERFLOW, 3455231437Sluigi RXF_PORT_STATS_N_WORDS 3456231437Sluigi}; 3457231437Sluigi 3458231437Sluigienum OCE_RXF_ADDL_STATS { 3459231437Sluigi RXF_RX_DROPS_NO_PBUF, 3460231437Sluigi RXF_RX_DROPS_NO_TXPB, 3461231437Sluigi RXF_RX_DROPS_NO_ERX_DESCR, 3462231437Sluigi RXF_RX_DROPS_NO_TPRE_DESCR, 3463231437Sluigi RXF_MANAGEMENT_RX_PORT_PACKETS, 3464231437Sluigi RXF_MANAGEMENT_RX_PORT_BYTES, 3465231437Sluigi RXF_MANAGEMENT_RX_PORT_PAUSE_FRAMES, 3466231437Sluigi RXF_MANAGEMENT_RX_PORT_ERRORS, 3467231437Sluigi RXF_MANAGEMENT_TX_PORT_PACKETS, 3468231437Sluigi RXF_MANAGEMENT_TX_PORT_BYTES, 3469231437Sluigi RXF_MANAGEMENT_TX_PORT_PAUSE, 3470231437Sluigi RXF_MANAGEMENT_RX_PORT_RXFIFO_OVERFLOW, 3471231437Sluigi RXF_RX_DROPS_TOO_MANY_FRAGS, 3472231437Sluigi RXF_RX_DROPS_INVALID_RING, 3473231437Sluigi RXF_FORWARDED_PACKETS, 3474231437Sluigi RXF_RX_DROPS_MTU, 3475231437Sluigi RXF_ADDL_STATS_N_WORDS 3476231437Sluigi}; 3477231437Sluigi 3478231437Sluigienum OCE_TX_CHUTE_PORT_STATS { 3479231437Sluigi CTPT_XMT_IPV4_PKTS, 3480231437Sluigi CTPT_XMT_IPV4_LSD, 3481231437Sluigi CTPT_XMT_IPV4_MSD, 3482231437Sluigi CTPT_XMT_IPV6_PKTS, 3483231437Sluigi CTPT_XMT_IPV6_LSD, 3484231437Sluigi CTPT_XMT_IPV6_MSD, 3485231437Sluigi CTPT_REXMT_IPV4_PKTs, 3486231437Sluigi CTPT_REXMT_IPV4_LSD, 3487231437Sluigi CTPT_REXMT_IPV4_MSD, 3488231437Sluigi CTPT_REXMT_IPV6_PKTs, 3489231437Sluigi CTPT_REXMT_IPV6_LSD, 3490231437Sluigi CTPT_REXMT_IPV6_MSD, 3491231437Sluigi CTPT_N_WORDS, 3492231437Sluigi}; 3493231437Sluigi 3494231437Sluigienum OCE_RX_ERR_STATS { 3495231437Sluigi RX_DROPS_NO_FRAGMENTS_0, 3496231437Sluigi RX_DROPS_NO_FRAGMENTS_1, 3497231437Sluigi RX_DROPS_NO_FRAGMENTS_2, 3498231437Sluigi RX_DROPS_NO_FRAGMENTS_3, 3499231437Sluigi RX_DROPS_NO_FRAGMENTS_4, 3500231437Sluigi RX_DROPS_NO_FRAGMENTS_5, 3501231437Sluigi RX_DROPS_NO_FRAGMENTS_6, 3502231437Sluigi RX_DROPS_NO_FRAGMENTS_7, 3503231437Sluigi RX_DROPS_NO_FRAGMENTS_8, 3504231437Sluigi RX_DROPS_NO_FRAGMENTS_9, 3505231437Sluigi RX_DROPS_NO_FRAGMENTS_10, 3506231437Sluigi RX_DROPS_NO_FRAGMENTS_11, 3507231437Sluigi RX_DROPS_NO_FRAGMENTS_12, 3508231437Sluigi RX_DROPS_NO_FRAGMENTS_13, 3509231437Sluigi RX_DROPS_NO_FRAGMENTS_14, 3510231437Sluigi RX_DROPS_NO_FRAGMENTS_15, 3511231437Sluigi RX_DROPS_NO_FRAGMENTS_16, 3512231437Sluigi RX_DROPS_NO_FRAGMENTS_17, 3513231437Sluigi RX_DROPS_NO_FRAGMENTS_18, 3514231437Sluigi RX_DROPS_NO_FRAGMENTS_19, 3515231437Sluigi RX_DROPS_NO_FRAGMENTS_20, 3516231437Sluigi RX_DROPS_NO_FRAGMENTS_21, 3517231437Sluigi RX_DROPS_NO_FRAGMENTS_22, 3518231437Sluigi RX_DROPS_NO_FRAGMENTS_23, 3519231437Sluigi RX_DROPS_NO_FRAGMENTS_24, 3520231437Sluigi RX_DROPS_NO_FRAGMENTS_25, 3521231437Sluigi RX_DROPS_NO_FRAGMENTS_26, 3522231437Sluigi RX_DROPS_NO_FRAGMENTS_27, 3523231437Sluigi RX_DROPS_NO_FRAGMENTS_28, 3524231437Sluigi RX_DROPS_NO_FRAGMENTS_29, 3525231437Sluigi RX_DROPS_NO_FRAGMENTS_30, 3526231437Sluigi RX_DROPS_NO_FRAGMENTS_31, 3527231437Sluigi RX_DROPS_NO_FRAGMENTS_32, 3528231437Sluigi RX_DROPS_NO_FRAGMENTS_33, 3529231437Sluigi RX_DROPS_NO_FRAGMENTS_34, 3530231437Sluigi RX_DROPS_NO_FRAGMENTS_35, 3531231437Sluigi RX_DROPS_NO_FRAGMENTS_36, 3532231437Sluigi RX_DROPS_NO_FRAGMENTS_37, 3533231437Sluigi RX_DROPS_NO_FRAGMENTS_38, 3534231437Sluigi RX_DROPS_NO_FRAGMENTS_39, 3535231437Sluigi RX_DROPS_NO_FRAGMENTS_40, 3536231437Sluigi RX_DROPS_NO_FRAGMENTS_41, 3537231437Sluigi RX_DROPS_NO_FRAGMENTS_42, 3538231437Sluigi RX_DROPS_NO_FRAGMENTS_43, 3539231437Sluigi RX_DEBUG_WDMA_SENT_HOLD, 3540231437Sluigi RX_DEBUG_WDMA_PBFREE_SENT_HOLD, 3541231437Sluigi RX_DEBUG_WDMA_0B_PBFREE_SENT_HOLD, 3542231437Sluigi RX_DEBUG_PMEM_PBUF_DEALLOC, 3543231437Sluigi RX_ERRORS_N_WORDS 3544231437Sluigi}; 3545231437Sluigi 3546231437Sluigienum OCE_PMEM_ERR_STATS { 3547231437Sluigi PMEM_ETH_RED_DROPS, 3548231437Sluigi PMEM_LRO_RED_DROPS, 3549231437Sluigi PMEM_ULP0_RED_DROPS, 3550231437Sluigi PMEM_ULP1_RED_DROPS, 3551231437Sluigi PMEM_GLOBAL_RED_DROPS, 3552231437Sluigi PMEM_ERRORS_N_WORDS 3553231437Sluigi}; 3554231437Sluigi 3555231437Sluigi/** 3556231437Sluigi * @brief Statistics for a given Physical Port 3557231437Sluigi * These satisfy all the required BE2 statistics and also the 3558231437Sluigi * following MIB objects: 3559231437Sluigi * 3560231437Sluigi * RFC 2863 - The Interfaces Group MIB 3561231437Sluigi * RFC 2819 - Remote Network Monitoring Management Information Base (RMON) 3562231437Sluigi * RFC 3635 - Managed Objects for the Ethernet-like Interface Types 3563231437Sluigi * RFC 4502 - Remote Network Monitoring Mgmt Information Base Ver-2 (RMON2) 3564231437Sluigi * 3565231437Sluigi */ 3566231437Sluigienum OCE_PPORT_STATS { 3567231437Sluigi PPORT_TX_PKTS = 0, 3568231437Sluigi PPORT_TX_UNICAST_PKTS = 2, 3569231437Sluigi PPORT_TX_MULTICAST_PKTS = 4, 3570231437Sluigi PPORT_TX_BROADCAST_PKTS = 6, 3571231437Sluigi PPORT_TX_BYTES = 8, 3572231437Sluigi PPORT_TX_UNICAST_BYTES = 10, 3573231437Sluigi PPORT_TX_MULTICAST_BYTES = 12, 3574231437Sluigi PPORT_TX_BROADCAST_BYTES = 14, 3575231437Sluigi PPORT_TX_DISCARDS = 16, 3576231437Sluigi PPORT_TX_ERRORS = 18, 3577231437Sluigi PPORT_TX_PAUSE_FRAMES = 20, 3578231437Sluigi PPORT_TX_PAUSE_ON_FRAMES = 22, 3579231437Sluigi PPORT_TX_PAUSE_OFF_FRAMES = 24, 3580231437Sluigi PPORT_TX_INTERNAL_MAC_ERRORS = 26, 3581231437Sluigi PPORT_TX_CONTROL_FRAMES = 28, 3582231437Sluigi PPORT_TX_PKTS_64_BYTES = 30, 3583231437Sluigi PPORT_TX_PKTS_65_TO_127_BYTES = 32, 3584231437Sluigi PPORT_TX_PKTS_128_TO_255_BYTES = 34, 3585231437Sluigi PPORT_TX_PKTS_256_TO_511_BYTES = 36, 3586231437Sluigi PPORT_TX_PKTS_512_TO_1023_BYTES = 38, 3587231437Sluigi PPORT_TX_PKTS_1024_TO_1518_BYTES = 40, 3588231437Sluigi PPORT_TX_PKTS_1519_TO_2047_BYTES = 42, 3589231437Sluigi PPORT_TX_PKTS_2048_TO_4095_BYTES = 44, 3590231437Sluigi PPORT_TX_PKTS_4096_TO_8191_BYTES = 46, 3591231437Sluigi PPORT_TX_PKTS_8192_TO_9216_BYTES = 48, 3592231437Sluigi PPORT_TX_LSO_PKTS = 50, 3593231437Sluigi PPORT_RX_PKTS = 52, 3594231437Sluigi PPORT_RX_UNICAST_PKTS = 54, 3595231437Sluigi PPORT_RX_MULTICAST_PKTS = 56, 3596231437Sluigi PPORT_RX_BROADCAST_PKTS = 58, 3597231437Sluigi PPORT_RX_BYTES = 60, 3598231437Sluigi PPORT_RX_UNICAST_BYTES = 62, 3599231437Sluigi PPORT_RX_MULTICAST_BYTES = 64, 3600231437Sluigi PPORT_RX_BROADCAST_BYTES = 66, 3601231437Sluigi PPORT_RX_UNKNOWN_PROTOS = 68, 3602231437Sluigi PPORT_RESERVED_WORD69 = 69, 3603231437Sluigi PPORT_RX_DISCARDS = 70, 3604231437Sluigi PPORT_RX_ERRORS = 72, 3605231437Sluigi PPORT_RX_CRC_ERRORS = 74, 3606231437Sluigi PPORT_RX_ALIGNMENT_ERRORS = 76, 3607231437Sluigi PPORT_RX_SYMBOL_ERRORS = 78, 3608231437Sluigi PPORT_RX_PAUSE_FRAMES = 80, 3609231437Sluigi PPORT_RX_PAUSE_ON_FRAMES = 82, 3610231437Sluigi PPORT_RX_PAUSE_OFF_FRAMES = 84, 3611231437Sluigi PPORT_RX_FRAMES_TOO_LONG = 86, 3612231437Sluigi PPORT_RX_INTERNAL_MAC_ERRORS = 88, 3613231437Sluigi PPORT_RX_UNDERSIZE_PKTS = 90, 3614231437Sluigi PPORT_RX_OVERSIZE_PKTS = 91, 3615231437Sluigi PPORT_RX_FRAGMENT_PKTS = 92, 3616231437Sluigi PPORT_RX_JABBERS = 93, 3617231437Sluigi PPORT_RX_CONTROL_FRAMES = 94, 3618231437Sluigi PPORT_RX_CONTROL_FRAMES_UNK_OPCODE = 96, 3619231437Sluigi PPORT_RX_IN_RANGE_ERRORS = 98, 3620231437Sluigi PPORT_RX_OUT_OF_RANGE_ERRORS = 99, 3621231437Sluigi PPORT_RX_ADDRESS_MATCH_ERRORS = 100, 3622231437Sluigi PPORT_RX_VLAN_MISMATCH_ERRORS = 101, 3623231437Sluigi PPORT_RX_DROPPED_TOO_SMALL = 102, 3624231437Sluigi PPORT_RX_DROPPED_TOO_SHORT = 103, 3625231437Sluigi PPORT_RX_DROPPED_HEADER_TOO_SMALL = 104, 3626231437Sluigi PPORT_RX_DROPPED_INVALID_TCP_LENGTH = 105, 3627231437Sluigi PPORT_RX_DROPPED_RUNT = 106, 3628231437Sluigi PPORT_RX_IP_CHECKSUM_ERRORS = 107, 3629231437Sluigi PPORT_RX_TCP_CHECKSUM_ERRORS = 108, 3630231437Sluigi PPORT_RX_UDP_CHECKSUM_ERRORS = 109, 3631231437Sluigi PPORT_RX_NON_RSS_PKTS = 110, 3632231437Sluigi PPORT_RESERVED_WORD111 = 111, 3633231437Sluigi PPORT_RX_IPV4_PKTS = 112, 3634231437Sluigi PPORT_RX_IPV6_PKTS = 114, 3635231437Sluigi PPORT_RX_IPV4_BYTES = 116, 3636231437Sluigi PPORT_RX_IPV6_BYTES = 118, 3637231437Sluigi PPORT_RX_NIC_PKTS = 120, 3638231437Sluigi PPORT_RX_TCP_PKTS = 122, 3639231437Sluigi PPORT_RX_ISCSI_PKTS = 124, 3640231437Sluigi PPORT_RX_MANAGEMENT_PKTS = 126, 3641231437Sluigi PPORT_RX_SWITCHED_UNICAST_PKTS = 128, 3642231437Sluigi PPORT_RX_SWITCHED_MULTICAST_PKTS = 130, 3643231437Sluigi PPORT_RX_SWITCHED_BROADCAST_PKTS = 132, 3644231437Sluigi PPORT_NUM_FORWARDS = 134, 3645231437Sluigi PPORT_RX_FIFO_OVERFLOW = 136, 3646231437Sluigi PPORT_RX_INPUT_FIFO_OVERFLOW = 137, 3647231437Sluigi PPORT_RX_DROPS_TOO_MANY_FRAGS = 138, 3648231437Sluigi PPORT_RX_DROPS_INVALID_QUEUE = 140, 3649231437Sluigi PPORT_RESERVED_WORD141 = 141, 3650231437Sluigi PPORT_RX_DROPS_MTU = 142, 3651231437Sluigi PPORT_RX_PKTS_64_BYTES = 144, 3652231437Sluigi PPORT_RX_PKTS_65_TO_127_BYTES = 146, 3653231437Sluigi PPORT_RX_PKTS_128_TO_255_BYTES = 148, 3654231437Sluigi PPORT_RX_PKTS_256_TO_511_BYTES = 150, 3655231437Sluigi PPORT_RX_PKTS_512_TO_1023_BYTES = 152, 3656231437Sluigi PPORT_RX_PKTS_1024_TO_1518_BYTES = 154, 3657231437Sluigi PPORT_RX_PKTS_1519_TO_2047_BYTES = 156, 3658231437Sluigi PPORT_RX_PKTS_2048_TO_4095_BYTES = 158, 3659231437Sluigi PPORT_RX_PKTS_4096_TO_8191_BYTES = 160, 3660231437Sluigi PPORT_RX_PKTS_8192_TO_9216_BYTES = 162, 3661231437Sluigi PPORT_N_WORDS = 164 3662231437Sluigi}; 3663231437Sluigi 3664231437Sluigi/** 3665231437Sluigi * @brief Statistics for a given Virtual Port (vPort) 3666231437Sluigi * The following describes the vPort statistics satisfying 3667231437Sluigi * requirements of Linux/VMWare netdev statistics and 3668231437Sluigi * Microsoft Windows Statistics along with other Operating Systems. 3669231437Sluigi */ 3670231437Sluigienum OCE_VPORT_STATS { 3671231437Sluigi VPORT_TX_PKTS = 0, 3672231437Sluigi VPORT_TX_UNICAST_PKTS = 2, 3673231437Sluigi VPORT_TX_MULTICAST_PKTS = 4, 3674231437Sluigi VPORT_TX_BROADCAST_PKTS = 6, 3675231437Sluigi VPORT_TX_BYTES = 8, 3676231437Sluigi VPORT_TX_UNICAST_BYTES = 10, 3677231437Sluigi VPORT_TX_MULTICAST_BYTES = 12, 3678231437Sluigi VPORT_TX_BROADCAST_BYTES = 14, 3679231437Sluigi VPORT_TX_DISCARDS = 16, 3680231437Sluigi VPORT_TX_ERRORS = 18, 3681231437Sluigi VPORT_TX_PKTS_64_BYTES = 20, 3682231437Sluigi VPORT_TX_PKTS_65_TO_127_BYTES = 22, 3683231437Sluigi VPORT_TX_PKTS_128_TO_255_BYTES = 24, 3684231437Sluigi VPORT_TX_PKTS_256_TO_511_BYTES = 26, 3685231437Sluigi VPORT_TX_PKTS_512_TO_1023_BYTEs = 28, 3686231437Sluigi VPORT_TX_PKTS_1024_TO_1518_BYTEs = 30, 3687231437Sluigi VPORT_TX_PKTS_1519_TO_9699_BYTEs = 32, 3688231437Sluigi VPORT_TX_PKTS_OVER_9699_BYTES = 34, 3689231437Sluigi VPORT_RX_PKTS = 36, 3690231437Sluigi VPORT_RX_UNICAST_PKTS = 38, 3691231437Sluigi VPORT_RX_MULTICAST_PKTS = 40, 3692231437Sluigi VPORT_RX_BROADCAST_PKTS = 42, 3693231437Sluigi VPORT_RX_BYTES = 44, 3694231437Sluigi VPORT_RX_UNICAST_BYTES = 46, 3695231437Sluigi VPORT_RX_MULTICAST_BYTES = 48, 3696231437Sluigi VPORT_RX_BROADCAST_BYTES = 50, 3697231437Sluigi VPORT_RX_DISCARDS = 52, 3698231437Sluigi VPORT_RX_ERRORS = 54, 3699231437Sluigi VPORT_RX_PKTS_64_BYTES = 56, 3700231437Sluigi VPORT_RX_PKTS_65_TO_127_BYTES = 58, 3701231437Sluigi VPORT_RX_PKTS_128_TO_255_BYTES = 60, 3702231437Sluigi VPORT_RX_PKTS_256_TO_511_BYTES = 62, 3703231437Sluigi VPORT_RX_PKTS_512_TO_1023_BYTEs = 64, 3704231437Sluigi VPORT_RX_PKTS_1024_TO_1518_BYTEs = 66, 3705231437Sluigi VPORT_RX_PKTS_1519_TO_9699_BYTEs = 68, 3706231437Sluigi VPORT_RX_PKTS_OVER_9699_BYTES = 70, 3707231437Sluigi VPORT_N_WORDS = 72 3708231437Sluigi}; 3709231437Sluigi 3710231437Sluigi/** 3711231437Sluigi * @brief Statistics for a given queue (NIC WQ, RQ, or HDS RQ) 3712231437Sluigi * This set satisfies requirements of VMQare NetQueue and Microsoft VMQ 3713231437Sluigi */ 3714231437Sluigienum OCE_QUEUE_TX_STATS { 3715231437Sluigi QUEUE_TX_PKTS = 0, 3716231437Sluigi QUEUE_TX_BYTES = 2, 3717231437Sluigi QUEUE_TX_ERRORS = 4, 3718231437Sluigi QUEUE_TX_DROPS = 6, 3719231437Sluigi QUEUE_TX_N_WORDS = 8 3720231437Sluigi}; 3721231437Sluigi 3722231437Sluigienum OCE_QUEUE_RX_STATS { 3723231437Sluigi QUEUE_RX_PKTS = 0, 3724231437Sluigi QUEUE_RX_BYTES = 2, 3725231437Sluigi QUEUE_RX_ERRORS = 4, 3726231437Sluigi QUEUE_RX_DROPS = 6, 3727231437Sluigi QUEUE_RX_BUFFER_ERRORS = 8, 3728231437Sluigi QUEUE_RX_N_WORDS = 10 3729231437Sluigi}; 3730