1179337Syongari/*- 2179337Syongari * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3179337Syongari * All rights reserved. 4179337Syongari * 5179337Syongari * Redistribution and use in source and binary forms, with or without 6179337Syongari * modification, are permitted provided that the following conditions 7179337Syongari * are met: 8179337Syongari * 1. Redistributions of source code must retain the above copyright 9179337Syongari * notice unmodified, this list of conditions, and the following 10179337Syongari * disclaimer. 11179337Syongari * 2. Redistributions in binary form must reproduce the above copyright 12179337Syongari * notice, this list of conditions and the following disclaimer in the 13179337Syongari * documentation and/or other materials provided with the distribution. 14179337Syongari * 15179337Syongari * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16179337Syongari * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17179337Syongari * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18179337Syongari * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19179337Syongari * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20179337Syongari * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21179337Syongari * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22179337Syongari * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23179337Syongari * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24179337Syongari * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25179337Syongari * SUCH DAMAGE. 26179337Syongari */ 27179337Syongari 28179337Syongari#include <sys/cdefs.h> 29179337Syongari__FBSDID("$FreeBSD$"); 30179337Syongari 31179337Syongari#include <sys/param.h> 32179337Syongari#include <sys/systm.h> 33179337Syongari#include <sys/bus.h> 34179337Syongari#include <sys/endian.h> 35179337Syongari#include <sys/kernel.h> 36179337Syongari#include <sys/malloc.h> 37179337Syongari#include <sys/mbuf.h> 38179337Syongari#include <sys/rman.h> 39179337Syongari#include <sys/module.h> 40179337Syongari#include <sys/proc.h> 41179337Syongari#include <sys/queue.h> 42179337Syongari#include <sys/socket.h> 43179337Syongari#include <sys/sockio.h> 44179337Syongari#include <sys/sysctl.h> 45179337Syongari#include <sys/taskqueue.h> 46179337Syongari 47179337Syongari#include <net/bpf.h> 48179337Syongari#include <net/if.h> 49179337Syongari#include <net/if_arp.h> 50179337Syongari#include <net/ethernet.h> 51179337Syongari#include <net/if_dl.h> 52179337Syongari#include <net/if_media.h> 53179337Syongari#include <net/if_types.h> 54179337Syongari#include <net/if_vlan_var.h> 55179337Syongari 56179337Syongari#include <netinet/in.h> 57179337Syongari#include <netinet/in_systm.h> 58179337Syongari#include <netinet/ip.h> 59179337Syongari#include <netinet/tcp.h> 60179337Syongari 61179337Syongari#include <dev/mii/mii.h> 62179337Syongari#include <dev/mii/miivar.h> 63179337Syongari 64179337Syongari#include <dev/pci/pcireg.h> 65179337Syongari#include <dev/pci/pcivar.h> 66179337Syongari 67179337Syongari#include <machine/bus.h> 68179337Syongari#include <machine/in_cksum.h> 69179337Syongari 70179337Syongari#include <dev/jme/if_jmereg.h> 71179337Syongari#include <dev/jme/if_jmevar.h> 72179337Syongari 73179337Syongari/* "device miibus" required. See GENERIC if you get errors here. */ 74179337Syongari#include "miibus_if.h" 75179337Syongari 76179337Syongari/* Define the following to disable printing Rx errors. */ 77179337Syongari#undef JME_SHOW_ERRORS 78179337Syongari 79179337Syongari#define JME_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 80179337Syongari 81179337SyongariMODULE_DEPEND(jme, pci, 1, 1, 1); 82179337SyongariMODULE_DEPEND(jme, ether, 1, 1, 1); 83179337SyongariMODULE_DEPEND(jme, miibus, 1, 1, 1); 84179337Syongari 85179337Syongari/* Tunables. */ 86179337Syongaristatic int msi_disable = 0; 87179337Syongaristatic int msix_disable = 0; 88179337SyongariTUNABLE_INT("hw.jme.msi_disable", &msi_disable); 89179337SyongariTUNABLE_INT("hw.jme.msix_disable", &msix_disable); 90179337Syongari 91179337Syongari/* 92179337Syongari * Devices supported by this driver. 93179337Syongari */ 94179337Syongaristatic struct jme_dev { 95179337Syongari uint16_t jme_vendorid; 96179337Syongari uint16_t jme_deviceid; 97179337Syongari const char *jme_name; 98179337Syongari} jme_devs[] = { 99179337Syongari { VENDORID_JMICRON, DEVICEID_JMC250, 100216551Syongari "JMicron Inc, JMC25x Gigabit Ethernet" }, 101179337Syongari { VENDORID_JMICRON, DEVICEID_JMC260, 102216551Syongari "JMicron Inc, JMC26x Fast Ethernet" }, 103179337Syongari}; 104179337Syongari 105179337Syongaristatic int jme_miibus_readreg(device_t, int, int); 106179337Syongaristatic int jme_miibus_writereg(device_t, int, int, int); 107179337Syongaristatic void jme_miibus_statchg(device_t); 108179337Syongaristatic void jme_mediastatus(struct ifnet *, struct ifmediareq *); 109179337Syongaristatic int jme_mediachange(struct ifnet *); 110179337Syongaristatic int jme_probe(device_t); 111179337Syongaristatic int jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *); 112179337Syongaristatic int jme_eeprom_macaddr(struct jme_softc *); 113216551Syongaristatic int jme_efuse_macaddr(struct jme_softc *); 114179337Syongaristatic void jme_reg_macaddr(struct jme_softc *); 115216551Syongaristatic void jme_set_macaddr(struct jme_softc *, uint8_t *); 116179337Syongaristatic void jme_map_intr_vector(struct jme_softc *); 117179337Syongaristatic int jme_attach(device_t); 118179337Syongaristatic int jme_detach(device_t); 119179337Syongaristatic void jme_sysctl_node(struct jme_softc *); 120179337Syongaristatic void jme_dmamap_cb(void *, bus_dma_segment_t *, int, int); 121179337Syongaristatic int jme_dma_alloc(struct jme_softc *); 122179337Syongaristatic void jme_dma_free(struct jme_softc *); 123179337Syongaristatic int jme_shutdown(device_t); 124179337Syongaristatic void jme_setlinkspeed(struct jme_softc *); 125179337Syongaristatic void jme_setwol(struct jme_softc *); 126179337Syongaristatic int jme_suspend(device_t); 127179337Syongaristatic int jme_resume(device_t); 128179337Syongaristatic int jme_encap(struct jme_softc *, struct mbuf **); 129179337Syongaristatic void jme_start(struct ifnet *); 130217353Sjhbstatic void jme_start_locked(struct ifnet *); 131179337Syongaristatic void jme_watchdog(struct jme_softc *); 132179337Syongaristatic int jme_ioctl(struct ifnet *, u_long, caddr_t); 133179337Syongaristatic void jme_mac_config(struct jme_softc *); 134179337Syongaristatic void jme_link_task(void *, int); 135179337Syongaristatic int jme_intr(void *); 136179337Syongaristatic void jme_int_task(void *, int); 137179337Syongaristatic void jme_txeof(struct jme_softc *); 138179337Syongaristatic __inline void jme_discard_rxbuf(struct jme_softc *, int); 139179337Syongaristatic void jme_rxeof(struct jme_softc *); 140179337Syongaristatic int jme_rxintr(struct jme_softc *, int); 141179337Syongaristatic void jme_tick(void *); 142179337Syongaristatic void jme_reset(struct jme_softc *); 143179337Syongaristatic void jme_init(void *); 144179337Syongaristatic void jme_init_locked(struct jme_softc *); 145179337Syongaristatic void jme_stop(struct jme_softc *); 146179337Syongaristatic void jme_stop_tx(struct jme_softc *); 147179337Syongaristatic void jme_stop_rx(struct jme_softc *); 148179337Syongaristatic int jme_init_rx_ring(struct jme_softc *); 149179337Syongaristatic void jme_init_tx_ring(struct jme_softc *); 150179337Syongaristatic void jme_init_ssb(struct jme_softc *); 151179337Syongaristatic int jme_newbuf(struct jme_softc *, struct jme_rxdesc *); 152179337Syongaristatic void jme_set_vlan(struct jme_softc *); 153179337Syongaristatic void jme_set_filter(struct jme_softc *); 154185597Syongaristatic void jme_stats_clear(struct jme_softc *); 155185597Syongaristatic void jme_stats_save(struct jme_softc *); 156185597Syongaristatic void jme_stats_update(struct jme_softc *); 157216551Syongaristatic void jme_phy_down(struct jme_softc *); 158216551Syongaristatic void jme_phy_up(struct jme_softc *); 159179337Syongaristatic int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 160179337Syongaristatic int sysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS); 161179337Syongaristatic int sysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS); 162179337Syongaristatic int sysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS); 163179337Syongaristatic int sysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS); 164179337Syongaristatic int sysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS); 165179337Syongari 166179337Syongari 167179337Syongaristatic device_method_t jme_methods[] = { 168179337Syongari /* Device interface. */ 169179337Syongari DEVMETHOD(device_probe, jme_probe), 170179337Syongari DEVMETHOD(device_attach, jme_attach), 171179337Syongari DEVMETHOD(device_detach, jme_detach), 172179337Syongari DEVMETHOD(device_shutdown, jme_shutdown), 173179337Syongari DEVMETHOD(device_suspend, jme_suspend), 174179337Syongari DEVMETHOD(device_resume, jme_resume), 175179337Syongari 176179337Syongari /* MII interface. */ 177179337Syongari DEVMETHOD(miibus_readreg, jme_miibus_readreg), 178179337Syongari DEVMETHOD(miibus_writereg, jme_miibus_writereg), 179179337Syongari DEVMETHOD(miibus_statchg, jme_miibus_statchg), 180179337Syongari 181179337Syongari { NULL, NULL } 182179337Syongari}; 183179337Syongari 184179337Syongaristatic driver_t jme_driver = { 185179337Syongari "jme", 186179337Syongari jme_methods, 187179337Syongari sizeof(struct jme_softc) 188179337Syongari}; 189179337Syongari 190179337Syongaristatic devclass_t jme_devclass; 191179337Syongari 192179337SyongariDRIVER_MODULE(jme, pci, jme_driver, jme_devclass, 0, 0); 193179337SyongariDRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, 0, 0); 194179337Syongari 195179337Syongaristatic struct resource_spec jme_res_spec_mem[] = { 196179337Syongari { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 197179337Syongari { -1, 0, 0 } 198179337Syongari}; 199179337Syongari 200179337Syongaristatic struct resource_spec jme_irq_spec_legacy[] = { 201179337Syongari { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 202179337Syongari { -1, 0, 0 } 203179337Syongari}; 204179337Syongari 205179337Syongaristatic struct resource_spec jme_irq_spec_msi[] = { 206179337Syongari { SYS_RES_IRQ, 1, RF_ACTIVE }, 207179337Syongari { -1, 0, 0 } 208179337Syongari}; 209179337Syongari 210179337Syongari/* 211179337Syongari * Read a PHY register on the MII of the JMC250. 212179337Syongari */ 213179337Syongaristatic int 214179337Syongarijme_miibus_readreg(device_t dev, int phy, int reg) 215179337Syongari{ 216179337Syongari struct jme_softc *sc; 217179337Syongari uint32_t val; 218179337Syongari int i; 219179337Syongari 220179337Syongari sc = device_get_softc(dev); 221179337Syongari 222179337Syongari /* For FPGA version, PHY address 0 should be ignored. */ 223213893Smarius if ((sc->jme_flags & JME_FLAG_FPGA) != 0 && phy == 0) 224213893Smarius return (0); 225179337Syongari 226179337Syongari CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE | 227179337Syongari SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 228179337Syongari for (i = JME_PHY_TIMEOUT; i > 0; i--) { 229179337Syongari DELAY(1); 230179337Syongari if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) 231179337Syongari break; 232179337Syongari } 233179337Syongari 234179337Syongari if (i == 0) { 235179337Syongari device_printf(sc->jme_dev, "phy read timeout : %d\n", reg); 236179337Syongari return (0); 237179337Syongari } 238179337Syongari 239179337Syongari return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT); 240179337Syongari} 241179337Syongari 242179337Syongari/* 243179337Syongari * Write a PHY register on the MII of the JMC250. 244179337Syongari */ 245179337Syongaristatic int 246179337Syongarijme_miibus_writereg(device_t dev, int phy, int reg, int val) 247179337Syongari{ 248179337Syongari struct jme_softc *sc; 249179337Syongari int i; 250179337Syongari 251179337Syongari sc = device_get_softc(dev); 252179337Syongari 253179337Syongari /* For FPGA version, PHY address 0 should be ignored. */ 254213893Smarius if ((sc->jme_flags & JME_FLAG_FPGA) != 0 && phy == 0) 255213893Smarius return (0); 256179337Syongari 257179337Syongari CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE | 258179337Syongari ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) | 259179337Syongari SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg)); 260179337Syongari for (i = JME_PHY_TIMEOUT; i > 0; i--) { 261179337Syongari DELAY(1); 262179337Syongari if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0) 263179337Syongari break; 264179337Syongari } 265179337Syongari 266179337Syongari if (i == 0) 267179337Syongari device_printf(sc->jme_dev, "phy write timeout : %d\n", reg); 268179337Syongari 269179337Syongari return (0); 270179337Syongari} 271179337Syongari 272179337Syongari/* 273179337Syongari * Callback from MII layer when media changes. 274179337Syongari */ 275179337Syongaristatic void 276179337Syongarijme_miibus_statchg(device_t dev) 277179337Syongari{ 278179337Syongari struct jme_softc *sc; 279179337Syongari 280179337Syongari sc = device_get_softc(dev); 281179337Syongari taskqueue_enqueue(taskqueue_swi, &sc->jme_link_task); 282179337Syongari} 283179337Syongari 284179337Syongari/* 285179337Syongari * Get the current interface media status. 286179337Syongari */ 287179337Syongaristatic void 288179337Syongarijme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 289179337Syongari{ 290179337Syongari struct jme_softc *sc; 291179337Syongari struct mii_data *mii; 292179337Syongari 293179337Syongari sc = ifp->if_softc; 294179337Syongari JME_LOCK(sc); 295197585Syongari if ((ifp->if_flags & IFF_UP) == 0) { 296197585Syongari JME_UNLOCK(sc); 297197585Syongari return; 298197585Syongari } 299179337Syongari mii = device_get_softc(sc->jme_miibus); 300179337Syongari 301179337Syongari mii_pollstat(mii); 302179337Syongari ifmr->ifm_status = mii->mii_media_status; 303179337Syongari ifmr->ifm_active = mii->mii_media_active; 304179337Syongari JME_UNLOCK(sc); 305179337Syongari} 306179337Syongari 307179337Syongari/* 308179337Syongari * Set hardware to newly-selected media. 309179337Syongari */ 310179337Syongaristatic int 311179337Syongarijme_mediachange(struct ifnet *ifp) 312179337Syongari{ 313179337Syongari struct jme_softc *sc; 314179337Syongari struct mii_data *mii; 315179337Syongari struct mii_softc *miisc; 316179337Syongari int error; 317179337Syongari 318179337Syongari sc = ifp->if_softc; 319179337Syongari JME_LOCK(sc); 320179337Syongari mii = device_get_softc(sc->jme_miibus); 321221407Smarius LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 322221407Smarius PHY_RESET(miisc); 323179337Syongari error = mii_mediachg(mii); 324179337Syongari JME_UNLOCK(sc); 325179337Syongari 326179337Syongari return (error); 327179337Syongari} 328179337Syongari 329179337Syongaristatic int 330179337Syongarijme_probe(device_t dev) 331179337Syongari{ 332179337Syongari struct jme_dev *sp; 333179337Syongari int i; 334179337Syongari uint16_t vendor, devid; 335179337Syongari 336179337Syongari vendor = pci_get_vendor(dev); 337179337Syongari devid = pci_get_device(dev); 338179337Syongari sp = jme_devs; 339179337Syongari for (i = 0; i < sizeof(jme_devs) / sizeof(jme_devs[0]); 340179337Syongari i++, sp++) { 341179337Syongari if (vendor == sp->jme_vendorid && 342179337Syongari devid == sp->jme_deviceid) { 343179337Syongari device_set_desc(dev, sp->jme_name); 344179337Syongari return (BUS_PROBE_DEFAULT); 345179337Syongari } 346179337Syongari } 347179337Syongari 348179337Syongari return (ENXIO); 349179337Syongari} 350179337Syongari 351179337Syongaristatic int 352179337Syongarijme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val) 353179337Syongari{ 354179337Syongari uint32_t reg; 355179337Syongari int i; 356179337Syongari 357179337Syongari *val = 0; 358179337Syongari for (i = JME_TIMEOUT; i > 0; i--) { 359179337Syongari reg = CSR_READ_4(sc, JME_SMBCSR); 360179337Syongari if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE) 361179337Syongari break; 362179337Syongari DELAY(1); 363179337Syongari } 364179337Syongari 365179337Syongari if (i == 0) { 366179337Syongari device_printf(sc->jme_dev, "EEPROM idle timeout!\n"); 367179337Syongari return (ETIMEDOUT); 368179337Syongari } 369179337Syongari 370179337Syongari reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK; 371179337Syongari CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER); 372179337Syongari for (i = JME_TIMEOUT; i > 0; i--) { 373179337Syongari DELAY(1); 374179337Syongari reg = CSR_READ_4(sc, JME_SMBINTF); 375179337Syongari if ((reg & SMBINTF_CMD_TRIGGER) == 0) 376179337Syongari break; 377179337Syongari } 378179337Syongari 379179337Syongari if (i == 0) { 380179337Syongari device_printf(sc->jme_dev, "EEPROM read timeout!\n"); 381179337Syongari return (ETIMEDOUT); 382179337Syongari } 383179337Syongari 384179337Syongari reg = CSR_READ_4(sc, JME_SMBINTF); 385179337Syongari *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT; 386179337Syongari 387179337Syongari return (0); 388179337Syongari} 389179337Syongari 390179337Syongaristatic int 391179337Syongarijme_eeprom_macaddr(struct jme_softc *sc) 392179337Syongari{ 393179337Syongari uint8_t eaddr[ETHER_ADDR_LEN]; 394179337Syongari uint8_t fup, reg, val; 395179337Syongari uint32_t offset; 396179337Syongari int match; 397179337Syongari 398179337Syongari offset = 0; 399179337Syongari if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 400179337Syongari fup != JME_EEPROM_SIG0) 401179337Syongari return (ENOENT); 402179337Syongari if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 || 403179337Syongari fup != JME_EEPROM_SIG1) 404179337Syongari return (ENOENT); 405179337Syongari match = 0; 406179337Syongari do { 407179337Syongari if (jme_eeprom_read_byte(sc, offset, &fup) != 0) 408179337Syongari break; 409183859Syongari if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) == 410183859Syongari (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) { 411179337Syongari if (jme_eeprom_read_byte(sc, offset + 1, ®) != 0) 412179337Syongari break; 413179337Syongari if (reg >= JME_PAR0 && 414179337Syongari reg < JME_PAR0 + ETHER_ADDR_LEN) { 415179337Syongari if (jme_eeprom_read_byte(sc, offset + 2, 416179337Syongari &val) != 0) 417179337Syongari break; 418179337Syongari eaddr[reg - JME_PAR0] = val; 419179337Syongari match++; 420179337Syongari } 421179337Syongari } 422183859Syongari /* Check for the end of EEPROM descriptor. */ 423183859Syongari if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END) 424183859Syongari break; 425179337Syongari /* Try next eeprom descriptor. */ 426179337Syongari offset += JME_EEPROM_DESC_BYTES; 427179337Syongari } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END); 428179337Syongari 429179337Syongari if (match == ETHER_ADDR_LEN) { 430179337Syongari bcopy(eaddr, sc->jme_eaddr, ETHER_ADDR_LEN); 431179337Syongari return (0); 432179337Syongari } 433179337Syongari 434179337Syongari return (ENOENT); 435179337Syongari} 436179337Syongari 437216551Syongaristatic int 438216551Syongarijme_efuse_macaddr(struct jme_softc *sc) 439216551Syongari{ 440216551Syongari uint32_t reg; 441216551Syongari int i; 442216551Syongari 443216551Syongari reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4); 444216551Syongari if ((reg & (EFUSE_CTL1_AUTOLOAD_ERR | EFUSE_CTL1_AUTOLAOD_DONE)) != 445216551Syongari EFUSE_CTL1_AUTOLAOD_DONE) 446216551Syongari return (ENOENT); 447216551Syongari /* Reset eFuse controller. */ 448216551Syongari reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL2, 4); 449216551Syongari reg |= EFUSE_CTL2_RESET; 450216551Syongari pci_write_config(sc->jme_dev, JME_EFUSE_CTL2, reg, 4); 451216551Syongari reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL2, 4); 452216551Syongari reg &= ~EFUSE_CTL2_RESET; 453216551Syongari pci_write_config(sc->jme_dev, JME_EFUSE_CTL2, reg, 4); 454216551Syongari 455216551Syongari /* Have eFuse reload station address to MAC controller. */ 456216551Syongari reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4); 457216551Syongari reg &= ~EFUSE_CTL1_CMD_MASK; 458216551Syongari reg |= EFUSE_CTL1_CMD_AUTOLOAD | EFUSE_CTL1_EXECUTE; 459216551Syongari pci_write_config(sc->jme_dev, JME_EFUSE_CTL1, reg, 4); 460216551Syongari 461216551Syongari /* 462216551Syongari * Verify completion of eFuse autload command. It should be 463216551Syongari * completed within 108us. 464216551Syongari */ 465216551Syongari DELAY(110); 466216551Syongari for (i = 10; i > 0; i--) { 467216551Syongari reg = pci_read_config(sc->jme_dev, JME_EFUSE_CTL1, 4); 468216551Syongari if ((reg & (EFUSE_CTL1_AUTOLOAD_ERR | 469216551Syongari EFUSE_CTL1_AUTOLAOD_DONE)) != EFUSE_CTL1_AUTOLAOD_DONE) { 470216551Syongari DELAY(20); 471216551Syongari continue; 472216551Syongari } 473216551Syongari if ((reg & EFUSE_CTL1_EXECUTE) == 0) 474216551Syongari break; 475216551Syongari /* Station address loading is still in progress. */ 476216551Syongari DELAY(20); 477216551Syongari } 478216551Syongari if (i == 0) { 479216551Syongari device_printf(sc->jme_dev, "eFuse autoload timed out.\n"); 480216551Syongari return (ETIMEDOUT); 481216551Syongari } 482216551Syongari 483216551Syongari return (0); 484216551Syongari} 485216551Syongari 486179337Syongaristatic void 487179337Syongarijme_reg_macaddr(struct jme_softc *sc) 488179337Syongari{ 489179337Syongari uint32_t par0, par1; 490179337Syongari 491179337Syongari /* Read station address. */ 492179337Syongari par0 = CSR_READ_4(sc, JME_PAR0); 493179337Syongari par1 = CSR_READ_4(sc, JME_PAR1); 494179337Syongari par1 &= 0xFFFF; 495179337Syongari if ((par0 == 0 && par1 == 0) || 496179337Syongari (par0 == 0xFFFFFFFF && par1 == 0xFFFF)) { 497179337Syongari device_printf(sc->jme_dev, 498201781Sgavin "Failed to retrieve Ethernet address.\n"); 499179337Syongari } else { 500216551Syongari /* 501216551Syongari * For controllers that use eFuse, the station address 502216551Syongari * could also be extracted from JME_PCI_PAR0 and 503216551Syongari * JME_PCI_PAR1 registers in PCI configuration space. 504216551Syongari * Each register holds exactly half of station address(24bits) 505216551Syongari * so use JME_PAR0, JME_PAR1 registers instead. 506216551Syongari */ 507179337Syongari sc->jme_eaddr[0] = (par0 >> 0) & 0xFF; 508179337Syongari sc->jme_eaddr[1] = (par0 >> 8) & 0xFF; 509179337Syongari sc->jme_eaddr[2] = (par0 >> 16) & 0xFF; 510179337Syongari sc->jme_eaddr[3] = (par0 >> 24) & 0xFF; 511179337Syongari sc->jme_eaddr[4] = (par1 >> 0) & 0xFF; 512179337Syongari sc->jme_eaddr[5] = (par1 >> 8) & 0xFF; 513179337Syongari } 514179337Syongari} 515179337Syongari 516179337Syongaristatic void 517216551Syongarijme_set_macaddr(struct jme_softc *sc, uint8_t *eaddr) 518216551Syongari{ 519216551Syongari uint32_t val; 520216551Syongari int i; 521216551Syongari 522216551Syongari if ((sc->jme_flags & JME_FLAG_EFUSE) != 0) { 523216551Syongari /* 524216551Syongari * Avoid reprogramming station address if the address 525216551Syongari * is the same as previous one. Note, reprogrammed 526216551Syongari * station address is permanent as if it was written 527216551Syongari * to EEPROM. So if station address was changed by 528216551Syongari * admistrator it's possible to lose factory configured 529216551Syongari * address when driver fails to restore its address. 530216551Syongari * (e.g. reboot or system crash) 531216551Syongari */ 532216551Syongari if (bcmp(eaddr, sc->jme_eaddr, ETHER_ADDR_LEN) != 0) { 533216551Syongari for (i = 0; i < ETHER_ADDR_LEN; i++) { 534216551Syongari val = JME_EFUSE_EEPROM_FUNC0 << 535216551Syongari JME_EFUSE_EEPROM_FUNC_SHIFT; 536216551Syongari val |= JME_EFUSE_EEPROM_PAGE_BAR1 << 537216551Syongari JME_EFUSE_EEPROM_PAGE_SHIFT; 538216551Syongari val |= (JME_PAR0 + i) << 539216551Syongari JME_EFUSE_EEPROM_ADDR_SHIFT; 540216551Syongari val |= eaddr[i] << JME_EFUSE_EEPROM_DATA_SHIFT; 541216551Syongari pci_write_config(sc->jme_dev, JME_EFUSE_EEPROM, 542216551Syongari val | JME_EFUSE_EEPROM_WRITE, 4); 543216551Syongari } 544216551Syongari } 545216551Syongari } else { 546216551Syongari CSR_WRITE_4(sc, JME_PAR0, 547216551Syongari eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]); 548216551Syongari CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]); 549216551Syongari } 550216551Syongari} 551216551Syongari 552216551Syongaristatic void 553179337Syongarijme_map_intr_vector(struct jme_softc *sc) 554179337Syongari{ 555179337Syongari uint32_t map[MSINUM_NUM_INTR_SOURCE / JME_MSI_MESSAGES]; 556179337Syongari 557179337Syongari bzero(map, sizeof(map)); 558179337Syongari 559179337Syongari /* Map Tx interrupts source to MSI/MSIX vector 2. */ 560179337Syongari map[MSINUM_REG_INDEX(N_INTR_TXQ0_COMP)] = 561179337Syongari MSINUM_INTR_SOURCE(2, N_INTR_TXQ0_COMP); 562179337Syongari map[MSINUM_REG_INDEX(N_INTR_TXQ1_COMP)] |= 563179337Syongari MSINUM_INTR_SOURCE(2, N_INTR_TXQ1_COMP); 564179337Syongari map[MSINUM_REG_INDEX(N_INTR_TXQ2_COMP)] |= 565179337Syongari MSINUM_INTR_SOURCE(2, N_INTR_TXQ2_COMP); 566179337Syongari map[MSINUM_REG_INDEX(N_INTR_TXQ3_COMP)] |= 567179337Syongari MSINUM_INTR_SOURCE(2, N_INTR_TXQ3_COMP); 568179337Syongari map[MSINUM_REG_INDEX(N_INTR_TXQ4_COMP)] |= 569179337Syongari MSINUM_INTR_SOURCE(2, N_INTR_TXQ4_COMP); 570179337Syongari map[MSINUM_REG_INDEX(N_INTR_TXQ4_COMP)] |= 571179337Syongari MSINUM_INTR_SOURCE(2, N_INTR_TXQ5_COMP); 572179337Syongari map[MSINUM_REG_INDEX(N_INTR_TXQ6_COMP)] |= 573179337Syongari MSINUM_INTR_SOURCE(2, N_INTR_TXQ6_COMP); 574179337Syongari map[MSINUM_REG_INDEX(N_INTR_TXQ7_COMP)] |= 575179337Syongari MSINUM_INTR_SOURCE(2, N_INTR_TXQ7_COMP); 576179337Syongari map[MSINUM_REG_INDEX(N_INTR_TXQ_COAL)] |= 577179337Syongari MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL); 578179337Syongari map[MSINUM_REG_INDEX(N_INTR_TXQ_COAL_TO)] |= 579179337Syongari MSINUM_INTR_SOURCE(2, N_INTR_TXQ_COAL_TO); 580179337Syongari 581179337Syongari /* Map Rx interrupts source to MSI/MSIX vector 1. */ 582179337Syongari map[MSINUM_REG_INDEX(N_INTR_RXQ0_COMP)] = 583179337Syongari MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COMP); 584179337Syongari map[MSINUM_REG_INDEX(N_INTR_RXQ1_COMP)] = 585179337Syongari MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COMP); 586179337Syongari map[MSINUM_REG_INDEX(N_INTR_RXQ2_COMP)] = 587179337Syongari MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COMP); 588179337Syongari map[MSINUM_REG_INDEX(N_INTR_RXQ3_COMP)] = 589179337Syongari MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COMP); 590179337Syongari map[MSINUM_REG_INDEX(N_INTR_RXQ0_DESC_EMPTY)] = 591179337Syongari MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_DESC_EMPTY); 592179337Syongari map[MSINUM_REG_INDEX(N_INTR_RXQ1_DESC_EMPTY)] = 593179337Syongari MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_DESC_EMPTY); 594179337Syongari map[MSINUM_REG_INDEX(N_INTR_RXQ2_DESC_EMPTY)] = 595179337Syongari MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_DESC_EMPTY); 596179337Syongari map[MSINUM_REG_INDEX(N_INTR_RXQ3_DESC_EMPTY)] = 597179337Syongari MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_DESC_EMPTY); 598179337Syongari map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL)] = 599179337Syongari MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL); 600179337Syongari map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL)] = 601179337Syongari MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL); 602179337Syongari map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL)] = 603179337Syongari MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL); 604179337Syongari map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL)] = 605179337Syongari MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL); 606179337Syongari map[MSINUM_REG_INDEX(N_INTR_RXQ0_COAL_TO)] = 607179337Syongari MSINUM_INTR_SOURCE(1, N_INTR_RXQ0_COAL_TO); 608179337Syongari map[MSINUM_REG_INDEX(N_INTR_RXQ1_COAL_TO)] = 609179337Syongari MSINUM_INTR_SOURCE(1, N_INTR_RXQ1_COAL_TO); 610179337Syongari map[MSINUM_REG_INDEX(N_INTR_RXQ2_COAL_TO)] = 611179337Syongari MSINUM_INTR_SOURCE(1, N_INTR_RXQ2_COAL_TO); 612179337Syongari map[MSINUM_REG_INDEX(N_INTR_RXQ3_COAL_TO)] = 613179337Syongari MSINUM_INTR_SOURCE(1, N_INTR_RXQ3_COAL_TO); 614179337Syongari 615179337Syongari /* Map all other interrupts source to MSI/MSIX vector 0. */ 616179337Syongari CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 0, map[0]); 617179337Syongari CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 1, map[1]); 618179337Syongari CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 2, map[2]); 619179337Syongari CSR_WRITE_4(sc, JME_MSINUM_BASE + sizeof(uint32_t) * 3, map[3]); 620179337Syongari} 621179337Syongari 622179337Syongaristatic int 623179337Syongarijme_attach(device_t dev) 624179337Syongari{ 625179337Syongari struct jme_softc *sc; 626179337Syongari struct ifnet *ifp; 627179337Syongari struct mii_softc *miisc; 628179337Syongari struct mii_data *mii; 629179337Syongari uint32_t reg; 630179337Syongari uint16_t burst; 631216551Syongari int error, i, mii_flags, msic, msixc, pmc; 632179337Syongari 633179337Syongari error = 0; 634179337Syongari sc = device_get_softc(dev); 635179337Syongari sc->jme_dev = dev; 636179337Syongari 637179337Syongari mtx_init(&sc->jme_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 638179337Syongari MTX_DEF); 639179337Syongari callout_init_mtx(&sc->jme_tick_ch, &sc->jme_mtx, 0); 640179337Syongari TASK_INIT(&sc->jme_int_task, 0, jme_int_task, sc); 641179337Syongari TASK_INIT(&sc->jme_link_task, 0, jme_link_task, sc); 642179337Syongari 643179337Syongari /* 644179337Syongari * Map the device. JMC250 supports both memory mapped and I/O 645179337Syongari * register space access. Because I/O register access should 646179337Syongari * use different BARs to access registers it's waste of time 647179337Syongari * to use I/O register spce access. JMC250 uses 16K to map 648179337Syongari * entire memory space. 649179337Syongari */ 650179337Syongari pci_enable_busmaster(dev); 651179337Syongari sc->jme_res_spec = jme_res_spec_mem; 652179337Syongari sc->jme_irq_spec = jme_irq_spec_legacy; 653179337Syongari error = bus_alloc_resources(dev, sc->jme_res_spec, sc->jme_res); 654179337Syongari if (error != 0) { 655179337Syongari device_printf(dev, "cannot allocate memory resources.\n"); 656179337Syongari goto fail; 657179337Syongari } 658179337Syongari 659179337Syongari /* Allocate IRQ resources. */ 660179337Syongari msixc = pci_msix_count(dev); 661179337Syongari msic = pci_msi_count(dev); 662179337Syongari if (bootverbose) { 663179337Syongari device_printf(dev, "MSIX count : %d\n", msixc); 664179337Syongari device_printf(dev, "MSI count : %d\n", msic); 665179337Syongari } 666179337Syongari 667215848Syongari /* Use 1 MSI/MSI-X. */ 668215848Syongari if (msixc > 1) 669215848Syongari msixc = 1; 670215848Syongari if (msic > 1) 671215848Syongari msic = 1; 672179337Syongari /* Prefer MSIX over MSI. */ 673179337Syongari if (msix_disable == 0 || msi_disable == 0) { 674215848Syongari if (msix_disable == 0 && msixc > 0 && 675179337Syongari pci_alloc_msix(dev, &msixc) == 0) { 676215848Syongari if (msixc == 1) { 677179337Syongari device_printf(dev, "Using %d MSIX messages.\n", 678179337Syongari msixc); 679179337Syongari sc->jme_flags |= JME_FLAG_MSIX; 680179337Syongari sc->jme_irq_spec = jme_irq_spec_msi; 681179337Syongari } else 682179337Syongari pci_release_msi(dev); 683179337Syongari } 684179337Syongari if (msi_disable == 0 && (sc->jme_flags & JME_FLAG_MSIX) == 0 && 685215848Syongari msic > 0 && pci_alloc_msi(dev, &msic) == 0) { 686215848Syongari if (msic == 1) { 687179337Syongari device_printf(dev, "Using %d MSI messages.\n", 688179337Syongari msic); 689179337Syongari sc->jme_flags |= JME_FLAG_MSI; 690179337Syongari sc->jme_irq_spec = jme_irq_spec_msi; 691179337Syongari } else 692179337Syongari pci_release_msi(dev); 693179337Syongari } 694179337Syongari /* Map interrupt vector 0, 1 and 2. */ 695179337Syongari if ((sc->jme_flags & JME_FLAG_MSI) != 0 || 696179337Syongari (sc->jme_flags & JME_FLAG_MSIX) != 0) 697179337Syongari jme_map_intr_vector(sc); 698179337Syongari } 699179337Syongari 700179337Syongari error = bus_alloc_resources(dev, sc->jme_irq_spec, sc->jme_irq); 701179337Syongari if (error != 0) { 702179337Syongari device_printf(dev, "cannot allocate IRQ resources.\n"); 703179337Syongari goto fail; 704179337Syongari } 705179337Syongari 706183814Syongari sc->jme_rev = pci_get_device(dev); 707183814Syongari if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260) { 708179337Syongari sc->jme_flags |= JME_FLAG_FASTETH; 709179337Syongari sc->jme_flags |= JME_FLAG_NOJUMBO; 710179337Syongari } 711179337Syongari reg = CSR_READ_4(sc, JME_CHIPMODE); 712179337Syongari sc->jme_chip_rev = (reg & CHIPMODE_REV_MASK) >> CHIPMODE_REV_SHIFT; 713179337Syongari if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) != 714179337Syongari CHIPMODE_NOT_FPGA) 715179337Syongari sc->jme_flags |= JME_FLAG_FPGA; 716179337Syongari if (bootverbose) { 717179337Syongari device_printf(dev, "PCI device revision : 0x%04x\n", 718179337Syongari sc->jme_rev); 719179337Syongari device_printf(dev, "Chip revision : 0x%02x\n", 720179337Syongari sc->jme_chip_rev); 721179337Syongari if ((sc->jme_flags & JME_FLAG_FPGA) != 0) 722179337Syongari device_printf(dev, "FPGA revision : 0x%04x\n", 723179337Syongari (reg & CHIPMODE_FPGA_REV_MASK) >> 724179337Syongari CHIPMODE_FPGA_REV_SHIFT); 725179337Syongari } 726179337Syongari if (sc->jme_chip_rev == 0xFF) { 727179337Syongari device_printf(dev, "Unknown chip revision : 0x%02x\n", 728179337Syongari sc->jme_rev); 729179337Syongari error = ENXIO; 730179337Syongari goto fail; 731179337Syongari } 732179337Syongari 733216551Syongari /* Identify controller features and bugs. */ 734185596Syongari if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2) { 735185596Syongari if ((sc->jme_rev & DEVICEID_JMC2XX_MASK) == DEVICEID_JMC260 && 736185596Syongari CHIPMODE_REVFM(sc->jme_chip_rev) == 2) 737185596Syongari sc->jme_flags |= JME_FLAG_DMA32BIT; 738216551Syongari if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5) 739216551Syongari sc->jme_flags |= JME_FLAG_EFUSE | JME_FLAG_PCCPCD; 740216551Syongari sc->jme_flags |= JME_FLAG_TXCLK | JME_FLAG_RXCLK; 741185597Syongari sc->jme_flags |= JME_FLAG_HWMIB; 742185596Syongari } 743185596Syongari 744179337Syongari /* Reset the ethernet controller. */ 745179337Syongari jme_reset(sc); 746179337Syongari 747179337Syongari /* Get station address. */ 748216551Syongari if ((sc->jme_flags & JME_FLAG_EFUSE) != 0) { 749216551Syongari error = jme_efuse_macaddr(sc); 750216551Syongari if (error == 0) 751216551Syongari jme_reg_macaddr(sc); 752216551Syongari } else { 753216551Syongari error = ENOENT; 754216551Syongari reg = CSR_READ_4(sc, JME_SMBCSR); 755216551Syongari if ((reg & SMBCSR_EEPROM_PRESENT) != 0) 756216551Syongari error = jme_eeprom_macaddr(sc); 757216551Syongari if (error != 0 && bootverbose) 758179337Syongari device_printf(sc->jme_dev, 759179337Syongari "ethernet hardware address not found in EEPROM.\n"); 760216551Syongari if (error != 0) 761216551Syongari jme_reg_macaddr(sc); 762179337Syongari } 763179337Syongari 764179337Syongari /* 765179337Syongari * Save PHY address. 766179337Syongari * Integrated JR0211 has fixed PHY address whereas FPGA version 767179337Syongari * requires PHY probing to get correct PHY address. 768179337Syongari */ 769179337Syongari if ((sc->jme_flags & JME_FLAG_FPGA) == 0) { 770179337Syongari sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) & 771179337Syongari GPREG0_PHY_ADDR_MASK; 772179337Syongari if (bootverbose) 773179337Syongari device_printf(dev, "PHY is at address %d.\n", 774179337Syongari sc->jme_phyaddr); 775179337Syongari } else 776179337Syongari sc->jme_phyaddr = 0; 777179337Syongari 778179337Syongari /* Set max allowable DMA size. */ 779219902Sjhb if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 780179337Syongari sc->jme_flags |= JME_FLAG_PCIE; 781240680Sgavin burst = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2); 782179337Syongari if (bootverbose) { 783179337Syongari device_printf(dev, "Read request size : %d bytes.\n", 784179337Syongari 128 << ((burst >> 12) & 0x07)); 785179337Syongari device_printf(dev, "TLP payload size : %d bytes.\n", 786179337Syongari 128 << ((burst >> 5) & 0x07)); 787179337Syongari } 788179337Syongari switch ((burst >> 12) & 0x07) { 789179337Syongari case 0: 790179337Syongari sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128; 791179337Syongari break; 792179337Syongari case 1: 793179337Syongari sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256; 794179337Syongari break; 795179337Syongari default: 796179337Syongari sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512; 797179337Syongari break; 798179337Syongari } 799179337Syongari sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128; 800179337Syongari } else { 801179337Syongari sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512; 802179337Syongari sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128; 803179337Syongari } 804179337Syongari /* Create coalescing sysctl node. */ 805179337Syongari jme_sysctl_node(sc); 806179337Syongari if ((error = jme_dma_alloc(sc) != 0)) 807179337Syongari goto fail; 808179337Syongari 809179337Syongari ifp = sc->jme_ifp = if_alloc(IFT_ETHER); 810179337Syongari if (ifp == NULL) { 811179337Syongari device_printf(dev, "cannot allocate ifnet structure.\n"); 812179337Syongari error = ENXIO; 813179337Syongari goto fail; 814179337Syongari } 815179337Syongari 816179337Syongari ifp->if_softc = sc; 817179337Syongari if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 818179337Syongari ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 819179337Syongari ifp->if_ioctl = jme_ioctl; 820179337Syongari ifp->if_start = jme_start; 821179337Syongari ifp->if_init = jme_init; 822179337Syongari ifp->if_snd.ifq_drv_maxlen = JME_TX_RING_CNT - 1; 823179337Syongari IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 824179337Syongari IFQ_SET_READY(&ifp->if_snd); 825179337Syongari /* JMC250 supports Tx/Rx checksum offload as well as TSO. */ 826179337Syongari ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 827179337Syongari ifp->if_hwassist = JME_CSUM_FEATURES | CSUM_TSO; 828219902Sjhb if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 829179337Syongari sc->jme_flags |= JME_FLAG_PMCAP; 830179337Syongari ifp->if_capabilities |= IFCAP_WOL_MAGIC; 831179337Syongari } 832179337Syongari ifp->if_capenable = ifp->if_capabilities; 833179337Syongari 834216551Syongari /* Wakeup PHY. */ 835216551Syongari jme_phy_up(sc); 836216551Syongari mii_flags = MIIF_DOPAUSE; 837216551Syongari /* Ask PHY calibration to PHY driver. */ 838216551Syongari if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5) 839216551Syongari mii_flags |= MIIF_MACPRIV0; 840179337Syongari /* Set up MII bus. */ 841213893Smarius error = mii_attach(dev, &sc->jme_miibus, ifp, jme_mediachange, 842216548Syongari jme_mediastatus, BMSR_DEFCAPMASK, 843216548Syongari sc->jme_flags & JME_FLAG_FPGA ? MII_PHY_ANY : sc->jme_phyaddr, 844216551Syongari MII_OFFSET_ANY, mii_flags); 845213893Smarius if (error != 0) { 846213893Smarius device_printf(dev, "attaching PHYs failed\n"); 847179337Syongari goto fail; 848179337Syongari } 849179337Syongari 850179337Syongari /* 851179337Syongari * Force PHY to FPGA mode. 852179337Syongari */ 853179337Syongari if ((sc->jme_flags & JME_FLAG_FPGA) != 0) { 854179337Syongari mii = device_get_softc(sc->jme_miibus); 855179337Syongari if (mii->mii_instance != 0) { 856179337Syongari LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 857179337Syongari if (miisc->mii_phy != 0) { 858179337Syongari sc->jme_phyaddr = miisc->mii_phy; 859179337Syongari break; 860179337Syongari } 861179337Syongari } 862179337Syongari if (sc->jme_phyaddr != 0) { 863179337Syongari device_printf(sc->jme_dev, 864179337Syongari "FPGA PHY is at %d\n", sc->jme_phyaddr); 865179337Syongari /* vendor magic. */ 866179337Syongari jme_miibus_writereg(dev, sc->jme_phyaddr, 27, 867179337Syongari 0x0004); 868179337Syongari } 869179337Syongari } 870179337Syongari } 871179337Syongari 872179337Syongari ether_ifattach(ifp, sc->jme_eaddr); 873179337Syongari 874179337Syongari /* VLAN capability setup */ 875179337Syongari ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 876204225Syongari IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 877179337Syongari ifp->if_capenable = ifp->if_capabilities; 878179337Syongari 879179337Syongari /* Tell the upper layer(s) we support long frames. */ 880179337Syongari ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 881179337Syongari 882179337Syongari /* Create local taskq. */ 883179337Syongari sc->jme_tq = taskqueue_create_fast("jme_taskq", M_WAITOK, 884179337Syongari taskqueue_thread_enqueue, &sc->jme_tq); 885179337Syongari if (sc->jme_tq == NULL) { 886179337Syongari device_printf(dev, "could not create taskqueue.\n"); 887179337Syongari ether_ifdetach(ifp); 888179337Syongari error = ENXIO; 889179337Syongari goto fail; 890179337Syongari } 891179337Syongari taskqueue_start_threads(&sc->jme_tq, 1, PI_NET, "%s taskq", 892179337Syongari device_get_nameunit(sc->jme_dev)); 893179337Syongari 894215848Syongari for (i = 0; i < 1; i++) { 895179337Syongari error = bus_setup_intr(dev, sc->jme_irq[i], 896179337Syongari INTR_TYPE_NET | INTR_MPSAFE, jme_intr, NULL, sc, 897179337Syongari &sc->jme_intrhand[i]); 898179337Syongari if (error != 0) 899179337Syongari break; 900179337Syongari } 901179337Syongari 902179337Syongari if (error != 0) { 903179337Syongari device_printf(dev, "could not set up interrupt handler.\n"); 904179337Syongari taskqueue_free(sc->jme_tq); 905179337Syongari sc->jme_tq = NULL; 906179337Syongari ether_ifdetach(ifp); 907179337Syongari goto fail; 908179337Syongari } 909179337Syongari 910179337Syongarifail: 911179337Syongari if (error != 0) 912179337Syongari jme_detach(dev); 913179337Syongari 914179337Syongari return (error); 915179337Syongari} 916179337Syongari 917179337Syongaristatic int 918179337Syongarijme_detach(device_t dev) 919179337Syongari{ 920179337Syongari struct jme_softc *sc; 921179337Syongari struct ifnet *ifp; 922215848Syongari int i; 923179337Syongari 924179337Syongari sc = device_get_softc(dev); 925179337Syongari 926179337Syongari ifp = sc->jme_ifp; 927179337Syongari if (device_is_attached(dev)) { 928179337Syongari JME_LOCK(sc); 929179337Syongari sc->jme_flags |= JME_FLAG_DETACH; 930179337Syongari jme_stop(sc); 931179337Syongari JME_UNLOCK(sc); 932179337Syongari callout_drain(&sc->jme_tick_ch); 933179337Syongari taskqueue_drain(sc->jme_tq, &sc->jme_int_task); 934179337Syongari taskqueue_drain(taskqueue_swi, &sc->jme_link_task); 935216551Syongari /* Restore possibly modified station address. */ 936216551Syongari if ((sc->jme_flags & JME_FLAG_EFUSE) != 0) 937216551Syongari jme_set_macaddr(sc, sc->jme_eaddr); 938179337Syongari ether_ifdetach(ifp); 939179337Syongari } 940179337Syongari 941179337Syongari if (sc->jme_tq != NULL) { 942179337Syongari taskqueue_drain(sc->jme_tq, &sc->jme_int_task); 943179337Syongari taskqueue_free(sc->jme_tq); 944179337Syongari sc->jme_tq = NULL; 945179337Syongari } 946179337Syongari 947179337Syongari if (sc->jme_miibus != NULL) { 948179337Syongari device_delete_child(dev, sc->jme_miibus); 949179337Syongari sc->jme_miibus = NULL; 950179337Syongari } 951179337Syongari bus_generic_detach(dev); 952179337Syongari jme_dma_free(sc); 953179337Syongari 954179337Syongari if (ifp != NULL) { 955179337Syongari if_free(ifp); 956179337Syongari sc->jme_ifp = NULL; 957179337Syongari } 958179337Syongari 959215848Syongari for (i = 0; i < 1; i++) { 960179337Syongari if (sc->jme_intrhand[i] != NULL) { 961179337Syongari bus_teardown_intr(dev, sc->jme_irq[i], 962179337Syongari sc->jme_intrhand[i]); 963179337Syongari sc->jme_intrhand[i] = NULL; 964179337Syongari } 965179337Syongari } 966179337Syongari 967216549Syongari if (sc->jme_irq[0] != NULL) 968216549Syongari bus_release_resources(dev, sc->jme_irq_spec, sc->jme_irq); 969179337Syongari if ((sc->jme_flags & (JME_FLAG_MSIX | JME_FLAG_MSI)) != 0) 970179337Syongari pci_release_msi(dev); 971216549Syongari if (sc->jme_res[0] != NULL) 972216549Syongari bus_release_resources(dev, sc->jme_res_spec, sc->jme_res); 973179337Syongari mtx_destroy(&sc->jme_mtx); 974179337Syongari 975179337Syongari return (0); 976179337Syongari} 977179337Syongari 978185597Syongari#define JME_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 979185597Syongari SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 980185597Syongari 981179337Syongaristatic void 982179337Syongarijme_sysctl_node(struct jme_softc *sc) 983179337Syongari{ 984185597Syongari struct sysctl_ctx_list *ctx; 985185597Syongari struct sysctl_oid_list *child, *parent; 986185597Syongari struct sysctl_oid *tree; 987185597Syongari struct jme_hw_stats *stats; 988179337Syongari int error; 989179337Syongari 990185597Syongari stats = &sc->jme_stats; 991185597Syongari ctx = device_get_sysctl_ctx(sc->jme_dev); 992185597Syongari child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->jme_dev)); 993179337Syongari 994185597Syongari SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "tx_coal_to", 995185597Syongari CTLTYPE_INT | CTLFLAG_RW, &sc->jme_tx_coal_to, 0, 996185597Syongari sysctl_hw_jme_tx_coal_to, "I", "jme tx coalescing timeout"); 997179337Syongari 998185597Syongari SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "tx_coal_pkt", 999185597Syongari CTLTYPE_INT | CTLFLAG_RW, &sc->jme_tx_coal_pkt, 0, 1000185597Syongari sysctl_hw_jme_tx_coal_pkt, "I", "jme tx coalescing packet"); 1001179337Syongari 1002185597Syongari SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_coal_to", 1003185597Syongari CTLTYPE_INT | CTLFLAG_RW, &sc->jme_rx_coal_to, 0, 1004185597Syongari sysctl_hw_jme_rx_coal_to, "I", "jme rx coalescing timeout"); 1005179337Syongari 1006185597Syongari SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "rx_coal_pkt", 1007185597Syongari CTLTYPE_INT | CTLFLAG_RW, &sc->jme_rx_coal_pkt, 0, 1008185597Syongari sysctl_hw_jme_rx_coal_pkt, "I", "jme rx coalescing packet"); 1009185597Syongari 1010185597Syongari SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 1011185597Syongari CTLTYPE_INT | CTLFLAG_RW, &sc->jme_process_limit, 0, 1012185597Syongari sysctl_hw_jme_proc_limit, "I", 1013179337Syongari "max number of Rx events to process"); 1014179337Syongari 1015179337Syongari /* Pull in device tunables. */ 1016179337Syongari sc->jme_process_limit = JME_PROC_DEFAULT; 1017179337Syongari error = resource_int_value(device_get_name(sc->jme_dev), 1018179337Syongari device_get_unit(sc->jme_dev), "process_limit", 1019179337Syongari &sc->jme_process_limit); 1020179337Syongari if (error == 0) { 1021179337Syongari if (sc->jme_process_limit < JME_PROC_MIN || 1022179337Syongari sc->jme_process_limit > JME_PROC_MAX) { 1023179337Syongari device_printf(sc->jme_dev, 1024179337Syongari "process_limit value out of range; " 1025179337Syongari "using default: %d\n", JME_PROC_DEFAULT); 1026179337Syongari sc->jme_process_limit = JME_PROC_DEFAULT; 1027179337Syongari } 1028179337Syongari } 1029179337Syongari 1030179337Syongari sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT; 1031179337Syongari error = resource_int_value(device_get_name(sc->jme_dev), 1032179337Syongari device_get_unit(sc->jme_dev), "tx_coal_to", &sc->jme_tx_coal_to); 1033179337Syongari if (error == 0) { 1034179337Syongari if (sc->jme_tx_coal_to < PCCTX_COAL_TO_MIN || 1035179337Syongari sc->jme_tx_coal_to > PCCTX_COAL_TO_MAX) { 1036179337Syongari device_printf(sc->jme_dev, 1037179337Syongari "tx_coal_to value out of range; " 1038179337Syongari "using default: %d\n", PCCTX_COAL_TO_DEFAULT); 1039179337Syongari sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT; 1040179337Syongari } 1041179337Syongari } 1042179337Syongari 1043179337Syongari sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT; 1044179337Syongari error = resource_int_value(device_get_name(sc->jme_dev), 1045179337Syongari device_get_unit(sc->jme_dev), "tx_coal_pkt", &sc->jme_tx_coal_to); 1046179337Syongari if (error == 0) { 1047179337Syongari if (sc->jme_tx_coal_pkt < PCCTX_COAL_PKT_MIN || 1048179337Syongari sc->jme_tx_coal_pkt > PCCTX_COAL_PKT_MAX) { 1049179337Syongari device_printf(sc->jme_dev, 1050179337Syongari "tx_coal_pkt value out of range; " 1051179337Syongari "using default: %d\n", PCCTX_COAL_PKT_DEFAULT); 1052179337Syongari sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT; 1053179337Syongari } 1054179337Syongari } 1055179337Syongari 1056179337Syongari sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT; 1057179337Syongari error = resource_int_value(device_get_name(sc->jme_dev), 1058179337Syongari device_get_unit(sc->jme_dev), "rx_coal_to", &sc->jme_rx_coal_to); 1059179337Syongari if (error == 0) { 1060179337Syongari if (sc->jme_rx_coal_to < PCCRX_COAL_TO_MIN || 1061179337Syongari sc->jme_rx_coal_to > PCCRX_COAL_TO_MAX) { 1062179337Syongari device_printf(sc->jme_dev, 1063179337Syongari "rx_coal_to value out of range; " 1064179337Syongari "using default: %d\n", PCCRX_COAL_TO_DEFAULT); 1065179337Syongari sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT; 1066179337Syongari } 1067179337Syongari } 1068179337Syongari 1069179337Syongari sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT; 1070179337Syongari error = resource_int_value(device_get_name(sc->jme_dev), 1071179337Syongari device_get_unit(sc->jme_dev), "rx_coal_pkt", &sc->jme_rx_coal_to); 1072179337Syongari if (error == 0) { 1073179337Syongari if (sc->jme_rx_coal_pkt < PCCRX_COAL_PKT_MIN || 1074179337Syongari sc->jme_rx_coal_pkt > PCCRX_COAL_PKT_MAX) { 1075179337Syongari device_printf(sc->jme_dev, 1076179337Syongari "tx_coal_pkt value out of range; " 1077179337Syongari "using default: %d\n", PCCRX_COAL_PKT_DEFAULT); 1078179337Syongari sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT; 1079179337Syongari } 1080179337Syongari } 1081185597Syongari 1082185597Syongari if ((sc->jme_flags & JME_FLAG_HWMIB) == 0) 1083185597Syongari return; 1084185597Syongari 1085185597Syongari tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 1086185597Syongari NULL, "JME statistics"); 1087185597Syongari parent = SYSCTL_CHILDREN(tree); 1088185597Syongari 1089185597Syongari /* Rx statistics. */ 1090185597Syongari tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 1091185597Syongari NULL, "Rx MAC statistics"); 1092185597Syongari child = SYSCTL_CHILDREN(tree); 1093185597Syongari JME_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1094185597Syongari &stats->rx_good_frames, "Good frames"); 1095185597Syongari JME_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 1096185597Syongari &stats->rx_crc_errs, "CRC errors"); 1097185597Syongari JME_SYSCTL_STAT_ADD32(ctx, child, "mii_errs", 1098185597Syongari &stats->rx_mii_errs, "MII errors"); 1099185597Syongari JME_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 1100185597Syongari &stats->rx_fifo_oflows, "FIFO overflows"); 1101185597Syongari JME_SYSCTL_STAT_ADD32(ctx, child, "desc_empty", 1102185597Syongari &stats->rx_desc_empty, "Descriptor empty"); 1103185597Syongari JME_SYSCTL_STAT_ADD32(ctx, child, "bad_frames", 1104185597Syongari &stats->rx_bad_frames, "Bad frames"); 1105185597Syongari 1106185597Syongari /* Tx statistics. */ 1107185597Syongari tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 1108185597Syongari NULL, "Tx MAC statistics"); 1109185597Syongari child = SYSCTL_CHILDREN(tree); 1110185597Syongari JME_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1111185597Syongari &stats->tx_good_frames, "Good frames"); 1112185597Syongari JME_SYSCTL_STAT_ADD32(ctx, child, "bad_frames", 1113185597Syongari &stats->tx_bad_frames, "Bad frames"); 1114179337Syongari} 1115179337Syongari 1116185597Syongari#undef JME_SYSCTL_STAT_ADD32 1117185597Syongari 1118179337Syongaristruct jme_dmamap_arg { 1119179337Syongari bus_addr_t jme_busaddr; 1120179337Syongari}; 1121179337Syongari 1122179337Syongaristatic void 1123179337Syongarijme_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1124179337Syongari{ 1125179337Syongari struct jme_dmamap_arg *ctx; 1126179337Syongari 1127179337Syongari if (error != 0) 1128179337Syongari return; 1129179337Syongari 1130179337Syongari KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1131179337Syongari 1132179337Syongari ctx = (struct jme_dmamap_arg *)arg; 1133179337Syongari ctx->jme_busaddr = segs[0].ds_addr; 1134179337Syongari} 1135179337Syongari 1136179337Syongaristatic int 1137179337Syongarijme_dma_alloc(struct jme_softc *sc) 1138179337Syongari{ 1139179337Syongari struct jme_dmamap_arg ctx; 1140179337Syongari struct jme_txdesc *txd; 1141179337Syongari struct jme_rxdesc *rxd; 1142179337Syongari bus_addr_t lowaddr, rx_ring_end, tx_ring_end; 1143179337Syongari int error, i; 1144179337Syongari 1145179337Syongari lowaddr = BUS_SPACE_MAXADDR; 1146185596Syongari if ((sc->jme_flags & JME_FLAG_DMA32BIT) != 0) 1147185596Syongari lowaddr = BUS_SPACE_MAXADDR_32BIT; 1148179337Syongari 1149179337Syongariagain: 1150179337Syongari /* Create parent ring tag. */ 1151179337Syongari error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */ 1152179337Syongari 1, 0, /* algnmnt, boundary */ 1153179337Syongari lowaddr, /* lowaddr */ 1154179337Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1155179337Syongari NULL, NULL, /* filter, filterarg */ 1156179337Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1157179337Syongari 0, /* nsegments */ 1158179337Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1159179337Syongari 0, /* flags */ 1160179337Syongari NULL, NULL, /* lockfunc, lockarg */ 1161179337Syongari &sc->jme_cdata.jme_ring_tag); 1162179337Syongari if (error != 0) { 1163179337Syongari device_printf(sc->jme_dev, 1164179337Syongari "could not create parent ring DMA tag.\n"); 1165179337Syongari goto fail; 1166179337Syongari } 1167179337Syongari /* Create tag for Tx ring. */ 1168179337Syongari error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */ 1169179337Syongari JME_TX_RING_ALIGN, 0, /* algnmnt, boundary */ 1170179337Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1171179337Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1172179337Syongari NULL, NULL, /* filter, filterarg */ 1173179337Syongari JME_TX_RING_SIZE, /* maxsize */ 1174179337Syongari 1, /* nsegments */ 1175179337Syongari JME_TX_RING_SIZE, /* maxsegsize */ 1176179337Syongari 0, /* flags */ 1177179337Syongari NULL, NULL, /* lockfunc, lockarg */ 1178179337Syongari &sc->jme_cdata.jme_tx_ring_tag); 1179179337Syongari if (error != 0) { 1180179337Syongari device_printf(sc->jme_dev, 1181179337Syongari "could not allocate Tx ring DMA tag.\n"); 1182179337Syongari goto fail; 1183179337Syongari } 1184179337Syongari 1185179337Syongari /* Create tag for Rx ring. */ 1186179337Syongari error = bus_dma_tag_create(sc->jme_cdata.jme_ring_tag,/* parent */ 1187179337Syongari JME_RX_RING_ALIGN, 0, /* algnmnt, boundary */ 1188179337Syongari lowaddr, /* lowaddr */ 1189179337Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1190179337Syongari NULL, NULL, /* filter, filterarg */ 1191179337Syongari JME_RX_RING_SIZE, /* maxsize */ 1192179337Syongari 1, /* nsegments */ 1193179337Syongari JME_RX_RING_SIZE, /* maxsegsize */ 1194179337Syongari 0, /* flags */ 1195179337Syongari NULL, NULL, /* lockfunc, lockarg */ 1196179337Syongari &sc->jme_cdata.jme_rx_ring_tag); 1197179337Syongari if (error != 0) { 1198179337Syongari device_printf(sc->jme_dev, 1199179337Syongari "could not allocate Rx ring DMA tag.\n"); 1200179337Syongari goto fail; 1201179337Syongari } 1202179337Syongari 1203179337Syongari /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1204179337Syongari error = bus_dmamem_alloc(sc->jme_cdata.jme_tx_ring_tag, 1205179337Syongari (void **)&sc->jme_rdata.jme_tx_ring, 1206179337Syongari BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1207179337Syongari &sc->jme_cdata.jme_tx_ring_map); 1208179337Syongari if (error != 0) { 1209179337Syongari device_printf(sc->jme_dev, 1210179337Syongari "could not allocate DMA'able memory for Tx ring.\n"); 1211179337Syongari goto fail; 1212179337Syongari } 1213179337Syongari 1214179337Syongari ctx.jme_busaddr = 0; 1215179337Syongari error = bus_dmamap_load(sc->jme_cdata.jme_tx_ring_tag, 1216179337Syongari sc->jme_cdata.jme_tx_ring_map, sc->jme_rdata.jme_tx_ring, 1217179337Syongari JME_TX_RING_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 1218179337Syongari if (error != 0 || ctx.jme_busaddr == 0) { 1219179337Syongari device_printf(sc->jme_dev, 1220179337Syongari "could not load DMA'able memory for Tx ring.\n"); 1221179337Syongari goto fail; 1222179337Syongari } 1223179337Syongari sc->jme_rdata.jme_tx_ring_paddr = ctx.jme_busaddr; 1224179337Syongari 1225179337Syongari /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1226179337Syongari error = bus_dmamem_alloc(sc->jme_cdata.jme_rx_ring_tag, 1227179337Syongari (void **)&sc->jme_rdata.jme_rx_ring, 1228179337Syongari BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1229179337Syongari &sc->jme_cdata.jme_rx_ring_map); 1230179337Syongari if (error != 0) { 1231179337Syongari device_printf(sc->jme_dev, 1232179337Syongari "could not allocate DMA'able memory for Rx ring.\n"); 1233179337Syongari goto fail; 1234179337Syongari } 1235179337Syongari 1236179337Syongari ctx.jme_busaddr = 0; 1237179337Syongari error = bus_dmamap_load(sc->jme_cdata.jme_rx_ring_tag, 1238179337Syongari sc->jme_cdata.jme_rx_ring_map, sc->jme_rdata.jme_rx_ring, 1239179337Syongari JME_RX_RING_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 1240179337Syongari if (error != 0 || ctx.jme_busaddr == 0) { 1241179337Syongari device_printf(sc->jme_dev, 1242179337Syongari "could not load DMA'able memory for Rx ring.\n"); 1243179337Syongari goto fail; 1244179337Syongari } 1245179337Syongari sc->jme_rdata.jme_rx_ring_paddr = ctx.jme_busaddr; 1246179337Syongari 1247185596Syongari if (lowaddr != BUS_SPACE_MAXADDR_32BIT) { 1248185596Syongari /* Tx/Rx descriptor queue should reside within 4GB boundary. */ 1249185596Syongari tx_ring_end = sc->jme_rdata.jme_tx_ring_paddr + 1250185596Syongari JME_TX_RING_SIZE; 1251185596Syongari rx_ring_end = sc->jme_rdata.jme_rx_ring_paddr + 1252185596Syongari JME_RX_RING_SIZE; 1253185596Syongari if ((JME_ADDR_HI(tx_ring_end) != 1254185596Syongari JME_ADDR_HI(sc->jme_rdata.jme_tx_ring_paddr)) || 1255185596Syongari (JME_ADDR_HI(rx_ring_end) != 1256185596Syongari JME_ADDR_HI(sc->jme_rdata.jme_rx_ring_paddr))) { 1257185596Syongari device_printf(sc->jme_dev, "4GB boundary crossed, " 1258185596Syongari "switching to 32bit DMA address mode.\n"); 1259185596Syongari jme_dma_free(sc); 1260185596Syongari /* Limit DMA address space to 32bit and try again. */ 1261185596Syongari lowaddr = BUS_SPACE_MAXADDR_32BIT; 1262185596Syongari goto again; 1263185596Syongari } 1264179337Syongari } 1265179337Syongari 1266185596Syongari lowaddr = BUS_SPACE_MAXADDR; 1267185596Syongari if ((sc->jme_flags & JME_FLAG_DMA32BIT) != 0) 1268185596Syongari lowaddr = BUS_SPACE_MAXADDR_32BIT; 1269179337Syongari /* Create parent buffer tag. */ 1270179337Syongari error = bus_dma_tag_create(bus_get_dma_tag(sc->jme_dev),/* parent */ 1271179337Syongari 1, 0, /* algnmnt, boundary */ 1272185596Syongari lowaddr, /* lowaddr */ 1273179337Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1274179337Syongari NULL, NULL, /* filter, filterarg */ 1275179337Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1276179337Syongari 0, /* nsegments */ 1277179337Syongari BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1278179337Syongari 0, /* flags */ 1279179337Syongari NULL, NULL, /* lockfunc, lockarg */ 1280179337Syongari &sc->jme_cdata.jme_buffer_tag); 1281179337Syongari if (error != 0) { 1282179337Syongari device_printf(sc->jme_dev, 1283179337Syongari "could not create parent buffer DMA tag.\n"); 1284179337Syongari goto fail; 1285179337Syongari } 1286179337Syongari 1287179337Syongari /* Create shadow status block tag. */ 1288179337Syongari error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */ 1289179337Syongari JME_SSB_ALIGN, 0, /* algnmnt, boundary */ 1290179337Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1291179337Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1292179337Syongari NULL, NULL, /* filter, filterarg */ 1293179337Syongari JME_SSB_SIZE, /* maxsize */ 1294179337Syongari 1, /* nsegments */ 1295179337Syongari JME_SSB_SIZE, /* maxsegsize */ 1296179337Syongari 0, /* flags */ 1297179337Syongari NULL, NULL, /* lockfunc, lockarg */ 1298179337Syongari &sc->jme_cdata.jme_ssb_tag); 1299179337Syongari if (error != 0) { 1300179337Syongari device_printf(sc->jme_dev, 1301179337Syongari "could not create shared status block DMA tag.\n"); 1302179337Syongari goto fail; 1303179337Syongari } 1304179337Syongari 1305179337Syongari /* Create tag for Tx buffers. */ 1306179337Syongari error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */ 1307179337Syongari 1, 0, /* algnmnt, boundary */ 1308179337Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1309179337Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1310179337Syongari NULL, NULL, /* filter, filterarg */ 1311179337Syongari JME_TSO_MAXSIZE, /* maxsize */ 1312179337Syongari JME_MAXTXSEGS, /* nsegments */ 1313179337Syongari JME_TSO_MAXSEGSIZE, /* maxsegsize */ 1314179337Syongari 0, /* flags */ 1315179337Syongari NULL, NULL, /* lockfunc, lockarg */ 1316179337Syongari &sc->jme_cdata.jme_tx_tag); 1317179337Syongari if (error != 0) { 1318179337Syongari device_printf(sc->jme_dev, "could not create Tx DMA tag.\n"); 1319179337Syongari goto fail; 1320179337Syongari } 1321179337Syongari 1322179337Syongari /* Create tag for Rx buffers. */ 1323179337Syongari error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */ 1324179337Syongari JME_RX_BUF_ALIGN, 0, /* algnmnt, boundary */ 1325179337Syongari BUS_SPACE_MAXADDR, /* lowaddr */ 1326179337Syongari BUS_SPACE_MAXADDR, /* highaddr */ 1327179337Syongari NULL, NULL, /* filter, filterarg */ 1328179337Syongari MCLBYTES, /* maxsize */ 1329179337Syongari 1, /* nsegments */ 1330179337Syongari MCLBYTES, /* maxsegsize */ 1331179337Syongari 0, /* flags */ 1332179337Syongari NULL, NULL, /* lockfunc, lockarg */ 1333179337Syongari &sc->jme_cdata.jme_rx_tag); 1334179337Syongari if (error != 0) { 1335179337Syongari device_printf(sc->jme_dev, "could not create Rx DMA tag.\n"); 1336179337Syongari goto fail; 1337179337Syongari } 1338179337Syongari 1339179337Syongari /* 1340179337Syongari * Allocate DMA'able memory and load the DMA map for shared 1341179337Syongari * status block. 1342179337Syongari */ 1343179337Syongari error = bus_dmamem_alloc(sc->jme_cdata.jme_ssb_tag, 1344179337Syongari (void **)&sc->jme_rdata.jme_ssb_block, 1345179337Syongari BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1346179337Syongari &sc->jme_cdata.jme_ssb_map); 1347179337Syongari if (error != 0) { 1348179337Syongari device_printf(sc->jme_dev, "could not allocate DMA'able " 1349179337Syongari "memory for shared status block.\n"); 1350179337Syongari goto fail; 1351179337Syongari } 1352179337Syongari 1353179337Syongari ctx.jme_busaddr = 0; 1354179337Syongari error = bus_dmamap_load(sc->jme_cdata.jme_ssb_tag, 1355179337Syongari sc->jme_cdata.jme_ssb_map, sc->jme_rdata.jme_ssb_block, 1356179337Syongari JME_SSB_SIZE, jme_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 1357179337Syongari if (error != 0 || ctx.jme_busaddr == 0) { 1358179337Syongari device_printf(sc->jme_dev, "could not load DMA'able memory " 1359179337Syongari "for shared status block.\n"); 1360179337Syongari goto fail; 1361179337Syongari } 1362179337Syongari sc->jme_rdata.jme_ssb_block_paddr = ctx.jme_busaddr; 1363179337Syongari 1364179337Syongari /* Create DMA maps for Tx buffers. */ 1365179337Syongari for (i = 0; i < JME_TX_RING_CNT; i++) { 1366179337Syongari txd = &sc->jme_cdata.jme_txdesc[i]; 1367179337Syongari txd->tx_m = NULL; 1368179337Syongari txd->tx_dmamap = NULL; 1369179337Syongari error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag, 0, 1370179337Syongari &txd->tx_dmamap); 1371179337Syongari if (error != 0) { 1372179337Syongari device_printf(sc->jme_dev, 1373179337Syongari "could not create Tx dmamap.\n"); 1374179337Syongari goto fail; 1375179337Syongari } 1376179337Syongari } 1377179337Syongari /* Create DMA maps for Rx buffers. */ 1378179337Syongari if ((error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0, 1379179337Syongari &sc->jme_cdata.jme_rx_sparemap)) != 0) { 1380179337Syongari device_printf(sc->jme_dev, 1381179337Syongari "could not create spare Rx dmamap.\n"); 1382179337Syongari goto fail; 1383179337Syongari } 1384179337Syongari for (i = 0; i < JME_RX_RING_CNT; i++) { 1385179337Syongari rxd = &sc->jme_cdata.jme_rxdesc[i]; 1386179337Syongari rxd->rx_m = NULL; 1387179337Syongari rxd->rx_dmamap = NULL; 1388179337Syongari error = bus_dmamap_create(sc->jme_cdata.jme_rx_tag, 0, 1389179337Syongari &rxd->rx_dmamap); 1390179337Syongari if (error != 0) { 1391179337Syongari device_printf(sc->jme_dev, 1392179337Syongari "could not create Rx dmamap.\n"); 1393179337Syongari goto fail; 1394179337Syongari } 1395179337Syongari } 1396179337Syongari 1397179337Syongarifail: 1398179337Syongari return (error); 1399179337Syongari} 1400179337Syongari 1401179337Syongaristatic void 1402179337Syongarijme_dma_free(struct jme_softc *sc) 1403179337Syongari{ 1404179337Syongari struct jme_txdesc *txd; 1405179337Syongari struct jme_rxdesc *rxd; 1406179337Syongari int i; 1407179337Syongari 1408179337Syongari /* Tx ring */ 1409179337Syongari if (sc->jme_cdata.jme_tx_ring_tag != NULL) { 1410179337Syongari if (sc->jme_cdata.jme_tx_ring_map) 1411179337Syongari bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag, 1412179337Syongari sc->jme_cdata.jme_tx_ring_map); 1413179337Syongari if (sc->jme_cdata.jme_tx_ring_map && 1414179337Syongari sc->jme_rdata.jme_tx_ring) 1415179337Syongari bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag, 1416179337Syongari sc->jme_rdata.jme_tx_ring, 1417179337Syongari sc->jme_cdata.jme_tx_ring_map); 1418179337Syongari sc->jme_rdata.jme_tx_ring = NULL; 1419179337Syongari sc->jme_cdata.jme_tx_ring_map = NULL; 1420179337Syongari bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag); 1421179337Syongari sc->jme_cdata.jme_tx_ring_tag = NULL; 1422179337Syongari } 1423179337Syongari /* Rx ring */ 1424179337Syongari if (sc->jme_cdata.jme_rx_ring_tag != NULL) { 1425179337Syongari if (sc->jme_cdata.jme_rx_ring_map) 1426179337Syongari bus_dmamap_unload(sc->jme_cdata.jme_rx_ring_tag, 1427179337Syongari sc->jme_cdata.jme_rx_ring_map); 1428179337Syongari if (sc->jme_cdata.jme_rx_ring_map && 1429179337Syongari sc->jme_rdata.jme_rx_ring) 1430179337Syongari bus_dmamem_free(sc->jme_cdata.jme_rx_ring_tag, 1431179337Syongari sc->jme_rdata.jme_rx_ring, 1432179337Syongari sc->jme_cdata.jme_rx_ring_map); 1433179337Syongari sc->jme_rdata.jme_rx_ring = NULL; 1434179337Syongari sc->jme_cdata.jme_rx_ring_map = NULL; 1435179337Syongari bus_dma_tag_destroy(sc->jme_cdata.jme_rx_ring_tag); 1436179337Syongari sc->jme_cdata.jme_rx_ring_tag = NULL; 1437179337Syongari } 1438179337Syongari /* Tx buffers */ 1439179337Syongari if (sc->jme_cdata.jme_tx_tag != NULL) { 1440179337Syongari for (i = 0; i < JME_TX_RING_CNT; i++) { 1441179337Syongari txd = &sc->jme_cdata.jme_txdesc[i]; 1442179337Syongari if (txd->tx_dmamap != NULL) { 1443179337Syongari bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag, 1444179337Syongari txd->tx_dmamap); 1445179337Syongari txd->tx_dmamap = NULL; 1446179337Syongari } 1447179337Syongari } 1448179337Syongari bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag); 1449179337Syongari sc->jme_cdata.jme_tx_tag = NULL; 1450179337Syongari } 1451179337Syongari /* Rx buffers */ 1452179337Syongari if (sc->jme_cdata.jme_rx_tag != NULL) { 1453179337Syongari for (i = 0; i < JME_RX_RING_CNT; i++) { 1454179337Syongari rxd = &sc->jme_cdata.jme_rxdesc[i]; 1455179337Syongari if (rxd->rx_dmamap != NULL) { 1456179337Syongari bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag, 1457179337Syongari rxd->rx_dmamap); 1458179337Syongari rxd->rx_dmamap = NULL; 1459179337Syongari } 1460179337Syongari } 1461179337Syongari if (sc->jme_cdata.jme_rx_sparemap != NULL) { 1462179337Syongari bus_dmamap_destroy(sc->jme_cdata.jme_rx_tag, 1463179337Syongari sc->jme_cdata.jme_rx_sparemap); 1464179337Syongari sc->jme_cdata.jme_rx_sparemap = NULL; 1465179337Syongari } 1466179337Syongari bus_dma_tag_destroy(sc->jme_cdata.jme_rx_tag); 1467179337Syongari sc->jme_cdata.jme_rx_tag = NULL; 1468179337Syongari } 1469179337Syongari 1470179337Syongari /* Shared status block. */ 1471179337Syongari if (sc->jme_cdata.jme_ssb_tag != NULL) { 1472179337Syongari if (sc->jme_cdata.jme_ssb_map) 1473179337Syongari bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag, 1474179337Syongari sc->jme_cdata.jme_ssb_map); 1475179337Syongari if (sc->jme_cdata.jme_ssb_map && sc->jme_rdata.jme_ssb_block) 1476179337Syongari bus_dmamem_free(sc->jme_cdata.jme_ssb_tag, 1477179337Syongari sc->jme_rdata.jme_ssb_block, 1478179337Syongari sc->jme_cdata.jme_ssb_map); 1479179337Syongari sc->jme_rdata.jme_ssb_block = NULL; 1480179337Syongari sc->jme_cdata.jme_ssb_map = NULL; 1481179337Syongari bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag); 1482179337Syongari sc->jme_cdata.jme_ssb_tag = NULL; 1483179337Syongari } 1484179337Syongari 1485179337Syongari if (sc->jme_cdata.jme_buffer_tag != NULL) { 1486179337Syongari bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag); 1487179337Syongari sc->jme_cdata.jme_buffer_tag = NULL; 1488179337Syongari } 1489179337Syongari if (sc->jme_cdata.jme_ring_tag != NULL) { 1490179337Syongari bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag); 1491179337Syongari sc->jme_cdata.jme_ring_tag = NULL; 1492179337Syongari } 1493179337Syongari} 1494179337Syongari 1495179337Syongari/* 1496179337Syongari * Make sure the interface is stopped at reboot time. 1497179337Syongari */ 1498179337Syongaristatic int 1499179337Syongarijme_shutdown(device_t dev) 1500179337Syongari{ 1501179337Syongari 1502179337Syongari return (jme_suspend(dev)); 1503179337Syongari} 1504179337Syongari 1505179337Syongari/* 1506179337Syongari * Unlike other ethernet controllers, JMC250 requires 1507179337Syongari * explicit resetting link speed to 10/100Mbps as gigabit 1508179337Syongari * link will cunsume more power than 375mA. 1509179337Syongari * Note, we reset the link speed to 10/100Mbps with 1510179337Syongari * auto-negotiation but we don't know whether that operation 1511179337Syongari * would succeed or not as we have no control after powering 1512179337Syongari * off. If the renegotiation fail WOL may not work. Running 1513179337Syongari * at 1Gbps draws more power than 375mA at 3.3V which is 1514179337Syongari * specified in PCI specification and that would result in 1515179337Syongari * complete shutdowning power to ethernet controller. 1516179337Syongari * 1517179337Syongari * TODO 1518179337Syongari * Save current negotiated media speed/duplex/flow-control 1519179337Syongari * to softc and restore the same link again after resuming. 1520179337Syongari * PHY handling such as power down/resetting to 100Mbps 1521179337Syongari * may be better handled in suspend method in phy driver. 1522179337Syongari */ 1523179337Syongaristatic void 1524179337Syongarijme_setlinkspeed(struct jme_softc *sc) 1525179337Syongari{ 1526179337Syongari struct mii_data *mii; 1527179337Syongari int aneg, i; 1528179337Syongari 1529179337Syongari JME_LOCK_ASSERT(sc); 1530179337Syongari 1531179337Syongari mii = device_get_softc(sc->jme_miibus); 1532179337Syongari mii_pollstat(mii); 1533179337Syongari aneg = 0; 1534179337Syongari if ((mii->mii_media_status & IFM_AVALID) != 0) { 1535179337Syongari switch IFM_SUBTYPE(mii->mii_media_active) { 1536179337Syongari case IFM_10_T: 1537179337Syongari case IFM_100_TX: 1538179337Syongari return; 1539179337Syongari case IFM_1000_T: 1540179337Syongari aneg++; 1541179337Syongari default: 1542179337Syongari break; 1543179337Syongari } 1544179337Syongari } 1545179337Syongari jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0); 1546179337Syongari jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR, 1547179337Syongari ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1548179337Syongari jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, 1549179337Syongari BMCR_AUTOEN | BMCR_STARTNEG); 1550179337Syongari DELAY(1000); 1551179337Syongari if (aneg != 0) { 1552179337Syongari /* Poll link state until jme(4) get a 10/100 link. */ 1553179337Syongari for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1554179337Syongari mii_pollstat(mii); 1555179337Syongari if ((mii->mii_media_status & IFM_AVALID) != 0) { 1556179337Syongari switch (IFM_SUBTYPE(mii->mii_media_active)) { 1557179337Syongari case IFM_10_T: 1558179337Syongari case IFM_100_TX: 1559179337Syongari jme_mac_config(sc); 1560179337Syongari return; 1561179337Syongari default: 1562179337Syongari break; 1563179337Syongari } 1564179337Syongari } 1565179337Syongari JME_UNLOCK(sc); 1566179337Syongari pause("jmelnk", hz); 1567179337Syongari JME_LOCK(sc); 1568179337Syongari } 1569179337Syongari if (i == MII_ANEGTICKS_GIGE) 1570179337Syongari device_printf(sc->jme_dev, "establishing link failed, " 1571179337Syongari "WOL may not work!"); 1572179337Syongari } 1573179337Syongari /* 1574179337Syongari * No link, force MAC to have 100Mbps, full-duplex link. 1575179337Syongari * This is the last resort and may/may not work. 1576179337Syongari */ 1577179337Syongari mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1578179337Syongari mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1579179337Syongari jme_mac_config(sc); 1580179337Syongari} 1581179337Syongari 1582179337Syongaristatic void 1583179337Syongarijme_setwol(struct jme_softc *sc) 1584179337Syongari{ 1585179337Syongari struct ifnet *ifp; 1586179337Syongari uint32_t gpr, pmcs; 1587179337Syongari uint16_t pmstat; 1588179337Syongari int pmc; 1589179337Syongari 1590179337Syongari JME_LOCK_ASSERT(sc); 1591179337Syongari 1592219902Sjhb if (pci_find_cap(sc->jme_dev, PCIY_PMG, &pmc) != 0) { 1593185596Syongari /* Remove Tx MAC/offload clock to save more power. */ 1594185596Syongari if ((sc->jme_flags & JME_FLAG_TXCLK) != 0) 1595185596Syongari CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) & 1596185596Syongari ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 | 1597185596Syongari GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000)); 1598216551Syongari if ((sc->jme_flags & JME_FLAG_RXCLK) != 0) 1599216551Syongari CSR_WRITE_4(sc, JME_GPREG1, 1600216551Syongari CSR_READ_4(sc, JME_GPREG1) | GPREG1_RX_MAC_CLK_DIS); 1601179337Syongari /* No PME capability, PHY power down. */ 1602216551Syongari jme_phy_down(sc); 1603179337Syongari return; 1604179337Syongari } 1605179337Syongari 1606179337Syongari ifp = sc->jme_ifp; 1607179337Syongari gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB; 1608179337Syongari pmcs = CSR_READ_4(sc, JME_PMCS); 1609179337Syongari pmcs &= ~PMCS_WOL_ENB_MASK; 1610179337Syongari if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) { 1611179337Syongari pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB; 1612179337Syongari /* Enable PME message. */ 1613179337Syongari gpr |= GPREG0_PME_ENB; 1614179337Syongari /* For gigabit controllers, reset link speed to 10/100. */ 1615179337Syongari if ((sc->jme_flags & JME_FLAG_FASTETH) == 0) 1616179337Syongari jme_setlinkspeed(sc); 1617179337Syongari } 1618179337Syongari 1619179337Syongari CSR_WRITE_4(sc, JME_PMCS, pmcs); 1620179337Syongari CSR_WRITE_4(sc, JME_GPREG0, gpr); 1621185596Syongari /* Remove Tx MAC/offload clock to save more power. */ 1622185596Syongari if ((sc->jme_flags & JME_FLAG_TXCLK) != 0) 1623185596Syongari CSR_WRITE_4(sc, JME_GHC, CSR_READ_4(sc, JME_GHC) & 1624185596Syongari ~(GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100 | 1625185596Syongari GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000)); 1626179337Syongari /* Request PME. */ 1627179337Syongari pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2); 1628179337Syongari pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1629179337Syongari if ((ifp->if_capenable & IFCAP_WOL) != 0) 1630179337Syongari pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1631179337Syongari pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1632179337Syongari if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1633179337Syongari /* No WOL, PHY power down. */ 1634216551Syongari jme_phy_down(sc); 1635179337Syongari } 1636179337Syongari} 1637179337Syongari 1638179337Syongaristatic int 1639179337Syongarijme_suspend(device_t dev) 1640179337Syongari{ 1641179337Syongari struct jme_softc *sc; 1642179337Syongari 1643179337Syongari sc = device_get_softc(dev); 1644179337Syongari 1645179337Syongari JME_LOCK(sc); 1646179337Syongari jme_stop(sc); 1647179337Syongari jme_setwol(sc); 1648179337Syongari JME_UNLOCK(sc); 1649179337Syongari 1650179337Syongari return (0); 1651179337Syongari} 1652179337Syongari 1653179337Syongaristatic int 1654179337Syongarijme_resume(device_t dev) 1655179337Syongari{ 1656179337Syongari struct jme_softc *sc; 1657179337Syongari struct ifnet *ifp; 1658179337Syongari uint16_t pmstat; 1659179337Syongari int pmc; 1660179337Syongari 1661179337Syongari sc = device_get_softc(dev); 1662179337Syongari 1663179337Syongari JME_LOCK(sc); 1664236700Skevlo if (pci_find_cap(sc->jme_dev, PCIY_PMG, &pmc) == 0) { 1665179337Syongari pmstat = pci_read_config(sc->jme_dev, 1666179337Syongari pmc + PCIR_POWER_STATUS, 2); 1667179337Syongari /* Disable PME clear PME status. */ 1668179337Syongari pmstat &= ~PCIM_PSTAT_PMEENABLE; 1669179337Syongari pci_write_config(sc->jme_dev, 1670179337Syongari pmc + PCIR_POWER_STATUS, pmstat, 2); 1671179337Syongari } 1672216551Syongari /* Wakeup PHY. */ 1673216551Syongari jme_phy_up(sc); 1674179337Syongari ifp = sc->jme_ifp; 1675197585Syongari if ((ifp->if_flags & IFF_UP) != 0) { 1676197585Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1677179337Syongari jme_init_locked(sc); 1678197585Syongari } 1679179337Syongari 1680179337Syongari JME_UNLOCK(sc); 1681179337Syongari 1682179337Syongari return (0); 1683179337Syongari} 1684179337Syongari 1685179337Syongaristatic int 1686179337Syongarijme_encap(struct jme_softc *sc, struct mbuf **m_head) 1687179337Syongari{ 1688179337Syongari struct jme_txdesc *txd; 1689179337Syongari struct jme_desc *desc; 1690179337Syongari struct mbuf *m; 1691179337Syongari bus_dma_segment_t txsegs[JME_MAXTXSEGS]; 1692179337Syongari int error, i, nsegs, prod; 1693254803Sandre uint32_t cflags, tsosegsz; 1694179337Syongari 1695179337Syongari JME_LOCK_ASSERT(sc); 1696179337Syongari 1697179337Syongari M_ASSERTPKTHDR((*m_head)); 1698179337Syongari 1699179337Syongari if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1700179337Syongari /* 1701179337Syongari * Due to the adherence to NDIS specification JMC250 1702179337Syongari * assumes upper stack computed TCP pseudo checksum 1703179337Syongari * without including payload length. This breaks 1704179337Syongari * checksum offload for TSO case so recompute TCP 1705179337Syongari * pseudo checksum for JMC250. Hopefully this wouldn't 1706179337Syongari * be much burden on modern CPUs. 1707179337Syongari */ 1708179337Syongari struct ether_header *eh; 1709179337Syongari struct ip *ip; 1710179337Syongari struct tcphdr *tcp; 1711179337Syongari uint32_t ip_off, poff; 1712179337Syongari 1713179337Syongari if (M_WRITABLE(*m_head) == 0) { 1714179337Syongari /* Get a writable copy. */ 1715243857Sglebius m = m_dup(*m_head, M_NOWAIT); 1716179337Syongari m_freem(*m_head); 1717179337Syongari if (m == NULL) { 1718179337Syongari *m_head = NULL; 1719179337Syongari return (ENOBUFS); 1720179337Syongari } 1721179337Syongari *m_head = m; 1722179337Syongari } 1723179337Syongari ip_off = sizeof(struct ether_header); 1724179337Syongari m = m_pullup(*m_head, ip_off); 1725179337Syongari if (m == NULL) { 1726179337Syongari *m_head = NULL; 1727179337Syongari return (ENOBUFS); 1728179337Syongari } 1729179337Syongari eh = mtod(m, struct ether_header *); 1730179337Syongari /* Check the existence of VLAN tag. */ 1731179337Syongari if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1732179337Syongari ip_off = sizeof(struct ether_vlan_header); 1733179337Syongari m = m_pullup(m, ip_off); 1734179337Syongari if (m == NULL) { 1735179337Syongari *m_head = NULL; 1736179337Syongari return (ENOBUFS); 1737179337Syongari } 1738179337Syongari } 1739179337Syongari m = m_pullup(m, ip_off + sizeof(struct ip)); 1740179337Syongari if (m == NULL) { 1741179337Syongari *m_head = NULL; 1742179337Syongari return (ENOBUFS); 1743179337Syongari } 1744179337Syongari ip = (struct ip *)(mtod(m, char *) + ip_off); 1745179337Syongari poff = ip_off + (ip->ip_hl << 2); 1746179337Syongari m = m_pullup(m, poff + sizeof(struct tcphdr)); 1747179337Syongari if (m == NULL) { 1748179337Syongari *m_head = NULL; 1749179337Syongari return (ENOBUFS); 1750179337Syongari } 1751179337Syongari /* 1752179337Syongari * Reset IP checksum and recompute TCP pseudo 1753179337Syongari * checksum that NDIS specification requires. 1754179337Syongari */ 1755213844Syongari ip = (struct ip *)(mtod(m, char *) + ip_off); 1756213844Syongari tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1757179337Syongari ip->ip_sum = 0; 1758179337Syongari if (poff + (tcp->th_off << 2) == m->m_pkthdr.len) { 1759179337Syongari tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1760179337Syongari ip->ip_dst.s_addr, 1761179337Syongari htons((tcp->th_off << 2) + IPPROTO_TCP)); 1762179337Syongari /* No need to TSO, force IP checksum offload. */ 1763179337Syongari (*m_head)->m_pkthdr.csum_flags &= ~CSUM_TSO; 1764179337Syongari (*m_head)->m_pkthdr.csum_flags |= CSUM_IP; 1765179337Syongari } else 1766179337Syongari tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1767179337Syongari ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1768179337Syongari *m_head = m; 1769179337Syongari } 1770179337Syongari 1771179337Syongari prod = sc->jme_cdata.jme_tx_prod; 1772179337Syongari txd = &sc->jme_cdata.jme_txdesc[prod]; 1773179337Syongari 1774179337Syongari error = bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_tx_tag, 1775179337Syongari txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1776179337Syongari if (error == EFBIG) { 1777243857Sglebius m = m_collapse(*m_head, M_NOWAIT, JME_MAXTXSEGS); 1778179337Syongari if (m == NULL) { 1779179337Syongari m_freem(*m_head); 1780179337Syongari *m_head = NULL; 1781179337Syongari return (ENOMEM); 1782179337Syongari } 1783179337Syongari *m_head = m; 1784179337Syongari error = bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_tx_tag, 1785179337Syongari txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1786179337Syongari if (error != 0) { 1787179337Syongari m_freem(*m_head); 1788179337Syongari *m_head = NULL; 1789179337Syongari return (error); 1790179337Syongari } 1791179337Syongari } else if (error != 0) 1792179337Syongari return (error); 1793179337Syongari if (nsegs == 0) { 1794179337Syongari m_freem(*m_head); 1795179337Syongari *m_head = NULL; 1796179337Syongari return (EIO); 1797179337Syongari } 1798179337Syongari 1799179337Syongari /* 1800179337Syongari * Check descriptor overrun. Leave one free descriptor. 1801179337Syongari * Since we always use 64bit address mode for transmitting, 1802179337Syongari * each Tx request requires one more dummy descriptor. 1803179337Syongari */ 1804179337Syongari if (sc->jme_cdata.jme_tx_cnt + nsegs + 1 > JME_TX_RING_CNT - 1) { 1805179337Syongari bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap); 1806179337Syongari return (ENOBUFS); 1807179337Syongari } 1808179337Syongari 1809179337Syongari m = *m_head; 1810179337Syongari cflags = 0; 1811254803Sandre tsosegsz = 0; 1812179337Syongari /* Configure checksum offload and TSO. */ 1813179337Syongari if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1814254803Sandre tsosegsz = (uint32_t)m->m_pkthdr.tso_segsz << 1815179337Syongari JME_TD_MSS_SHIFT; 1816179337Syongari cflags |= JME_TD_TSO; 1817179337Syongari } else { 1818179337Syongari if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 1819179337Syongari cflags |= JME_TD_IPCSUM; 1820179337Syongari if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1821179337Syongari cflags |= JME_TD_TCPCSUM; 1822179337Syongari if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1823179337Syongari cflags |= JME_TD_UDPCSUM; 1824179337Syongari } 1825179337Syongari /* Configure VLAN. */ 1826179337Syongari if ((m->m_flags & M_VLANTAG) != 0) { 1827179337Syongari cflags |= (m->m_pkthdr.ether_vtag & JME_TD_VLAN_MASK); 1828179337Syongari cflags |= JME_TD_VLAN_TAG; 1829179337Syongari } 1830179337Syongari 1831179337Syongari desc = &sc->jme_rdata.jme_tx_ring[prod]; 1832179337Syongari desc->flags = htole32(cflags); 1833254803Sandre desc->buflen = htole32(tsosegsz); 1834179337Syongari desc->addr_hi = htole32(m->m_pkthdr.len); 1835179337Syongari desc->addr_lo = 0; 1836179337Syongari sc->jme_cdata.jme_tx_cnt++; 1837179337Syongari JME_DESC_INC(prod, JME_TX_RING_CNT); 1838179337Syongari for (i = 0; i < nsegs; i++) { 1839179337Syongari desc = &sc->jme_rdata.jme_tx_ring[prod]; 1840179337Syongari desc->flags = htole32(JME_TD_OWN | JME_TD_64BIT); 1841179337Syongari desc->buflen = htole32(txsegs[i].ds_len); 1842179337Syongari desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr)); 1843179337Syongari desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr)); 1844179337Syongari sc->jme_cdata.jme_tx_cnt++; 1845179337Syongari JME_DESC_INC(prod, JME_TX_RING_CNT); 1846179337Syongari } 1847179337Syongari 1848179337Syongari /* Update producer index. */ 1849179337Syongari sc->jme_cdata.jme_tx_prod = prod; 1850179337Syongari /* 1851179337Syongari * Finally request interrupt and give the first descriptor 1852179337Syongari * owenership to hardware. 1853179337Syongari */ 1854179337Syongari desc = txd->tx_desc; 1855179337Syongari desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR); 1856179337Syongari 1857179337Syongari txd->tx_m = m; 1858179337Syongari txd->tx_ndesc = nsegs + 1; 1859179337Syongari 1860179337Syongari /* Sync descriptors. */ 1861179337Syongari bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap, 1862179337Syongari BUS_DMASYNC_PREWRITE); 1863179337Syongari bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 1864179337Syongari sc->jme_cdata.jme_tx_ring_map, 1865179337Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1866179337Syongari 1867179337Syongari return (0); 1868179337Syongari} 1869179337Syongari 1870179337Syongaristatic void 1871217353Sjhbjme_start(struct ifnet *ifp) 1872179337Syongari{ 1873217353Sjhb struct jme_softc *sc; 1874179337Syongari 1875217353Sjhb sc = ifp->if_softc; 1876217353Sjhb JME_LOCK(sc); 1877217353Sjhb jme_start_locked(ifp); 1878217353Sjhb JME_UNLOCK(sc); 1879179337Syongari} 1880179337Syongari 1881179337Syongaristatic void 1882217353Sjhbjme_start_locked(struct ifnet *ifp) 1883179337Syongari{ 1884179337Syongari struct jme_softc *sc; 1885179337Syongari struct mbuf *m_head; 1886179337Syongari int enq; 1887179337Syongari 1888179337Syongari sc = ifp->if_softc; 1889179337Syongari 1890217353Sjhb JME_LOCK_ASSERT(sc); 1891179337Syongari 1892179337Syongari if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT) 1893179337Syongari jme_txeof(sc); 1894179337Syongari 1895179337Syongari if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1896217353Sjhb IFF_DRV_RUNNING || (sc->jme_flags & JME_FLAG_LINK) == 0) 1897179337Syongari return; 1898179337Syongari 1899179337Syongari for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1900179337Syongari IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1901179337Syongari if (m_head == NULL) 1902179337Syongari break; 1903179337Syongari /* 1904179337Syongari * Pack the data into the transmit ring. If we 1905179337Syongari * don't have room, set the OACTIVE flag and wait 1906179337Syongari * for the NIC to drain the ring. 1907179337Syongari */ 1908179337Syongari if (jme_encap(sc, &m_head)) { 1909179337Syongari if (m_head == NULL) 1910179337Syongari break; 1911179337Syongari IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1912179337Syongari ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1913179337Syongari break; 1914179337Syongari } 1915179337Syongari 1916179337Syongari enq++; 1917179337Syongari /* 1918179337Syongari * If there's a BPF listener, bounce a copy of this frame 1919179337Syongari * to him. 1920179337Syongari */ 1921179337Syongari ETHER_BPF_MTAP(ifp, m_head); 1922179337Syongari } 1923179337Syongari 1924179337Syongari if (enq > 0) { 1925179337Syongari /* 1926179337Syongari * Reading TXCSR takes very long time under heavy load 1927179337Syongari * so cache TXCSR value and writes the ORed value with 1928179337Syongari * the kick command to the TXCSR. This saves one register 1929179337Syongari * access cycle. 1930179337Syongari */ 1931179337Syongari CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB | 1932179337Syongari TXCSR_TXQ_N_START(TXCSR_TXQ0)); 1933179337Syongari /* Set a timeout in case the chip goes out to lunch. */ 1934179337Syongari sc->jme_watchdog_timer = JME_TX_TIMEOUT; 1935179337Syongari } 1936179337Syongari} 1937179337Syongari 1938179337Syongaristatic void 1939179337Syongarijme_watchdog(struct jme_softc *sc) 1940179337Syongari{ 1941179337Syongari struct ifnet *ifp; 1942179337Syongari 1943179337Syongari JME_LOCK_ASSERT(sc); 1944179337Syongari 1945179337Syongari if (sc->jme_watchdog_timer == 0 || --sc->jme_watchdog_timer) 1946179337Syongari return; 1947179337Syongari 1948179337Syongari ifp = sc->jme_ifp; 1949179337Syongari if ((sc->jme_flags & JME_FLAG_LINK) == 0) { 1950179337Syongari if_printf(sc->jme_ifp, "watchdog timeout (missed link)\n"); 1951179337Syongari ifp->if_oerrors++; 1952197585Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1953179337Syongari jme_init_locked(sc); 1954179337Syongari return; 1955179337Syongari } 1956179337Syongari jme_txeof(sc); 1957179337Syongari if (sc->jme_cdata.jme_tx_cnt == 0) { 1958179337Syongari if_printf(sc->jme_ifp, 1959179337Syongari "watchdog timeout (missed Tx interrupts) -- recovering\n"); 1960179337Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1961217353Sjhb jme_start_locked(ifp); 1962179337Syongari return; 1963179337Syongari } 1964179337Syongari 1965179337Syongari if_printf(sc->jme_ifp, "watchdog timeout\n"); 1966179337Syongari ifp->if_oerrors++; 1967197585Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1968179337Syongari jme_init_locked(sc); 1969179337Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1970217353Sjhb jme_start_locked(ifp); 1971179337Syongari} 1972179337Syongari 1973179337Syongaristatic int 1974179337Syongarijme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1975179337Syongari{ 1976179337Syongari struct jme_softc *sc; 1977179337Syongari struct ifreq *ifr; 1978179337Syongari struct mii_data *mii; 1979179337Syongari uint32_t reg; 1980179337Syongari int error, mask; 1981179337Syongari 1982179337Syongari sc = ifp->if_softc; 1983179337Syongari ifr = (struct ifreq *)data; 1984179337Syongari error = 0; 1985179337Syongari switch (cmd) { 1986179337Syongari case SIOCSIFMTU: 1987179337Syongari if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU || 1988179337Syongari ((sc->jme_flags & JME_FLAG_NOJUMBO) != 0 && 1989179337Syongari ifr->ifr_mtu > JME_MAX_MTU)) { 1990179337Syongari error = EINVAL; 1991179337Syongari break; 1992179337Syongari } 1993179337Syongari 1994179337Syongari if (ifp->if_mtu != ifr->ifr_mtu) { 1995179337Syongari /* 1996179337Syongari * No special configuration is required when interface 1997179337Syongari * MTU is changed but availability of TSO/Tx checksum 1998179337Syongari * offload should be chcked against new MTU size as 1999179337Syongari * FIFO size is just 2K. 2000179337Syongari */ 2001179337Syongari JME_LOCK(sc); 2002179337Syongari if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) { 2003179337Syongari ifp->if_capenable &= 2004179337Syongari ~(IFCAP_TXCSUM | IFCAP_TSO4); 2005179337Syongari ifp->if_hwassist &= 2006179337Syongari ~(JME_CSUM_FEATURES | CSUM_TSO); 2007179337Syongari VLAN_CAPABILITIES(ifp); 2008179337Syongari } 2009179337Syongari ifp->if_mtu = ifr->ifr_mtu; 2010197585Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2011197585Syongari ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2012179337Syongari jme_init_locked(sc); 2013197585Syongari } 2014179337Syongari JME_UNLOCK(sc); 2015179337Syongari } 2016179337Syongari break; 2017179337Syongari case SIOCSIFFLAGS: 2018179337Syongari JME_LOCK(sc); 2019179337Syongari if ((ifp->if_flags & IFF_UP) != 0) { 2020179337Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2021179337Syongari if (((ifp->if_flags ^ sc->jme_if_flags) 2022179337Syongari & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2023179337Syongari jme_set_filter(sc); 2024179337Syongari } else { 2025179337Syongari if ((sc->jme_flags & JME_FLAG_DETACH) == 0) 2026179337Syongari jme_init_locked(sc); 2027179337Syongari } 2028179337Syongari } else { 2029179337Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2030179337Syongari jme_stop(sc); 2031179337Syongari } 2032179337Syongari sc->jme_if_flags = ifp->if_flags; 2033179337Syongari JME_UNLOCK(sc); 2034179337Syongari break; 2035179337Syongari case SIOCADDMULTI: 2036179337Syongari case SIOCDELMULTI: 2037179337Syongari JME_LOCK(sc); 2038179337Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2039179337Syongari jme_set_filter(sc); 2040179337Syongari JME_UNLOCK(sc); 2041179337Syongari break; 2042179337Syongari case SIOCSIFMEDIA: 2043179337Syongari case SIOCGIFMEDIA: 2044179337Syongari mii = device_get_softc(sc->jme_miibus); 2045179337Syongari error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2046179337Syongari break; 2047179337Syongari case SIOCSIFCAP: 2048179337Syongari JME_LOCK(sc); 2049179337Syongari mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2050179337Syongari if ((mask & IFCAP_TXCSUM) != 0 && 2051179337Syongari ifp->if_mtu < JME_TX_FIFO_SIZE) { 2052179337Syongari if ((IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 2053179337Syongari ifp->if_capenable ^= IFCAP_TXCSUM; 2054179337Syongari if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 2055179337Syongari ifp->if_hwassist |= JME_CSUM_FEATURES; 2056179337Syongari else 2057179337Syongari ifp->if_hwassist &= ~JME_CSUM_FEATURES; 2058179337Syongari } 2059179337Syongari } 2060179337Syongari if ((mask & IFCAP_RXCSUM) != 0 && 2061179337Syongari (IFCAP_RXCSUM & ifp->if_capabilities) != 0) { 2062179337Syongari ifp->if_capenable ^= IFCAP_RXCSUM; 2063179337Syongari reg = CSR_READ_4(sc, JME_RXMAC); 2064179337Syongari reg &= ~RXMAC_CSUM_ENB; 2065179337Syongari if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2066179337Syongari reg |= RXMAC_CSUM_ENB; 2067179337Syongari CSR_WRITE_4(sc, JME_RXMAC, reg); 2068179337Syongari } 2069179337Syongari if ((mask & IFCAP_TSO4) != 0 && 2070179337Syongari ifp->if_mtu < JME_TX_FIFO_SIZE) { 2071179337Syongari if ((IFCAP_TSO4 & ifp->if_capabilities) != 0) { 2072179337Syongari ifp->if_capenable ^= IFCAP_TSO4; 2073179337Syongari if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 2074179337Syongari ifp->if_hwassist |= CSUM_TSO; 2075179337Syongari else 2076179337Syongari ifp->if_hwassist &= ~CSUM_TSO; 2077179337Syongari } 2078179337Syongari } 2079179337Syongari if ((mask & IFCAP_WOL_MAGIC) != 0 && 2080179337Syongari (IFCAP_WOL_MAGIC & ifp->if_capabilities) != 0) 2081179337Syongari ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2082179337Syongari if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2083179337Syongari (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2084179337Syongari ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2085204225Syongari if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2086204225Syongari (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2087204225Syongari ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2088179337Syongari if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2089179337Syongari (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) { 2090179337Syongari ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2091179337Syongari jme_set_vlan(sc); 2092179337Syongari } 2093179337Syongari JME_UNLOCK(sc); 2094179337Syongari VLAN_CAPABILITIES(ifp); 2095179337Syongari break; 2096179337Syongari default: 2097179337Syongari error = ether_ioctl(ifp, cmd, data); 2098179337Syongari break; 2099179337Syongari } 2100179337Syongari 2101179337Syongari return (error); 2102179337Syongari} 2103179337Syongari 2104179337Syongaristatic void 2105179337Syongarijme_mac_config(struct jme_softc *sc) 2106179337Syongari{ 2107179337Syongari struct mii_data *mii; 2108183264Syongari uint32_t ghc, gpreg, rxmac, txmac, txpause; 2109185596Syongari uint32_t txclk; 2110179337Syongari 2111179337Syongari JME_LOCK_ASSERT(sc); 2112179337Syongari 2113179337Syongari mii = device_get_softc(sc->jme_miibus); 2114179337Syongari 2115179337Syongari CSR_WRITE_4(sc, JME_GHC, GHC_RESET); 2116179337Syongari DELAY(10); 2117179337Syongari CSR_WRITE_4(sc, JME_GHC, 0); 2118179337Syongari ghc = 0; 2119185596Syongari txclk = 0; 2120179337Syongari rxmac = CSR_READ_4(sc, JME_RXMAC); 2121179337Syongari rxmac &= ~RXMAC_FC_ENB; 2122179337Syongari txmac = CSR_READ_4(sc, JME_TXMAC); 2123179337Syongari txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST); 2124179337Syongari txpause = CSR_READ_4(sc, JME_TXPFC); 2125179337Syongari txpause &= ~TXPFC_PAUSE_ENB; 2126179337Syongari if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2127179337Syongari ghc |= GHC_FULL_DUPLEX; 2128179337Syongari rxmac &= ~RXMAC_COLL_DET_ENB; 2129179337Syongari txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | 2130179337Syongari TXMAC_BACKOFF | TXMAC_CARRIER_EXT | 2131179337Syongari TXMAC_FRAME_BURST); 2132179337Syongari if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2133179337Syongari txpause |= TXPFC_PAUSE_ENB; 2134179337Syongari if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2135179337Syongari rxmac |= RXMAC_FC_ENB; 2136179337Syongari /* Disable retry transmit timer/retry limit. */ 2137179337Syongari CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) & 2138179337Syongari ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB)); 2139179337Syongari } else { 2140179337Syongari rxmac |= RXMAC_COLL_DET_ENB; 2141179337Syongari txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF; 2142179337Syongari /* Enable retry transmit timer/retry limit. */ 2143179337Syongari CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) | 2144179337Syongari TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB); 2145179337Syongari } 2146179337Syongari /* Reprogram Tx/Rx MACs with resolved speed/duplex. */ 2147179337Syongari switch (IFM_SUBTYPE(mii->mii_media_active)) { 2148179337Syongari case IFM_10_T: 2149179337Syongari ghc |= GHC_SPEED_10; 2150185596Syongari txclk |= GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100; 2151179337Syongari break; 2152179337Syongari case IFM_100_TX: 2153179337Syongari ghc |= GHC_SPEED_100; 2154185596Syongari txclk |= GHC_TX_OFFLD_CLK_100 | GHC_TX_MAC_CLK_100; 2155179337Syongari break; 2156179337Syongari case IFM_1000_T: 2157179337Syongari if ((sc->jme_flags & JME_FLAG_FASTETH) != 0) 2158179337Syongari break; 2159179337Syongari ghc |= GHC_SPEED_1000; 2160185596Syongari txclk |= GHC_TX_OFFLD_CLK_1000 | GHC_TX_MAC_CLK_1000; 2161179337Syongari if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0) 2162179337Syongari txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST; 2163179337Syongari break; 2164179337Syongari default: 2165179337Syongari break; 2166179337Syongari } 2167182888Syongari if (sc->jme_rev == DEVICEID_JMC250 && 2168182888Syongari sc->jme_chip_rev == DEVICEREVID_JMC250_A2) { 2169183264Syongari /* 2170183264Syongari * Workaround occasional packet loss issue of JMC250 A2 2171183264Syongari * when it runs on half-duplex media. 2172183264Syongari */ 2173183264Syongari gpreg = CSR_READ_4(sc, JME_GPREG1); 2174183264Syongari if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 2175183264Syongari gpreg &= ~GPREG1_HDPX_FIX; 2176183264Syongari else 2177183264Syongari gpreg |= GPREG1_HDPX_FIX; 2178183264Syongari CSR_WRITE_4(sc, JME_GPREG1, gpreg); 2179183264Syongari /* Workaround CRC errors at 100Mbps on JMC250 A2. */ 2180182888Syongari if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 2181182888Syongari /* Extend interface FIFO depth. */ 2182182888Syongari jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 2183182888Syongari 0x1B, 0x0000); 2184182888Syongari } else { 2185182888Syongari /* Select default interface FIFO depth. */ 2186182888Syongari jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, 2187182888Syongari 0x1B, 0x0004); 2188182888Syongari } 2189182888Syongari } 2190185596Syongari if ((sc->jme_flags & JME_FLAG_TXCLK) != 0) 2191185596Syongari ghc |= txclk; 2192179337Syongari CSR_WRITE_4(sc, JME_GHC, ghc); 2193179337Syongari CSR_WRITE_4(sc, JME_RXMAC, rxmac); 2194179337Syongari CSR_WRITE_4(sc, JME_TXMAC, txmac); 2195179337Syongari CSR_WRITE_4(sc, JME_TXPFC, txpause); 2196179337Syongari} 2197179337Syongari 2198179337Syongaristatic void 2199179337Syongarijme_link_task(void *arg, int pending) 2200179337Syongari{ 2201179337Syongari struct jme_softc *sc; 2202179337Syongari struct mii_data *mii; 2203179337Syongari struct ifnet *ifp; 2204179337Syongari struct jme_txdesc *txd; 2205179337Syongari bus_addr_t paddr; 2206179337Syongari int i; 2207179337Syongari 2208179337Syongari sc = (struct jme_softc *)arg; 2209179337Syongari 2210179337Syongari JME_LOCK(sc); 2211179337Syongari mii = device_get_softc(sc->jme_miibus); 2212179337Syongari ifp = sc->jme_ifp; 2213179337Syongari if (mii == NULL || ifp == NULL || 2214179337Syongari (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2215179337Syongari JME_UNLOCK(sc); 2216179337Syongari return; 2217179337Syongari } 2218179337Syongari 2219179337Syongari sc->jme_flags &= ~JME_FLAG_LINK; 2220179337Syongari if ((mii->mii_media_status & IFM_AVALID) != 0) { 2221179337Syongari switch (IFM_SUBTYPE(mii->mii_media_active)) { 2222179337Syongari case IFM_10_T: 2223179337Syongari case IFM_100_TX: 2224179337Syongari sc->jme_flags |= JME_FLAG_LINK; 2225179337Syongari break; 2226179337Syongari case IFM_1000_T: 2227180582Syongari if ((sc->jme_flags & JME_FLAG_FASTETH) != 0) 2228179337Syongari break; 2229179337Syongari sc->jme_flags |= JME_FLAG_LINK; 2230179337Syongari break; 2231179337Syongari default: 2232179337Syongari break; 2233179337Syongari } 2234179337Syongari } 2235179337Syongari 2236179337Syongari /* 2237179337Syongari * Disabling Rx/Tx MACs have a side-effect of resetting 2238179337Syongari * JME_TXNDA/JME_RXNDA register to the first address of 2239179337Syongari * Tx/Rx descriptor address. So driver should reset its 2240179337Syongari * internal procucer/consumer pointer and reclaim any 2241179337Syongari * allocated resources. Note, just saving the value of 2242179337Syongari * JME_TXNDA and JME_RXNDA registers before stopping MAC 2243179337Syongari * and restoring JME_TXNDA/JME_RXNDA register is not 2244179337Syongari * sufficient to make sure correct MAC state because 2245179337Syongari * stopping MAC operation can take a while and hardware 2246179337Syongari * might have updated JME_TXNDA/JME_RXNDA registers 2247179337Syongari * during the stop operation. 2248179337Syongari */ 2249179337Syongari /* Block execution of task. */ 2250179337Syongari taskqueue_block(sc->jme_tq); 2251179337Syongari /* Disable interrupts and stop driver. */ 2252179337Syongari CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 2253179337Syongari ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2254179337Syongari callout_stop(&sc->jme_tick_ch); 2255179337Syongari sc->jme_watchdog_timer = 0; 2256179337Syongari 2257179337Syongari /* Stop receiver/transmitter. */ 2258179337Syongari jme_stop_rx(sc); 2259179337Syongari jme_stop_tx(sc); 2260179337Syongari 2261179337Syongari /* XXX Drain all queued tasks. */ 2262179337Syongari JME_UNLOCK(sc); 2263179337Syongari taskqueue_drain(sc->jme_tq, &sc->jme_int_task); 2264179337Syongari JME_LOCK(sc); 2265179337Syongari 2266179337Syongari if (sc->jme_cdata.jme_rxhead != NULL) 2267179337Syongari m_freem(sc->jme_cdata.jme_rxhead); 2268179337Syongari JME_RXCHAIN_RESET(sc); 2269179337Syongari jme_txeof(sc); 2270179337Syongari if (sc->jme_cdata.jme_tx_cnt != 0) { 2271179337Syongari /* Remove queued packets for transmit. */ 2272179337Syongari for (i = 0; i < JME_TX_RING_CNT; i++) { 2273179337Syongari txd = &sc->jme_cdata.jme_txdesc[i]; 2274179337Syongari if (txd->tx_m != NULL) { 2275179337Syongari bus_dmamap_sync( 2276179337Syongari sc->jme_cdata.jme_tx_tag, 2277179337Syongari txd->tx_dmamap, 2278179337Syongari BUS_DMASYNC_POSTWRITE); 2279179337Syongari bus_dmamap_unload( 2280179337Syongari sc->jme_cdata.jme_tx_tag, 2281179337Syongari txd->tx_dmamap); 2282179337Syongari m_freem(txd->tx_m); 2283179337Syongari txd->tx_m = NULL; 2284179337Syongari txd->tx_ndesc = 0; 2285179337Syongari ifp->if_oerrors++; 2286179337Syongari } 2287179337Syongari } 2288179337Syongari } 2289179337Syongari 2290179337Syongari /* 2291179337Syongari * Reuse configured Rx descriptors and reset 2292217353Sjhb * producer/consumer index. 2293179337Syongari */ 2294179337Syongari sc->jme_cdata.jme_rx_cons = 0; 2295216362Syongari sc->jme_morework = 0; 2296179337Syongari jme_init_tx_ring(sc); 2297179337Syongari /* Initialize shadow status block. */ 2298179337Syongari jme_init_ssb(sc); 2299179337Syongari 2300179337Syongari /* Program MAC with resolved speed/duplex/flow-control. */ 2301179337Syongari if ((sc->jme_flags & JME_FLAG_LINK) != 0) { 2302179337Syongari jme_mac_config(sc); 2303185597Syongari jme_stats_clear(sc); 2304179337Syongari 2305179337Syongari CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr); 2306179337Syongari CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr); 2307179337Syongari 2308179337Syongari /* Set Tx ring address to the hardware. */ 2309179337Syongari paddr = JME_TX_RING_ADDR(sc, 0); 2310179337Syongari CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr)); 2311179337Syongari CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr)); 2312179337Syongari 2313179337Syongari /* Set Rx ring address to the hardware. */ 2314179337Syongari paddr = JME_RX_RING_ADDR(sc, 0); 2315179337Syongari CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr)); 2316179337Syongari CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr)); 2317179337Syongari 2318179337Syongari /* Restart receiver/transmitter. */ 2319179337Syongari CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB | 2320179337Syongari RXCSR_RXQ_START); 2321179337Syongari CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB); 2322216551Syongari /* Lastly enable TX/RX clock. */ 2323216551Syongari if ((sc->jme_flags & JME_FLAG_TXCLK) != 0) 2324216551Syongari CSR_WRITE_4(sc, JME_GHC, 2325216551Syongari CSR_READ_4(sc, JME_GHC) & ~GHC_TX_MAC_CLK_DIS); 2326216551Syongari if ((sc->jme_flags & JME_FLAG_RXCLK) != 0) 2327216551Syongari CSR_WRITE_4(sc, JME_GPREG1, 2328216551Syongari CSR_READ_4(sc, JME_GPREG1) & ~GPREG1_RX_MAC_CLK_DIS); 2329179337Syongari } 2330179337Syongari 2331179337Syongari ifp->if_drv_flags |= IFF_DRV_RUNNING; 2332179337Syongari ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2333179337Syongari callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); 2334179337Syongari /* Unblock execution of task. */ 2335179337Syongari taskqueue_unblock(sc->jme_tq); 2336179337Syongari /* Reenable interrupts. */ 2337179337Syongari CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 2338179337Syongari 2339179337Syongari JME_UNLOCK(sc); 2340179337Syongari} 2341179337Syongari 2342179337Syongaristatic int 2343179337Syongarijme_intr(void *arg) 2344179337Syongari{ 2345179337Syongari struct jme_softc *sc; 2346179337Syongari uint32_t status; 2347179337Syongari 2348179337Syongari sc = (struct jme_softc *)arg; 2349179337Syongari 2350179337Syongari status = CSR_READ_4(sc, JME_INTR_REQ_STATUS); 2351179337Syongari if (status == 0 || status == 0xFFFFFFFF) 2352179337Syongari return (FILTER_STRAY); 2353179337Syongari /* Disable interrupts. */ 2354179337Syongari CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 2355179337Syongari taskqueue_enqueue(sc->jme_tq, &sc->jme_int_task); 2356179337Syongari 2357179337Syongari return (FILTER_HANDLED); 2358179337Syongari} 2359179337Syongari 2360179337Syongaristatic void 2361179337Syongarijme_int_task(void *arg, int pending) 2362179337Syongari{ 2363179337Syongari struct jme_softc *sc; 2364179337Syongari struct ifnet *ifp; 2365179337Syongari uint32_t status; 2366179337Syongari int more; 2367179337Syongari 2368179337Syongari sc = (struct jme_softc *)arg; 2369179337Syongari ifp = sc->jme_ifp; 2370179337Syongari 2371217353Sjhb JME_LOCK(sc); 2372179337Syongari status = CSR_READ_4(sc, JME_INTR_STATUS); 2373216362Syongari if (sc->jme_morework != 0) { 2374216362Syongari sc->jme_morework = 0; 2375179337Syongari status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO; 2376179337Syongari } 2377179337Syongari if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF) 2378179337Syongari goto done; 2379179337Syongari /* Reset PCC counter/timer and Ack interrupts. */ 2380179337Syongari status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP); 2381179337Syongari if ((status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) != 0) 2382179337Syongari status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP; 2383179337Syongari if ((status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) 2384179337Syongari status |= INTR_RXQ_COAL | INTR_RXQ_COAL_TO | INTR_RXQ_COMP; 2385179337Syongari CSR_WRITE_4(sc, JME_INTR_STATUS, status); 2386179337Syongari more = 0; 2387179337Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2388179337Syongari if ((status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO)) != 0) { 2389179337Syongari more = jme_rxintr(sc, sc->jme_process_limit); 2390179337Syongari if (more != 0) 2391216362Syongari sc->jme_morework = 1; 2392179337Syongari } 2393179337Syongari if ((status & INTR_RXQ_DESC_EMPTY) != 0) { 2394179337Syongari /* 2395179337Syongari * Notify hardware availability of new Rx 2396179337Syongari * buffers. 2397179337Syongari * Reading RXCSR takes very long time under 2398179337Syongari * heavy load so cache RXCSR value and writes 2399179337Syongari * the ORed value with the kick command to 2400179337Syongari * the RXCSR. This saves one register access 2401179337Syongari * cycle. 2402179337Syongari */ 2403179337Syongari CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | 2404179337Syongari RXCSR_RX_ENB | RXCSR_RXQ_START); 2405179337Syongari } 2406179337Syongari if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2407217353Sjhb jme_start_locked(ifp); 2408179337Syongari } 2409179337Syongari 2410179337Syongari if (more != 0 || (CSR_READ_4(sc, JME_INTR_STATUS) & JME_INTRS) != 0) { 2411179337Syongari taskqueue_enqueue(sc->jme_tq, &sc->jme_int_task); 2412217353Sjhb JME_UNLOCK(sc); 2413179337Syongari return; 2414179337Syongari } 2415179337Syongaridone: 2416217353Sjhb JME_UNLOCK(sc); 2417217353Sjhb 2418179337Syongari /* Reenable interrupts. */ 2419179337Syongari CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 2420179337Syongari} 2421179337Syongari 2422179337Syongaristatic void 2423179337Syongarijme_txeof(struct jme_softc *sc) 2424179337Syongari{ 2425179337Syongari struct ifnet *ifp; 2426179337Syongari struct jme_txdesc *txd; 2427179337Syongari uint32_t status; 2428179337Syongari int cons, nsegs; 2429179337Syongari 2430179337Syongari JME_LOCK_ASSERT(sc); 2431179337Syongari 2432179337Syongari ifp = sc->jme_ifp; 2433179337Syongari 2434179337Syongari cons = sc->jme_cdata.jme_tx_cons; 2435179337Syongari if (cons == sc->jme_cdata.jme_tx_prod) 2436179337Syongari return; 2437179337Syongari 2438179337Syongari bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 2439179337Syongari sc->jme_cdata.jme_tx_ring_map, 2440179337Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2441179337Syongari 2442179337Syongari /* 2443179337Syongari * Go through our Tx list and free mbufs for those 2444179337Syongari * frames which have been transmitted. 2445179337Syongari */ 2446179337Syongari for (; cons != sc->jme_cdata.jme_tx_prod;) { 2447179337Syongari txd = &sc->jme_cdata.jme_txdesc[cons]; 2448179337Syongari status = le32toh(txd->tx_desc->flags); 2449179337Syongari if ((status & JME_TD_OWN) == JME_TD_OWN) 2450179337Syongari break; 2451179337Syongari 2452179337Syongari if ((status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) != 0) 2453179337Syongari ifp->if_oerrors++; 2454179337Syongari else { 2455179337Syongari ifp->if_opackets++; 2456179337Syongari if ((status & JME_TD_COLLISION) != 0) 2457179337Syongari ifp->if_collisions += 2458179337Syongari le32toh(txd->tx_desc->buflen) & 2459179337Syongari JME_TD_BUF_LEN_MASK; 2460179337Syongari } 2461179337Syongari /* 2462179337Syongari * Only the first descriptor of multi-descriptor 2463179337Syongari * transmission is updated so driver have to skip entire 2464179337Syongari * chained buffers for the transmiited frame. In other 2465179337Syongari * words, JME_TD_OWN bit is valid only at the first 2466179337Syongari * descriptor of a multi-descriptor transmission. 2467179337Syongari */ 2468179337Syongari for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) { 2469179337Syongari sc->jme_rdata.jme_tx_ring[cons].flags = 0; 2470179337Syongari JME_DESC_INC(cons, JME_TX_RING_CNT); 2471179337Syongari } 2472179337Syongari 2473179337Syongari /* Reclaim transferred mbufs. */ 2474179337Syongari bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap, 2475179337Syongari BUS_DMASYNC_POSTWRITE); 2476179337Syongari bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap); 2477179337Syongari 2478179337Syongari KASSERT(txd->tx_m != NULL, 2479179337Syongari ("%s: freeing NULL mbuf!\n", __func__)); 2480179337Syongari m_freem(txd->tx_m); 2481179337Syongari txd->tx_m = NULL; 2482179337Syongari sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc; 2483179337Syongari KASSERT(sc->jme_cdata.jme_tx_cnt >= 0, 2484179337Syongari ("%s: Active Tx desc counter was garbled\n", __func__)); 2485179337Syongari txd->tx_ndesc = 0; 2486179337Syongari ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2487179337Syongari } 2488179337Syongari sc->jme_cdata.jme_tx_cons = cons; 2489179337Syongari /* Unarm watchog timer when there is no pending descriptors in queue. */ 2490179337Syongari if (sc->jme_cdata.jme_tx_cnt == 0) 2491179337Syongari sc->jme_watchdog_timer = 0; 2492179337Syongari 2493179337Syongari bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 2494179337Syongari sc->jme_cdata.jme_tx_ring_map, 2495179337Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2496179337Syongari} 2497179337Syongari 2498179337Syongaristatic __inline void 2499179337Syongarijme_discard_rxbuf(struct jme_softc *sc, int cons) 2500179337Syongari{ 2501179337Syongari struct jme_desc *desc; 2502179337Syongari 2503179337Syongari desc = &sc->jme_rdata.jme_rx_ring[cons]; 2504179337Syongari desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); 2505179337Syongari desc->buflen = htole32(MCLBYTES); 2506179337Syongari} 2507179337Syongari 2508179337Syongari/* Receive a frame. */ 2509179337Syongaristatic void 2510179337Syongarijme_rxeof(struct jme_softc *sc) 2511179337Syongari{ 2512179337Syongari struct ifnet *ifp; 2513179337Syongari struct jme_desc *desc; 2514179337Syongari struct jme_rxdesc *rxd; 2515179337Syongari struct mbuf *mp, *m; 2516179337Syongari uint32_t flags, status; 2517179337Syongari int cons, count, nsegs; 2518179337Syongari 2519217353Sjhb JME_LOCK_ASSERT(sc); 2520217353Sjhb 2521179337Syongari ifp = sc->jme_ifp; 2522179337Syongari 2523179337Syongari cons = sc->jme_cdata.jme_rx_cons; 2524179337Syongari desc = &sc->jme_rdata.jme_rx_ring[cons]; 2525179337Syongari flags = le32toh(desc->flags); 2526179337Syongari status = le32toh(desc->buflen); 2527179337Syongari nsegs = JME_RX_NSEGS(status); 2528179337Syongari sc->jme_cdata.jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES; 2529179337Syongari if ((status & JME_RX_ERR_STAT) != 0) { 2530179337Syongari ifp->if_ierrors++; 2531179337Syongari jme_discard_rxbuf(sc, sc->jme_cdata.jme_rx_cons); 2532179337Syongari#ifdef JME_SHOW_ERRORS 2533179337Syongari device_printf(sc->jme_dev, "%s : receive error = 0x%b\n", 2534179337Syongari __func__, JME_RX_ERR(status), JME_RX_ERR_BITS); 2535179337Syongari#endif 2536179337Syongari sc->jme_cdata.jme_rx_cons += nsegs; 2537179337Syongari sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT; 2538179337Syongari return; 2539179337Syongari } 2540179337Syongari 2541179337Syongari for (count = 0; count < nsegs; count++, 2542179337Syongari JME_DESC_INC(cons, JME_RX_RING_CNT)) { 2543179337Syongari rxd = &sc->jme_cdata.jme_rxdesc[cons]; 2544179337Syongari mp = rxd->rx_m; 2545179337Syongari /* Add a new receive buffer to the ring. */ 2546179337Syongari if (jme_newbuf(sc, rxd) != 0) { 2547179337Syongari ifp->if_iqdrops++; 2548179337Syongari /* Reuse buffer. */ 2549180869Syongari for (; count < nsegs; count++) { 2550180869Syongari jme_discard_rxbuf(sc, cons); 2551180869Syongari JME_DESC_INC(cons, JME_RX_RING_CNT); 2552180869Syongari } 2553179337Syongari if (sc->jme_cdata.jme_rxhead != NULL) { 2554179337Syongari m_freem(sc->jme_cdata.jme_rxhead); 2555179337Syongari JME_RXCHAIN_RESET(sc); 2556179337Syongari } 2557179337Syongari break; 2558179337Syongari } 2559179337Syongari 2560179337Syongari /* 2561179337Syongari * Assume we've received a full sized frame. 2562179337Syongari * Actual size is fixed when we encounter the end of 2563179337Syongari * multi-segmented frame. 2564179337Syongari */ 2565179337Syongari mp->m_len = MCLBYTES; 2566179337Syongari 2567179337Syongari /* Chain received mbufs. */ 2568179337Syongari if (sc->jme_cdata.jme_rxhead == NULL) { 2569179337Syongari sc->jme_cdata.jme_rxhead = mp; 2570179337Syongari sc->jme_cdata.jme_rxtail = mp; 2571179337Syongari } else { 2572179337Syongari /* 2573179337Syongari * Receive processor can receive a maximum frame 2574179337Syongari * size of 65535 bytes. 2575179337Syongari */ 2576179337Syongari mp->m_flags &= ~M_PKTHDR; 2577179337Syongari sc->jme_cdata.jme_rxtail->m_next = mp; 2578179337Syongari sc->jme_cdata.jme_rxtail = mp; 2579179337Syongari } 2580179337Syongari 2581179337Syongari if (count == nsegs - 1) { 2582179337Syongari /* Last desc. for this frame. */ 2583179337Syongari m = sc->jme_cdata.jme_rxhead; 2584179337Syongari m->m_flags |= M_PKTHDR; 2585179337Syongari m->m_pkthdr.len = sc->jme_cdata.jme_rxlen; 2586179337Syongari if (nsegs > 1) { 2587179337Syongari /* Set first mbuf size. */ 2588179337Syongari m->m_len = MCLBYTES - JME_RX_PAD_BYTES; 2589179337Syongari /* Set last mbuf size. */ 2590179337Syongari mp->m_len = sc->jme_cdata.jme_rxlen - 2591179337Syongari ((MCLBYTES - JME_RX_PAD_BYTES) + 2592179337Syongari (MCLBYTES * (nsegs - 2))); 2593179337Syongari } else 2594179337Syongari m->m_len = sc->jme_cdata.jme_rxlen; 2595179337Syongari m->m_pkthdr.rcvif = ifp; 2596179337Syongari 2597179337Syongari /* 2598179337Syongari * Account for 10bytes auto padding which is used 2599179337Syongari * to align IP header on 32bit boundary. Also note, 2600179337Syongari * CRC bytes is automatically removed by the 2601179337Syongari * hardware. 2602179337Syongari */ 2603179337Syongari m->m_data += JME_RX_PAD_BYTES; 2604179337Syongari 2605179337Syongari /* Set checksum information. */ 2606179337Syongari if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2607179337Syongari (flags & JME_RD_IPV4) != 0) { 2608179337Syongari m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2609179337Syongari if ((flags & JME_RD_IPCSUM) != 0) 2610179337Syongari m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2611179337Syongari if (((flags & JME_RD_MORE_FRAG) == 0) && 2612179337Syongari ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) == 2613179337Syongari (JME_RD_TCP | JME_RD_TCPCSUM) || 2614179337Syongari (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) == 2615179337Syongari (JME_RD_UDP | JME_RD_UDPCSUM))) { 2616179337Syongari m->m_pkthdr.csum_flags |= 2617179337Syongari CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2618179337Syongari m->m_pkthdr.csum_data = 0xffff; 2619179337Syongari } 2620179337Syongari } 2621179337Syongari 2622179337Syongari /* Check for VLAN tagged packets. */ 2623179337Syongari if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2624179337Syongari (flags & JME_RD_VLAN_TAG) != 0) { 2625179337Syongari m->m_pkthdr.ether_vtag = 2626179337Syongari flags & JME_RD_VLAN_MASK; 2627179337Syongari m->m_flags |= M_VLANTAG; 2628179337Syongari } 2629179337Syongari 2630179337Syongari ifp->if_ipackets++; 2631179337Syongari /* Pass it on. */ 2632217353Sjhb JME_UNLOCK(sc); 2633179337Syongari (*ifp->if_input)(ifp, m); 2634217353Sjhb JME_LOCK(sc); 2635179337Syongari 2636179337Syongari /* Reset mbuf chains. */ 2637179337Syongari JME_RXCHAIN_RESET(sc); 2638179337Syongari } 2639179337Syongari } 2640179337Syongari 2641179337Syongari sc->jme_cdata.jme_rx_cons += nsegs; 2642179337Syongari sc->jme_cdata.jme_rx_cons %= JME_RX_RING_CNT; 2643179337Syongari} 2644179337Syongari 2645179337Syongaristatic int 2646179337Syongarijme_rxintr(struct jme_softc *sc, int count) 2647179337Syongari{ 2648179337Syongari struct jme_desc *desc; 2649179337Syongari int nsegs, prog, pktlen; 2650179337Syongari 2651179337Syongari bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag, 2652179337Syongari sc->jme_cdata.jme_rx_ring_map, 2653179337Syongari BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2654179337Syongari 2655179337Syongari for (prog = 0; count > 0; prog++) { 2656179337Syongari desc = &sc->jme_rdata.jme_rx_ring[sc->jme_cdata.jme_rx_cons]; 2657179337Syongari if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN) 2658179337Syongari break; 2659179337Syongari if ((le32toh(desc->buflen) & JME_RD_VALID) == 0) 2660179337Syongari break; 2661179337Syongari nsegs = JME_RX_NSEGS(le32toh(desc->buflen)); 2662179337Syongari /* 2663179337Syongari * Check number of segments against received bytes. 2664179337Syongari * Non-matching value would indicate that hardware 2665179337Syongari * is still trying to update Rx descriptors. I'm not 2666179337Syongari * sure whether this check is needed. 2667179337Syongari */ 2668179337Syongari pktlen = JME_RX_BYTES(le32toh(desc->buflen)); 2669179337Syongari if (nsegs != ((pktlen + (MCLBYTES - 1)) / MCLBYTES)) 2670179337Syongari break; 2671179337Syongari prog++; 2672179337Syongari /* Received a frame. */ 2673179337Syongari jme_rxeof(sc); 2674179337Syongari count -= nsegs; 2675179337Syongari } 2676179337Syongari 2677179337Syongari if (prog > 0) 2678179337Syongari bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag, 2679179337Syongari sc->jme_cdata.jme_rx_ring_map, 2680179337Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2681179337Syongari 2682179337Syongari return (count > 0 ? 0 : EAGAIN); 2683179337Syongari} 2684179337Syongari 2685179337Syongaristatic void 2686179337Syongarijme_tick(void *arg) 2687179337Syongari{ 2688179337Syongari struct jme_softc *sc; 2689179337Syongari struct mii_data *mii; 2690179337Syongari 2691179337Syongari sc = (struct jme_softc *)arg; 2692179337Syongari 2693179337Syongari JME_LOCK_ASSERT(sc); 2694179337Syongari 2695179337Syongari mii = device_get_softc(sc->jme_miibus); 2696179337Syongari mii_tick(mii); 2697179337Syongari /* 2698179337Syongari * Reclaim Tx buffers that have been completed. It's not 2699179337Syongari * needed here but it would release allocated mbuf chains 2700179337Syongari * faster and limit the maximum delay to a hz. 2701179337Syongari */ 2702179337Syongari jme_txeof(sc); 2703185597Syongari jme_stats_update(sc); 2704179337Syongari jme_watchdog(sc); 2705179337Syongari callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); 2706179337Syongari} 2707179337Syongari 2708179337Syongaristatic void 2709179337Syongarijme_reset(struct jme_softc *sc) 2710179337Syongari{ 2711216551Syongari uint32_t ghc, gpreg; 2712179337Syongari 2713179337Syongari /* Stop receiver, transmitter. */ 2714179337Syongari jme_stop_rx(sc); 2715179337Syongari jme_stop_tx(sc); 2716216551Syongari 2717216551Syongari /* Reset controller. */ 2718179337Syongari CSR_WRITE_4(sc, JME_GHC, GHC_RESET); 2719216551Syongari CSR_READ_4(sc, JME_GHC); 2720179337Syongari DELAY(10); 2721216551Syongari /* 2722216551Syongari * Workaround Rx FIFO overruns seen under certain conditions. 2723216551Syongari * Explicitly synchorize TX/RX clock. TX/RX clock should be 2724216551Syongari * enabled only after enabling TX/RX MACs. 2725216551Syongari */ 2726216551Syongari if ((sc->jme_flags & (JME_FLAG_TXCLK | JME_FLAG_RXCLK)) != 0) { 2727216551Syongari /* Disable TX clock. */ 2728216551Syongari CSR_WRITE_4(sc, JME_GHC, GHC_RESET | GHC_TX_MAC_CLK_DIS); 2729216551Syongari /* Disable RX clock. */ 2730216551Syongari gpreg = CSR_READ_4(sc, JME_GPREG1); 2731216551Syongari CSR_WRITE_4(sc, JME_GPREG1, gpreg | GPREG1_RX_MAC_CLK_DIS); 2732216551Syongari gpreg = CSR_READ_4(sc, JME_GPREG1); 2733216551Syongari /* De-assert RESET but still disable TX clock. */ 2734216551Syongari CSR_WRITE_4(sc, JME_GHC, GHC_TX_MAC_CLK_DIS); 2735216551Syongari ghc = CSR_READ_4(sc, JME_GHC); 2736216551Syongari 2737216551Syongari /* Enable TX clock. */ 2738216551Syongari CSR_WRITE_4(sc, JME_GHC, ghc & ~GHC_TX_MAC_CLK_DIS); 2739216551Syongari /* Enable RX clock. */ 2740216551Syongari CSR_WRITE_4(sc, JME_GPREG1, gpreg & ~GPREG1_RX_MAC_CLK_DIS); 2741216551Syongari CSR_READ_4(sc, JME_GPREG1); 2742216551Syongari 2743216551Syongari /* Disable TX/RX clock again. */ 2744216551Syongari CSR_WRITE_4(sc, JME_GHC, GHC_TX_MAC_CLK_DIS); 2745216551Syongari CSR_WRITE_4(sc, JME_GPREG1, gpreg | GPREG1_RX_MAC_CLK_DIS); 2746216551Syongari } else 2747216551Syongari CSR_WRITE_4(sc, JME_GHC, 0); 2748216551Syongari CSR_READ_4(sc, JME_GHC); 2749216551Syongari DELAY(10); 2750179337Syongari} 2751179337Syongari 2752179337Syongaristatic void 2753179337Syongarijme_init(void *xsc) 2754179337Syongari{ 2755179337Syongari struct jme_softc *sc; 2756179337Syongari 2757179337Syongari sc = (struct jme_softc *)xsc; 2758179337Syongari JME_LOCK(sc); 2759179337Syongari jme_init_locked(sc); 2760179337Syongari JME_UNLOCK(sc); 2761179337Syongari} 2762179337Syongari 2763179337Syongaristatic void 2764179337Syongarijme_init_locked(struct jme_softc *sc) 2765179337Syongari{ 2766179337Syongari struct ifnet *ifp; 2767179337Syongari struct mii_data *mii; 2768179337Syongari bus_addr_t paddr; 2769179337Syongari uint32_t reg; 2770179337Syongari int error; 2771179337Syongari 2772179337Syongari JME_LOCK_ASSERT(sc); 2773179337Syongari 2774179337Syongari ifp = sc->jme_ifp; 2775179337Syongari mii = device_get_softc(sc->jme_miibus); 2776179337Syongari 2777197585Syongari if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2778197585Syongari return; 2779179337Syongari /* 2780179337Syongari * Cancel any pending I/O. 2781179337Syongari */ 2782179337Syongari jme_stop(sc); 2783179337Syongari 2784179337Syongari /* 2785179337Syongari * Reset the chip to a known state. 2786179337Syongari */ 2787179337Syongari jme_reset(sc); 2788179337Syongari 2789179337Syongari /* Init descriptors. */ 2790179337Syongari error = jme_init_rx_ring(sc); 2791179337Syongari if (error != 0) { 2792179337Syongari device_printf(sc->jme_dev, 2793179337Syongari "%s: initialization failed: no memory for Rx buffers.\n", 2794179337Syongari __func__); 2795179337Syongari jme_stop(sc); 2796179337Syongari return; 2797179337Syongari } 2798179337Syongari jme_init_tx_ring(sc); 2799179337Syongari /* Initialize shadow status block. */ 2800179337Syongari jme_init_ssb(sc); 2801179337Syongari 2802179337Syongari /* Reprogram the station address. */ 2803216551Syongari jme_set_macaddr(sc, IF_LLADDR(sc->jme_ifp)); 2804179337Syongari 2805179337Syongari /* 2806179337Syongari * Configure Tx queue. 2807179337Syongari * Tx priority queue weight value : 0 2808179337Syongari * Tx FIFO threshold for processing next packet : 16QW 2809179337Syongari * Maximum Tx DMA length : 512 2810179337Syongari * Allow Tx DMA burst. 2811179337Syongari */ 2812179337Syongari sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0); 2813179337Syongari sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN); 2814179337Syongari sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW; 2815179337Syongari sc->jme_txcsr |= sc->jme_tx_dma_size; 2816179337Syongari sc->jme_txcsr |= TXCSR_DMA_BURST; 2817179337Syongari CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr); 2818179337Syongari 2819179337Syongari /* Set Tx descriptor counter. */ 2820179337Syongari CSR_WRITE_4(sc, JME_TXQDC, JME_TX_RING_CNT); 2821179337Syongari 2822179337Syongari /* Set Tx ring address to the hardware. */ 2823179337Syongari paddr = JME_TX_RING_ADDR(sc, 0); 2824179337Syongari CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr)); 2825179337Syongari CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr)); 2826179337Syongari 2827179337Syongari /* Configure TxMAC parameters. */ 2828179337Syongari reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB; 2829179337Syongari reg |= TXMAC_THRESH_1_PKT; 2830179337Syongari reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB; 2831179337Syongari CSR_WRITE_4(sc, JME_TXMAC, reg); 2832179337Syongari 2833179337Syongari /* 2834179337Syongari * Configure Rx queue. 2835179337Syongari * FIFO full threshold for transmitting Tx pause packet : 128T 2836179337Syongari * FIFO threshold for processing next packet : 128QW 2837179337Syongari * Rx queue 0 select 2838179337Syongari * Max Rx DMA length : 128 2839179337Syongari * Rx descriptor retry : 32 2840179337Syongari * Rx descriptor retry time gap : 256ns 2841179337Syongari * Don't receive runt/bad frame. 2842179337Syongari */ 2843179337Syongari sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T; 2844179337Syongari /* 2845179337Syongari * Since Rx FIFO size is 4K bytes, receiving frames larger 2846179337Syongari * than 4K bytes will suffer from Rx FIFO overruns. So 2847179337Syongari * decrease FIFO threshold to reduce the FIFO overruns for 2848179337Syongari * frames larger than 4000 bytes. 2849179337Syongari * For best performance of standard MTU sized frames use 2850185596Syongari * maximum allowable FIFO threshold, 128QW. Note these do 2851185596Syongari * not hold on chip full mask verion >=2. For these 2852185596Syongari * controllers 64QW and 128QW are not valid value. 2853179337Syongari */ 2854185596Syongari if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 2) 2855179337Syongari sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 2856185596Syongari else { 2857185596Syongari if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2858185596Syongari ETHER_CRC_LEN) > JME_RX_FIFO_SIZE) 2859185596Syongari sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW; 2860185596Syongari else 2861185596Syongari sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW; 2862185596Syongari } 2863179337Syongari sc->jme_rxcsr |= sc->jme_rx_dma_size | RXCSR_RXQ_N_SEL(RXCSR_RXQ0); 2864179337Syongari sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT); 2865179337Syongari sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK; 2866179337Syongari CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr); 2867179337Syongari 2868179337Syongari /* Set Rx descriptor counter. */ 2869179337Syongari CSR_WRITE_4(sc, JME_RXQDC, JME_RX_RING_CNT); 2870179337Syongari 2871179337Syongari /* Set Rx ring address to the hardware. */ 2872179337Syongari paddr = JME_RX_RING_ADDR(sc, 0); 2873179337Syongari CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr)); 2874179337Syongari CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr)); 2875179337Syongari 2876179337Syongari /* Clear receive filter. */ 2877179337Syongari CSR_WRITE_4(sc, JME_RXMAC, 0); 2878179337Syongari /* Set up the receive filter. */ 2879179337Syongari jme_set_filter(sc); 2880179337Syongari jme_set_vlan(sc); 2881179337Syongari 2882179337Syongari /* 2883179337Syongari * Disable all WOL bits as WOL can interfere normal Rx 2884179337Syongari * operation. Also clear WOL detection status bits. 2885179337Syongari */ 2886179337Syongari reg = CSR_READ_4(sc, JME_PMCS); 2887179337Syongari reg &= ~PMCS_WOL_ENB_MASK; 2888179337Syongari CSR_WRITE_4(sc, JME_PMCS, reg); 2889179337Syongari 2890179337Syongari reg = CSR_READ_4(sc, JME_RXMAC); 2891179337Syongari /* 2892179337Syongari * Pad 10bytes right before received frame. This will greatly 2893179337Syongari * help Rx performance on strict-alignment architectures as 2894179337Syongari * it does not need to copy the frame to align the payload. 2895179337Syongari */ 2896179337Syongari reg |= RXMAC_PAD_10BYTES; 2897179337Syongari if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2898179337Syongari reg |= RXMAC_CSUM_ENB; 2899179337Syongari CSR_WRITE_4(sc, JME_RXMAC, reg); 2900179337Syongari 2901179337Syongari /* Configure general purpose reg0 */ 2902179337Syongari reg = CSR_READ_4(sc, JME_GPREG0); 2903179337Syongari reg &= ~GPREG0_PCC_UNIT_MASK; 2904179337Syongari /* Set PCC timer resolution to micro-seconds unit. */ 2905179337Syongari reg |= GPREG0_PCC_UNIT_US; 2906179337Syongari /* 2907179337Syongari * Disable all shadow register posting as we have to read 2908179337Syongari * JME_INTR_STATUS register in jme_int_task. Also it seems 2909179337Syongari * that it's hard to synchronize interrupt status between 2910179337Syongari * hardware and software with shadow posting due to 2911179337Syongari * requirements of bus_dmamap_sync(9). 2912179337Syongari */ 2913179337Syongari reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS | 2914179337Syongari GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS | 2915179337Syongari GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS | 2916179337Syongari GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS; 2917179337Syongari /* Disable posting of DW0. */ 2918179337Syongari reg &= ~GPREG0_POST_DW0_ENB; 2919179337Syongari /* Clear PME message. */ 2920179337Syongari reg &= ~GPREG0_PME_ENB; 2921179337Syongari /* Set PHY address. */ 2922179337Syongari reg &= ~GPREG0_PHY_ADDR_MASK; 2923179337Syongari reg |= sc->jme_phyaddr; 2924179337Syongari CSR_WRITE_4(sc, JME_GPREG0, reg); 2925179337Syongari 2926179337Syongari /* Configure Tx queue 0 packet completion coalescing. */ 2927179337Syongari reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) & 2928179337Syongari PCCTX_COAL_TO_MASK; 2929179337Syongari reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) & 2930179337Syongari PCCTX_COAL_PKT_MASK; 2931179337Syongari reg |= PCCTX_COAL_TXQ0; 2932179337Syongari CSR_WRITE_4(sc, JME_PCCTX, reg); 2933179337Syongari 2934179337Syongari /* Configure Rx queue 0 packet completion coalescing. */ 2935179337Syongari reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) & 2936179337Syongari PCCRX_COAL_TO_MASK; 2937179337Syongari reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) & 2938179337Syongari PCCRX_COAL_PKT_MASK; 2939179337Syongari CSR_WRITE_4(sc, JME_PCCRX0, reg); 2940179337Syongari 2941216551Syongari /* 2942216551Syongari * Configure PCD(Packet Completion Deferring). It seems PCD 2943216551Syongari * generates an interrupt when the time interval between two 2944216551Syongari * back-to-back incoming/outgoing packet is long enough for 2945216551Syongari * it to reach its timer value 0. The arrival of new packets 2946216551Syongari * after timer has started causes the PCD timer to restart. 2947216551Syongari * Unfortunately, it's not clear how PCD is useful at this 2948216551Syongari * moment, so just use the same of PCC parameters. 2949216551Syongari */ 2950216551Syongari if ((sc->jme_flags & JME_FLAG_PCCPCD) != 0) { 2951216551Syongari sc->jme_rx_pcd_to = sc->jme_rx_coal_to; 2952216551Syongari if (sc->jme_rx_coal_to > PCDRX_TO_MAX) 2953216551Syongari sc->jme_rx_pcd_to = PCDRX_TO_MAX; 2954216551Syongari sc->jme_tx_pcd_to = sc->jme_tx_coal_to; 2955216551Syongari if (sc->jme_tx_coal_to > PCDTX_TO_MAX) 2956216551Syongari sc->jme_tx_pcd_to = PCDTX_TO_MAX; 2957216551Syongari reg = sc->jme_rx_pcd_to << PCDRX0_TO_THROTTLE_SHIFT; 2958216551Syongari reg |= sc->jme_rx_pcd_to << PCDRX0_TO_SHIFT; 2959216551Syongari CSR_WRITE_4(sc, PCDRX_REG(0), reg); 2960216551Syongari reg = sc->jme_tx_pcd_to << PCDTX_TO_THROTTLE_SHIFT; 2961216551Syongari reg |= sc->jme_tx_pcd_to << PCDTX_TO_SHIFT; 2962216551Syongari CSR_WRITE_4(sc, JME_PCDTX, reg); 2963216551Syongari } 2964216551Syongari 2965179337Syongari /* Configure shadow status block but don't enable posting. */ 2966179337Syongari paddr = sc->jme_rdata.jme_ssb_block_paddr; 2967179337Syongari CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr)); 2968179337Syongari CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr)); 2969179337Syongari 2970179337Syongari /* Disable Timer 1 and Timer 2. */ 2971179337Syongari CSR_WRITE_4(sc, JME_TIMER1, 0); 2972179337Syongari CSR_WRITE_4(sc, JME_TIMER2, 0); 2973179337Syongari 2974179337Syongari /* Configure retry transmit period, retry limit value. */ 2975179337Syongari CSR_WRITE_4(sc, JME_TXTRHD, 2976179337Syongari ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) & 2977179337Syongari TXTRHD_RT_PERIOD_MASK) | 2978179337Syongari ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) & 2979179337Syongari TXTRHD_RT_LIMIT_SHIFT)); 2980179337Syongari 2981179337Syongari /* Disable RSS. */ 2982179337Syongari CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS); 2983179337Syongari 2984179337Syongari /* Initialize the interrupt mask. */ 2985179337Syongari CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS); 2986179337Syongari CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF); 2987179337Syongari 2988179337Syongari /* 2989179337Syongari * Enabling Tx/Rx DMA engines and Rx queue processing is 2990179337Syongari * done after detection of valid link in jme_link_task. 2991179337Syongari */ 2992179337Syongari 2993179337Syongari sc->jme_flags &= ~JME_FLAG_LINK; 2994179337Syongari /* Set the current media. */ 2995179337Syongari mii_mediachg(mii); 2996179337Syongari 2997179337Syongari callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc); 2998179337Syongari 2999179337Syongari ifp->if_drv_flags |= IFF_DRV_RUNNING; 3000179337Syongari ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3001179337Syongari} 3002179337Syongari 3003179337Syongaristatic void 3004179337Syongarijme_stop(struct jme_softc *sc) 3005179337Syongari{ 3006179337Syongari struct ifnet *ifp; 3007179337Syongari struct jme_txdesc *txd; 3008179337Syongari struct jme_rxdesc *rxd; 3009179337Syongari int i; 3010179337Syongari 3011179337Syongari JME_LOCK_ASSERT(sc); 3012179337Syongari /* 3013179337Syongari * Mark the interface down and cancel the watchdog timer. 3014179337Syongari */ 3015179337Syongari ifp = sc->jme_ifp; 3016179337Syongari ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3017179337Syongari sc->jme_flags &= ~JME_FLAG_LINK; 3018179337Syongari callout_stop(&sc->jme_tick_ch); 3019179337Syongari sc->jme_watchdog_timer = 0; 3020179337Syongari 3021179337Syongari /* 3022179337Syongari * Disable interrupts. 3023179337Syongari */ 3024179337Syongari CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS); 3025179337Syongari CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF); 3026179337Syongari 3027179337Syongari /* Disable updating shadow status block. */ 3028179337Syongari CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, 3029179337Syongari CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB); 3030179337Syongari 3031179337Syongari /* Stop receiver, transmitter. */ 3032179337Syongari jme_stop_rx(sc); 3033179337Syongari jme_stop_tx(sc); 3034179337Syongari 3035179337Syongari /* Reclaim Rx/Tx buffers that have been completed. */ 3036179337Syongari jme_rxintr(sc, JME_RX_RING_CNT); 3037179337Syongari if (sc->jme_cdata.jme_rxhead != NULL) 3038179337Syongari m_freem(sc->jme_cdata.jme_rxhead); 3039179337Syongari JME_RXCHAIN_RESET(sc); 3040179337Syongari jme_txeof(sc); 3041179337Syongari /* 3042179337Syongari * Free RX and TX mbufs still in the queues. 3043179337Syongari */ 3044179337Syongari for (i = 0; i < JME_RX_RING_CNT; i++) { 3045179337Syongari rxd = &sc->jme_cdata.jme_rxdesc[i]; 3046179337Syongari if (rxd->rx_m != NULL) { 3047179337Syongari bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, 3048179337Syongari rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3049179337Syongari bus_dmamap_unload(sc->jme_cdata.jme_rx_tag, 3050179337Syongari rxd->rx_dmamap); 3051179337Syongari m_freem(rxd->rx_m); 3052179337Syongari rxd->rx_m = NULL; 3053179337Syongari } 3054179337Syongari } 3055179337Syongari for (i = 0; i < JME_TX_RING_CNT; i++) { 3056179337Syongari txd = &sc->jme_cdata.jme_txdesc[i]; 3057179337Syongari if (txd->tx_m != NULL) { 3058179337Syongari bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, 3059179337Syongari txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3060179337Syongari bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, 3061179337Syongari txd->tx_dmamap); 3062179337Syongari m_freem(txd->tx_m); 3063179337Syongari txd->tx_m = NULL; 3064179337Syongari txd->tx_ndesc = 0; 3065179337Syongari } 3066179337Syongari } 3067185597Syongari jme_stats_update(sc); 3068185597Syongari jme_stats_save(sc); 3069179337Syongari} 3070179337Syongari 3071179337Syongaristatic void 3072179337Syongarijme_stop_tx(struct jme_softc *sc) 3073179337Syongari{ 3074179337Syongari uint32_t reg; 3075179337Syongari int i; 3076179337Syongari 3077179337Syongari reg = CSR_READ_4(sc, JME_TXCSR); 3078179337Syongari if ((reg & TXCSR_TX_ENB) == 0) 3079179337Syongari return; 3080179337Syongari reg &= ~TXCSR_TX_ENB; 3081179337Syongari CSR_WRITE_4(sc, JME_TXCSR, reg); 3082179337Syongari for (i = JME_TIMEOUT; i > 0; i--) { 3083179337Syongari DELAY(1); 3084179337Syongari if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0) 3085179337Syongari break; 3086179337Syongari } 3087179337Syongari if (i == 0) 3088179337Syongari device_printf(sc->jme_dev, "stopping transmitter timeout!\n"); 3089179337Syongari} 3090179337Syongari 3091179337Syongaristatic void 3092179337Syongarijme_stop_rx(struct jme_softc *sc) 3093179337Syongari{ 3094179337Syongari uint32_t reg; 3095179337Syongari int i; 3096179337Syongari 3097179337Syongari reg = CSR_READ_4(sc, JME_RXCSR); 3098179337Syongari if ((reg & RXCSR_RX_ENB) == 0) 3099179337Syongari return; 3100179337Syongari reg &= ~RXCSR_RX_ENB; 3101179337Syongari CSR_WRITE_4(sc, JME_RXCSR, reg); 3102179337Syongari for (i = JME_TIMEOUT; i > 0; i--) { 3103179337Syongari DELAY(1); 3104179337Syongari if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0) 3105179337Syongari break; 3106179337Syongari } 3107179337Syongari if (i == 0) 3108179337Syongari device_printf(sc->jme_dev, "stopping recevier timeout!\n"); 3109179337Syongari} 3110179337Syongari 3111179337Syongaristatic void 3112179337Syongarijme_init_tx_ring(struct jme_softc *sc) 3113179337Syongari{ 3114179337Syongari struct jme_ring_data *rd; 3115179337Syongari struct jme_txdesc *txd; 3116179337Syongari int i; 3117179337Syongari 3118179337Syongari sc->jme_cdata.jme_tx_prod = 0; 3119179337Syongari sc->jme_cdata.jme_tx_cons = 0; 3120179337Syongari sc->jme_cdata.jme_tx_cnt = 0; 3121179337Syongari 3122179337Syongari rd = &sc->jme_rdata; 3123179337Syongari bzero(rd->jme_tx_ring, JME_TX_RING_SIZE); 3124179337Syongari for (i = 0; i < JME_TX_RING_CNT; i++) { 3125179337Syongari txd = &sc->jme_cdata.jme_txdesc[i]; 3126179337Syongari txd->tx_m = NULL; 3127179337Syongari txd->tx_desc = &rd->jme_tx_ring[i]; 3128179337Syongari txd->tx_ndesc = 0; 3129179337Syongari } 3130179337Syongari 3131179337Syongari bus_dmamap_sync(sc->jme_cdata.jme_tx_ring_tag, 3132179337Syongari sc->jme_cdata.jme_tx_ring_map, 3133179337Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3134179337Syongari} 3135179337Syongari 3136179337Syongaristatic void 3137179337Syongarijme_init_ssb(struct jme_softc *sc) 3138179337Syongari{ 3139179337Syongari struct jme_ring_data *rd; 3140179337Syongari 3141179337Syongari rd = &sc->jme_rdata; 3142179337Syongari bzero(rd->jme_ssb_block, JME_SSB_SIZE); 3143179337Syongari bus_dmamap_sync(sc->jme_cdata.jme_ssb_tag, sc->jme_cdata.jme_ssb_map, 3144179337Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3145179337Syongari} 3146179337Syongari 3147179337Syongaristatic int 3148179337Syongarijme_init_rx_ring(struct jme_softc *sc) 3149179337Syongari{ 3150179337Syongari struct jme_ring_data *rd; 3151179337Syongari struct jme_rxdesc *rxd; 3152179337Syongari int i; 3153179337Syongari 3154179337Syongari sc->jme_cdata.jme_rx_cons = 0; 3155179337Syongari JME_RXCHAIN_RESET(sc); 3156216362Syongari sc->jme_morework = 0; 3157179337Syongari 3158179337Syongari rd = &sc->jme_rdata; 3159179337Syongari bzero(rd->jme_rx_ring, JME_RX_RING_SIZE); 3160179337Syongari for (i = 0; i < JME_RX_RING_CNT; i++) { 3161179337Syongari rxd = &sc->jme_cdata.jme_rxdesc[i]; 3162179337Syongari rxd->rx_m = NULL; 3163179337Syongari rxd->rx_desc = &rd->jme_rx_ring[i]; 3164179337Syongari if (jme_newbuf(sc, rxd) != 0) 3165179337Syongari return (ENOBUFS); 3166179337Syongari } 3167179337Syongari 3168179337Syongari bus_dmamap_sync(sc->jme_cdata.jme_rx_ring_tag, 3169179337Syongari sc->jme_cdata.jme_rx_ring_map, 3170179337Syongari BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3171179337Syongari 3172179337Syongari return (0); 3173179337Syongari} 3174179337Syongari 3175179337Syongaristatic int 3176179337Syongarijme_newbuf(struct jme_softc *sc, struct jme_rxdesc *rxd) 3177179337Syongari{ 3178179337Syongari struct jme_desc *desc; 3179179337Syongari struct mbuf *m; 3180179337Syongari bus_dma_segment_t segs[1]; 3181179337Syongari bus_dmamap_t map; 3182179337Syongari int nsegs; 3183179337Syongari 3184243857Sglebius m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3185179337Syongari if (m == NULL) 3186179337Syongari return (ENOBUFS); 3187179337Syongari /* 3188179337Syongari * JMC250 has 64bit boundary alignment limitation so jme(4) 3189179337Syongari * takes advantage of 10 bytes padding feature of hardware 3190179337Syongari * in order not to copy entire frame to align IP header on 3191179337Syongari * 32bit boundary. 3192179337Syongari */ 3193179337Syongari m->m_len = m->m_pkthdr.len = MCLBYTES; 3194179337Syongari 3195179337Syongari if (bus_dmamap_load_mbuf_sg(sc->jme_cdata.jme_rx_tag, 3196179337Syongari sc->jme_cdata.jme_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3197179337Syongari m_freem(m); 3198179337Syongari return (ENOBUFS); 3199179337Syongari } 3200179337Syongari KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3201179337Syongari 3202179337Syongari if (rxd->rx_m != NULL) { 3203179337Syongari bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap, 3204179337Syongari BUS_DMASYNC_POSTREAD); 3205179337Syongari bus_dmamap_unload(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap); 3206179337Syongari } 3207179337Syongari map = rxd->rx_dmamap; 3208179337Syongari rxd->rx_dmamap = sc->jme_cdata.jme_rx_sparemap; 3209179337Syongari sc->jme_cdata.jme_rx_sparemap = map; 3210179337Syongari bus_dmamap_sync(sc->jme_cdata.jme_rx_tag, rxd->rx_dmamap, 3211179337Syongari BUS_DMASYNC_PREREAD); 3212179337Syongari rxd->rx_m = m; 3213179337Syongari 3214179337Syongari desc = rxd->rx_desc; 3215179337Syongari desc->buflen = htole32(segs[0].ds_len); 3216179337Syongari desc->addr_lo = htole32(JME_ADDR_LO(segs[0].ds_addr)); 3217179337Syongari desc->addr_hi = htole32(JME_ADDR_HI(segs[0].ds_addr)); 3218179337Syongari desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT); 3219179337Syongari 3220179337Syongari return (0); 3221179337Syongari} 3222179337Syongari 3223179337Syongaristatic void 3224179337Syongarijme_set_vlan(struct jme_softc *sc) 3225179337Syongari{ 3226179337Syongari struct ifnet *ifp; 3227179337Syongari uint32_t reg; 3228179337Syongari 3229179337Syongari JME_LOCK_ASSERT(sc); 3230179337Syongari 3231179337Syongari ifp = sc->jme_ifp; 3232179337Syongari reg = CSR_READ_4(sc, JME_RXMAC); 3233179337Syongari reg &= ~RXMAC_VLAN_ENB; 3234179337Syongari if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3235179337Syongari reg |= RXMAC_VLAN_ENB; 3236179337Syongari CSR_WRITE_4(sc, JME_RXMAC, reg); 3237179337Syongari} 3238179337Syongari 3239179337Syongaristatic void 3240179337Syongarijme_set_filter(struct jme_softc *sc) 3241179337Syongari{ 3242179337Syongari struct ifnet *ifp; 3243179337Syongari struct ifmultiaddr *ifma; 3244179337Syongari uint32_t crc; 3245179337Syongari uint32_t mchash[2]; 3246179337Syongari uint32_t rxcfg; 3247179337Syongari 3248179337Syongari JME_LOCK_ASSERT(sc); 3249179337Syongari 3250179337Syongari ifp = sc->jme_ifp; 3251179337Syongari 3252179337Syongari rxcfg = CSR_READ_4(sc, JME_RXMAC); 3253179337Syongari rxcfg &= ~ (RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST | 3254179337Syongari RXMAC_ALLMULTI); 3255179337Syongari /* Always accept frames destined to our station address. */ 3256179337Syongari rxcfg |= RXMAC_UNICAST; 3257179337Syongari if ((ifp->if_flags & IFF_BROADCAST) != 0) 3258179337Syongari rxcfg |= RXMAC_BROADCAST; 3259179337Syongari if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3260179337Syongari if ((ifp->if_flags & IFF_PROMISC) != 0) 3261179337Syongari rxcfg |= RXMAC_PROMISC; 3262179337Syongari if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3263179337Syongari rxcfg |= RXMAC_ALLMULTI; 3264179337Syongari CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF); 3265179337Syongari CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF); 3266179337Syongari CSR_WRITE_4(sc, JME_RXMAC, rxcfg); 3267179337Syongari return; 3268179337Syongari } 3269179337Syongari 3270179337Syongari /* 3271179337Syongari * Set up the multicast address filter by passing all multicast 3272179337Syongari * addresses through a CRC generator, and then using the low-order 3273179337Syongari * 6 bits as an index into the 64 bit multicast hash table. The 3274179337Syongari * high order bits select the register, while the rest of the bits 3275179337Syongari * select the bit within the register. 3276179337Syongari */ 3277179337Syongari rxcfg |= RXMAC_MULTICAST; 3278179337Syongari bzero(mchash, sizeof(mchash)); 3279179337Syongari 3280195049Srwatson if_maddr_rlock(ifp); 3281179337Syongari TAILQ_FOREACH(ifma, &sc->jme_ifp->if_multiaddrs, ifma_link) { 3282179337Syongari if (ifma->ifma_addr->sa_family != AF_LINK) 3283179337Syongari continue; 3284179337Syongari crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3285179337Syongari ifma->ifma_addr), ETHER_ADDR_LEN); 3286179337Syongari 3287179337Syongari /* Just want the 6 least significant bits. */ 3288179337Syongari crc &= 0x3f; 3289179337Syongari 3290179337Syongari /* Set the corresponding bit in the hash table. */ 3291179337Syongari mchash[crc >> 5] |= 1 << (crc & 0x1f); 3292179337Syongari } 3293195049Srwatson if_maddr_runlock(ifp); 3294179337Syongari 3295179337Syongari CSR_WRITE_4(sc, JME_MAR0, mchash[0]); 3296179337Syongari CSR_WRITE_4(sc, JME_MAR1, mchash[1]); 3297179337Syongari CSR_WRITE_4(sc, JME_RXMAC, rxcfg); 3298179337Syongari} 3299179337Syongari 3300185597Syongaristatic void 3301185597Syongarijme_stats_clear(struct jme_softc *sc) 3302185597Syongari{ 3303185597Syongari 3304185597Syongari JME_LOCK_ASSERT(sc); 3305185597Syongari 3306185597Syongari if ((sc->jme_flags & JME_FLAG_HWMIB) == 0) 3307185597Syongari return; 3308185597Syongari 3309185597Syongari /* Disable and clear counters. */ 3310185597Syongari CSR_WRITE_4(sc, JME_STATCSR, 0xFFFFFFFF); 3311185597Syongari /* Activate hw counters. */ 3312185597Syongari CSR_WRITE_4(sc, JME_STATCSR, 0); 3313185597Syongari CSR_READ_4(sc, JME_STATCSR); 3314185597Syongari bzero(&sc->jme_stats, sizeof(struct jme_hw_stats)); 3315185597Syongari} 3316185597Syongari 3317185597Syongaristatic void 3318185597Syongarijme_stats_save(struct jme_softc *sc) 3319185597Syongari{ 3320185597Syongari 3321185597Syongari JME_LOCK_ASSERT(sc); 3322185597Syongari 3323185597Syongari if ((sc->jme_flags & JME_FLAG_HWMIB) == 0) 3324185597Syongari return; 3325185597Syongari /* Save current counters. */ 3326185597Syongari bcopy(&sc->jme_stats, &sc->jme_ostats, sizeof(struct jme_hw_stats)); 3327185597Syongari /* Disable and clear counters. */ 3328185597Syongari CSR_WRITE_4(sc, JME_STATCSR, 0xFFFFFFFF); 3329185597Syongari} 3330185597Syongari 3331185597Syongaristatic void 3332185597Syongarijme_stats_update(struct jme_softc *sc) 3333185597Syongari{ 3334185597Syongari struct jme_hw_stats *stat, *ostat; 3335185597Syongari uint32_t reg; 3336185597Syongari 3337185597Syongari JME_LOCK_ASSERT(sc); 3338185597Syongari 3339185597Syongari if ((sc->jme_flags & JME_FLAG_HWMIB) == 0) 3340185597Syongari return; 3341185597Syongari stat = &sc->jme_stats; 3342185597Syongari ostat = &sc->jme_ostats; 3343185597Syongari stat->tx_good_frames = CSR_READ_4(sc, JME_STAT_TXGOOD); 3344185597Syongari stat->rx_good_frames = CSR_READ_4(sc, JME_STAT_RXGOOD); 3345185597Syongari reg = CSR_READ_4(sc, JME_STAT_CRCMII); 3346185597Syongari stat->rx_crc_errs = (reg & STAT_RX_CRC_ERR_MASK) >> 3347185597Syongari STAT_RX_CRC_ERR_SHIFT; 3348185597Syongari stat->rx_mii_errs = (reg & STAT_RX_MII_ERR_MASK) >> 3349185597Syongari STAT_RX_MII_ERR_SHIFT; 3350185597Syongari reg = CSR_READ_4(sc, JME_STAT_RXERR); 3351185597Syongari stat->rx_fifo_oflows = (reg & STAT_RXERR_OFLOW_MASK) >> 3352185597Syongari STAT_RXERR_OFLOW_SHIFT; 3353185597Syongari stat->rx_desc_empty = (reg & STAT_RXERR_MPTY_MASK) >> 3354185597Syongari STAT_RXERR_MPTY_SHIFT; 3355185597Syongari reg = CSR_READ_4(sc, JME_STAT_FAIL); 3356185597Syongari stat->rx_bad_frames = (reg & STAT_FAIL_RX_MASK) >> STAT_FAIL_RX_SHIFT; 3357185597Syongari stat->tx_bad_frames = (reg & STAT_FAIL_TX_MASK) >> STAT_FAIL_TX_SHIFT; 3358185597Syongari 3359185597Syongari /* Account for previous counters. */ 3360185597Syongari stat->rx_good_frames += ostat->rx_good_frames; 3361185597Syongari stat->rx_crc_errs += ostat->rx_crc_errs; 3362185597Syongari stat->rx_mii_errs += ostat->rx_mii_errs; 3363185597Syongari stat->rx_fifo_oflows += ostat->rx_fifo_oflows; 3364185597Syongari stat->rx_desc_empty += ostat->rx_desc_empty; 3365185597Syongari stat->rx_bad_frames += ostat->rx_bad_frames; 3366185597Syongari stat->tx_good_frames += ostat->tx_good_frames; 3367185597Syongari stat->tx_bad_frames += ostat->tx_bad_frames; 3368185597Syongari} 3369185597Syongari 3370216551Syongaristatic void 3371216551Syongarijme_phy_down(struct jme_softc *sc) 3372216551Syongari{ 3373216551Syongari uint32_t reg; 3374216551Syongari 3375216551Syongari jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, BMCR_PDOWN); 3376216551Syongari if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5) { 3377216551Syongari reg = CSR_READ_4(sc, JME_PHYPOWDN); 3378216551Syongari reg |= 0x0000000F; 3379216551Syongari CSR_WRITE_4(sc, JME_PHYPOWDN, reg); 3380216551Syongari reg = pci_read_config(sc->jme_dev, JME_PCI_PE1, 4); 3381216551Syongari reg &= ~PE1_GIGA_PDOWN_MASK; 3382216551Syongari reg |= PE1_GIGA_PDOWN_D3; 3383216551Syongari pci_write_config(sc->jme_dev, JME_PCI_PE1, reg, 4); 3384216551Syongari } 3385216551Syongari} 3386216551Syongari 3387216551Syongaristatic void 3388216551Syongarijme_phy_up(struct jme_softc *sc) 3389216551Syongari{ 3390216551Syongari uint32_t reg; 3391216551Syongari uint16_t bmcr; 3392216551Syongari 3393216551Syongari bmcr = jme_miibus_readreg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR); 3394216551Syongari bmcr &= ~BMCR_PDOWN; 3395216551Syongari jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR, bmcr); 3396216551Syongari if (CHIPMODE_REVFM(sc->jme_chip_rev) >= 5) { 3397216551Syongari reg = CSR_READ_4(sc, JME_PHYPOWDN); 3398216551Syongari reg &= ~0x0000000F; 3399216551Syongari CSR_WRITE_4(sc, JME_PHYPOWDN, reg); 3400216551Syongari reg = pci_read_config(sc->jme_dev, JME_PCI_PE1, 4); 3401216551Syongari reg &= ~PE1_GIGA_PDOWN_MASK; 3402216551Syongari reg |= PE1_GIGA_PDOWN_DIS; 3403216551Syongari pci_write_config(sc->jme_dev, JME_PCI_PE1, reg, 4); 3404216551Syongari } 3405216551Syongari} 3406216551Syongari 3407179337Syongaristatic int 3408179337Syongarisysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3409179337Syongari{ 3410179337Syongari int error, value; 3411179337Syongari 3412179337Syongari if (arg1 == NULL) 3413179337Syongari return (EINVAL); 3414179337Syongari value = *(int *)arg1; 3415179337Syongari error = sysctl_handle_int(oidp, &value, 0, req); 3416179337Syongari if (error || req->newptr == NULL) 3417179337Syongari return (error); 3418179337Syongari if (value < low || value > high) 3419179337Syongari return (EINVAL); 3420179337Syongari *(int *)arg1 = value; 3421179337Syongari 3422179337Syongari return (0); 3423179337Syongari} 3424179337Syongari 3425179337Syongaristatic int 3426179337Syongarisysctl_hw_jme_tx_coal_to(SYSCTL_HANDLER_ARGS) 3427179337Syongari{ 3428179337Syongari return (sysctl_int_range(oidp, arg1, arg2, req, 3429179337Syongari PCCTX_COAL_TO_MIN, PCCTX_COAL_TO_MAX)); 3430179337Syongari} 3431179337Syongari 3432179337Syongaristatic int 3433179337Syongarisysctl_hw_jme_tx_coal_pkt(SYSCTL_HANDLER_ARGS) 3434179337Syongari{ 3435179337Syongari return (sysctl_int_range(oidp, arg1, arg2, req, 3436179337Syongari PCCTX_COAL_PKT_MIN, PCCTX_COAL_PKT_MAX)); 3437179337Syongari} 3438179337Syongari 3439179337Syongaristatic int 3440179337Syongarisysctl_hw_jme_rx_coal_to(SYSCTL_HANDLER_ARGS) 3441179337Syongari{ 3442179337Syongari return (sysctl_int_range(oidp, arg1, arg2, req, 3443179337Syongari PCCRX_COAL_TO_MIN, PCCRX_COAL_TO_MAX)); 3444179337Syongari} 3445179337Syongari 3446179337Syongaristatic int 3447179337Syongarisysctl_hw_jme_rx_coal_pkt(SYSCTL_HANDLER_ARGS) 3448179337Syongari{ 3449179337Syongari return (sysctl_int_range(oidp, arg1, arg2, req, 3450179337Syongari PCCRX_COAL_PKT_MIN, PCCRX_COAL_PKT_MAX)); 3451179337Syongari} 3452179337Syongari 3453179337Syongaristatic int 3454179337Syongarisysctl_hw_jme_proc_limit(SYSCTL_HANDLER_ARGS) 3455179337Syongari{ 3456179337Syongari return (sysctl_int_range(oidp, arg1, arg2, req, 3457179337Syongari JME_PROC_MIN, JME_PROC_MAX)); 3458179337Syongari} 3459