ixgbe_common.c revision 205720
1/****************************************************************************** 2 3 Copyright (c) 2001-2010, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_common.c 205720 2010-03-27 00:21:40Z jfv $*/ 34 35#include "ixgbe_common.h" 36#include "ixgbe_api.h" 37 38static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 39static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 40static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 41static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); 42static void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 43static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 44 u16 count); 45static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 46static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 47static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 48static void ixgbe_release_eeprom(struct ixgbe_hw *hw); 49 50static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 51static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 52 u16 *san_mac_offset); 53s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan); 54 55/** 56 * ixgbe_init_ops_generic - Inits function ptrs 57 * @hw: pointer to the hardware structure 58 * 59 * Initialize the function pointers. 60 **/ 61s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw) 62{ 63 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 64 struct ixgbe_mac_info *mac = &hw->mac; 65 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 66 67 DEBUGFUNC("ixgbe_init_ops_generic"); 68 69 /* EEPROM */ 70 eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic; 71 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */ 72 if (eec & (1 << 8)) 73 eeprom->ops.read = &ixgbe_read_eerd_generic; 74 else 75 eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic; 76 eeprom->ops.write = &ixgbe_write_eeprom_generic; 77 eeprom->ops.validate_checksum = 78 &ixgbe_validate_eeprom_checksum_generic; 79 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic; 80 eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_generic; 81 82 /* MAC */ 83 mac->ops.init_hw = &ixgbe_init_hw_generic; 84 mac->ops.reset_hw = NULL; 85 mac->ops.start_hw = &ixgbe_start_hw_generic; 86 mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic; 87 mac->ops.get_media_type = NULL; 88 mac->ops.get_supported_physical_layer = NULL; 89 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_generic; 90 mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic; 91 mac->ops.stop_adapter = &ixgbe_stop_adapter_generic; 92 mac->ops.get_bus_info = &ixgbe_get_bus_info_generic; 93 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie; 94 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync; 95 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync; 96 97 /* LEDs */ 98 mac->ops.led_on = &ixgbe_led_on_generic; 99 mac->ops.led_off = &ixgbe_led_off_generic; 100 mac->ops.blink_led_start = &ixgbe_blink_led_start_generic; 101 mac->ops.blink_led_stop = &ixgbe_blink_led_stop_generic; 102 103 /* RAR, Multicast, VLAN */ 104 mac->ops.set_rar = &ixgbe_set_rar_generic; 105 mac->ops.clear_rar = &ixgbe_clear_rar_generic; 106 mac->ops.insert_mac_addr = NULL; 107 mac->ops.set_vmdq = NULL; 108 mac->ops.clear_vmdq = NULL; 109 mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic; 110 mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic; 111 mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic; 112 mac->ops.enable_mc = &ixgbe_enable_mc_generic; 113 mac->ops.disable_mc = &ixgbe_disable_mc_generic; 114 mac->ops.clear_vfta = NULL; 115 mac->ops.set_vfta = NULL; 116 mac->ops.init_uta_tables = NULL; 117 118 /* Flow Control */ 119 mac->ops.fc_enable = &ixgbe_fc_enable_generic; 120 121 /* Link */ 122 mac->ops.get_link_capabilities = NULL; 123 mac->ops.setup_link = NULL; 124 mac->ops.check_link = NULL; 125 126 return IXGBE_SUCCESS; 127} 128 129/** 130 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 131 * @hw: pointer to hardware structure 132 * 133 * Starts the hardware by filling the bus info structure and media type, clears 134 * all on chip counters, initializes receive address registers, multicast 135 * table, VLAN filter table, calls routine to set up link and flow control 136 * settings, and leaves transmit and receive units disabled and uninitialized 137 **/ 138s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 139{ 140 u32 ctrl_ext; 141 s32 ret_val = IXGBE_SUCCESS; 142 143 DEBUGFUNC("ixgbe_start_hw_generic"); 144 145 /* Set the media type */ 146 hw->phy.media_type = hw->mac.ops.get_media_type(hw); 147 148 /* PHY ops initialization must be done in reset_hw() */ 149 150 /* Clear the VLAN filter table */ 151 hw->mac.ops.clear_vfta(hw); 152 153 /* Clear statistics registers */ 154 hw->mac.ops.clear_hw_cntrs(hw); 155 156 /* Set No Snoop Disable */ 157 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 158 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 159 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 160 IXGBE_WRITE_FLUSH(hw); 161 162 /* Setup flow control */ 163 ixgbe_setup_fc(hw, 0); 164 165 /* Clear adapter stopped flag */ 166 hw->adapter_stopped = FALSE; 167 168 return ret_val; 169} 170 171/** 172 * ixgbe_init_hw_generic - Generic hardware initialization 173 * @hw: pointer to hardware structure 174 * 175 * Initialize the hardware by resetting the hardware, filling the bus info 176 * structure and media type, clears all on chip counters, initializes receive 177 * address registers, multicast table, VLAN filter table, calls routine to set 178 * up link and flow control settings, and leaves transmit and receive units 179 * disabled and uninitialized 180 **/ 181s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) 182{ 183 s32 status = IXGBE_SUCCESS; 184 185 DEBUGFUNC("ixgbe_init_hw_generic"); 186 187 /* Reset the hardware */ 188 status = hw->mac.ops.reset_hw(hw); 189 190 if (status == IXGBE_SUCCESS) { 191 /* Start the HW */ 192 status = hw->mac.ops.start_hw(hw); 193 } 194 195 return status; 196} 197 198/** 199 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 200 * @hw: pointer to hardware structure 201 * 202 * Clears all hardware statistics counters by reading them from the hardware 203 * Statistics counters are clear on read. 204 **/ 205s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 206{ 207 u16 i = 0; 208 209 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic"); 210 211 IXGBE_READ_REG(hw, IXGBE_CRCERRS); 212 IXGBE_READ_REG(hw, IXGBE_ILLERRC); 213 IXGBE_READ_REG(hw, IXGBE_ERRBC); 214 IXGBE_READ_REG(hw, IXGBE_MSPDC); 215 for (i = 0; i < 8; i++) 216 IXGBE_READ_REG(hw, IXGBE_MPC(i)); 217 218 IXGBE_READ_REG(hw, IXGBE_MLFC); 219 IXGBE_READ_REG(hw, IXGBE_MRFC); 220 IXGBE_READ_REG(hw, IXGBE_RLEC); 221 IXGBE_READ_REG(hw, IXGBE_LXONTXC); 222 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 223 if (hw->mac.type >= ixgbe_mac_82599EB) { 224 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 225 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 226 } else { 227 IXGBE_READ_REG(hw, IXGBE_LXONRXC); 228 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 229 } 230 231 for (i = 0; i < 8; i++) { 232 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 233 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 234 if (hw->mac.type >= ixgbe_mac_82599EB) { 235 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 236 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 237 } else { 238 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 239 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 240 } 241 } 242 if (hw->mac.type >= ixgbe_mac_82599EB) 243 for (i = 0; i < 8; i++) 244 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 245 IXGBE_READ_REG(hw, IXGBE_PRC64); 246 IXGBE_READ_REG(hw, IXGBE_PRC127); 247 IXGBE_READ_REG(hw, IXGBE_PRC255); 248 IXGBE_READ_REG(hw, IXGBE_PRC511); 249 IXGBE_READ_REG(hw, IXGBE_PRC1023); 250 IXGBE_READ_REG(hw, IXGBE_PRC1522); 251 IXGBE_READ_REG(hw, IXGBE_GPRC); 252 IXGBE_READ_REG(hw, IXGBE_BPRC); 253 IXGBE_READ_REG(hw, IXGBE_MPRC); 254 IXGBE_READ_REG(hw, IXGBE_GPTC); 255 IXGBE_READ_REG(hw, IXGBE_GORCL); 256 IXGBE_READ_REG(hw, IXGBE_GORCH); 257 IXGBE_READ_REG(hw, IXGBE_GOTCL); 258 IXGBE_READ_REG(hw, IXGBE_GOTCH); 259 for (i = 0; i < 8; i++) 260 IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 261 IXGBE_READ_REG(hw, IXGBE_RUC); 262 IXGBE_READ_REG(hw, IXGBE_RFC); 263 IXGBE_READ_REG(hw, IXGBE_ROC); 264 IXGBE_READ_REG(hw, IXGBE_RJC); 265 IXGBE_READ_REG(hw, IXGBE_MNGPRC); 266 IXGBE_READ_REG(hw, IXGBE_MNGPDC); 267 IXGBE_READ_REG(hw, IXGBE_MNGPTC); 268 IXGBE_READ_REG(hw, IXGBE_TORL); 269 IXGBE_READ_REG(hw, IXGBE_TORH); 270 IXGBE_READ_REG(hw, IXGBE_TPR); 271 IXGBE_READ_REG(hw, IXGBE_TPT); 272 IXGBE_READ_REG(hw, IXGBE_PTC64); 273 IXGBE_READ_REG(hw, IXGBE_PTC127); 274 IXGBE_READ_REG(hw, IXGBE_PTC255); 275 IXGBE_READ_REG(hw, IXGBE_PTC511); 276 IXGBE_READ_REG(hw, IXGBE_PTC1023); 277 IXGBE_READ_REG(hw, IXGBE_PTC1522); 278 IXGBE_READ_REG(hw, IXGBE_MPTC); 279 IXGBE_READ_REG(hw, IXGBE_BPTC); 280 for (i = 0; i < 16; i++) { 281 IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 282 IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 283 IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 284 IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 285 } 286 287 return IXGBE_SUCCESS; 288} 289 290/** 291 * ixgbe_read_pba_num_generic - Reads part number from EEPROM 292 * @hw: pointer to hardware structure 293 * @pba_num: stores the part number from the EEPROM 294 * 295 * Reads the part number from the EEPROM. 296 **/ 297s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num) 298{ 299 s32 ret_val; 300 u16 data; 301 302 DEBUGFUNC("ixgbe_read_pba_num_generic"); 303 304 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 305 if (ret_val) { 306 DEBUGOUT("NVM Read Error\n"); 307 return ret_val; 308 } 309 *pba_num = (u32)(data << 16); 310 311 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data); 312 if (ret_val) { 313 DEBUGOUT("NVM Read Error\n"); 314 return ret_val; 315 } 316 *pba_num |= data; 317 318 return IXGBE_SUCCESS; 319} 320 321/** 322 * ixgbe_get_mac_addr_generic - Generic get MAC address 323 * @hw: pointer to hardware structure 324 * @mac_addr: Adapter MAC address 325 * 326 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 327 * A reset of the adapter must be performed prior to calling this function 328 * in order for the MAC address to have been loaded from the EEPROM into RAR0 329 **/ 330s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 331{ 332 u32 rar_high; 333 u32 rar_low; 334 u16 i; 335 336 DEBUGFUNC("ixgbe_get_mac_addr_generic"); 337 338 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 339 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 340 341 for (i = 0; i < 4; i++) 342 mac_addr[i] = (u8)(rar_low >> (i*8)); 343 344 for (i = 0; i < 2; i++) 345 mac_addr[i+4] = (u8)(rar_high >> (i*8)); 346 347 return IXGBE_SUCCESS; 348} 349 350/** 351 * ixgbe_get_bus_info_generic - Generic set PCI bus info 352 * @hw: pointer to hardware structure 353 * 354 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 355 **/ 356s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 357{ 358 struct ixgbe_mac_info *mac = &hw->mac; 359 u16 link_status; 360 361 DEBUGFUNC("ixgbe_get_bus_info_generic"); 362 363 hw->bus.type = ixgbe_bus_type_pci_express; 364 365 /* Get the negotiated link width and speed from PCI config space */ 366 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS); 367 368 switch (link_status & IXGBE_PCI_LINK_WIDTH) { 369 case IXGBE_PCI_LINK_WIDTH_1: 370 hw->bus.width = ixgbe_bus_width_pcie_x1; 371 break; 372 case IXGBE_PCI_LINK_WIDTH_2: 373 hw->bus.width = ixgbe_bus_width_pcie_x2; 374 break; 375 case IXGBE_PCI_LINK_WIDTH_4: 376 hw->bus.width = ixgbe_bus_width_pcie_x4; 377 break; 378 case IXGBE_PCI_LINK_WIDTH_8: 379 hw->bus.width = ixgbe_bus_width_pcie_x8; 380 break; 381 default: 382 hw->bus.width = ixgbe_bus_width_unknown; 383 break; 384 } 385 386 switch (link_status & IXGBE_PCI_LINK_SPEED) { 387 case IXGBE_PCI_LINK_SPEED_2500: 388 hw->bus.speed = ixgbe_bus_speed_2500; 389 break; 390 case IXGBE_PCI_LINK_SPEED_5000: 391 hw->bus.speed = ixgbe_bus_speed_5000; 392 break; 393 default: 394 hw->bus.speed = ixgbe_bus_speed_unknown; 395 break; 396 } 397 398 mac->ops.set_lan_id(hw); 399 400 return IXGBE_SUCCESS; 401} 402 403/** 404 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 405 * @hw: pointer to the HW structure 406 * 407 * Determines the LAN function id by reading memory-mapped registers 408 * and swaps the port value if requested. 409 **/ 410void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) 411{ 412 struct ixgbe_bus_info *bus = &hw->bus; 413 u32 reg; 414 415 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie"); 416 417 reg = IXGBE_READ_REG(hw, IXGBE_STATUS); 418 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; 419 bus->lan_id = bus->func; 420 421 /* check for a port swap */ 422 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS); 423 if (reg & IXGBE_FACTPS_LFS) 424 bus->func ^= 0x1; 425} 426 427/** 428 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 429 * @hw: pointer to hardware structure 430 * 431 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 432 * disables transmit and receive units. The adapter_stopped flag is used by 433 * the shared code and drivers to determine if the adapter is in a stopped 434 * state and should not touch the hardware. 435 **/ 436s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 437{ 438 u32 number_of_queues; 439 u32 reg_val; 440 u16 i; 441 442 DEBUGFUNC("ixgbe_stop_adapter_generic"); 443 444 /* 445 * Set the adapter_stopped flag so other driver functions stop touching 446 * the hardware 447 */ 448 hw->adapter_stopped = TRUE; 449 450 /* Disable the receive unit */ 451 reg_val = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 452 reg_val &= ~(IXGBE_RXCTRL_RXEN); 453 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_val); 454 IXGBE_WRITE_FLUSH(hw); 455 msec_delay(2); 456 457 /* Clear interrupt mask to stop from interrupts being generated */ 458 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 459 460 /* Clear any pending interrupts */ 461 IXGBE_READ_REG(hw, IXGBE_EICR); 462 463 /* Disable the transmit unit. Each queue must be disabled. */ 464 number_of_queues = hw->mac.max_tx_queues; 465 for (i = 0; i < number_of_queues; i++) { 466 reg_val = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i)); 467 if (reg_val & IXGBE_TXDCTL_ENABLE) { 468 reg_val &= ~IXGBE_TXDCTL_ENABLE; 469 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), reg_val); 470 } 471 } 472 473 /* 474 * Prevent the PCI-E bus from from hanging by disabling PCI-E master 475 * access and verify no pending requests 476 */ 477 ixgbe_disable_pcie_master(hw); 478 479 return IXGBE_SUCCESS; 480} 481 482/** 483 * ixgbe_led_on_generic - Turns on the software controllable LEDs. 484 * @hw: pointer to hardware structure 485 * @index: led number to turn on 486 **/ 487s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 488{ 489 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 490 491 DEBUGFUNC("ixgbe_led_on_generic"); 492 493 /* To turn on the LED, set mode to ON. */ 494 led_reg &= ~IXGBE_LED_MODE_MASK(index); 495 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 496 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 497 IXGBE_WRITE_FLUSH(hw); 498 499 return IXGBE_SUCCESS; 500} 501 502/** 503 * ixgbe_led_off_generic - Turns off the software controllable LEDs. 504 * @hw: pointer to hardware structure 505 * @index: led number to turn off 506 **/ 507s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 508{ 509 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 510 511 DEBUGFUNC("ixgbe_led_off_generic"); 512 513 /* To turn off the LED, set mode to OFF. */ 514 led_reg &= ~IXGBE_LED_MODE_MASK(index); 515 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 516 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 517 IXGBE_WRITE_FLUSH(hw); 518 519 return IXGBE_SUCCESS; 520} 521 522/** 523 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 524 * @hw: pointer to hardware structure 525 * 526 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 527 * ixgbe_hw struct in order to set up EEPROM access. 528 **/ 529s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 530{ 531 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 532 u32 eec; 533 u16 eeprom_size; 534 535 DEBUGFUNC("ixgbe_init_eeprom_params_generic"); 536 537 if (eeprom->type == ixgbe_eeprom_uninitialized) { 538 eeprom->type = ixgbe_eeprom_none; 539 /* Set default semaphore delay to 10ms which is a well 540 * tested value */ 541 eeprom->semaphore_delay = 10; 542 543 /* 544 * Check for EEPROM present first. 545 * If not present leave as none 546 */ 547 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 548 if (eec & IXGBE_EEC_PRES) { 549 eeprom->type = ixgbe_eeprom_spi; 550 551 /* 552 * SPI EEPROM is assumed here. This code would need to 553 * change if a future EEPROM is not SPI. 554 */ 555 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 556 IXGBE_EEC_SIZE_SHIFT); 557 eeprom->word_size = 1 << (eeprom_size + 558 IXGBE_EEPROM_WORD_SIZE_BASE_SHIFT); 559 } 560 561 if (eec & IXGBE_EEC_ADDR_SIZE) 562 eeprom->address_bits = 16; 563 else 564 eeprom->address_bits = 8; 565 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: " 566 "%d\n", eeprom->type, eeprom->word_size, 567 eeprom->address_bits); 568 } 569 570 return IXGBE_SUCCESS; 571} 572 573/** 574 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 575 * @hw: pointer to hardware structure 576 * @offset: offset within the EEPROM to be written to 577 * @data: 16 bit word to be written to the EEPROM 578 * 579 * If ixgbe_eeprom_update_checksum is not called after this function, the 580 * EEPROM will most likely contain an invalid checksum. 581 **/ 582s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 583{ 584 s32 status; 585 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 586 587 DEBUGFUNC("ixgbe_write_eeprom_generic"); 588 589 hw->eeprom.ops.init_params(hw); 590 591 if (offset >= hw->eeprom.word_size) { 592 status = IXGBE_ERR_EEPROM; 593 goto out; 594 } 595 596 /* Prepare the EEPROM for writing */ 597 status = ixgbe_acquire_eeprom(hw); 598 599 if (status == IXGBE_SUCCESS) { 600 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 601 ixgbe_release_eeprom(hw); 602 status = IXGBE_ERR_EEPROM; 603 } 604 } 605 606 if (status == IXGBE_SUCCESS) { 607 ixgbe_standby_eeprom(hw); 608 609 /* Send the WRITE ENABLE command (8 bit opcode ) */ 610 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_WREN_OPCODE_SPI, 611 IXGBE_EEPROM_OPCODE_BITS); 612 613 ixgbe_standby_eeprom(hw); 614 615 /* 616 * Some SPI eeproms use the 8th address bit embedded in the 617 * opcode 618 */ 619 if ((hw->eeprom.address_bits == 8) && (offset >= 128)) 620 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 621 622 /* Send the Write command (8-bit opcode + addr) */ 623 ixgbe_shift_out_eeprom_bits(hw, write_opcode, 624 IXGBE_EEPROM_OPCODE_BITS); 625 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2), 626 hw->eeprom.address_bits); 627 628 /* Send the data */ 629 data = (data >> 8) | (data << 8); 630 ixgbe_shift_out_eeprom_bits(hw, data, 16); 631 ixgbe_standby_eeprom(hw); 632 633 /* Done with writing - release the EEPROM */ 634 ixgbe_release_eeprom(hw); 635 } 636 637out: 638 return status; 639} 640 641/** 642 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 643 * @hw: pointer to hardware structure 644 * @offset: offset within the EEPROM to be read 645 * @data: read 16 bit value from EEPROM 646 * 647 * Reads 16 bit value from EEPROM through bit-bang method 648 **/ 649s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 650 u16 *data) 651{ 652 s32 status; 653 u16 word_in; 654 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 655 656 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic"); 657 658 hw->eeprom.ops.init_params(hw); 659 660 if (offset >= hw->eeprom.word_size) { 661 status = IXGBE_ERR_EEPROM; 662 goto out; 663 } 664 665 /* Prepare the EEPROM for reading */ 666 status = ixgbe_acquire_eeprom(hw); 667 668 if (status == IXGBE_SUCCESS) { 669 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 670 ixgbe_release_eeprom(hw); 671 status = IXGBE_ERR_EEPROM; 672 } 673 } 674 675 if (status == IXGBE_SUCCESS) { 676 ixgbe_standby_eeprom(hw); 677 678 /* 679 * Some SPI eeproms use the 8th address bit embedded in the 680 * opcode 681 */ 682 if ((hw->eeprom.address_bits == 8) && (offset >= 128)) 683 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 684 685 /* Send the READ command (opcode + addr) */ 686 ixgbe_shift_out_eeprom_bits(hw, read_opcode, 687 IXGBE_EEPROM_OPCODE_BITS); 688 ixgbe_shift_out_eeprom_bits(hw, (u16)(offset*2), 689 hw->eeprom.address_bits); 690 691 /* Read the data. */ 692 word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 693 *data = (word_in >> 8) | (word_in << 8); 694 695 /* End this read operation */ 696 ixgbe_release_eeprom(hw); 697 } 698 699out: 700 return status; 701} 702 703/** 704 * ixgbe_read_eerd_generic - Read EEPROM word using EERD 705 * @hw: pointer to hardware structure 706 * @offset: offset of word in the EEPROM to read 707 * @data: word read from the EEPROM 708 * 709 * Reads a 16 bit word from the EEPROM using the EERD register. 710 **/ 711s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 712{ 713 u32 eerd; 714 s32 status; 715 716 DEBUGFUNC("ixgbe_read_eerd_generic"); 717 718 hw->eeprom.ops.init_params(hw); 719 720 if (offset >= hw->eeprom.word_size) { 721 status = IXGBE_ERR_EEPROM; 722 goto out; 723 } 724 725 eerd = (offset << IXGBE_EEPROM_RW_ADDR_SHIFT) + 726 IXGBE_EEPROM_RW_REG_START; 727 728 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 729 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); 730 731 if (status == IXGBE_SUCCESS) 732 *data = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 733 IXGBE_EEPROM_RW_REG_DATA); 734 else 735 DEBUGOUT("Eeprom read timed out\n"); 736 737out: 738 return status; 739} 740 741/** 742 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status 743 * @hw: pointer to hardware structure 744 * @ee_reg: EEPROM flag for polling 745 * 746 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the 747 * read or write is done respectively. 748 **/ 749s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) 750{ 751 u32 i; 752 u32 reg; 753 s32 status = IXGBE_ERR_EEPROM; 754 755 DEBUGFUNC("ixgbe_poll_eerd_eewr_done"); 756 757 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) { 758 if (ee_reg == IXGBE_NVM_POLL_READ) 759 reg = IXGBE_READ_REG(hw, IXGBE_EERD); 760 else 761 reg = IXGBE_READ_REG(hw, IXGBE_EEWR); 762 763 if (reg & IXGBE_EEPROM_RW_REG_DONE) { 764 status = IXGBE_SUCCESS; 765 break; 766 } 767 usec_delay(5); 768 } 769 return status; 770} 771 772/** 773 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 774 * @hw: pointer to hardware structure 775 * 776 * Prepares EEPROM for access using bit-bang method. This function should 777 * be called before issuing a command to the EEPROM. 778 **/ 779static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 780{ 781 s32 status = IXGBE_SUCCESS; 782 u32 eec; 783 u32 i; 784 785 DEBUGFUNC("ixgbe_acquire_eeprom"); 786 787 if (ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != IXGBE_SUCCESS) 788 status = IXGBE_ERR_SWFW_SYNC; 789 790 if (status == IXGBE_SUCCESS) { 791 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 792 793 /* Request EEPROM Access */ 794 eec |= IXGBE_EEC_REQ; 795 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 796 797 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 798 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 799 if (eec & IXGBE_EEC_GNT) 800 break; 801 usec_delay(5); 802 } 803 804 /* Release if grant not acquired */ 805 if (!(eec & IXGBE_EEC_GNT)) { 806 eec &= ~IXGBE_EEC_REQ; 807 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 808 DEBUGOUT("Could not acquire EEPROM grant\n"); 809 810 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 811 status = IXGBE_ERR_EEPROM; 812 } 813 } 814 815 /* Setup EEPROM for Read/Write */ 816 if (status == IXGBE_SUCCESS) { 817 /* Clear CS and SK */ 818 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 819 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 820 IXGBE_WRITE_FLUSH(hw); 821 usec_delay(1); 822 } 823 return status; 824} 825 826/** 827 * ixgbe_get_eeprom_semaphore - Get hardware semaphore 828 * @hw: pointer to hardware structure 829 * 830 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 831 **/ 832static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 833{ 834 s32 status = IXGBE_ERR_EEPROM; 835 u32 timeout = 2000; 836 u32 i; 837 u32 swsm; 838 839 DEBUGFUNC("ixgbe_get_eeprom_semaphore"); 840 841 /* Get SMBI software semaphore between device drivers first */ 842 for (i = 0; i < timeout; i++) { 843 /* 844 * If the SMBI bit is 0 when we read it, then the bit will be 845 * set and we have the semaphore 846 */ 847 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 848 if (!(swsm & IXGBE_SWSM_SMBI)) { 849 status = IXGBE_SUCCESS; 850 break; 851 } 852 usec_delay(50); 853 } 854 855 /* Now get the semaphore between SW/FW through the SWESMBI bit */ 856 if (status == IXGBE_SUCCESS) { 857 for (i = 0; i < timeout; i++) { 858 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 859 860 /* Set the SW EEPROM semaphore bit to request access */ 861 swsm |= IXGBE_SWSM_SWESMBI; 862 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 863 864 /* 865 * If we set the bit successfully then we got the 866 * semaphore. 867 */ 868 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 869 if (swsm & IXGBE_SWSM_SWESMBI) 870 break; 871 872 usec_delay(50); 873 } 874 875 /* 876 * Release semaphores and return error if SW EEPROM semaphore 877 * was not granted because we don't have access to the EEPROM 878 */ 879 if (i >= timeout) { 880 DEBUGOUT("SWESMBI Software EEPROM semaphore " 881 "not granted.\n"); 882 ixgbe_release_eeprom_semaphore(hw); 883 status = IXGBE_ERR_EEPROM; 884 } 885 } else { 886 DEBUGOUT("Software semaphore SMBI between device drivers " 887 "not granted.\n"); 888 } 889 890 return status; 891} 892 893/** 894 * ixgbe_release_eeprom_semaphore - Release hardware semaphore 895 * @hw: pointer to hardware structure 896 * 897 * This function clears hardware semaphore bits. 898 **/ 899static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 900{ 901 u32 swsm; 902 903 DEBUGFUNC("ixgbe_release_eeprom_semaphore"); 904 905 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 906 907 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 908 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 909 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 910 IXGBE_WRITE_FLUSH(hw); 911} 912 913/** 914 * ixgbe_ready_eeprom - Polls for EEPROM ready 915 * @hw: pointer to hardware structure 916 **/ 917static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) 918{ 919 s32 status = IXGBE_SUCCESS; 920 u16 i; 921 u8 spi_stat_reg; 922 923 DEBUGFUNC("ixgbe_ready_eeprom"); 924 925 /* 926 * Read "Status Register" repeatedly until the LSB is cleared. The 927 * EEPROM will signal that the command has been completed by clearing 928 * bit 0 of the internal status register. If it's not cleared within 929 * 5 milliseconds, then error out. 930 */ 931 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 932 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 933 IXGBE_EEPROM_OPCODE_BITS); 934 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 935 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 936 break; 937 938 usec_delay(5); 939 ixgbe_standby_eeprom(hw); 940 }; 941 942 /* 943 * On some parts, SPI write time could vary from 0-20mSec on 3.3V 944 * devices (and only 0-5mSec on 5V devices) 945 */ 946 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 947 DEBUGOUT("SPI EEPROM Status error\n"); 948 status = IXGBE_ERR_EEPROM; 949 } 950 951 return status; 952} 953 954/** 955 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 956 * @hw: pointer to hardware structure 957 **/ 958static void ixgbe_standby_eeprom(struct ixgbe_hw *hw) 959{ 960 u32 eec; 961 962 DEBUGFUNC("ixgbe_standby_eeprom"); 963 964 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 965 966 /* Toggle CS to flush commands */ 967 eec |= IXGBE_EEC_CS; 968 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 969 IXGBE_WRITE_FLUSH(hw); 970 usec_delay(1); 971 eec &= ~IXGBE_EEC_CS; 972 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 973 IXGBE_WRITE_FLUSH(hw); 974 usec_delay(1); 975} 976 977/** 978 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 979 * @hw: pointer to hardware structure 980 * @data: data to send to the EEPROM 981 * @count: number of bits to shift out 982 **/ 983static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 984 u16 count) 985{ 986 u32 eec; 987 u32 mask; 988 u32 i; 989 990 DEBUGFUNC("ixgbe_shift_out_eeprom_bits"); 991 992 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 993 994 /* 995 * Mask is used to shift "count" bits of "data" out to the EEPROM 996 * one bit at a time. Determine the starting bit based on count 997 */ 998 mask = 0x01 << (count - 1); 999 1000 for (i = 0; i < count; i++) { 1001 /* 1002 * A "1" is shifted out to the EEPROM by setting bit "DI" to a 1003 * "1", and then raising and then lowering the clock (the SK 1004 * bit controls the clock input to the EEPROM). A "0" is 1005 * shifted out to the EEPROM by setting "DI" to "0" and then 1006 * raising and then lowering the clock. 1007 */ 1008 if (data & mask) 1009 eec |= IXGBE_EEC_DI; 1010 else 1011 eec &= ~IXGBE_EEC_DI; 1012 1013 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1014 IXGBE_WRITE_FLUSH(hw); 1015 1016 usec_delay(1); 1017 1018 ixgbe_raise_eeprom_clk(hw, &eec); 1019 ixgbe_lower_eeprom_clk(hw, &eec); 1020 1021 /* 1022 * Shift mask to signify next bit of data to shift in to the 1023 * EEPROM 1024 */ 1025 mask = mask >> 1; 1026 }; 1027 1028 /* We leave the "DI" bit set to "0" when we leave this routine. */ 1029 eec &= ~IXGBE_EEC_DI; 1030 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1031 IXGBE_WRITE_FLUSH(hw); 1032} 1033 1034/** 1035 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 1036 * @hw: pointer to hardware structure 1037 **/ 1038static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 1039{ 1040 u32 eec; 1041 u32 i; 1042 u16 data = 0; 1043 1044 DEBUGFUNC("ixgbe_shift_in_eeprom_bits"); 1045 1046 /* 1047 * In order to read a register from the EEPROM, we need to shift 1048 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 1049 * the clock input to the EEPROM (setting the SK bit), and then reading 1050 * the value of the "DO" bit. During this "shifting in" process the 1051 * "DI" bit should always be clear. 1052 */ 1053 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1054 1055 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 1056 1057 for (i = 0; i < count; i++) { 1058 data = data << 1; 1059 ixgbe_raise_eeprom_clk(hw, &eec); 1060 1061 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1062 1063 eec &= ~(IXGBE_EEC_DI); 1064 if (eec & IXGBE_EEC_DO) 1065 data |= 1; 1066 1067 ixgbe_lower_eeprom_clk(hw, &eec); 1068 } 1069 1070 return data; 1071} 1072 1073/** 1074 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 1075 * @hw: pointer to hardware structure 1076 * @eec: EEC register's current value 1077 **/ 1078static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1079{ 1080 DEBUGFUNC("ixgbe_raise_eeprom_clk"); 1081 1082 /* 1083 * Raise the clock input to the EEPROM 1084 * (setting the SK bit), then delay 1085 */ 1086 *eec = *eec | IXGBE_EEC_SK; 1087 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 1088 IXGBE_WRITE_FLUSH(hw); 1089 usec_delay(1); 1090} 1091 1092/** 1093 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 1094 * @hw: pointer to hardware structure 1095 * @eecd: EECD's current value 1096 **/ 1097static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 1098{ 1099 DEBUGFUNC("ixgbe_lower_eeprom_clk"); 1100 1101 /* 1102 * Lower the clock input to the EEPROM (clearing the SK bit), then 1103 * delay 1104 */ 1105 *eec = *eec & ~IXGBE_EEC_SK; 1106 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 1107 IXGBE_WRITE_FLUSH(hw); 1108 usec_delay(1); 1109} 1110 1111/** 1112 * ixgbe_release_eeprom - Release EEPROM, release semaphores 1113 * @hw: pointer to hardware structure 1114 **/ 1115static void ixgbe_release_eeprom(struct ixgbe_hw *hw) 1116{ 1117 u32 eec; 1118 1119 DEBUGFUNC("ixgbe_release_eeprom"); 1120 1121 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1122 1123 eec |= IXGBE_EEC_CS; /* Pull CS high */ 1124 eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 1125 1126 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1127 IXGBE_WRITE_FLUSH(hw); 1128 1129 usec_delay(1); 1130 1131 /* Stop requesting EEPROM access */ 1132 eec &= ~IXGBE_EEC_REQ; 1133 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1134 1135 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1136 1137 /* Delay before attempt to obtain semaphore again to allow FW access */ 1138 msec_delay(hw->eeprom.semaphore_delay); 1139} 1140 1141/** 1142 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum 1143 * @hw: pointer to hardware structure 1144 **/ 1145u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) 1146{ 1147 u16 i; 1148 u16 j; 1149 u16 checksum = 0; 1150 u16 length = 0; 1151 u16 pointer = 0; 1152 u16 word = 0; 1153 1154 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic"); 1155 1156 /* Include 0x0-0x3F in the checksum */ 1157 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 1158 if (hw->eeprom.ops.read(hw, i, &word) != IXGBE_SUCCESS) { 1159 DEBUGOUT("EEPROM read failed\n"); 1160 break; 1161 } 1162 checksum += word; 1163 } 1164 1165 /* Include all data from pointers except for the fw pointer */ 1166 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 1167 hw->eeprom.ops.read(hw, i, &pointer); 1168 1169 /* Make sure the pointer seems valid */ 1170 if (pointer != 0xFFFF && pointer != 0) { 1171 hw->eeprom.ops.read(hw, pointer, &length); 1172 1173 if (length != 0xFFFF && length != 0) { 1174 for (j = pointer+1; j <= pointer+length; j++) { 1175 hw->eeprom.ops.read(hw, j, &word); 1176 checksum += word; 1177 } 1178 } 1179 } 1180 } 1181 1182 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 1183 1184 return checksum; 1185} 1186 1187/** 1188 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 1189 * @hw: pointer to hardware structure 1190 * @checksum_val: calculated checksum 1191 * 1192 * Performs checksum calculation and validates the EEPROM checksum. If the 1193 * caller does not need checksum_val, the value can be NULL. 1194 **/ 1195s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 1196 u16 *checksum_val) 1197{ 1198 s32 status; 1199 u16 checksum; 1200 u16 read_checksum = 0; 1201 1202 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic"); 1203 1204 /* 1205 * Read the first word from the EEPROM. If this times out or fails, do 1206 * not continue or we could be in for a very long wait while every 1207 * EEPROM read fails 1208 */ 1209 status = hw->eeprom.ops.read(hw, 0, &checksum); 1210 1211 if (status == IXGBE_SUCCESS) { 1212 checksum = hw->eeprom.ops.calc_checksum(hw); 1213 1214 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 1215 1216 /* 1217 * Verify read checksum from EEPROM is the same as 1218 * calculated checksum 1219 */ 1220 if (read_checksum != checksum) 1221 status = IXGBE_ERR_EEPROM_CHECKSUM; 1222 1223 /* If the user cares, return the calculated checksum */ 1224 if (checksum_val) 1225 *checksum_val = checksum; 1226 } else { 1227 DEBUGOUT("EEPROM read failed\n"); 1228 } 1229 1230 return status; 1231} 1232 1233/** 1234 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 1235 * @hw: pointer to hardware structure 1236 **/ 1237s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 1238{ 1239 s32 status; 1240 u16 checksum; 1241 1242 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic"); 1243 1244 /* 1245 * Read the first word from the EEPROM. If this times out or fails, do 1246 * not continue or we could be in for a very long wait while every 1247 * EEPROM read fails 1248 */ 1249 status = hw->eeprom.ops.read(hw, 0, &checksum); 1250 1251 if (status == IXGBE_SUCCESS) { 1252 checksum = hw->eeprom.ops.calc_checksum(hw); 1253 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, 1254 checksum); 1255 } else { 1256 DEBUGOUT("EEPROM read failed\n"); 1257 } 1258 1259 return status; 1260} 1261 1262/** 1263 * ixgbe_validate_mac_addr - Validate MAC address 1264 * @mac_addr: pointer to MAC address. 1265 * 1266 * Tests a MAC address to ensure it is a valid Individual Address 1267 **/ 1268s32 ixgbe_validate_mac_addr(u8 *mac_addr) 1269{ 1270 s32 status = IXGBE_SUCCESS; 1271 1272 DEBUGFUNC("ixgbe_validate_mac_addr"); 1273 1274 /* Make sure it is not a multicast address */ 1275 if (IXGBE_IS_MULTICAST(mac_addr)) { 1276 DEBUGOUT("MAC address is multicast\n"); 1277 status = IXGBE_ERR_INVALID_MAC_ADDR; 1278 /* Not a broadcast address */ 1279 } else if (IXGBE_IS_BROADCAST(mac_addr)) { 1280 DEBUGOUT("MAC address is broadcast\n"); 1281 status = IXGBE_ERR_INVALID_MAC_ADDR; 1282 /* Reject the zero address */ 1283 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 1284 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) { 1285 DEBUGOUT("MAC address is all zeros\n"); 1286 status = IXGBE_ERR_INVALID_MAC_ADDR; 1287 } 1288 return status; 1289} 1290 1291/** 1292 * ixgbe_set_rar_generic - Set Rx address register 1293 * @hw: pointer to hardware structure 1294 * @index: Receive address register to write 1295 * @addr: Address to put into receive address register 1296 * @vmdq: VMDq "set" or "pool" index 1297 * @enable_addr: set flag that address is active 1298 * 1299 * Puts an ethernet address into a receive address register. 1300 **/ 1301s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 1302 u32 enable_addr) 1303{ 1304 u32 rar_low, rar_high; 1305 u32 rar_entries = hw->mac.num_rar_entries; 1306 1307 DEBUGFUNC("ixgbe_set_rar_generic"); 1308 1309 /* setup VMDq pool selection before this RAR gets enabled */ 1310 hw->mac.ops.set_vmdq(hw, index, vmdq); 1311 1312 /* Make sure we are using a valid rar index range */ 1313 if (index < rar_entries) { 1314 /* 1315 * HW expects these in little endian so we reverse the byte 1316 * order from network order (big endian) to little endian 1317 */ 1318 rar_low = ((u32)addr[0] | 1319 ((u32)addr[1] << 8) | 1320 ((u32)addr[2] << 16) | 1321 ((u32)addr[3] << 24)); 1322 /* 1323 * Some parts put the VMDq setting in the extra RAH bits, 1324 * so save everything except the lower 16 bits that hold part 1325 * of the address and the address valid bit. 1326 */ 1327 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1328 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1329 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); 1330 1331 if (enable_addr != 0) 1332 rar_high |= IXGBE_RAH_AV; 1333 1334 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 1335 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1336 } else { 1337 DEBUGOUT1("RAR index %d is out of range.\n", index); 1338 } 1339 1340 return IXGBE_SUCCESS; 1341} 1342 1343/** 1344 * ixgbe_clear_rar_generic - Remove Rx address register 1345 * @hw: pointer to hardware structure 1346 * @index: Receive address register to write 1347 * 1348 * Clears an ethernet address from a receive address register. 1349 **/ 1350s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) 1351{ 1352 u32 rar_high; 1353 u32 rar_entries = hw->mac.num_rar_entries; 1354 1355 DEBUGFUNC("ixgbe_clear_rar_generic"); 1356 1357 /* Make sure we are using a valid rar index range */ 1358 if (index < rar_entries) { 1359 /* 1360 * Some parts put the VMDq setting in the extra RAH bits, 1361 * so save everything except the lower 16 bits that hold part 1362 * of the address and the address valid bit. 1363 */ 1364 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 1365 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 1366 1367 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); 1368 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 1369 } else { 1370 DEBUGOUT1("RAR index %d is out of range.\n", index); 1371 } 1372 1373 /* clear VMDq pool/queue selection for this RAR */ 1374 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); 1375 1376 return IXGBE_SUCCESS; 1377} 1378 1379/** 1380 * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 1381 * @hw: pointer to hardware structure 1382 * 1383 * Places the MAC address in receive address register 0 and clears the rest 1384 * of the receive address registers. Clears the multicast table. Assumes 1385 * the receiver is in reset when the routine is called. 1386 **/ 1387s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 1388{ 1389 u32 i; 1390 u32 rar_entries = hw->mac.num_rar_entries; 1391 1392 DEBUGFUNC("ixgbe_init_rx_addrs_generic"); 1393 1394 /* 1395 * If the current mac address is valid, assume it is a software override 1396 * to the permanent address. 1397 * Otherwise, use the permanent address from the eeprom. 1398 */ 1399 if (ixgbe_validate_mac_addr(hw->mac.addr) == 1400 IXGBE_ERR_INVALID_MAC_ADDR) { 1401 /* Get the MAC address from the RAR0 for later reference */ 1402 hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 1403 1404 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ", 1405 hw->mac.addr[0], hw->mac.addr[1], 1406 hw->mac.addr[2]); 1407 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 1408 hw->mac.addr[4], hw->mac.addr[5]); 1409 } else { 1410 /* Setup the receive address. */ 1411 DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 1412 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 1413 hw->mac.addr[0], hw->mac.addr[1], 1414 hw->mac.addr[2]); 1415 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 1416 hw->mac.addr[4], hw->mac.addr[5]); 1417 1418 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 1419 } 1420 hw->addr_ctrl.overflow_promisc = 0; 1421 1422 hw->addr_ctrl.rar_used_count = 1; 1423 1424 /* Zero out the other receive addresses. */ 1425 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1); 1426 for (i = 1; i < rar_entries; i++) { 1427 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 1428 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 1429 } 1430 1431 /* Clear the MTA */ 1432 hw->addr_ctrl.mta_in_use = 0; 1433 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1434 1435 DEBUGOUT(" Clearing MTA\n"); 1436 for (i = 0; i < hw->mac.mcft_size; i++) 1437 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 1438 1439 ixgbe_init_uta_tables(hw); 1440 1441 return IXGBE_SUCCESS; 1442} 1443 1444/** 1445 * ixgbe_add_uc_addr - Adds a secondary unicast address. 1446 * @hw: pointer to hardware structure 1447 * @addr: new address 1448 * 1449 * Adds it to unused receive address register or goes into promiscuous mode. 1450 **/ 1451void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 1452{ 1453 u32 rar_entries = hw->mac.num_rar_entries; 1454 u32 rar; 1455 1456 DEBUGFUNC("ixgbe_add_uc_addr"); 1457 1458 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n", 1459 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); 1460 1461 /* 1462 * Place this address in the RAR if there is room, 1463 * else put the controller into promiscuous mode 1464 */ 1465 if (hw->addr_ctrl.rar_used_count < rar_entries) { 1466 rar = hw->addr_ctrl.rar_used_count; 1467 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 1468 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar); 1469 hw->addr_ctrl.rar_used_count++; 1470 } else { 1471 hw->addr_ctrl.overflow_promisc++; 1472 } 1473 1474 DEBUGOUT("ixgbe_add_uc_addr Complete\n"); 1475} 1476 1477/** 1478 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses 1479 * @hw: pointer to hardware structure 1480 * @addr_list: the list of new addresses 1481 * @addr_count: number of addresses 1482 * @next: iterator function to walk the address list 1483 * 1484 * The given list replaces any existing list. Clears the secondary addrs from 1485 * receive address registers. Uses unused receive address registers for the 1486 * first secondary addresses, and falls back to promiscuous mode as needed. 1487 * 1488 * Drivers using secondary unicast addresses must set user_set_promisc when 1489 * manually putting the device into promiscuous mode. 1490 **/ 1491s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, 1492 u32 addr_count, ixgbe_mc_addr_itr next) 1493{ 1494 u8 *addr; 1495 u32 i; 1496 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc; 1497 u32 uc_addr_in_use; 1498 u32 fctrl; 1499 u32 vmdq; 1500 1501 DEBUGFUNC("ixgbe_update_uc_addr_list_generic"); 1502 1503 /* 1504 * Clear accounting of old secondary address list, 1505 * don't count RAR[0] 1506 */ 1507 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1; 1508 hw->addr_ctrl.rar_used_count -= uc_addr_in_use; 1509 hw->addr_ctrl.overflow_promisc = 0; 1510 1511 /* Zero out the other receive addresses */ 1512 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1); 1513 for (i = 0; i < uc_addr_in_use; i++) { 1514 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0); 1515 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0); 1516 } 1517 1518 /* Add the new addresses */ 1519 for (i = 0; i < addr_count; i++) { 1520 DEBUGOUT(" Adding the secondary addresses:\n"); 1521 addr = next(hw, &addr_list, &vmdq); 1522 ixgbe_add_uc_addr(hw, addr, vmdq); 1523 } 1524 1525 if (hw->addr_ctrl.overflow_promisc) { 1526 /* enable promisc if not already in overflow or set by user */ 1527 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 1528 DEBUGOUT(" Entering address overflow promisc mode\n"); 1529 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1530 fctrl |= IXGBE_FCTRL_UPE; 1531 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 1532 } 1533 } else { 1534 /* only disable if set by overflow, not by user */ 1535 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 1536 DEBUGOUT(" Leaving address overflow promisc mode\n"); 1537 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 1538 fctrl &= ~IXGBE_FCTRL_UPE; 1539 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 1540 } 1541 } 1542 1543 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n"); 1544 return IXGBE_SUCCESS; 1545} 1546 1547/** 1548 * ixgbe_mta_vector - Determines bit-vector in multicast table to set 1549 * @hw: pointer to hardware structure 1550 * @mc_addr: the multicast address 1551 * 1552 * Extracts the 12 bits, from a multicast address, to determine which 1553 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 1554 * incoming rx multicast addresses, to determine the bit-vector to check in 1555 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 1556 * by the MO field of the MCSTCTRL. The MO field is set during initialization 1557 * to mc_filter_type. 1558 **/ 1559static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 1560{ 1561 u32 vector = 0; 1562 1563 DEBUGFUNC("ixgbe_mta_vector"); 1564 1565 switch (hw->mac.mc_filter_type) { 1566 case 0: /* use bits [47:36] of the address */ 1567 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 1568 break; 1569 case 1: /* use bits [46:35] of the address */ 1570 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 1571 break; 1572 case 2: /* use bits [45:34] of the address */ 1573 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 1574 break; 1575 case 3: /* use bits [43:32] of the address */ 1576 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 1577 break; 1578 default: /* Invalid mc_filter_type */ 1579 DEBUGOUT("MC filter type param set incorrectly\n"); 1580 ASSERT(0); 1581 break; 1582 } 1583 1584 /* vector can only be 12-bits or boundary will be exceeded */ 1585 vector &= 0xFFF; 1586 return vector; 1587} 1588 1589/** 1590 * ixgbe_set_mta - Set bit-vector in multicast table 1591 * @hw: pointer to hardware structure 1592 * @hash_value: Multicast address hash value 1593 * 1594 * Sets the bit-vector in the multicast table. 1595 **/ 1596void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 1597{ 1598 u32 vector; 1599 u32 vector_bit; 1600 u32 vector_reg; 1601 u32 mta_reg; 1602 1603 DEBUGFUNC("ixgbe_set_mta"); 1604 1605 hw->addr_ctrl.mta_in_use++; 1606 1607 vector = ixgbe_mta_vector(hw, mc_addr); 1608 DEBUGOUT1(" bit-vector = 0x%03X\n", vector); 1609 1610 /* 1611 * The MTA is a register array of 128 32-bit registers. It is treated 1612 * like an array of 4096 bits. We want to set bit 1613 * BitArray[vector_value]. So we figure out what register the bit is 1614 * in, read it, OR in the new bit, then write back the new value. The 1615 * register is determined by the upper 7 bits of the vector value and 1616 * the bit within that register are determined by the lower 5 bits of 1617 * the value. 1618 */ 1619 vector_reg = (vector >> 5) & 0x7F; 1620 vector_bit = vector & 0x1F; 1621 mta_reg = IXGBE_READ_REG(hw, IXGBE_MTA(vector_reg)); 1622 mta_reg |= (1 << vector_bit); 1623 IXGBE_WRITE_REG(hw, IXGBE_MTA(vector_reg), mta_reg); 1624} 1625 1626/** 1627 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 1628 * @hw: pointer to hardware structure 1629 * @mc_addr_list: the list of new multicast addresses 1630 * @mc_addr_count: number of addresses 1631 * @next: iterator function to walk the multicast address list 1632 * 1633 * The given list replaces any existing list. Clears the MC addrs from receive 1634 * address registers and the multicast table. Uses unused receive address 1635 * registers for the first multicast addresses, and hashes the rest into the 1636 * multicast table. 1637 **/ 1638s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, 1639 u32 mc_addr_count, ixgbe_mc_addr_itr next) 1640{ 1641 u32 i; 1642 u32 vmdq; 1643 1644 DEBUGFUNC("ixgbe_update_mc_addr_list_generic"); 1645 1646 /* 1647 * Set the new number of MC addresses that we are being requested to 1648 * use. 1649 */ 1650 hw->addr_ctrl.num_mc_addrs = mc_addr_count; 1651 hw->addr_ctrl.mta_in_use = 0; 1652 1653 /* Clear the MTA */ 1654 DEBUGOUT(" Clearing MTA\n"); 1655 for (i = 0; i < hw->mac.mcft_size; i++) 1656 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 1657 1658 /* Add the new addresses */ 1659 for (i = 0; i < mc_addr_count; i++) { 1660 DEBUGOUT(" Adding the multicast addresses:\n"); 1661 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq)); 1662 } 1663 1664 /* Enable mta */ 1665 if (hw->addr_ctrl.mta_in_use > 0) 1666 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 1667 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 1668 1669 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n"); 1670 return IXGBE_SUCCESS; 1671} 1672 1673/** 1674 * ixgbe_enable_mc_generic - Enable multicast address in RAR 1675 * @hw: pointer to hardware structure 1676 * 1677 * Enables multicast address in RAR and the use of the multicast hash table. 1678 **/ 1679s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 1680{ 1681 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 1682 1683 DEBUGFUNC("ixgbe_enable_mc_generic"); 1684 1685 if (a->mta_in_use > 0) 1686 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 1687 hw->mac.mc_filter_type); 1688 1689 return IXGBE_SUCCESS; 1690} 1691 1692/** 1693 * ixgbe_disable_mc_generic - Disable multicast address in RAR 1694 * @hw: pointer to hardware structure 1695 * 1696 * Disables multicast address in RAR and the use of the multicast hash table. 1697 **/ 1698s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 1699{ 1700 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 1701 1702 DEBUGFUNC("ixgbe_disable_mc_generic"); 1703 1704 if (a->mta_in_use > 0) 1705 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 1706 1707 return IXGBE_SUCCESS; 1708} 1709 1710/** 1711 * ixgbe_fc_enable_generic - Enable flow control 1712 * @hw: pointer to hardware structure 1713 * @packetbuf_num: packet buffer number (0-7) 1714 * 1715 * Enable flow control according to the current settings. 1716 **/ 1717s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw, s32 packetbuf_num) 1718{ 1719 s32 ret_val = IXGBE_SUCCESS; 1720 u32 mflcn_reg, fccfg_reg; 1721 u32 reg; 1722 u32 rx_pba_size; 1723 1724 DEBUGFUNC("ixgbe_fc_enable_generic"); 1725 1726 /* Negotiate the fc mode to use */ 1727 ret_val = ixgbe_fc_autoneg(hw); 1728 if (ret_val) 1729 goto out; 1730 1731 /* Disable any previous flow control settings */ 1732 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 1733 mflcn_reg &= ~(IXGBE_MFLCN_RFCE | IXGBE_MFLCN_RPFCE); 1734 1735 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 1736 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 1737 1738 /* 1739 * The possible values of fc.current_mode are: 1740 * 0: Flow control is completely disabled 1741 * 1: Rx flow control is enabled (we can receive pause frames, 1742 * but not send pause frames). 1743 * 2: Tx flow control is enabled (we can send pause frames but 1744 * we do not support receiving pause frames). 1745 * 3: Both Rx and Tx flow control (symmetric) are enabled. 1746 * other: Invalid. 1747 */ 1748 switch (hw->fc.current_mode) { 1749 case ixgbe_fc_none: 1750 /* Flow control is disabled by software override or autoneg. 1751 * The code below will actually disable it in the HW. 1752 */ 1753 break; 1754 case ixgbe_fc_rx_pause: 1755 /* 1756 * Rx Flow control is enabled and Tx Flow control is 1757 * disabled by software override. Since there really 1758 * isn't a way to advertise that we are capable of RX 1759 * Pause ONLY, we will advertise that we support both 1760 * symmetric and asymmetric Rx PAUSE. Later, we will 1761 * disable the adapter's ability to send PAUSE frames. 1762 */ 1763 mflcn_reg |= IXGBE_MFLCN_RFCE; 1764 break; 1765 case ixgbe_fc_tx_pause: 1766 /* 1767 * Tx Flow control is enabled, and Rx Flow control is 1768 * disabled by software override. 1769 */ 1770 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 1771 break; 1772 case ixgbe_fc_full: 1773 /* Flow control (both Rx and Tx) is enabled by SW override. */ 1774 mflcn_reg |= IXGBE_MFLCN_RFCE; 1775 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 1776 break; 1777 default: 1778 DEBUGOUT("Flow control param set incorrectly\n"); 1779 ret_val = IXGBE_ERR_CONFIG; 1780 goto out; 1781 break; 1782 } 1783 1784 /* Set 802.3x based flow control settings. */ 1785 mflcn_reg |= IXGBE_MFLCN_DPF; 1786 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 1787 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 1788 1789 reg = IXGBE_READ_REG(hw, IXGBE_MTQC); 1790 /* Thresholds are different for link flow control when in DCB mode */ 1791 if (reg & IXGBE_MTQC_RT_ENA) { 1792 rx_pba_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(packetbuf_num)); 1793 1794 /* Always disable XON for LFC when in DCB mode */ 1795 reg = (rx_pba_size >> 5) & 0xFFE0; 1796 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(packetbuf_num), reg); 1797 1798 reg = (rx_pba_size >> 2) & 0xFFE0; 1799 if (hw->fc.current_mode & ixgbe_fc_tx_pause) 1800 reg |= IXGBE_FCRTH_FCEN; 1801 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), reg); 1802 } else { 1803 /* Set up and enable Rx high/low water mark thresholds, 1804 * enable XON. */ 1805 if (hw->fc.current_mode & ixgbe_fc_tx_pause) { 1806 if (hw->fc.send_xon) { 1807 IXGBE_WRITE_REG(hw, 1808 IXGBE_FCRTL_82599(packetbuf_num), 1809 (hw->fc.low_water | 1810 IXGBE_FCRTL_XONE)); 1811 } else { 1812 IXGBE_WRITE_REG(hw, 1813 IXGBE_FCRTL_82599(packetbuf_num), 1814 hw->fc.low_water); 1815 } 1816 1817 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(packetbuf_num), 1818 (hw->fc.high_water | IXGBE_FCRTH_FCEN)); 1819 } 1820 } 1821 1822 /* Configure pause time (2 TCs per register) */ 1823 reg = IXGBE_READ_REG(hw, IXGBE_FCTTV(packetbuf_num / 2)); 1824 if ((packetbuf_num & 1) == 0) 1825 reg = (reg & 0xFFFF0000) | hw->fc.pause_time; 1826 else 1827 reg = (reg & 0x0000FFFF) | (hw->fc.pause_time << 16); 1828 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(packetbuf_num / 2), reg); 1829 1830 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, (hw->fc.pause_time >> 1)); 1831 1832out: 1833 return ret_val; 1834} 1835 1836/** 1837 * ixgbe_fc_autoneg - Configure flow control 1838 * @hw: pointer to hardware structure 1839 * 1840 * Compares our advertised flow control capabilities to those advertised by 1841 * our link partner, and determines the proper flow control mode to use. 1842 **/ 1843s32 ixgbe_fc_autoneg(struct ixgbe_hw *hw) 1844{ 1845 s32 ret_val = IXGBE_SUCCESS; 1846 ixgbe_link_speed speed; 1847 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; 1848 u32 links2, anlp1_reg, autoc_reg, links; 1849 bool link_up; 1850 1851 DEBUGFUNC("ixgbe_fc_autoneg"); 1852 1853 /* 1854 * AN should have completed when the cable was plugged in. 1855 * Look for reasons to bail out. Bail out if: 1856 * - FC autoneg is disabled, or if 1857 * - link is not up. 1858 * 1859 * Since we're being called from an LSC, link is already known to be up. 1860 * So use link_up_wait_to_complete=FALSE. 1861 */ 1862 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 1863 1864 if (hw->fc.disable_fc_autoneg || (!link_up)) { 1865 hw->fc.fc_was_autonegged = FALSE; 1866 hw->fc.current_mode = hw->fc.requested_mode; 1867 goto out; 1868 } 1869 1870 /* 1871 * On backplane, bail out if 1872 * - backplane autoneg was not completed, or if 1873 * - we are 82599 and link partner is not AN enabled 1874 */ 1875 if (hw->phy.media_type == ixgbe_media_type_backplane) { 1876 links = IXGBE_READ_REG(hw, IXGBE_LINKS); 1877 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) { 1878 hw->fc.fc_was_autonegged = FALSE; 1879 hw->fc.current_mode = hw->fc.requested_mode; 1880 goto out; 1881 } 1882 1883 if (hw->mac.type == ixgbe_mac_82599EB) { 1884 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); 1885 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) { 1886 hw->fc.fc_was_autonegged = FALSE; 1887 hw->fc.current_mode = hw->fc.requested_mode; 1888 goto out; 1889 } 1890 } 1891 } 1892 1893 /* 1894 * On multispeed fiber at 1g, bail out if 1895 * - link is up but AN did not complete, or if 1896 * - link is up and AN completed but timed out 1897 */ 1898 if (hw->phy.multispeed_fiber && (speed == IXGBE_LINK_SPEED_1GB_FULL)) { 1899 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 1900 if (((linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || 1901 ((linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) { 1902 hw->fc.fc_was_autonegged = FALSE; 1903 hw->fc.current_mode = hw->fc.requested_mode; 1904 goto out; 1905 } 1906 } 1907 1908 /* 1909 * Bail out on 1910 * - copper or CX4 adapters 1911 * - fiber adapters running at 10gig 1912 */ 1913 if ((hw->phy.media_type == ixgbe_media_type_copper) || 1914 (hw->phy.media_type == ixgbe_media_type_cx4) || 1915 ((hw->phy.media_type == ixgbe_media_type_fiber) && 1916 (speed == IXGBE_LINK_SPEED_10GB_FULL))) { 1917 hw->fc.fc_was_autonegged = FALSE; 1918 hw->fc.current_mode = hw->fc.requested_mode; 1919 goto out; 1920 } 1921 1922 /* 1923 * Read the AN advertisement and LP ability registers and resolve 1924 * local flow control settings accordingly 1925 */ 1926 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) && 1927 (hw->phy.media_type != ixgbe_media_type_backplane)) { 1928 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 1929 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 1930 if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1931 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE)) { 1932 /* 1933 * Now we need to check if the user selected Rx ONLY 1934 * of pause frames. In this case, we had to advertise 1935 * FULL flow control because we could not advertise RX 1936 * ONLY. Hence, we must now check to see if we need to 1937 * turn OFF the TRANSMISSION of PAUSE frames. 1938 */ 1939 if (hw->fc.requested_mode == ixgbe_fc_full) { 1940 hw->fc.current_mode = ixgbe_fc_full; 1941 DEBUGOUT("Flow Control = FULL.\n"); 1942 } else { 1943 hw->fc.current_mode = ixgbe_fc_rx_pause; 1944 DEBUGOUT("Flow Control=RX PAUSE frames only\n"); 1945 } 1946 } else if (!(pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1947 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && 1948 (pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1949 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { 1950 hw->fc.current_mode = ixgbe_fc_tx_pause; 1951 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 1952 } else if ((pcs_anadv_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1953 (pcs_anadv_reg & IXGBE_PCS1GANA_ASM_PAUSE) && 1954 !(pcs_lpab_reg & IXGBE_PCS1GANA_SYM_PAUSE) && 1955 (pcs_lpab_reg & IXGBE_PCS1GANA_ASM_PAUSE)) { 1956 hw->fc.current_mode = ixgbe_fc_rx_pause; 1957 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 1958 } else { 1959 hw->fc.current_mode = ixgbe_fc_none; 1960 DEBUGOUT("Flow Control = NONE.\n"); 1961 } 1962 } 1963 1964 if (hw->phy.media_type == ixgbe_media_type_backplane) { 1965 /* 1966 * Read the 10g AN autoc and LP ability registers and resolve 1967 * local flow control settings accordingly 1968 */ 1969 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 1970 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 1971 1972 if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) && 1973 (anlp1_reg & IXGBE_ANLP1_SYM_PAUSE)) { 1974 /* 1975 * Now we need to check if the user selected Rx ONLY 1976 * of pause frames. In this case, we had to advertise 1977 * FULL flow control because we could not advertise RX 1978 * ONLY. Hence, we must now check to see if we need to 1979 * turn OFF the TRANSMISSION of PAUSE frames. 1980 */ 1981 if (hw->fc.requested_mode == ixgbe_fc_full) { 1982 hw->fc.current_mode = ixgbe_fc_full; 1983 DEBUGOUT("Flow Control = FULL.\n"); 1984 } else { 1985 hw->fc.current_mode = ixgbe_fc_rx_pause; 1986 DEBUGOUT("Flow Control=RX PAUSE frames only\n"); 1987 } 1988 } else if (!(autoc_reg & IXGBE_AUTOC_SYM_PAUSE) && 1989 (autoc_reg & IXGBE_AUTOC_ASM_PAUSE) && 1990 (anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) && 1991 (anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) { 1992 hw->fc.current_mode = ixgbe_fc_tx_pause; 1993 DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 1994 } else if ((autoc_reg & IXGBE_AUTOC_SYM_PAUSE) && 1995 (autoc_reg & IXGBE_AUTOC_ASM_PAUSE) && 1996 !(anlp1_reg & IXGBE_ANLP1_SYM_PAUSE) && 1997 (anlp1_reg & IXGBE_ANLP1_ASM_PAUSE)) { 1998 hw->fc.current_mode = ixgbe_fc_rx_pause; 1999 DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 2000 } else { 2001 hw->fc.current_mode = ixgbe_fc_none; 2002 DEBUGOUT("Flow Control = NONE.\n"); 2003 } 2004 } 2005 /* Record that current_mode is the result of a successful autoneg */ 2006 hw->fc.fc_was_autonegged = TRUE; 2007 2008out: 2009 return ret_val; 2010} 2011 2012/** 2013 * ixgbe_setup_fc - Set up flow control 2014 * @hw: pointer to hardware structure 2015 * 2016 * Called at init time to set up flow control. 2017 **/ 2018s32 ixgbe_setup_fc(struct ixgbe_hw *hw, s32 packetbuf_num) 2019{ 2020 s32 ret_val = IXGBE_SUCCESS; 2021 u32 reg; 2022 2023 DEBUGFUNC("ixgbe_setup_fc"); 2024 2025 2026 /* Validate the packetbuf configuration */ 2027 if (packetbuf_num < 0 || packetbuf_num > 7) { 2028 DEBUGOUT1("Invalid packet buffer number [%d], expected range is" 2029 " 0-7\n", packetbuf_num); 2030 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2031 goto out; 2032 } 2033 2034 /* 2035 * Validate the water mark configuration. Zero water marks are invalid 2036 * because it causes the controller to just blast out fc packets. 2037 */ 2038 if (!hw->fc.low_water || !hw->fc.high_water || !hw->fc.pause_time) { 2039 DEBUGOUT("Invalid water mark configuration\n"); 2040 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2041 goto out; 2042 } 2043 2044 /* 2045 * Validate the requested mode. Strict IEEE mode does not allow 2046 * ixgbe_fc_rx_pause because it will cause us to fail at UNH. 2047 */ 2048 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 2049 DEBUGOUT("ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 2050 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2051 goto out; 2052 } 2053 2054 /* 2055 * 10gig parts do not have a word in the EEPROM to determine the 2056 * default flow control setting, so we explicitly set it to full. 2057 */ 2058 if (hw->fc.requested_mode == ixgbe_fc_default) 2059 hw->fc.requested_mode = ixgbe_fc_full; 2060 2061 /* 2062 * Set up the 1G flow control advertisement registers so the HW will be 2063 * able to do fc autoneg once the cable is plugged in. If we end up 2064 * using 10g instead, this is harmless. 2065 */ 2066 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 2067 2068 /* 2069 * The possible values of fc.requested_mode are: 2070 * 0: Flow control is completely disabled 2071 * 1: Rx flow control is enabled (we can receive pause frames, 2072 * but not send pause frames). 2073 * 2: Tx flow control is enabled (we can send pause frames but 2074 * we do not support receiving pause frames). 2075 * 3: Both Rx and Tx flow control (symmetric) are enabled. 2076 * other: Invalid. 2077 */ 2078 switch (hw->fc.requested_mode) { 2079 case ixgbe_fc_none: 2080 /* Flow control completely disabled by software override. */ 2081 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 2082 break; 2083 case ixgbe_fc_rx_pause: 2084 /* 2085 * Rx Flow control is enabled and Tx Flow control is 2086 * disabled by software override. Since there really 2087 * isn't a way to advertise that we are capable of RX 2088 * Pause ONLY, we will advertise that we support both 2089 * symmetric and asymmetric Rx PAUSE. Later, we will 2090 * disable the adapter's ability to send PAUSE frames. 2091 */ 2092 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 2093 break; 2094 case ixgbe_fc_tx_pause: 2095 /* 2096 * Tx Flow control is enabled, and Rx Flow control is 2097 * disabled by software override. 2098 */ 2099 reg |= (IXGBE_PCS1GANA_ASM_PAUSE); 2100 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE); 2101 break; 2102 case ixgbe_fc_full: 2103 /* Flow control (both Rx and Tx) is enabled by SW override. */ 2104 reg |= (IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 2105 break; 2106 default: 2107 DEBUGOUT("Flow control param set incorrectly\n"); 2108 ret_val = IXGBE_ERR_CONFIG; 2109 goto out; 2110 break; 2111 } 2112 2113 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 2114 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 2115 2116 /* Disable AN timeout */ 2117 if (hw->fc.strict_ieee) 2118 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; 2119 2120 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 2121 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); 2122 2123 /* 2124 * Set up the 10G flow control advertisement registers so the HW 2125 * can do fc autoneg once the cable is plugged in. If we end up 2126 * using 1g instead, this is harmless. 2127 */ 2128 reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2129 2130 /* 2131 * The possible values of fc.requested_mode are: 2132 * 0: Flow control is completely disabled 2133 * 1: Rx flow control is enabled (we can receive pause frames, 2134 * but not send pause frames). 2135 * 2: Tx flow control is enabled (we can send pause frames but 2136 * we do not support receiving pause frames). 2137 * 3: Both Rx and Tx flow control (symmetric) are enabled. 2138 * other: Invalid. 2139 */ 2140 switch (hw->fc.requested_mode) { 2141 case ixgbe_fc_none: 2142 /* Flow control completely disabled by software override. */ 2143 reg &= ~(IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE); 2144 break; 2145 case ixgbe_fc_rx_pause: 2146 /* 2147 * Rx Flow control is enabled and Tx Flow control is 2148 * disabled by software override. Since there really 2149 * isn't a way to advertise that we are capable of RX 2150 * Pause ONLY, we will advertise that we support both 2151 * symmetric and asymmetric Rx PAUSE. Later, we will 2152 * disable the adapter's ability to send PAUSE frames. 2153 */ 2154 reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE); 2155 break; 2156 case ixgbe_fc_tx_pause: 2157 /* 2158 * Tx Flow control is enabled, and Rx Flow control is 2159 * disabled by software override. 2160 */ 2161 reg |= (IXGBE_AUTOC_ASM_PAUSE); 2162 reg &= ~(IXGBE_AUTOC_SYM_PAUSE); 2163 break; 2164 case ixgbe_fc_full: 2165 /* Flow control (both Rx and Tx) is enabled by SW override. */ 2166 reg |= (IXGBE_AUTOC_SYM_PAUSE | IXGBE_AUTOC_ASM_PAUSE); 2167 break; 2168 default: 2169 DEBUGOUT("Flow control param set incorrectly\n"); 2170 ret_val = IXGBE_ERR_CONFIG; 2171 goto out; 2172 break; 2173 } 2174 /* 2175 * AUTOC restart handles negotiation of 1G and 10G. There is 2176 * no need to set the PCS1GCTL register. 2177 */ 2178 reg |= IXGBE_AUTOC_AN_RESTART; 2179 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg); 2180 DEBUGOUT1("Set up FC; IXGBE_AUTOC = 0x%08X\n", reg); 2181 2182out: 2183 return ret_val; 2184} 2185 2186/** 2187 * ixgbe_disable_pcie_master - Disable PCI-express master access 2188 * @hw: pointer to hardware structure 2189 * 2190 * Disables PCI-Express master access and verifies there are no pending 2191 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable 2192 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS 2193 * is returned signifying master requests disabled. 2194 **/ 2195s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) 2196{ 2197 u32 i; 2198 u32 reg_val; 2199 u32 number_of_queues; 2200 s32 status = IXGBE_SUCCESS; 2201 2202 DEBUGFUNC("ixgbe_disable_pcie_master"); 2203 2204 /* Just jump out if bus mastering is already disabled */ 2205 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) 2206 goto out; 2207 2208 /* Disable the receive unit by stopping each queue */ 2209 number_of_queues = hw->mac.max_rx_queues; 2210 for (i = 0; i < number_of_queues; i++) { 2211 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 2212 if (reg_val & IXGBE_RXDCTL_ENABLE) { 2213 reg_val &= ~IXGBE_RXDCTL_ENABLE; 2214 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); 2215 } 2216 } 2217 2218 reg_val = IXGBE_READ_REG(hw, IXGBE_CTRL); 2219 reg_val |= IXGBE_CTRL_GIO_DIS; 2220 IXGBE_WRITE_REG(hw, IXGBE_CTRL, reg_val); 2221 2222 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 2223 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) 2224 goto out; 2225 usec_delay(100); 2226 } 2227 2228 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n"); 2229 status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 2230 2231 /* 2232 * The GIO Master Disable bit didn't clear. There are multiple reasons 2233 * for this listed in the datasheet 5.2.5.3.2 Master Disable, and they 2234 * all require a double reset to recover from. Before proceeding, we 2235 * first wait a little more to try to ensure that, at a minimum, the 2236 * PCIe block has no transactions pending. 2237 */ 2238 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 2239 if (!(IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS) & 2240 IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 2241 break; 2242 usec_delay(100); 2243 } 2244 2245 if (i == IXGBE_PCI_MASTER_DISABLE_TIMEOUT) 2246 DEBUGOUT("PCIe transaction pending bit also did not clear.\n"); 2247 2248 /* 2249 * Two consecutive resets are required via CTRL.RST per datasheet 2250 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine 2251 * of this need. The first reset prevents new master requests from 2252 * being issued by our device. We then must wait 1usec for any 2253 * remaining completions from the PCIe bus to trickle in, and then reset 2254 * again to clear out any effects they may have had on our device. 2255 */ 2256 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 2257 2258out: 2259 return status; 2260} 2261 2262 2263/** 2264 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 2265 * @hw: pointer to hardware structure 2266 * @mask: Mask to specify which semaphore to acquire 2267 * 2268 * Acquires the SWFW semaphore thought the GSSR register for the specified 2269 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2270 **/ 2271s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask) 2272{ 2273 u32 gssr; 2274 u32 swmask = mask; 2275 u32 fwmask = mask << 5; 2276 s32 timeout = 200; 2277 2278 DEBUGFUNC("ixgbe_acquire_swfw_sync"); 2279 2280 while (timeout) { 2281 /* 2282 * SW EEPROM semaphore bit is used for access to all 2283 * SW_FW_SYNC/GSSR bits (not just EEPROM) 2284 */ 2285 if (ixgbe_get_eeprom_semaphore(hw)) 2286 return IXGBE_ERR_SWFW_SYNC; 2287 2288 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2289 if (!(gssr & (fwmask | swmask))) 2290 break; 2291 2292 /* 2293 * Firmware currently using resource (fwmask) or other software 2294 * thread currently using resource (swmask) 2295 */ 2296 ixgbe_release_eeprom_semaphore(hw); 2297 msec_delay(5); 2298 timeout--; 2299 } 2300 2301 if (!timeout) { 2302 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n"); 2303 return IXGBE_ERR_SWFW_SYNC; 2304 } 2305 2306 gssr |= swmask; 2307 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2308 2309 ixgbe_release_eeprom_semaphore(hw); 2310 return IXGBE_SUCCESS; 2311} 2312 2313/** 2314 * ixgbe_release_swfw_sync - Release SWFW semaphore 2315 * @hw: pointer to hardware structure 2316 * @mask: Mask to specify which semaphore to release 2317 * 2318 * Releases the SWFW semaphore thought the GSSR register for the specified 2319 * function (CSR, PHY0, PHY1, EEPROM, Flash) 2320 **/ 2321void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask) 2322{ 2323 u32 gssr; 2324 u32 swmask = mask; 2325 2326 DEBUGFUNC("ixgbe_release_swfw_sync"); 2327 2328 ixgbe_get_eeprom_semaphore(hw); 2329 2330 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 2331 gssr &= ~swmask; 2332 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 2333 2334 ixgbe_release_eeprom_semaphore(hw); 2335} 2336 2337/** 2338 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit 2339 * @hw: pointer to hardware structure 2340 * @regval: register value to write to RXCTRL 2341 * 2342 * Enables the Rx DMA unit 2343 **/ 2344s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) 2345{ 2346 DEBUGFUNC("ixgbe_enable_rx_dma_generic"); 2347 2348 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); 2349 2350 return IXGBE_SUCCESS; 2351} 2352 2353/** 2354 * ixgbe_blink_led_start_generic - Blink LED based on index. 2355 * @hw: pointer to hardware structure 2356 * @index: led number to blink 2357 **/ 2358s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) 2359{ 2360 ixgbe_link_speed speed = 0; 2361 bool link_up = 0; 2362 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2363 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2364 2365 DEBUGFUNC("ixgbe_blink_led_start_generic"); 2366 2367 /* 2368 * Link must be up to auto-blink the LEDs; 2369 * Force it if link is down. 2370 */ 2371 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 2372 2373 if (!link_up) { 2374 2375 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2376 autoc_reg |= IXGBE_AUTOC_FLU; 2377 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 2378 msec_delay(10); 2379 } 2380 2381 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2382 led_reg |= IXGBE_LED_BLINK(index); 2383 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2384 IXGBE_WRITE_FLUSH(hw); 2385 2386 return IXGBE_SUCCESS; 2387} 2388 2389/** 2390 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. 2391 * @hw: pointer to hardware structure 2392 * @index: led number to stop blinking 2393 **/ 2394s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) 2395{ 2396 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2397 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 2398 2399 DEBUGFUNC("ixgbe_blink_led_stop_generic"); 2400 2401 2402 autoc_reg &= ~IXGBE_AUTOC_FLU; 2403 autoc_reg |= IXGBE_AUTOC_AN_RESTART; 2404 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 2405 2406 led_reg &= ~IXGBE_LED_MODE_MASK(index); 2407 led_reg &= ~IXGBE_LED_BLINK(index); 2408 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 2409 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 2410 IXGBE_WRITE_FLUSH(hw); 2411 2412 return IXGBE_SUCCESS; 2413} 2414 2415/** 2416 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM 2417 * @hw: pointer to hardware structure 2418 * @san_mac_offset: SAN MAC address offset 2419 * 2420 * This function will read the EEPROM location for the SAN MAC address 2421 * pointer, and returns the value at that location. This is used in both 2422 * get and set mac_addr routines. 2423 **/ 2424static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 2425 u16 *san_mac_offset) 2426{ 2427 DEBUGFUNC("ixgbe_get_san_mac_addr_offset"); 2428 2429 /* 2430 * First read the EEPROM pointer to see if the MAC addresses are 2431 * available. 2432 */ 2433 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset); 2434 2435 return IXGBE_SUCCESS; 2436} 2437 2438/** 2439 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM 2440 * @hw: pointer to hardware structure 2441 * @san_mac_addr: SAN MAC address 2442 * 2443 * Reads the SAN MAC address from the EEPROM, if it's available. This is 2444 * per-port, so set_lan_id() must be called before reading the addresses. 2445 * set_lan_id() is called by identify_sfp(), but this cannot be relied 2446 * upon for non-SFP connections, so we must call it here. 2447 **/ 2448s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 2449{ 2450 u16 san_mac_data, san_mac_offset; 2451 u8 i; 2452 2453 DEBUGFUNC("ixgbe_get_san_mac_addr_generic"); 2454 2455 /* 2456 * First read the EEPROM pointer to see if the MAC addresses are 2457 * available. If they're not, no point in calling set_lan_id() here. 2458 */ 2459 ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 2460 2461 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) { 2462 /* 2463 * No addresses available in this EEPROM. It's not an 2464 * error though, so just wipe the local address and return. 2465 */ 2466 for (i = 0; i < 6; i++) 2467 san_mac_addr[i] = 0xFF; 2468 2469 goto san_mac_addr_out; 2470 } 2471 2472 /* make sure we know which port we need to program */ 2473 hw->mac.ops.set_lan_id(hw); 2474 /* apply the port offset to the address offset */ 2475 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 2476 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 2477 for (i = 0; i < 3; i++) { 2478 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data); 2479 san_mac_addr[i * 2] = (u8)(san_mac_data); 2480 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8); 2481 san_mac_offset++; 2482 } 2483 2484san_mac_addr_out: 2485 return IXGBE_SUCCESS; 2486} 2487 2488/** 2489 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM 2490 * @hw: pointer to hardware structure 2491 * @san_mac_addr: SAN MAC address 2492 * 2493 * Write a SAN MAC address to the EEPROM. 2494 **/ 2495s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 2496{ 2497 s32 status = IXGBE_SUCCESS; 2498 u16 san_mac_data, san_mac_offset; 2499 u8 i; 2500 2501 DEBUGFUNC("ixgbe_set_san_mac_addr_generic"); 2502 2503 /* Look for SAN mac address pointer. If not defined, return */ 2504 ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 2505 2506 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) { 2507 status = IXGBE_ERR_NO_SAN_ADDR_PTR; 2508 goto san_mac_addr_out; 2509 } 2510 2511 /* Make sure we know which port we need to write */ 2512 hw->mac.ops.set_lan_id(hw); 2513 /* Apply the port offset to the address offset */ 2514 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 2515 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 2516 2517 for (i = 0; i < 3; i++) { 2518 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8); 2519 san_mac_data |= (u16)(san_mac_addr[i * 2]); 2520 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data); 2521 san_mac_offset++; 2522 } 2523 2524san_mac_addr_out: 2525 return status; 2526} 2527 2528/** 2529 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count 2530 * @hw: pointer to hardware structure 2531 * 2532 * Read PCIe configuration space, and get the MSI-X vector count from 2533 * the capabilities table. 2534 **/ 2535u32 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) 2536{ 2537 u32 msix_count = 64; 2538 2539 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic"); 2540 if (hw->mac.msix_vectors_from_pcie) { 2541 msix_count = IXGBE_READ_PCIE_WORD(hw, 2542 IXGBE_PCIE_MSIX_82599_CAPS); 2543 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 2544 2545 /* MSI-X count is zero-based in HW, so increment to give 2546 * proper value */ 2547 msix_count++; 2548 } 2549 2550 return msix_count; 2551} 2552 2553/** 2554 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address 2555 * @hw: pointer to hardware structure 2556 * @addr: Address to put into receive address register 2557 * @vmdq: VMDq pool to assign 2558 * 2559 * Puts an ethernet address into a receive address register, or 2560 * finds the rar that it is aleady in; adds to the pool list 2561 **/ 2562s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 2563{ 2564 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF; 2565 u32 first_empty_rar = NO_EMPTY_RAR_FOUND; 2566 u32 rar; 2567 u32 rar_low, rar_high; 2568 u32 addr_low, addr_high; 2569 2570 DEBUGFUNC("ixgbe_insert_mac_addr_generic"); 2571 2572 /* swap bytes for HW little endian */ 2573 addr_low = addr[0] | (addr[1] << 8) 2574 | (addr[2] << 16) 2575 | (addr[3] << 24); 2576 addr_high = addr[4] | (addr[5] << 8); 2577 2578 /* 2579 * Either find the mac_id in rar or find the first empty space. 2580 * rar_highwater points to just after the highest currently used 2581 * rar in order to shorten the search. It grows when we add a new 2582 * rar to the top. 2583 */ 2584 for (rar = 0; rar < hw->mac.rar_highwater; rar++) { 2585 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 2586 2587 if (((IXGBE_RAH_AV & rar_high) == 0) 2588 && first_empty_rar == NO_EMPTY_RAR_FOUND) { 2589 first_empty_rar = rar; 2590 } else if ((rar_high & 0xFFFF) == addr_high) { 2591 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar)); 2592 if (rar_low == addr_low) 2593 break; /* found it already in the rars */ 2594 } 2595 } 2596 2597 if (rar < hw->mac.rar_highwater) { 2598 /* already there so just add to the pool bits */ 2599 ixgbe_set_vmdq(hw, rar, vmdq); 2600 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) { 2601 /* stick it into first empty RAR slot we found */ 2602 rar = first_empty_rar; 2603 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 2604 } else if (rar == hw->mac.rar_highwater) { 2605 /* add it to the top of the list and inc the highwater mark */ 2606 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 2607 hw->mac.rar_highwater++; 2608 } else if (rar >= hw->mac.num_rar_entries) { 2609 return IXGBE_ERR_INVALID_MAC_ADDR; 2610 } 2611 2612 /* 2613 * If we found rar[0], make sure the default pool bit (we use pool 0) 2614 * remains cleared to be sure default pool packets will get delivered 2615 */ 2616 if (rar == 0) 2617 ixgbe_clear_vmdq(hw, rar, 0); 2618 2619 return rar; 2620} 2621 2622/** 2623 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address 2624 * @hw: pointer to hardware struct 2625 * @rar: receive address register index to disassociate 2626 * @vmdq: VMDq pool index to remove from the rar 2627 **/ 2628s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 2629{ 2630 u32 mpsar_lo, mpsar_hi; 2631 u32 rar_entries = hw->mac.num_rar_entries; 2632 2633 DEBUGFUNC("ixgbe_clear_vmdq_generic"); 2634 2635 if (rar < rar_entries) { 2636 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 2637 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 2638 2639 if (!mpsar_lo && !mpsar_hi) 2640 goto done; 2641 2642 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { 2643 if (mpsar_lo) { 2644 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 2645 mpsar_lo = 0; 2646 } 2647 if (mpsar_hi) { 2648 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 2649 mpsar_hi = 0; 2650 } 2651 } else if (vmdq < 32) { 2652 mpsar_lo &= ~(1 << vmdq); 2653 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); 2654 } else { 2655 mpsar_hi &= ~(1 << (vmdq - 32)); 2656 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); 2657 } 2658 2659 /* was that the last pool using this rar? */ 2660 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0) 2661 hw->mac.ops.clear_rar(hw, rar); 2662 } else { 2663 DEBUGOUT1("RAR index %d is out of range.\n", rar); 2664 } 2665 2666done: 2667 return IXGBE_SUCCESS; 2668} 2669 2670/** 2671 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address 2672 * @hw: pointer to hardware struct 2673 * @rar: receive address register index to associate with a VMDq index 2674 * @vmdq: VMDq pool index 2675 **/ 2676s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 2677{ 2678 u32 mpsar; 2679 u32 rar_entries = hw->mac.num_rar_entries; 2680 2681 DEBUGFUNC("ixgbe_set_vmdq_generic"); 2682 2683 if (rar < rar_entries) { 2684 if (vmdq < 32) { 2685 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 2686 mpsar |= 1 << vmdq; 2687 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); 2688 } else { 2689 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 2690 mpsar |= 1 << (vmdq - 32); 2691 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); 2692 } 2693 } else { 2694 DEBUGOUT1("RAR index %d is out of range.\n", rar); 2695 } 2696 return IXGBE_SUCCESS; 2697} 2698 2699/** 2700 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array 2701 * @hw: pointer to hardware structure 2702 **/ 2703s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) 2704{ 2705 int i; 2706 2707 DEBUGFUNC("ixgbe_init_uta_tables_generic"); 2708 DEBUGOUT(" Clearing UTA\n"); 2709 2710 for (i = 0; i < 128; i++) 2711 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 2712 2713 return IXGBE_SUCCESS; 2714} 2715 2716/** 2717 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot 2718 * @hw: pointer to hardware structure 2719 * @vlan: VLAN id to write to VLAN filter 2720 * 2721 * return the VLVF index where this VLAN id should be placed 2722 * 2723 **/ 2724s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan) 2725{ 2726 u32 bits = 0; 2727 u32 first_empty_slot = 0; 2728 s32 regindex; 2729 2730 /* short cut the special case */ 2731 if (vlan == 0) 2732 return 0; 2733 2734 /* 2735 * Search for the vlan id in the VLVF entries. Save off the first empty 2736 * slot found along the way 2737 */ 2738 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) { 2739 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); 2740 if (!bits && !(first_empty_slot)) 2741 first_empty_slot = regindex; 2742 else if ((bits & 0x0FFF) == vlan) 2743 break; 2744 } 2745 2746 /* 2747 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan 2748 * in the VLVF. Else use the first empty VLVF register for this 2749 * vlan id. 2750 */ 2751 if (regindex >= IXGBE_VLVF_ENTRIES) { 2752 if (first_empty_slot) 2753 regindex = first_empty_slot; 2754 else { 2755 DEBUGOUT("No space in VLVF.\n"); 2756 regindex = IXGBE_ERR_NO_SPACE; 2757 } 2758 } 2759 2760 return regindex; 2761} 2762 2763/** 2764 * ixgbe_set_vfta_generic - Set VLAN filter table 2765 * @hw: pointer to hardware structure 2766 * @vlan: VLAN id to write to VLAN filter 2767 * @vind: VMDq output index that maps queue to VLAN id in VFVFB 2768 * @vlan_on: boolean flag to turn on/off VLAN in VFVF 2769 * 2770 * Turn on/off specified VLAN in the VLAN filter table. 2771 **/ 2772s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 2773 bool vlan_on) 2774{ 2775 s32 regindex; 2776 u32 bitindex; 2777 u32 vfta; 2778 u32 bits; 2779 u32 vt; 2780 u32 targetbit; 2781 bool vfta_changed = FALSE; 2782 2783 DEBUGFUNC("ixgbe_set_vfta_generic"); 2784 2785 if (vlan > 4095) 2786 return IXGBE_ERR_PARAM; 2787 2788 /* 2789 * this is a 2 part operation - first the VFTA, then the 2790 * VLVF and VLVFB if VT Mode is set 2791 * We don't write the VFTA until we know the VLVF part succeeded. 2792 */ 2793 2794 /* Part 1 2795 * The VFTA is a bitstring made up of 128 32-bit registers 2796 * that enable the particular VLAN id, much like the MTA: 2797 * bits[11-5]: which register 2798 * bits[4-0]: which bit in the register 2799 */ 2800 regindex = (vlan >> 5) & 0x7F; 2801 bitindex = vlan & 0x1F; 2802 targetbit = (1 << bitindex); 2803 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); 2804 2805 if (vlan_on) { 2806 if (!(vfta & targetbit)) { 2807 vfta |= targetbit; 2808 vfta_changed = TRUE; 2809 } 2810 } else { 2811 if ((vfta & targetbit)) { 2812 vfta &= ~targetbit; 2813 vfta_changed = TRUE; 2814 } 2815 } 2816 2817 /* Part 2 2818 * If VT Mode is set 2819 * Either vlan_on 2820 * make sure the vlan is in VLVF 2821 * set the vind bit in the matching VLVFB 2822 * Or !vlan_on 2823 * clear the pool bit and possibly the vind 2824 */ 2825 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 2826 if (vt & IXGBE_VT_CTL_VT_ENABLE) { 2827 s32 vlvf_index; 2828 2829 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan); 2830 if (vlvf_index < 0) 2831 return vlvf_index; 2832 2833 if (vlan_on) { 2834 /* set the pool bit */ 2835 if (vind < 32) { 2836 bits = IXGBE_READ_REG(hw, 2837 IXGBE_VLVFB(vlvf_index*2)); 2838 bits |= (1 << vind); 2839 IXGBE_WRITE_REG(hw, 2840 IXGBE_VLVFB(vlvf_index*2), 2841 bits); 2842 } else { 2843 bits = IXGBE_READ_REG(hw, 2844 IXGBE_VLVFB((vlvf_index*2)+1)); 2845 bits |= (1 << (vind-32)); 2846 IXGBE_WRITE_REG(hw, 2847 IXGBE_VLVFB((vlvf_index*2)+1), 2848 bits); 2849 } 2850 } else { 2851 /* clear the pool bit */ 2852 if (vind < 32) { 2853 bits = IXGBE_READ_REG(hw, 2854 IXGBE_VLVFB(vlvf_index*2)); 2855 bits &= ~(1 << vind); 2856 IXGBE_WRITE_REG(hw, 2857 IXGBE_VLVFB(vlvf_index*2), 2858 bits); 2859 bits |= IXGBE_READ_REG(hw, 2860 IXGBE_VLVFB((vlvf_index*2)+1)); 2861 } else { 2862 bits = IXGBE_READ_REG(hw, 2863 IXGBE_VLVFB((vlvf_index*2)+1)); 2864 bits &= ~(1 << (vind-32)); 2865 IXGBE_WRITE_REG(hw, 2866 IXGBE_VLVFB((vlvf_index*2)+1), 2867 bits); 2868 bits |= IXGBE_READ_REG(hw, 2869 IXGBE_VLVFB(vlvf_index*2)); 2870 } 2871 } 2872 2873 /* 2874 * If there are still bits set in the VLVFB registers 2875 * for the VLAN ID indicated we need to see if the 2876 * caller is requesting that we clear the VFTA entry bit. 2877 * If the caller has requested that we clear the VFTA 2878 * entry bit but there are still pools/VFs using this VLAN 2879 * ID entry then ignore the request. We're not worried 2880 * about the case where we're turning the VFTA VLAN ID 2881 * entry bit on, only when requested to turn it off as 2882 * there may be multiple pools and/or VFs using the 2883 * VLAN ID entry. In that case we cannot clear the 2884 * VFTA bit until all pools/VFs using that VLAN ID have also 2885 * been cleared. This will be indicated by "bits" being 2886 * zero. 2887 */ 2888 if (bits) { 2889 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 2890 (IXGBE_VLVF_VIEN | vlan)); 2891 if (!vlan_on) { 2892 /* someone wants to clear the vfta entry 2893 * but some pools/VFs are still using it. 2894 * Ignore it. */ 2895 vfta_changed = FALSE; 2896 } 2897 } 2898 else 2899 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); 2900 } 2901 2902 if (vfta_changed) 2903 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta); 2904 2905 return IXGBE_SUCCESS; 2906} 2907 2908/** 2909 * ixgbe_clear_vfta_generic - Clear VLAN filter table 2910 * @hw: pointer to hardware structure 2911 * 2912 * Clears the VLAN filer table, and the VMDq index associated with the filter 2913 **/ 2914s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) 2915{ 2916 u32 offset; 2917 2918 DEBUGFUNC("ixgbe_clear_vfta_generic"); 2919 2920 for (offset = 0; offset < hw->mac.vft_size; offset++) 2921 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 2922 2923 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { 2924 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); 2925 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0); 2926 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0); 2927 } 2928 2929 return IXGBE_SUCCESS; 2930} 2931 2932/** 2933 * ixgbe_check_mac_link_generic - Determine link and speed status 2934 * @hw: pointer to hardware structure 2935 * @speed: pointer to link speed 2936 * @link_up: TRUE when link is up 2937 * @link_up_wait_to_complete: bool used to wait for link up or not 2938 * 2939 * Reads the links register to determine if link is up and the current speed 2940 **/ 2941s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 2942 bool *link_up, bool link_up_wait_to_complete) 2943{ 2944 u32 links_reg, links_orig; 2945 u32 i; 2946 2947 DEBUGFUNC("ixgbe_check_mac_link_generic"); 2948 2949 /* clear the old state */ 2950 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); 2951 2952 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 2953 2954 if (links_orig != links_reg) { 2955 DEBUGOUT2("LINKS changed from %08X to %08X\n", 2956 links_orig, links_reg); 2957 } 2958 2959 if (link_up_wait_to_complete) { 2960 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 2961 if (links_reg & IXGBE_LINKS_UP) { 2962 *link_up = TRUE; 2963 break; 2964 } else { 2965 *link_up = FALSE; 2966 } 2967 msec_delay(100); 2968 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 2969 } 2970 } else { 2971 if (links_reg & IXGBE_LINKS_UP) 2972 *link_up = TRUE; 2973 else 2974 *link_up = FALSE; 2975 } 2976 2977 if ((links_reg & IXGBE_LINKS_SPEED_82599) == 2978 IXGBE_LINKS_SPEED_10G_82599) 2979 *speed = IXGBE_LINK_SPEED_10GB_FULL; 2980 else if ((links_reg & IXGBE_LINKS_SPEED_82599) == 2981 IXGBE_LINKS_SPEED_1G_82599) 2982 *speed = IXGBE_LINK_SPEED_1GB_FULL; 2983 else 2984 *speed = IXGBE_LINK_SPEED_100_FULL; 2985 2986 /* if link is down, zero out the current_mode */ 2987 if (*link_up == FALSE) { 2988 hw->fc.current_mode = ixgbe_fc_none; 2989 hw->fc.fc_was_autonegged = FALSE; 2990 } 2991 2992 return IXGBE_SUCCESS; 2993} 2994 2995/** 2996 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from 2997 * the EEPROM 2998 * @hw: pointer to hardware structure 2999 * @wwnn_prefix: the alternative WWNN prefix 3000 * @wwpn_prefix: the alternative WWPN prefix 3001 * 3002 * This function will read the EEPROM from the alternative SAN MAC address 3003 * block to check the support for the alternative WWNN/WWPN prefix support. 3004 **/ 3005s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, 3006 u16 *wwpn_prefix) 3007{ 3008 u16 offset, caps; 3009 u16 alt_san_mac_blk_offset; 3010 3011 DEBUGFUNC("ixgbe_get_wwn_prefix_generic"); 3012 3013 /* clear output first */ 3014 *wwnn_prefix = 0xFFFF; 3015 *wwpn_prefix = 0xFFFF; 3016 3017 /* check if alternative SAN MAC is supported */ 3018 hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR, 3019 &alt_san_mac_blk_offset); 3020 3021 if ((alt_san_mac_blk_offset == 0) || 3022 (alt_san_mac_blk_offset == 0xFFFF)) 3023 goto wwn_prefix_out; 3024 3025 /* check capability in alternative san mac address block */ 3026 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET; 3027 hw->eeprom.ops.read(hw, offset, &caps); 3028 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN)) 3029 goto wwn_prefix_out; 3030 3031 /* get the corresponding prefix for WWNN/WWPN */ 3032 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET; 3033 hw->eeprom.ops.read(hw, offset, wwnn_prefix); 3034 3035 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET; 3036 hw->eeprom.ops.read(hw, offset, wwpn_prefix); 3037 3038wwn_prefix_out: 3039 return IXGBE_SUCCESS; 3040} 3041