1179055Sjfv/****************************************************************************** 2171384Sjfv 3247822Sjfv Copyright (c) 2001-2013, Intel Corporation 4171384Sjfv All rights reserved. 5171384Sjfv 6171384Sjfv Redistribution and use in source and binary forms, with or without 7171384Sjfv modification, are permitted provided that the following conditions are met: 8171384Sjfv 9171384Sjfv 1. Redistributions of source code must retain the above copyright notice, 10171384Sjfv this list of conditions and the following disclaimer. 11171384Sjfv 12171384Sjfv 2. Redistributions in binary form must reproduce the above copyright 13171384Sjfv notice, this list of conditions and the following disclaimer in the 14171384Sjfv documentation and/or other materials provided with the distribution. 15171384Sjfv 16171384Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17171384Sjfv contributors may be used to endorse or promote products derived from 18171384Sjfv this software without specific prior written permission. 19171384Sjfv 20171384Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21171384Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22171384Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23171384Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24171384Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25171384Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26171384Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27171384Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28171384Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29171384Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30171384Sjfv POSSIBILITY OF SUCH DAMAGE. 31171384Sjfv 32179055Sjfv******************************************************************************/ 33179055Sjfv/*$FreeBSD$*/ 34171384Sjfv 35171384Sjfv#include "ixgbe_common.h" 36215911Sjfv#include "ixgbe_phy.h" 37251964Sjfv#include "ixgbe_dcb.h" 38251964Sjfv#include "ixgbe_dcb_82599.h" 39171384Sjfv#include "ixgbe_api.h" 40171384Sjfv 41171384Sjfvstatic s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw); 42171384Sjfvstatic s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw); 43171384Sjfvstatic void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw); 44171384Sjfvstatic s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw); 45171384Sjfvstatic void ixgbe_standby_eeprom(struct ixgbe_hw *hw); 46171384Sjfvstatic void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 47230775Sjfv u16 count); 48171384Sjfvstatic u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count); 49171384Sjfvstatic void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 50171384Sjfvstatic void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec); 51171384Sjfvstatic void ixgbe_release_eeprom(struct ixgbe_hw *hw); 52171384Sjfv 53171384Sjfvstatic s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr); 54200239Sjfvstatic s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 55230775Sjfv u16 *san_mac_offset); 56230775Sjfvstatic s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 57230775Sjfv u16 words, u16 *data); 58230775Sjfvstatic s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 59230775Sjfv u16 words, u16 *data); 60230775Sjfvstatic s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 61230775Sjfv u16 offset); 62215911Sjfv 63171384Sjfv/** 64179055Sjfv * ixgbe_init_ops_generic - Inits function ptrs 65179055Sjfv * @hw: pointer to the hardware structure 66171384Sjfv * 67179055Sjfv * Initialize the function pointers. 68171384Sjfv **/ 69179055Sjfvs32 ixgbe_init_ops_generic(struct ixgbe_hw *hw) 70171384Sjfv{ 71179055Sjfv struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 72179055Sjfv struct ixgbe_mac_info *mac = &hw->mac; 73179055Sjfv u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 74171384Sjfv 75200239Sjfv DEBUGFUNC("ixgbe_init_ops_generic"); 76200239Sjfv 77171384Sjfv /* EEPROM */ 78179055Sjfv eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic; 79179055Sjfv /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */ 80230775Sjfv if (eec & IXGBE_EEC_PRES) { 81200239Sjfv eeprom->ops.read = &ixgbe_read_eerd_generic; 82230775Sjfv eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_generic; 83230775Sjfv } else { 84179055Sjfv eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic; 85230775Sjfv eeprom->ops.read_buffer = 86230775Sjfv &ixgbe_read_eeprom_buffer_bit_bang_generic; 87230775Sjfv } 88179055Sjfv eeprom->ops.write = &ixgbe_write_eeprom_generic; 89230775Sjfv eeprom->ops.write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic; 90179055Sjfv eeprom->ops.validate_checksum = 91230775Sjfv &ixgbe_validate_eeprom_checksum_generic; 92179055Sjfv eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic; 93200239Sjfv eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_generic; 94179055Sjfv 95179055Sjfv /* MAC */ 96179055Sjfv mac->ops.init_hw = &ixgbe_init_hw_generic; 97179055Sjfv mac->ops.reset_hw = NULL; 98179055Sjfv mac->ops.start_hw = &ixgbe_start_hw_generic; 99179055Sjfv mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic; 100179055Sjfv mac->ops.get_media_type = NULL; 101185352Sjfv mac->ops.get_supported_physical_layer = NULL; 102190873Sjfv mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_generic; 103179055Sjfv mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic; 104179055Sjfv mac->ops.stop_adapter = &ixgbe_stop_adapter_generic; 105179055Sjfv mac->ops.get_bus_info = &ixgbe_get_bus_info_generic; 106185352Sjfv mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie; 107194875Sjfv mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync; 108194875Sjfv mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync; 109179055Sjfv 110179055Sjfv /* LEDs */ 111179055Sjfv mac->ops.led_on = &ixgbe_led_on_generic; 112179055Sjfv mac->ops.led_off = &ixgbe_led_off_generic; 113190873Sjfv mac->ops.blink_led_start = &ixgbe_blink_led_start_generic; 114190873Sjfv mac->ops.blink_led_stop = &ixgbe_blink_led_stop_generic; 115179055Sjfv 116171384Sjfv /* RAR, Multicast, VLAN */ 117179055Sjfv mac->ops.set_rar = &ixgbe_set_rar_generic; 118181003Sjfv mac->ops.clear_rar = &ixgbe_clear_rar_generic; 119190873Sjfv mac->ops.insert_mac_addr = NULL; 120179055Sjfv mac->ops.set_vmdq = NULL; 121181003Sjfv mac->ops.clear_vmdq = NULL; 122179055Sjfv mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic; 123179055Sjfv mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic; 124179055Sjfv mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic; 125179055Sjfv mac->ops.enable_mc = &ixgbe_enable_mc_generic; 126179055Sjfv mac->ops.disable_mc = &ixgbe_disable_mc_generic; 127181003Sjfv mac->ops.clear_vfta = NULL; 128181003Sjfv mac->ops.set_vfta = NULL; 129230775Sjfv mac->ops.set_vlvf = NULL; 130181003Sjfv mac->ops.init_uta_tables = NULL; 131171384Sjfv 132190873Sjfv /* Flow Control */ 133190873Sjfv mac->ops.fc_enable = &ixgbe_fc_enable_generic; 134179055Sjfv 135179055Sjfv /* Link */ 136179055Sjfv mac->ops.get_link_capabilities = NULL; 137179055Sjfv mac->ops.setup_link = NULL; 138179055Sjfv mac->ops.check_link = NULL; 139251964Sjfv mac->ops.dmac_config = NULL; 140251964Sjfv mac->ops.dmac_update_tcs = NULL; 141251964Sjfv mac->ops.dmac_config_tcs = NULL; 142179055Sjfv 143171384Sjfv return IXGBE_SUCCESS; 144171384Sjfv} 145171384Sjfv 146171384Sjfv/** 147251964Sjfv * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation 148251964Sjfv * of flow control 149251964Sjfv * @hw: pointer to hardware structure 150238149Sjfv * 151251964Sjfv * This function returns TRUE if the device supports flow control 152251964Sjfv * autonegotiation, and FALSE if it does not. 153251964Sjfv * 154238149Sjfv **/ 155251964Sjfvbool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw) 156238149Sjfv{ 157251964Sjfv bool supported = FALSE; 158251964Sjfv ixgbe_link_speed speed; 159251964Sjfv bool link_up; 160238149Sjfv 161238149Sjfv DEBUGFUNC("ixgbe_device_supports_autoneg_fc"); 162238149Sjfv 163251964Sjfv switch (hw->phy.media_type) { 164251964Sjfv case ixgbe_media_type_fiber_fixed: 165251964Sjfv case ixgbe_media_type_fiber: 166251964Sjfv hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 167251964Sjfv /* if link is down, assume supported */ 168251964Sjfv if (link_up) 169251964Sjfv supported = speed == IXGBE_LINK_SPEED_1GB_FULL ? 170251964Sjfv TRUE : FALSE; 171251964Sjfv else 172251964Sjfv supported = TRUE; 173251964Sjfv break; 174251964Sjfv case ixgbe_media_type_backplane: 175251964Sjfv supported = TRUE; 176251964Sjfv break; 177251964Sjfv case ixgbe_media_type_copper: 178251964Sjfv /* only some copper devices support flow control autoneg */ 179251964Sjfv switch (hw->device_id) { 180251964Sjfv case IXGBE_DEV_ID_82599_T3_LOM: 181251964Sjfv case IXGBE_DEV_ID_X540T: 182251964Sjfv case IXGBE_DEV_ID_X540_BYPASS: 183251964Sjfv supported = TRUE; 184251964Sjfv break; 185251964Sjfv default: 186251964Sjfv supported = FALSE; 187251964Sjfv } 188238149Sjfv default: 189251964Sjfv break; 190238149Sjfv } 191251964Sjfv 192251964Sjfv ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 193251964Sjfv "Device %x does not support flow control autoneg", 194251964Sjfv hw->device_id); 195251964Sjfv return supported; 196238149Sjfv} 197238149Sjfv 198238149Sjfv/** 199238149Sjfv * ixgbe_setup_fc - Set up flow control 200238149Sjfv * @hw: pointer to hardware structure 201238149Sjfv * 202238149Sjfv * Called at init time to set up flow control. 203238149Sjfv **/ 204238149Sjfvstatic s32 ixgbe_setup_fc(struct ixgbe_hw *hw) 205238149Sjfv{ 206238149Sjfv s32 ret_val = IXGBE_SUCCESS; 207238149Sjfv u32 reg = 0, reg_bp = 0; 208238149Sjfv u16 reg_cu = 0; 209247822Sjfv bool got_lock = FALSE; 210238149Sjfv 211238149Sjfv DEBUGFUNC("ixgbe_setup_fc"); 212238149Sjfv 213238149Sjfv /* 214238149Sjfv * Validate the requested mode. Strict IEEE mode does not allow 215238149Sjfv * ixgbe_fc_rx_pause because it will cause us to fail at UNH. 216238149Sjfv */ 217238149Sjfv if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 218251964Sjfv ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 219251964Sjfv "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 220238149Sjfv ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 221238149Sjfv goto out; 222238149Sjfv } 223238149Sjfv 224238149Sjfv /* 225238149Sjfv * 10gig parts do not have a word in the EEPROM to determine the 226238149Sjfv * default flow control setting, so we explicitly set it to full. 227238149Sjfv */ 228238149Sjfv if (hw->fc.requested_mode == ixgbe_fc_default) 229238149Sjfv hw->fc.requested_mode = ixgbe_fc_full; 230238149Sjfv 231238149Sjfv /* 232238149Sjfv * Set up the 1G and 10G flow control advertisement registers so the 233238149Sjfv * HW will be able to do fc autoneg once the cable is plugged in. If 234238149Sjfv * we link at 10G, the 1G advertisement is harmless and vice versa. 235238149Sjfv */ 236238149Sjfv switch (hw->phy.media_type) { 237247822Sjfv case ixgbe_media_type_fiber_fixed: 238238149Sjfv case ixgbe_media_type_fiber: 239238149Sjfv case ixgbe_media_type_backplane: 240238149Sjfv reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 241238149Sjfv reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC); 242238149Sjfv break; 243238149Sjfv case ixgbe_media_type_copper: 244238149Sjfv hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 245238149Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu); 246238149Sjfv break; 247238149Sjfv default: 248238149Sjfv break; 249238149Sjfv } 250238149Sjfv 251238149Sjfv /* 252238149Sjfv * The possible values of fc.requested_mode are: 253238149Sjfv * 0: Flow control is completely disabled 254238149Sjfv * 1: Rx flow control is enabled (we can receive pause frames, 255238149Sjfv * but not send pause frames). 256238149Sjfv * 2: Tx flow control is enabled (we can send pause frames but 257238149Sjfv * we do not support receiving pause frames). 258238149Sjfv * 3: Both Rx and Tx flow control (symmetric) are enabled. 259238149Sjfv * other: Invalid. 260238149Sjfv */ 261238149Sjfv switch (hw->fc.requested_mode) { 262238149Sjfv case ixgbe_fc_none: 263238149Sjfv /* Flow control completely disabled by software override. */ 264238149Sjfv reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE); 265238149Sjfv if (hw->phy.media_type == ixgbe_media_type_backplane) 266238149Sjfv reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE | 267238149Sjfv IXGBE_AUTOC_ASM_PAUSE); 268238149Sjfv else if (hw->phy.media_type == ixgbe_media_type_copper) 269238149Sjfv reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE); 270238149Sjfv break; 271238149Sjfv case ixgbe_fc_tx_pause: 272238149Sjfv /* 273238149Sjfv * Tx Flow control is enabled, and Rx Flow control is 274238149Sjfv * disabled by software override. 275238149Sjfv */ 276238149Sjfv reg |= IXGBE_PCS1GANA_ASM_PAUSE; 277238149Sjfv reg &= ~IXGBE_PCS1GANA_SYM_PAUSE; 278238149Sjfv if (hw->phy.media_type == ixgbe_media_type_backplane) { 279238149Sjfv reg_bp |= IXGBE_AUTOC_ASM_PAUSE; 280238149Sjfv reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE; 281238149Sjfv } else if (hw->phy.media_type == ixgbe_media_type_copper) { 282238149Sjfv reg_cu |= IXGBE_TAF_ASM_PAUSE; 283238149Sjfv reg_cu &= ~IXGBE_TAF_SYM_PAUSE; 284238149Sjfv } 285238149Sjfv break; 286238149Sjfv case ixgbe_fc_rx_pause: 287238149Sjfv /* 288238149Sjfv * Rx Flow control is enabled and Tx Flow control is 289238149Sjfv * disabled by software override. Since there really 290238149Sjfv * isn't a way to advertise that we are capable of RX 291238149Sjfv * Pause ONLY, we will advertise that we support both 292238149Sjfv * symmetric and asymmetric Rx PAUSE, as such we fall 293238149Sjfv * through to the fc_full statement. Later, we will 294238149Sjfv * disable the adapter's ability to send PAUSE frames. 295238149Sjfv */ 296238149Sjfv case ixgbe_fc_full: 297238149Sjfv /* Flow control (both Rx and Tx) is enabled by SW override. */ 298238149Sjfv reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE; 299238149Sjfv if (hw->phy.media_type == ixgbe_media_type_backplane) 300238149Sjfv reg_bp |= IXGBE_AUTOC_SYM_PAUSE | 301238149Sjfv IXGBE_AUTOC_ASM_PAUSE; 302238149Sjfv else if (hw->phy.media_type == ixgbe_media_type_copper) 303238149Sjfv reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE; 304238149Sjfv break; 305238149Sjfv default: 306251964Sjfv ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 307251964Sjfv "Flow control param set incorrectly\n"); 308238149Sjfv ret_val = IXGBE_ERR_CONFIG; 309238149Sjfv goto out; 310238149Sjfv break; 311238149Sjfv } 312238149Sjfv 313238149Sjfv if (hw->mac.type != ixgbe_mac_X540) { 314238149Sjfv /* 315238149Sjfv * Enable auto-negotiation between the MAC & PHY; 316238149Sjfv * the MAC will advertise clause 37 flow control. 317238149Sjfv */ 318238149Sjfv IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg); 319238149Sjfv reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL); 320238149Sjfv 321238149Sjfv /* Disable AN timeout */ 322238149Sjfv if (hw->fc.strict_ieee) 323238149Sjfv reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN; 324238149Sjfv 325238149Sjfv IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg); 326238149Sjfv DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg); 327238149Sjfv } 328238149Sjfv 329238149Sjfv /* 330238149Sjfv * AUTOC restart handles negotiation of 1G and 10G on backplane 331238149Sjfv * and copper. There is no need to set the PCS1GCTL register. 332238149Sjfv * 333238149Sjfv */ 334238149Sjfv if (hw->phy.media_type == ixgbe_media_type_backplane) { 335238149Sjfv reg_bp |= IXGBE_AUTOC_AN_RESTART; 336247822Sjfv /* Need the SW/FW semaphore around AUTOC writes if 82599 and 337247822Sjfv * LESM is on, likewise reset_pipeline requries the lock as 338247822Sjfv * it also writes AUTOC. 339247822Sjfv */ 340247822Sjfv if ((hw->mac.type == ixgbe_mac_82599EB) && 341247822Sjfv ixgbe_verify_lesm_fw_enabled_82599(hw)) { 342247822Sjfv ret_val = hw->mac.ops.acquire_swfw_sync(hw, 343247822Sjfv IXGBE_GSSR_MAC_CSR_SM); 344247822Sjfv if (ret_val != IXGBE_SUCCESS) { 345247822Sjfv ret_val = IXGBE_ERR_SWFW_SYNC; 346247822Sjfv goto out; 347247822Sjfv } 348247822Sjfv got_lock = TRUE; 349247822Sjfv } 350247822Sjfv 351238149Sjfv IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp); 352247822Sjfv if (hw->mac.type == ixgbe_mac_82599EB) 353247822Sjfv ixgbe_reset_pipeline_82599(hw); 354247822Sjfv 355247822Sjfv if (got_lock) 356247822Sjfv hw->mac.ops.release_swfw_sync(hw, 357247822Sjfv IXGBE_GSSR_MAC_CSR_SM); 358238149Sjfv } else if ((hw->phy.media_type == ixgbe_media_type_copper) && 359251964Sjfv (ixgbe_device_supports_autoneg_fc(hw))) { 360238149Sjfv hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 361238149Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu); 362238149Sjfv } 363238149Sjfv 364238149Sjfv DEBUGOUT1("Set up FC; IXGBE_AUTOC = 0x%08X\n", reg); 365238149Sjfvout: 366238149Sjfv return ret_val; 367238149Sjfv} 368238149Sjfv 369238149Sjfv/** 370179055Sjfv * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx 371171384Sjfv * @hw: pointer to hardware structure 372171384Sjfv * 373171384Sjfv * Starts the hardware by filling the bus info structure and media type, clears 374171384Sjfv * all on chip counters, initializes receive address registers, multicast 375171384Sjfv * table, VLAN filter table, calls routine to set up link and flow control 376171384Sjfv * settings, and leaves transmit and receive units disabled and uninitialized 377171384Sjfv **/ 378171384Sjfvs32 ixgbe_start_hw_generic(struct ixgbe_hw *hw) 379171384Sjfv{ 380238149Sjfv s32 ret_val; 381171384Sjfv u32 ctrl_ext; 382171384Sjfv 383200239Sjfv DEBUGFUNC("ixgbe_start_hw_generic"); 384200239Sjfv 385171384Sjfv /* Set the media type */ 386179055Sjfv hw->phy.media_type = hw->mac.ops.get_media_type(hw); 387171384Sjfv 388190873Sjfv /* PHY ops initialization must be done in reset_hw() */ 389171384Sjfv 390171384Sjfv /* Clear the VLAN filter table */ 391179055Sjfv hw->mac.ops.clear_vfta(hw); 392171384Sjfv 393171384Sjfv /* Clear statistics registers */ 394179055Sjfv hw->mac.ops.clear_hw_cntrs(hw); 395171384Sjfv 396171384Sjfv /* Set No Snoop Disable */ 397171384Sjfv ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT); 398171384Sjfv ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS; 399171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext); 400179055Sjfv IXGBE_WRITE_FLUSH(hw); 401171384Sjfv 402190873Sjfv /* Setup flow control */ 403238149Sjfv ret_val = ixgbe_setup_fc(hw); 404238149Sjfv if (ret_val != IXGBE_SUCCESS) 405238149Sjfv goto out; 406190873Sjfv 407171384Sjfv /* Clear adapter stopped flag */ 408171384Sjfv hw->adapter_stopped = FALSE; 409171384Sjfv 410238149Sjfvout: 411238149Sjfv return ret_val; 412171384Sjfv} 413171384Sjfv 414171384Sjfv/** 415215911Sjfv * ixgbe_start_hw_gen2 - Init sequence for common device family 416215911Sjfv * @hw: pointer to hw structure 417215911Sjfv * 418215911Sjfv * Performs the init sequence common to the second generation 419215911Sjfv * of 10 GbE devices. 420215911Sjfv * Devices in the second generation: 421215911Sjfv * 82599 422217593Sjfv * X540 423215911Sjfv **/ 424215911Sjfvs32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw) 425215911Sjfv{ 426215911Sjfv u32 i; 427215911Sjfv u32 regval; 428215911Sjfv 429215911Sjfv /* Clear the rate limiters */ 430215911Sjfv for (i = 0; i < hw->mac.max_tx_queues; i++) { 431215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i); 432215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0); 433215911Sjfv } 434215911Sjfv IXGBE_WRITE_FLUSH(hw); 435215911Sjfv 436215911Sjfv /* Disable relaxed ordering */ 437215911Sjfv for (i = 0; i < hw->mac.max_tx_queues; i++) { 438215911Sjfv regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 439238149Sjfv regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN; 440215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 441215911Sjfv } 442215911Sjfv 443215911Sjfv for (i = 0; i < hw->mac.max_rx_queues; i++) { 444215911Sjfv regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 445238149Sjfv regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN | 446238149Sjfv IXGBE_DCA_RXCTRL_HEAD_WRO_EN); 447215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 448215911Sjfv } 449215911Sjfv 450215911Sjfv return IXGBE_SUCCESS; 451215911Sjfv} 452215911Sjfv 453215911Sjfv/** 454171384Sjfv * ixgbe_init_hw_generic - Generic hardware initialization 455171384Sjfv * @hw: pointer to hardware structure 456171384Sjfv * 457179055Sjfv * Initialize the hardware by resetting the hardware, filling the bus info 458171384Sjfv * structure and media type, clears all on chip counters, initializes receive 459171384Sjfv * address registers, multicast table, VLAN filter table, calls routine to set 460171384Sjfv * up link and flow control settings, and leaves transmit and receive units 461171384Sjfv * disabled and uninitialized 462171384Sjfv **/ 463171384Sjfvs32 ixgbe_init_hw_generic(struct ixgbe_hw *hw) 464171384Sjfv{ 465215911Sjfv s32 status; 466190873Sjfv 467200239Sjfv DEBUGFUNC("ixgbe_init_hw_generic"); 468200239Sjfv 469171384Sjfv /* Reset the hardware */ 470190873Sjfv status = hw->mac.ops.reset_hw(hw); 471171384Sjfv 472190873Sjfv if (status == IXGBE_SUCCESS) { 473190873Sjfv /* Start the HW */ 474190873Sjfv status = hw->mac.ops.start_hw(hw); 475190873Sjfv } 476171384Sjfv 477190873Sjfv return status; 478171384Sjfv} 479171384Sjfv 480171384Sjfv/** 481171384Sjfv * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters 482171384Sjfv * @hw: pointer to hardware structure 483171384Sjfv * 484171384Sjfv * Clears all hardware statistics counters by reading them from the hardware 485171384Sjfv * Statistics counters are clear on read. 486171384Sjfv **/ 487171384Sjfvs32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw) 488171384Sjfv{ 489171384Sjfv u16 i = 0; 490171384Sjfv 491200239Sjfv DEBUGFUNC("ixgbe_clear_hw_cntrs_generic"); 492200239Sjfv 493171384Sjfv IXGBE_READ_REG(hw, IXGBE_CRCERRS); 494171384Sjfv IXGBE_READ_REG(hw, IXGBE_ILLERRC); 495171384Sjfv IXGBE_READ_REG(hw, IXGBE_ERRBC); 496171384Sjfv IXGBE_READ_REG(hw, IXGBE_MSPDC); 497171384Sjfv for (i = 0; i < 8; i++) 498171384Sjfv IXGBE_READ_REG(hw, IXGBE_MPC(i)); 499171384Sjfv 500171384Sjfv IXGBE_READ_REG(hw, IXGBE_MLFC); 501171384Sjfv IXGBE_READ_REG(hw, IXGBE_MRFC); 502171384Sjfv IXGBE_READ_REG(hw, IXGBE_RLEC); 503171384Sjfv IXGBE_READ_REG(hw, IXGBE_LXONTXC); 504185352Sjfv IXGBE_READ_REG(hw, IXGBE_LXOFFTXC); 505190873Sjfv if (hw->mac.type >= ixgbe_mac_82599EB) { 506190873Sjfv IXGBE_READ_REG(hw, IXGBE_LXONRXCNT); 507190873Sjfv IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT); 508190873Sjfv } else { 509190873Sjfv IXGBE_READ_REG(hw, IXGBE_LXONRXC); 510190873Sjfv IXGBE_READ_REG(hw, IXGBE_LXOFFRXC); 511190873Sjfv } 512171384Sjfv 513171384Sjfv for (i = 0; i < 8; i++) { 514171384Sjfv IXGBE_READ_REG(hw, IXGBE_PXONTXC(i)); 515185352Sjfv IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i)); 516190873Sjfv if (hw->mac.type >= ixgbe_mac_82599EB) { 517190873Sjfv IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i)); 518190873Sjfv IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i)); 519190873Sjfv } else { 520190873Sjfv IXGBE_READ_REG(hw, IXGBE_PXONRXC(i)); 521190873Sjfv IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i)); 522190873Sjfv } 523171384Sjfv } 524190873Sjfv if (hw->mac.type >= ixgbe_mac_82599EB) 525190873Sjfv for (i = 0; i < 8; i++) 526190873Sjfv IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i)); 527171384Sjfv IXGBE_READ_REG(hw, IXGBE_PRC64); 528171384Sjfv IXGBE_READ_REG(hw, IXGBE_PRC127); 529171384Sjfv IXGBE_READ_REG(hw, IXGBE_PRC255); 530171384Sjfv IXGBE_READ_REG(hw, IXGBE_PRC511); 531171384Sjfv IXGBE_READ_REG(hw, IXGBE_PRC1023); 532171384Sjfv IXGBE_READ_REG(hw, IXGBE_PRC1522); 533171384Sjfv IXGBE_READ_REG(hw, IXGBE_GPRC); 534171384Sjfv IXGBE_READ_REG(hw, IXGBE_BPRC); 535171384Sjfv IXGBE_READ_REG(hw, IXGBE_MPRC); 536171384Sjfv IXGBE_READ_REG(hw, IXGBE_GPTC); 537171384Sjfv IXGBE_READ_REG(hw, IXGBE_GORCL); 538171384Sjfv IXGBE_READ_REG(hw, IXGBE_GORCH); 539171384Sjfv IXGBE_READ_REG(hw, IXGBE_GOTCL); 540171384Sjfv IXGBE_READ_REG(hw, IXGBE_GOTCH); 541230775Sjfv if (hw->mac.type == ixgbe_mac_82598EB) 542230775Sjfv for (i = 0; i < 8; i++) 543230775Sjfv IXGBE_READ_REG(hw, IXGBE_RNBC(i)); 544171384Sjfv IXGBE_READ_REG(hw, IXGBE_RUC); 545171384Sjfv IXGBE_READ_REG(hw, IXGBE_RFC); 546171384Sjfv IXGBE_READ_REG(hw, IXGBE_ROC); 547171384Sjfv IXGBE_READ_REG(hw, IXGBE_RJC); 548171384Sjfv IXGBE_READ_REG(hw, IXGBE_MNGPRC); 549171384Sjfv IXGBE_READ_REG(hw, IXGBE_MNGPDC); 550171384Sjfv IXGBE_READ_REG(hw, IXGBE_MNGPTC); 551171384Sjfv IXGBE_READ_REG(hw, IXGBE_TORL); 552171384Sjfv IXGBE_READ_REG(hw, IXGBE_TORH); 553171384Sjfv IXGBE_READ_REG(hw, IXGBE_TPR); 554171384Sjfv IXGBE_READ_REG(hw, IXGBE_TPT); 555171384Sjfv IXGBE_READ_REG(hw, IXGBE_PTC64); 556171384Sjfv IXGBE_READ_REG(hw, IXGBE_PTC127); 557171384Sjfv IXGBE_READ_REG(hw, IXGBE_PTC255); 558171384Sjfv IXGBE_READ_REG(hw, IXGBE_PTC511); 559171384Sjfv IXGBE_READ_REG(hw, IXGBE_PTC1023); 560171384Sjfv IXGBE_READ_REG(hw, IXGBE_PTC1522); 561171384Sjfv IXGBE_READ_REG(hw, IXGBE_MPTC); 562171384Sjfv IXGBE_READ_REG(hw, IXGBE_BPTC); 563171384Sjfv for (i = 0; i < 16; i++) { 564171384Sjfv IXGBE_READ_REG(hw, IXGBE_QPRC(i)); 565171384Sjfv IXGBE_READ_REG(hw, IXGBE_QPTC(i)); 566215911Sjfv if (hw->mac.type >= ixgbe_mac_82599EB) { 567215911Sjfv IXGBE_READ_REG(hw, IXGBE_QBRC_L(i)); 568215911Sjfv IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); 569215911Sjfv IXGBE_READ_REG(hw, IXGBE_QBTC_L(i)); 570215911Sjfv IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); 571215911Sjfv IXGBE_READ_REG(hw, IXGBE_QPRDC(i)); 572215911Sjfv } else { 573215911Sjfv IXGBE_READ_REG(hw, IXGBE_QBRC(i)); 574215911Sjfv IXGBE_READ_REG(hw, IXGBE_QBTC(i)); 575215911Sjfv } 576171384Sjfv } 577171384Sjfv 578230775Sjfv if (hw->mac.type == ixgbe_mac_X540) { 579230775Sjfv if (hw->phy.id == 0) 580230775Sjfv ixgbe_identify_phy(hw); 581230775Sjfv hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, 582230775Sjfv IXGBE_MDIO_PCS_DEV_TYPE, &i); 583230775Sjfv hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, 584230775Sjfv IXGBE_MDIO_PCS_DEV_TYPE, &i); 585230775Sjfv hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, 586230775Sjfv IXGBE_MDIO_PCS_DEV_TYPE, &i); 587230775Sjfv hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, 588230775Sjfv IXGBE_MDIO_PCS_DEV_TYPE, &i); 589230775Sjfv } 590230775Sjfv 591171384Sjfv return IXGBE_SUCCESS; 592171384Sjfv} 593171384Sjfv 594171384Sjfv/** 595215911Sjfv * ixgbe_read_pba_string_generic - Reads part number string from EEPROM 596215911Sjfv * @hw: pointer to hardware structure 597215911Sjfv * @pba_num: stores the part number string from the EEPROM 598215911Sjfv * @pba_num_size: part number string buffer length 599215911Sjfv * 600215911Sjfv * Reads the part number string from the EEPROM. 601215911Sjfv **/ 602215911Sjfvs32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num, 603230775Sjfv u32 pba_num_size) 604215911Sjfv{ 605215911Sjfv s32 ret_val; 606215911Sjfv u16 data; 607215911Sjfv u16 pba_ptr; 608215911Sjfv u16 offset; 609215911Sjfv u16 length; 610215911Sjfv 611215911Sjfv DEBUGFUNC("ixgbe_read_pba_string_generic"); 612215911Sjfv 613215911Sjfv if (pba_num == NULL) { 614215911Sjfv DEBUGOUT("PBA string buffer was null\n"); 615215911Sjfv return IXGBE_ERR_INVALID_ARGUMENT; 616215911Sjfv } 617215911Sjfv 618215911Sjfv ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 619215911Sjfv if (ret_val) { 620215911Sjfv DEBUGOUT("NVM Read Error\n"); 621215911Sjfv return ret_val; 622215911Sjfv } 623215911Sjfv 624215911Sjfv ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr); 625215911Sjfv if (ret_val) { 626215911Sjfv DEBUGOUT("NVM Read Error\n"); 627215911Sjfv return ret_val; 628215911Sjfv } 629215911Sjfv 630215911Sjfv /* 631215911Sjfv * if data is not ptr guard the PBA must be in legacy format which 632215911Sjfv * means pba_ptr is actually our second data word for the PBA number 633215911Sjfv * and we can decode it into an ascii string 634215911Sjfv */ 635215911Sjfv if (data != IXGBE_PBANUM_PTR_GUARD) { 636215911Sjfv DEBUGOUT("NVM PBA number is not stored as string\n"); 637215911Sjfv 638215911Sjfv /* we will need 11 characters to store the PBA */ 639215911Sjfv if (pba_num_size < 11) { 640215911Sjfv DEBUGOUT("PBA string buffer too small\n"); 641215911Sjfv return IXGBE_ERR_NO_SPACE; 642215911Sjfv } 643215911Sjfv 644215911Sjfv /* extract hex string from data and pba_ptr */ 645215911Sjfv pba_num[0] = (data >> 12) & 0xF; 646215911Sjfv pba_num[1] = (data >> 8) & 0xF; 647215911Sjfv pba_num[2] = (data >> 4) & 0xF; 648215911Sjfv pba_num[3] = data & 0xF; 649215911Sjfv pba_num[4] = (pba_ptr >> 12) & 0xF; 650215911Sjfv pba_num[5] = (pba_ptr >> 8) & 0xF; 651215911Sjfv pba_num[6] = '-'; 652215911Sjfv pba_num[7] = 0; 653215911Sjfv pba_num[8] = (pba_ptr >> 4) & 0xF; 654215911Sjfv pba_num[9] = pba_ptr & 0xF; 655215911Sjfv 656215911Sjfv /* put a null character on the end of our string */ 657215911Sjfv pba_num[10] = '\0'; 658215911Sjfv 659215911Sjfv /* switch all the data but the '-' to hex char */ 660215911Sjfv for (offset = 0; offset < 10; offset++) { 661215911Sjfv if (pba_num[offset] < 0xA) 662215911Sjfv pba_num[offset] += '0'; 663215911Sjfv else if (pba_num[offset] < 0x10) 664215911Sjfv pba_num[offset] += 'A' - 0xA; 665215911Sjfv } 666215911Sjfv 667215911Sjfv return IXGBE_SUCCESS; 668215911Sjfv } 669215911Sjfv 670215911Sjfv ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length); 671215911Sjfv if (ret_val) { 672215911Sjfv DEBUGOUT("NVM Read Error\n"); 673215911Sjfv return ret_val; 674215911Sjfv } 675215911Sjfv 676215911Sjfv if (length == 0xFFFF || length == 0) { 677215911Sjfv DEBUGOUT("NVM PBA number section invalid length\n"); 678215911Sjfv return IXGBE_ERR_PBA_SECTION; 679215911Sjfv } 680215911Sjfv 681215911Sjfv /* check if pba_num buffer is big enough */ 682215911Sjfv if (pba_num_size < (((u32)length * 2) - 1)) { 683215911Sjfv DEBUGOUT("PBA string buffer too small\n"); 684215911Sjfv return IXGBE_ERR_NO_SPACE; 685215911Sjfv } 686215911Sjfv 687215911Sjfv /* trim pba length from start of string */ 688215911Sjfv pba_ptr++; 689215911Sjfv length--; 690215911Sjfv 691215911Sjfv for (offset = 0; offset < length; offset++) { 692215911Sjfv ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data); 693215911Sjfv if (ret_val) { 694215911Sjfv DEBUGOUT("NVM Read Error\n"); 695215911Sjfv return ret_val; 696215911Sjfv } 697215911Sjfv pba_num[offset * 2] = (u8)(data >> 8); 698215911Sjfv pba_num[(offset * 2) + 1] = (u8)(data & 0xFF); 699215911Sjfv } 700215911Sjfv pba_num[offset * 2] = '\0'; 701215911Sjfv 702215911Sjfv return IXGBE_SUCCESS; 703215911Sjfv} 704215911Sjfv 705215911Sjfv/** 706185352Sjfv * ixgbe_read_pba_num_generic - Reads part number from EEPROM 707179055Sjfv * @hw: pointer to hardware structure 708179055Sjfv * @pba_num: stores the part number from the EEPROM 709179055Sjfv * 710179055Sjfv * Reads the part number from the EEPROM. 711179055Sjfv **/ 712179055Sjfvs32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num) 713179055Sjfv{ 714179055Sjfv s32 ret_val; 715179055Sjfv u16 data; 716179055Sjfv 717179055Sjfv DEBUGFUNC("ixgbe_read_pba_num_generic"); 718179055Sjfv 719179055Sjfv ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data); 720179055Sjfv if (ret_val) { 721179055Sjfv DEBUGOUT("NVM Read Error\n"); 722179055Sjfv return ret_val; 723215911Sjfv } else if (data == IXGBE_PBANUM_PTR_GUARD) { 724215911Sjfv DEBUGOUT("NVM Not supported\n"); 725215911Sjfv return IXGBE_NOT_IMPLEMENTED; 726179055Sjfv } 727179055Sjfv *pba_num = (u32)(data << 16); 728179055Sjfv 729179055Sjfv ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data); 730179055Sjfv if (ret_val) { 731179055Sjfv DEBUGOUT("NVM Read Error\n"); 732179055Sjfv return ret_val; 733179055Sjfv } 734179055Sjfv *pba_num |= data; 735179055Sjfv 736179055Sjfv return IXGBE_SUCCESS; 737179055Sjfv} 738179055Sjfv 739179055Sjfv/** 740247822Sjfv * ixgbe_read_pba_raw 741247822Sjfv * @hw: pointer to the HW structure 742247822Sjfv * @eeprom_buf: optional pointer to EEPROM image 743247822Sjfv * @eeprom_buf_size: size of EEPROM image in words 744247822Sjfv * @max_pba_block_size: PBA block size limit 745247822Sjfv * @pba: pointer to output PBA structure 746247822Sjfv * 747247822Sjfv * Reads PBA from EEPROM image when eeprom_buf is not NULL. 748247822Sjfv * Reads PBA from physical EEPROM device when eeprom_buf is NULL. 749247822Sjfv * 750247822Sjfv **/ 751247822Sjfvs32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf, 752247822Sjfv u32 eeprom_buf_size, u16 max_pba_block_size, 753247822Sjfv struct ixgbe_pba *pba) 754247822Sjfv{ 755247822Sjfv s32 ret_val; 756247822Sjfv u16 pba_block_size; 757247822Sjfv 758247822Sjfv if (pba == NULL) 759247822Sjfv return IXGBE_ERR_PARAM; 760247822Sjfv 761247822Sjfv if (eeprom_buf == NULL) { 762247822Sjfv ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2, 763247822Sjfv &pba->word[0]); 764247822Sjfv if (ret_val) 765247822Sjfv return ret_val; 766247822Sjfv } else { 767247822Sjfv if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 768247822Sjfv pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR]; 769247822Sjfv pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR]; 770247822Sjfv } else { 771247822Sjfv return IXGBE_ERR_PARAM; 772247822Sjfv } 773247822Sjfv } 774247822Sjfv 775247822Sjfv if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) { 776247822Sjfv if (pba->pba_block == NULL) 777247822Sjfv return IXGBE_ERR_PARAM; 778247822Sjfv 779247822Sjfv ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf, 780247822Sjfv eeprom_buf_size, 781247822Sjfv &pba_block_size); 782247822Sjfv if (ret_val) 783247822Sjfv return ret_val; 784247822Sjfv 785247822Sjfv if (pba_block_size > max_pba_block_size) 786247822Sjfv return IXGBE_ERR_PARAM; 787247822Sjfv 788247822Sjfv if (eeprom_buf == NULL) { 789247822Sjfv ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1], 790247822Sjfv pba_block_size, 791247822Sjfv pba->pba_block); 792247822Sjfv if (ret_val) 793247822Sjfv return ret_val; 794247822Sjfv } else { 795247822Sjfv if (eeprom_buf_size > (u32)(pba->word[1] + 796247822Sjfv pba->pba_block[0])) { 797247822Sjfv memcpy(pba->pba_block, 798247822Sjfv &eeprom_buf[pba->word[1]], 799247822Sjfv pba_block_size * sizeof(u16)); 800247822Sjfv } else { 801247822Sjfv return IXGBE_ERR_PARAM; 802247822Sjfv } 803247822Sjfv } 804247822Sjfv } 805247822Sjfv 806247822Sjfv return IXGBE_SUCCESS; 807247822Sjfv} 808247822Sjfv 809247822Sjfv/** 810247822Sjfv * ixgbe_write_pba_raw 811247822Sjfv * @hw: pointer to the HW structure 812247822Sjfv * @eeprom_buf: optional pointer to EEPROM image 813247822Sjfv * @eeprom_buf_size: size of EEPROM image in words 814247822Sjfv * @pba: pointer to PBA structure 815247822Sjfv * 816247822Sjfv * Writes PBA to EEPROM image when eeprom_buf is not NULL. 817247822Sjfv * Writes PBA to physical EEPROM device when eeprom_buf is NULL. 818247822Sjfv * 819247822Sjfv **/ 820247822Sjfvs32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf, 821247822Sjfv u32 eeprom_buf_size, struct ixgbe_pba *pba) 822247822Sjfv{ 823247822Sjfv s32 ret_val; 824247822Sjfv 825247822Sjfv if (pba == NULL) 826247822Sjfv return IXGBE_ERR_PARAM; 827247822Sjfv 828247822Sjfv if (eeprom_buf == NULL) { 829247822Sjfv ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2, 830247822Sjfv &pba->word[0]); 831247822Sjfv if (ret_val) 832247822Sjfv return ret_val; 833247822Sjfv } else { 834247822Sjfv if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 835247822Sjfv eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0]; 836247822Sjfv eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1]; 837247822Sjfv } else { 838247822Sjfv return IXGBE_ERR_PARAM; 839247822Sjfv } 840247822Sjfv } 841247822Sjfv 842247822Sjfv if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) { 843247822Sjfv if (pba->pba_block == NULL) 844247822Sjfv return IXGBE_ERR_PARAM; 845247822Sjfv 846247822Sjfv if (eeprom_buf == NULL) { 847247822Sjfv ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1], 848247822Sjfv pba->pba_block[0], 849247822Sjfv pba->pba_block); 850247822Sjfv if (ret_val) 851247822Sjfv return ret_val; 852247822Sjfv } else { 853247822Sjfv if (eeprom_buf_size > (u32)(pba->word[1] + 854247822Sjfv pba->pba_block[0])) { 855247822Sjfv memcpy(&eeprom_buf[pba->word[1]], 856247822Sjfv pba->pba_block, 857247822Sjfv pba->pba_block[0] * sizeof(u16)); 858247822Sjfv } else { 859247822Sjfv return IXGBE_ERR_PARAM; 860247822Sjfv } 861247822Sjfv } 862247822Sjfv } 863247822Sjfv 864247822Sjfv return IXGBE_SUCCESS; 865247822Sjfv} 866247822Sjfv 867247822Sjfv/** 868247822Sjfv * ixgbe_get_pba_block_size 869247822Sjfv * @hw: pointer to the HW structure 870247822Sjfv * @eeprom_buf: optional pointer to EEPROM image 871247822Sjfv * @eeprom_buf_size: size of EEPROM image in words 872247822Sjfv * @pba_data_size: pointer to output variable 873247822Sjfv * 874247822Sjfv * Returns the size of the PBA block in words. Function operates on EEPROM 875247822Sjfv * image if the eeprom_buf pointer is not NULL otherwise it accesses physical 876247822Sjfv * EEPROM device. 877247822Sjfv * 878247822Sjfv **/ 879247822Sjfvs32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf, 880247822Sjfv u32 eeprom_buf_size, u16 *pba_block_size) 881247822Sjfv{ 882247822Sjfv s32 ret_val; 883247822Sjfv u16 pba_word[2]; 884247822Sjfv u16 length; 885247822Sjfv 886247822Sjfv DEBUGFUNC("ixgbe_get_pba_block_size"); 887247822Sjfv 888247822Sjfv if (eeprom_buf == NULL) { 889247822Sjfv ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2, 890247822Sjfv &pba_word[0]); 891247822Sjfv if (ret_val) 892247822Sjfv return ret_val; 893247822Sjfv } else { 894247822Sjfv if (eeprom_buf_size > IXGBE_PBANUM1_PTR) { 895247822Sjfv pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR]; 896247822Sjfv pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR]; 897247822Sjfv } else { 898247822Sjfv return IXGBE_ERR_PARAM; 899247822Sjfv } 900247822Sjfv } 901247822Sjfv 902247822Sjfv if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) { 903247822Sjfv if (eeprom_buf == NULL) { 904247822Sjfv ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0, 905247822Sjfv &length); 906247822Sjfv if (ret_val) 907247822Sjfv return ret_val; 908247822Sjfv } else { 909247822Sjfv if (eeprom_buf_size > pba_word[1]) 910247822Sjfv length = eeprom_buf[pba_word[1] + 0]; 911247822Sjfv else 912247822Sjfv return IXGBE_ERR_PARAM; 913247822Sjfv } 914247822Sjfv 915247822Sjfv if (length == 0xFFFF || length == 0) 916247822Sjfv return IXGBE_ERR_PBA_SECTION; 917247822Sjfv } else { 918247822Sjfv /* PBA number in legacy format, there is no PBA Block. */ 919247822Sjfv length = 0; 920247822Sjfv } 921247822Sjfv 922247822Sjfv if (pba_block_size != NULL) 923247822Sjfv *pba_block_size = length; 924247822Sjfv 925247822Sjfv return IXGBE_SUCCESS; 926247822Sjfv} 927247822Sjfv 928247822Sjfv/** 929171384Sjfv * ixgbe_get_mac_addr_generic - Generic get MAC address 930171384Sjfv * @hw: pointer to hardware structure 931171384Sjfv * @mac_addr: Adapter MAC address 932171384Sjfv * 933171384Sjfv * Reads the adapter's MAC address from first Receive Address Register (RAR0) 934171384Sjfv * A reset of the adapter must be performed prior to calling this function 935171384Sjfv * in order for the MAC address to have been loaded from the EEPROM into RAR0 936171384Sjfv **/ 937171384Sjfvs32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr) 938171384Sjfv{ 939171384Sjfv u32 rar_high; 940171384Sjfv u32 rar_low; 941171384Sjfv u16 i; 942171384Sjfv 943200239Sjfv DEBUGFUNC("ixgbe_get_mac_addr_generic"); 944200239Sjfv 945171384Sjfv rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0)); 946171384Sjfv rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0)); 947171384Sjfv 948171384Sjfv for (i = 0; i < 4; i++) 949171384Sjfv mac_addr[i] = (u8)(rar_low >> (i*8)); 950171384Sjfv 951171384Sjfv for (i = 0; i < 2; i++) 952171384Sjfv mac_addr[i+4] = (u8)(rar_high >> (i*8)); 953171384Sjfv 954171384Sjfv return IXGBE_SUCCESS; 955171384Sjfv} 956171384Sjfv 957171384Sjfv/** 958251964Sjfv * ixgbe_set_pci_config_data_generic - Generic store PCI bus info 959171384Sjfv * @hw: pointer to hardware structure 960251964Sjfv * @link_status: the link status returned by the PCI config space 961171384Sjfv * 962251964Sjfv * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure 963171384Sjfv **/ 964251964Sjfvvoid ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status) 965171384Sjfv{ 966185352Sjfv struct ixgbe_mac_info *mac = &hw->mac; 967171384Sjfv 968171384Sjfv hw->bus.type = ixgbe_bus_type_pci_express; 969171384Sjfv 970171384Sjfv switch (link_status & IXGBE_PCI_LINK_WIDTH) { 971171384Sjfv case IXGBE_PCI_LINK_WIDTH_1: 972171384Sjfv hw->bus.width = ixgbe_bus_width_pcie_x1; 973171384Sjfv break; 974171384Sjfv case IXGBE_PCI_LINK_WIDTH_2: 975171384Sjfv hw->bus.width = ixgbe_bus_width_pcie_x2; 976171384Sjfv break; 977171384Sjfv case IXGBE_PCI_LINK_WIDTH_4: 978171384Sjfv hw->bus.width = ixgbe_bus_width_pcie_x4; 979171384Sjfv break; 980171384Sjfv case IXGBE_PCI_LINK_WIDTH_8: 981171384Sjfv hw->bus.width = ixgbe_bus_width_pcie_x8; 982171384Sjfv break; 983171384Sjfv default: 984171384Sjfv hw->bus.width = ixgbe_bus_width_unknown; 985171384Sjfv break; 986171384Sjfv } 987171384Sjfv 988171384Sjfv switch (link_status & IXGBE_PCI_LINK_SPEED) { 989171384Sjfv case IXGBE_PCI_LINK_SPEED_2500: 990171384Sjfv hw->bus.speed = ixgbe_bus_speed_2500; 991171384Sjfv break; 992171384Sjfv case IXGBE_PCI_LINK_SPEED_5000: 993171384Sjfv hw->bus.speed = ixgbe_bus_speed_5000; 994171384Sjfv break; 995238149Sjfv case IXGBE_PCI_LINK_SPEED_8000: 996238149Sjfv hw->bus.speed = ixgbe_bus_speed_8000; 997238149Sjfv break; 998171384Sjfv default: 999171384Sjfv hw->bus.speed = ixgbe_bus_speed_unknown; 1000171384Sjfv break; 1001171384Sjfv } 1002171384Sjfv 1003185352Sjfv mac->ops.set_lan_id(hw); 1004251964Sjfv} 1005185352Sjfv 1006251964Sjfv/** 1007251964Sjfv * ixgbe_get_bus_info_generic - Generic set PCI bus info 1008251964Sjfv * @hw: pointer to hardware structure 1009251964Sjfv * 1010251964Sjfv * Gets the PCI bus info (speed, width, type) then calls helper function to 1011251964Sjfv * store this data within the ixgbe_hw structure. 1012251964Sjfv **/ 1013251964Sjfvs32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw) 1014251964Sjfv{ 1015251964Sjfv u16 link_status; 1016251964Sjfv 1017251964Sjfv DEBUGFUNC("ixgbe_get_bus_info_generic"); 1018251964Sjfv 1019251964Sjfv /* Get the negotiated link width and speed from PCI config space */ 1020251964Sjfv link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS); 1021251964Sjfv 1022251964Sjfv ixgbe_set_pci_config_data_generic(hw, link_status); 1023251964Sjfv 1024171384Sjfv return IXGBE_SUCCESS; 1025171384Sjfv} 1026171384Sjfv 1027171384Sjfv/** 1028185352Sjfv * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 1029185352Sjfv * @hw: pointer to the HW structure 1030185352Sjfv * 1031185352Sjfv * Determines the LAN function id by reading memory-mapped registers 1032185352Sjfv * and swaps the port value if requested. 1033185352Sjfv **/ 1034185352Sjfvvoid ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw) 1035185352Sjfv{ 1036185352Sjfv struct ixgbe_bus_info *bus = &hw->bus; 1037185352Sjfv u32 reg; 1038185352Sjfv 1039200239Sjfv DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie"); 1040200239Sjfv 1041185352Sjfv reg = IXGBE_READ_REG(hw, IXGBE_STATUS); 1042185352Sjfv bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT; 1043190873Sjfv bus->lan_id = bus->func; 1044185352Sjfv 1045185352Sjfv /* check for a port swap */ 1046185352Sjfv reg = IXGBE_READ_REG(hw, IXGBE_FACTPS); 1047185352Sjfv if (reg & IXGBE_FACTPS_LFS) 1048185352Sjfv bus->func ^= 0x1; 1049185352Sjfv} 1050185352Sjfv 1051185352Sjfv/** 1052179055Sjfv * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units 1053171384Sjfv * @hw: pointer to hardware structure 1054171384Sjfv * 1055171384Sjfv * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 1056171384Sjfv * disables transmit and receive units. The adapter_stopped flag is used by 1057171384Sjfv * the shared code and drivers to determine if the adapter is in a stopped 1058171384Sjfv * state and should not touch the hardware. 1059171384Sjfv **/ 1060171384Sjfvs32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw) 1061171384Sjfv{ 1062171384Sjfv u32 reg_val; 1063171384Sjfv u16 i; 1064171384Sjfv 1065200239Sjfv DEBUGFUNC("ixgbe_stop_adapter_generic"); 1066200239Sjfv 1067171384Sjfv /* 1068171384Sjfv * Set the adapter_stopped flag so other driver functions stop touching 1069171384Sjfv * the hardware 1070171384Sjfv */ 1071171384Sjfv hw->adapter_stopped = TRUE; 1072171384Sjfv 1073171384Sjfv /* Disable the receive unit */ 1074230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, 0); 1075171384Sjfv 1076230775Sjfv /* Clear interrupt mask to stop interrupts from being generated */ 1077171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK); 1078171384Sjfv 1079230775Sjfv /* Clear any pending interrupts, flush previous writes */ 1080171384Sjfv IXGBE_READ_REG(hw, IXGBE_EICR); 1081171384Sjfv 1082171384Sjfv /* Disable the transmit unit. Each queue must be disabled. */ 1083230775Sjfv for (i = 0; i < hw->mac.max_tx_queues; i++) 1084230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH); 1085230775Sjfv 1086230775Sjfv /* Disable the receive unit by stopping each queue */ 1087230775Sjfv for (i = 0; i < hw->mac.max_rx_queues; i++) { 1088230775Sjfv reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i)); 1089230775Sjfv reg_val &= ~IXGBE_RXDCTL_ENABLE; 1090230775Sjfv reg_val |= IXGBE_RXDCTL_SWFLSH; 1091230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val); 1092171384Sjfv } 1093171384Sjfv 1094230775Sjfv /* flush all queues disables */ 1095230775Sjfv IXGBE_WRITE_FLUSH(hw); 1096230775Sjfv msec_delay(2); 1097230775Sjfv 1098179055Sjfv /* 1099179055Sjfv * Prevent the PCI-E bus from from hanging by disabling PCI-E master 1100179055Sjfv * access and verify no pending requests 1101179055Sjfv */ 1102230775Sjfv return ixgbe_disable_pcie_master(hw); 1103171384Sjfv} 1104171384Sjfv 1105171384Sjfv/** 1106171384Sjfv * ixgbe_led_on_generic - Turns on the software controllable LEDs. 1107171384Sjfv * @hw: pointer to hardware structure 1108171384Sjfv * @index: led number to turn on 1109171384Sjfv **/ 1110171384Sjfvs32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index) 1111171384Sjfv{ 1112171384Sjfv u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1113171384Sjfv 1114200239Sjfv DEBUGFUNC("ixgbe_led_on_generic"); 1115200239Sjfv 1116171384Sjfv /* To turn on the LED, set mode to ON. */ 1117171384Sjfv led_reg &= ~IXGBE_LED_MODE_MASK(index); 1118171384Sjfv led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index); 1119171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 1120179055Sjfv IXGBE_WRITE_FLUSH(hw); 1121171384Sjfv 1122171384Sjfv return IXGBE_SUCCESS; 1123171384Sjfv} 1124171384Sjfv 1125171384Sjfv/** 1126171384Sjfv * ixgbe_led_off_generic - Turns off the software controllable LEDs. 1127171384Sjfv * @hw: pointer to hardware structure 1128171384Sjfv * @index: led number to turn off 1129171384Sjfv **/ 1130171384Sjfvs32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index) 1131171384Sjfv{ 1132171384Sjfv u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1133171384Sjfv 1134200239Sjfv DEBUGFUNC("ixgbe_led_off_generic"); 1135200239Sjfv 1136171384Sjfv /* To turn off the LED, set mode to OFF. */ 1137171384Sjfv led_reg &= ~IXGBE_LED_MODE_MASK(index); 1138171384Sjfv led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index); 1139171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 1140179055Sjfv IXGBE_WRITE_FLUSH(hw); 1141171384Sjfv 1142171384Sjfv return IXGBE_SUCCESS; 1143171384Sjfv} 1144171384Sjfv 1145171384Sjfv/** 1146171384Sjfv * ixgbe_init_eeprom_params_generic - Initialize EEPROM params 1147171384Sjfv * @hw: pointer to hardware structure 1148171384Sjfv * 1149171384Sjfv * Initializes the EEPROM parameters ixgbe_eeprom_info within the 1150171384Sjfv * ixgbe_hw struct in order to set up EEPROM access. 1151171384Sjfv **/ 1152171384Sjfvs32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw) 1153171384Sjfv{ 1154171384Sjfv struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 1155171384Sjfv u32 eec; 1156171384Sjfv u16 eeprom_size; 1157171384Sjfv 1158200239Sjfv DEBUGFUNC("ixgbe_init_eeprom_params_generic"); 1159200239Sjfv 1160171384Sjfv if (eeprom->type == ixgbe_eeprom_uninitialized) { 1161171384Sjfv eeprom->type = ixgbe_eeprom_none; 1162181003Sjfv /* Set default semaphore delay to 10ms which is a well 1163181003Sjfv * tested value */ 1164181003Sjfv eeprom->semaphore_delay = 10; 1165230775Sjfv /* Clear EEPROM page size, it will be initialized as needed */ 1166230775Sjfv eeprom->word_page_size = 0; 1167171384Sjfv 1168171384Sjfv /* 1169171384Sjfv * Check for EEPROM present first. 1170171384Sjfv * If not present leave as none 1171171384Sjfv */ 1172171384Sjfv eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1173171384Sjfv if (eec & IXGBE_EEC_PRES) { 1174171384Sjfv eeprom->type = ixgbe_eeprom_spi; 1175171384Sjfv 1176171384Sjfv /* 1177171384Sjfv * SPI EEPROM is assumed here. This code would need to 1178171384Sjfv * change if a future EEPROM is not SPI. 1179171384Sjfv */ 1180171384Sjfv eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 1181230775Sjfv IXGBE_EEC_SIZE_SHIFT); 1182171384Sjfv eeprom->word_size = 1 << (eeprom_size + 1183230775Sjfv IXGBE_EEPROM_WORD_SIZE_SHIFT); 1184171384Sjfv } 1185171384Sjfv 1186171384Sjfv if (eec & IXGBE_EEC_ADDR_SIZE) 1187171384Sjfv eeprom->address_bits = 16; 1188171384Sjfv else 1189171384Sjfv eeprom->address_bits = 8; 1190171384Sjfv DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: " 1191230775Sjfv "%d\n", eeprom->type, eeprom->word_size, 1192230775Sjfv eeprom->address_bits); 1193171384Sjfv } 1194171384Sjfv 1195171384Sjfv return IXGBE_SUCCESS; 1196171384Sjfv} 1197171384Sjfv 1198171384Sjfv/** 1199230775Sjfv * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang 1200171384Sjfv * @hw: pointer to hardware structure 1201230775Sjfv * @offset: offset within the EEPROM to write 1202230775Sjfv * @words: number of word(s) 1203230775Sjfv * @data: 16 bit word(s) to write to EEPROM 1204171384Sjfv * 1205230775Sjfv * Reads 16 bit word(s) from EEPROM through bit-bang method 1206171384Sjfv **/ 1207230775Sjfvs32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1208230775Sjfv u16 words, u16 *data) 1209171384Sjfv{ 1210230775Sjfv s32 status = IXGBE_SUCCESS; 1211230775Sjfv u16 i, count; 1212171384Sjfv 1213230775Sjfv DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic"); 1214200239Sjfv 1215179055Sjfv hw->eeprom.ops.init_params(hw); 1216179055Sjfv 1217230775Sjfv if (words == 0) { 1218230775Sjfv status = IXGBE_ERR_INVALID_ARGUMENT; 1219230775Sjfv goto out; 1220230775Sjfv } 1221230775Sjfv 1222230775Sjfv if (offset + words > hw->eeprom.word_size) { 1223179055Sjfv status = IXGBE_ERR_EEPROM; 1224179055Sjfv goto out; 1225179055Sjfv } 1226179055Sjfv 1227230775Sjfv /* 1228230775Sjfv * The EEPROM page size cannot be queried from the chip. We do lazy 1229230775Sjfv * initialization. It is worth to do that when we write large buffer. 1230230775Sjfv */ 1231230775Sjfv if ((hw->eeprom.word_page_size == 0) && 1232230775Sjfv (words > IXGBE_EEPROM_PAGE_SIZE_MAX)) 1233230775Sjfv ixgbe_detect_eeprom_page_size_generic(hw, offset); 1234230775Sjfv 1235230775Sjfv /* 1236230775Sjfv * We cannot hold synchronization semaphores for too long 1237230775Sjfv * to avoid other entity starvation. However it is more efficient 1238230775Sjfv * to read in bursts than synchronizing access for each word. 1239230775Sjfv */ 1240230775Sjfv for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 1241230775Sjfv count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 1242230775Sjfv IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 1243230775Sjfv status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i, 1244230775Sjfv count, &data[i]); 1245230775Sjfv 1246230775Sjfv if (status != IXGBE_SUCCESS) 1247230775Sjfv break; 1248230775Sjfv } 1249230775Sjfv 1250230775Sjfvout: 1251230775Sjfv return status; 1252230775Sjfv} 1253230775Sjfv 1254230775Sjfv/** 1255230775Sjfv * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM 1256230775Sjfv * @hw: pointer to hardware structure 1257230775Sjfv * @offset: offset within the EEPROM to be written to 1258230775Sjfv * @words: number of word(s) 1259230775Sjfv * @data: 16 bit word(s) to be written to the EEPROM 1260230775Sjfv * 1261230775Sjfv * If ixgbe_eeprom_update_checksum is not called after this function, the 1262230775Sjfv * EEPROM will most likely contain an invalid checksum. 1263230775Sjfv **/ 1264230775Sjfvstatic s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1265230775Sjfv u16 words, u16 *data) 1266230775Sjfv{ 1267230775Sjfv s32 status; 1268230775Sjfv u16 word; 1269230775Sjfv u16 page_size; 1270230775Sjfv u16 i; 1271230775Sjfv u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI; 1272230775Sjfv 1273230775Sjfv DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang"); 1274230775Sjfv 1275171384Sjfv /* Prepare the EEPROM for writing */ 1276171384Sjfv status = ixgbe_acquire_eeprom(hw); 1277171384Sjfv 1278171384Sjfv if (status == IXGBE_SUCCESS) { 1279171384Sjfv if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 1280171384Sjfv ixgbe_release_eeprom(hw); 1281171384Sjfv status = IXGBE_ERR_EEPROM; 1282171384Sjfv } 1283171384Sjfv } 1284171384Sjfv 1285171384Sjfv if (status == IXGBE_SUCCESS) { 1286230775Sjfv for (i = 0; i < words; i++) { 1287230775Sjfv ixgbe_standby_eeprom(hw); 1288171384Sjfv 1289230775Sjfv /* Send the WRITE ENABLE command (8 bit opcode ) */ 1290230775Sjfv ixgbe_shift_out_eeprom_bits(hw, 1291230775Sjfv IXGBE_EEPROM_WREN_OPCODE_SPI, 1292230775Sjfv IXGBE_EEPROM_OPCODE_BITS); 1293171384Sjfv 1294230775Sjfv ixgbe_standby_eeprom(hw); 1295171384Sjfv 1296230775Sjfv /* 1297230775Sjfv * Some SPI eeproms use the 8th address bit embedded 1298230775Sjfv * in the opcode 1299230775Sjfv */ 1300230775Sjfv if ((hw->eeprom.address_bits == 8) && 1301230775Sjfv ((offset + i) >= 128)) 1302230775Sjfv write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1303171384Sjfv 1304230775Sjfv /* Send the Write command (8-bit opcode + addr) */ 1305230775Sjfv ixgbe_shift_out_eeprom_bits(hw, write_opcode, 1306230775Sjfv IXGBE_EEPROM_OPCODE_BITS); 1307230775Sjfv ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1308230775Sjfv hw->eeprom.address_bits); 1309171384Sjfv 1310230775Sjfv page_size = hw->eeprom.word_page_size; 1311171384Sjfv 1312230775Sjfv /* Send the data in burst via SPI*/ 1313230775Sjfv do { 1314230775Sjfv word = data[i]; 1315230775Sjfv word = (word >> 8) | (word << 8); 1316230775Sjfv ixgbe_shift_out_eeprom_bits(hw, word, 16); 1317230775Sjfv 1318230775Sjfv if (page_size == 0) 1319230775Sjfv break; 1320230775Sjfv 1321230775Sjfv /* do not wrap around page */ 1322230775Sjfv if (((offset + i) & (page_size - 1)) == 1323230775Sjfv (page_size - 1)) 1324230775Sjfv break; 1325230775Sjfv } while (++i < words); 1326230775Sjfv 1327230775Sjfv ixgbe_standby_eeprom(hw); 1328230775Sjfv msec_delay(10); 1329230775Sjfv } 1330171384Sjfv /* Done with writing - release the EEPROM */ 1331171384Sjfv ixgbe_release_eeprom(hw); 1332171384Sjfv } 1333171384Sjfv 1334171384Sjfv return status; 1335171384Sjfv} 1336171384Sjfv 1337171384Sjfv/** 1338230775Sjfv * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM 1339171384Sjfv * @hw: pointer to hardware structure 1340230775Sjfv * @offset: offset within the EEPROM to be written to 1341230775Sjfv * @data: 16 bit word to be written to the EEPROM 1342171384Sjfv * 1343230775Sjfv * If ixgbe_eeprom_update_checksum is not called after this function, the 1344230775Sjfv * EEPROM will most likely contain an invalid checksum. 1345171384Sjfv **/ 1346230775Sjfvs32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1347171384Sjfv{ 1348171384Sjfv s32 status; 1349171384Sjfv 1350230775Sjfv DEBUGFUNC("ixgbe_write_eeprom_generic"); 1351200239Sjfv 1352179055Sjfv hw->eeprom.ops.init_params(hw); 1353179055Sjfv 1354179055Sjfv if (offset >= hw->eeprom.word_size) { 1355179055Sjfv status = IXGBE_ERR_EEPROM; 1356179055Sjfv goto out; 1357179055Sjfv } 1358179055Sjfv 1359230775Sjfv status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data); 1360230775Sjfv 1361230775Sjfvout: 1362230775Sjfv return status; 1363230775Sjfv} 1364230775Sjfv 1365230775Sjfv/** 1366230775Sjfv * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang 1367230775Sjfv * @hw: pointer to hardware structure 1368230775Sjfv * @offset: offset within the EEPROM to be read 1369230775Sjfv * @data: read 16 bit words(s) from EEPROM 1370230775Sjfv * @words: number of word(s) 1371230775Sjfv * 1372230775Sjfv * Reads 16 bit word(s) from EEPROM through bit-bang method 1373230775Sjfv **/ 1374230775Sjfvs32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1375230775Sjfv u16 words, u16 *data) 1376230775Sjfv{ 1377230775Sjfv s32 status = IXGBE_SUCCESS; 1378230775Sjfv u16 i, count; 1379230775Sjfv 1380230775Sjfv DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic"); 1381230775Sjfv 1382230775Sjfv hw->eeprom.ops.init_params(hw); 1383230775Sjfv 1384230775Sjfv if (words == 0) { 1385230775Sjfv status = IXGBE_ERR_INVALID_ARGUMENT; 1386230775Sjfv goto out; 1387230775Sjfv } 1388230775Sjfv 1389230775Sjfv if (offset + words > hw->eeprom.word_size) { 1390230775Sjfv status = IXGBE_ERR_EEPROM; 1391230775Sjfv goto out; 1392230775Sjfv } 1393230775Sjfv 1394230775Sjfv /* 1395230775Sjfv * We cannot hold synchronization semaphores for too long 1396230775Sjfv * to avoid other entity starvation. However it is more efficient 1397230775Sjfv * to read in bursts than synchronizing access for each word. 1398230775Sjfv */ 1399230775Sjfv for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) { 1400230775Sjfv count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ? 1401230775Sjfv IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i); 1402230775Sjfv 1403230775Sjfv status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i, 1404230775Sjfv count, &data[i]); 1405230775Sjfv 1406230775Sjfv if (status != IXGBE_SUCCESS) 1407230775Sjfv break; 1408230775Sjfv } 1409230775Sjfv 1410230775Sjfvout: 1411230775Sjfv return status; 1412230775Sjfv} 1413230775Sjfv 1414230775Sjfv/** 1415230775Sjfv * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang 1416230775Sjfv * @hw: pointer to hardware structure 1417230775Sjfv * @offset: offset within the EEPROM to be read 1418230775Sjfv * @words: number of word(s) 1419230775Sjfv * @data: read 16 bit word(s) from EEPROM 1420230775Sjfv * 1421230775Sjfv * Reads 16 bit word(s) from EEPROM through bit-bang method 1422230775Sjfv **/ 1423230775Sjfvstatic s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset, 1424230775Sjfv u16 words, u16 *data) 1425230775Sjfv{ 1426230775Sjfv s32 status; 1427230775Sjfv u16 word_in; 1428230775Sjfv u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI; 1429230775Sjfv u16 i; 1430230775Sjfv 1431230775Sjfv DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang"); 1432230775Sjfv 1433171384Sjfv /* Prepare the EEPROM for reading */ 1434171384Sjfv status = ixgbe_acquire_eeprom(hw); 1435171384Sjfv 1436171384Sjfv if (status == IXGBE_SUCCESS) { 1437171384Sjfv if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) { 1438171384Sjfv ixgbe_release_eeprom(hw); 1439171384Sjfv status = IXGBE_ERR_EEPROM; 1440171384Sjfv } 1441171384Sjfv } 1442171384Sjfv 1443171384Sjfv if (status == IXGBE_SUCCESS) { 1444230775Sjfv for (i = 0; i < words; i++) { 1445230775Sjfv ixgbe_standby_eeprom(hw); 1446230775Sjfv /* 1447230775Sjfv * Some SPI eeproms use the 8th address bit embedded 1448230775Sjfv * in the opcode 1449230775Sjfv */ 1450230775Sjfv if ((hw->eeprom.address_bits == 8) && 1451230775Sjfv ((offset + i) >= 128)) 1452230775Sjfv read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI; 1453171384Sjfv 1454230775Sjfv /* Send the READ command (opcode + addr) */ 1455230775Sjfv ixgbe_shift_out_eeprom_bits(hw, read_opcode, 1456230775Sjfv IXGBE_EEPROM_OPCODE_BITS); 1457230775Sjfv ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2), 1458230775Sjfv hw->eeprom.address_bits); 1459171384Sjfv 1460230775Sjfv /* Read the data. */ 1461230775Sjfv word_in = ixgbe_shift_in_eeprom_bits(hw, 16); 1462230775Sjfv data[i] = (word_in >> 8) | (word_in << 8); 1463230775Sjfv } 1464171384Sjfv 1465171384Sjfv /* End this read operation */ 1466171384Sjfv ixgbe_release_eeprom(hw); 1467171384Sjfv } 1468171384Sjfv 1469230775Sjfv return status; 1470230775Sjfv} 1471230775Sjfv 1472230775Sjfv/** 1473230775Sjfv * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang 1474230775Sjfv * @hw: pointer to hardware structure 1475230775Sjfv * @offset: offset within the EEPROM to be read 1476230775Sjfv * @data: read 16 bit value from EEPROM 1477230775Sjfv * 1478230775Sjfv * Reads 16 bit value from EEPROM through bit-bang method 1479230775Sjfv **/ 1480230775Sjfvs32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset, 1481230775Sjfv u16 *data) 1482230775Sjfv{ 1483230775Sjfv s32 status; 1484230775Sjfv 1485230775Sjfv DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic"); 1486230775Sjfv 1487230775Sjfv hw->eeprom.ops.init_params(hw); 1488230775Sjfv 1489230775Sjfv if (offset >= hw->eeprom.word_size) { 1490230775Sjfv status = IXGBE_ERR_EEPROM; 1491230775Sjfv goto out; 1492230775Sjfv } 1493230775Sjfv 1494230775Sjfv status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1495230775Sjfv 1496179055Sjfvout: 1497171384Sjfv return status; 1498171384Sjfv} 1499171384Sjfv 1500171384Sjfv/** 1501230775Sjfv * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD 1502171384Sjfv * @hw: pointer to hardware structure 1503230775Sjfv * @offset: offset of word in the EEPROM to read 1504230775Sjfv * @words: number of word(s) 1505230775Sjfv * @data: 16 bit word(s) from the EEPROM 1506171384Sjfv * 1507230775Sjfv * Reads a 16 bit word(s) from the EEPROM using the EERD register. 1508171384Sjfv **/ 1509230775Sjfvs32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1510230775Sjfv u16 words, u16 *data) 1511171384Sjfv{ 1512171384Sjfv u32 eerd; 1513230775Sjfv s32 status = IXGBE_SUCCESS; 1514230775Sjfv u32 i; 1515171384Sjfv 1516230775Sjfv DEBUGFUNC("ixgbe_read_eerd_buffer_generic"); 1517200239Sjfv 1518179055Sjfv hw->eeprom.ops.init_params(hw); 1519179055Sjfv 1520230775Sjfv if (words == 0) { 1521230775Sjfv status = IXGBE_ERR_INVALID_ARGUMENT; 1522251964Sjfv ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words"); 1523230775Sjfv goto out; 1524230775Sjfv } 1525230775Sjfv 1526179055Sjfv if (offset >= hw->eeprom.word_size) { 1527179055Sjfv status = IXGBE_ERR_EEPROM; 1528251964Sjfv ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset"); 1529179055Sjfv goto out; 1530179055Sjfv } 1531179055Sjfv 1532230775Sjfv for (i = 0; i < words; i++) { 1533247822Sjfv eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1534230775Sjfv IXGBE_EEPROM_RW_REG_START; 1535171384Sjfv 1536230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd); 1537230775Sjfv status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ); 1538171384Sjfv 1539230775Sjfv if (status == IXGBE_SUCCESS) { 1540230775Sjfv data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >> 1541230775Sjfv IXGBE_EEPROM_RW_REG_DATA); 1542230775Sjfv } else { 1543230775Sjfv DEBUGOUT("Eeprom read timed out\n"); 1544230775Sjfv goto out; 1545230775Sjfv } 1546230775Sjfv } 1547230775Sjfvout: 1548230775Sjfv return status; 1549230775Sjfv} 1550171384Sjfv 1551230775Sjfv/** 1552230775Sjfv * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size 1553230775Sjfv * @hw: pointer to hardware structure 1554230775Sjfv * @offset: offset within the EEPROM to be used as a scratch pad 1555230775Sjfv * 1556230775Sjfv * Discover EEPROM page size by writing marching data at given offset. 1557230775Sjfv * This function is called only when we are writing a new large buffer 1558230775Sjfv * at given offset so the data would be overwritten anyway. 1559230775Sjfv **/ 1560230775Sjfvstatic s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw, 1561230775Sjfv u16 offset) 1562230775Sjfv{ 1563230775Sjfv u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX]; 1564230775Sjfv s32 status = IXGBE_SUCCESS; 1565230775Sjfv u16 i; 1566230775Sjfv 1567230775Sjfv DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic"); 1568230775Sjfv 1569230775Sjfv for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++) 1570230775Sjfv data[i] = i; 1571230775Sjfv 1572230775Sjfv hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX; 1573230775Sjfv status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1574230775Sjfv IXGBE_EEPROM_PAGE_SIZE_MAX, data); 1575230775Sjfv hw->eeprom.word_page_size = 0; 1576230775Sjfv if (status != IXGBE_SUCCESS) 1577230775Sjfv goto out; 1578230775Sjfv 1579230775Sjfv status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data); 1580230775Sjfv if (status != IXGBE_SUCCESS) 1581230775Sjfv goto out; 1582230775Sjfv 1583230775Sjfv /* 1584230775Sjfv * When writing in burst more than the actual page size 1585230775Sjfv * EEPROM address wraps around current page. 1586230775Sjfv */ 1587230775Sjfv hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0]; 1588230775Sjfv 1589230775Sjfv DEBUGOUT1("Detected EEPROM page size = %d words.", 1590230775Sjfv hw->eeprom.word_page_size); 1591179055Sjfvout: 1592171384Sjfv return status; 1593171384Sjfv} 1594171384Sjfv 1595171384Sjfv/** 1596230775Sjfv * ixgbe_read_eerd_generic - Read EEPROM word using EERD 1597215911Sjfv * @hw: pointer to hardware structure 1598230775Sjfv * @offset: offset of word in the EEPROM to read 1599230775Sjfv * @data: word read from the EEPROM 1600230775Sjfv * 1601230775Sjfv * Reads a 16 bit word from the EEPROM using the EERD register. 1602230775Sjfv **/ 1603230775Sjfvs32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data) 1604230775Sjfv{ 1605230775Sjfv return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data); 1606230775Sjfv} 1607230775Sjfv 1608230775Sjfv/** 1609230775Sjfv * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR 1610230775Sjfv * @hw: pointer to hardware structure 1611215911Sjfv * @offset: offset of word in the EEPROM to write 1612230775Sjfv * @words: number of word(s) 1613230775Sjfv * @data: word(s) write to the EEPROM 1614215911Sjfv * 1615230775Sjfv * Write a 16 bit word(s) to the EEPROM using the EEWR register. 1616215911Sjfv **/ 1617230775Sjfvs32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset, 1618230775Sjfv u16 words, u16 *data) 1619215911Sjfv{ 1620215911Sjfv u32 eewr; 1621230775Sjfv s32 status = IXGBE_SUCCESS; 1622230775Sjfv u16 i; 1623215911Sjfv 1624215911Sjfv DEBUGFUNC("ixgbe_write_eewr_generic"); 1625215911Sjfv 1626215911Sjfv hw->eeprom.ops.init_params(hw); 1627215911Sjfv 1628230775Sjfv if (words == 0) { 1629230775Sjfv status = IXGBE_ERR_INVALID_ARGUMENT; 1630251964Sjfv ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words"); 1631230775Sjfv goto out; 1632230775Sjfv } 1633230775Sjfv 1634215911Sjfv if (offset >= hw->eeprom.word_size) { 1635215911Sjfv status = IXGBE_ERR_EEPROM; 1636251964Sjfv ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset"); 1637215911Sjfv goto out; 1638215911Sjfv } 1639215911Sjfv 1640230775Sjfv for (i = 0; i < words; i++) { 1641230775Sjfv eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) | 1642230775Sjfv (data[i] << IXGBE_EEPROM_RW_REG_DATA) | 1643230775Sjfv IXGBE_EEPROM_RW_REG_START; 1644215911Sjfv 1645230775Sjfv status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1646230775Sjfv if (status != IXGBE_SUCCESS) { 1647230775Sjfv DEBUGOUT("Eeprom write EEWR timed out\n"); 1648230775Sjfv goto out; 1649230775Sjfv } 1650215911Sjfv 1651230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr); 1652215911Sjfv 1653230775Sjfv status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE); 1654230775Sjfv if (status != IXGBE_SUCCESS) { 1655230775Sjfv DEBUGOUT("Eeprom write EEWR timed out\n"); 1656230775Sjfv goto out; 1657230775Sjfv } 1658215911Sjfv } 1659215911Sjfv 1660215911Sjfvout: 1661215911Sjfv return status; 1662215911Sjfv} 1663215911Sjfv 1664215911Sjfv/** 1665230775Sjfv * ixgbe_write_eewr_generic - Write EEPROM word using EEWR 1666230775Sjfv * @hw: pointer to hardware structure 1667230775Sjfv * @offset: offset of word in the EEPROM to write 1668230775Sjfv * @data: word write to the EEPROM 1669230775Sjfv * 1670230775Sjfv * Write a 16 bit word to the EEPROM using the EEWR register. 1671230775Sjfv **/ 1672230775Sjfvs32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data) 1673230775Sjfv{ 1674230775Sjfv return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data); 1675230775Sjfv} 1676230775Sjfv 1677230775Sjfv/** 1678200239Sjfv * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status 1679171384Sjfv * @hw: pointer to hardware structure 1680200239Sjfv * @ee_reg: EEPROM flag for polling 1681171384Sjfv * 1682200239Sjfv * Polls the status bit (bit 1) of the EERD or EEWR to determine when the 1683200239Sjfv * read or write is done respectively. 1684171384Sjfv **/ 1685200239Sjfvs32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg) 1686171384Sjfv{ 1687171384Sjfv u32 i; 1688171384Sjfv u32 reg; 1689171384Sjfv s32 status = IXGBE_ERR_EEPROM; 1690171384Sjfv 1691200239Sjfv DEBUGFUNC("ixgbe_poll_eerd_eewr_done"); 1692200239Sjfv 1693200239Sjfv for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) { 1694200239Sjfv if (ee_reg == IXGBE_NVM_POLL_READ) 1695200239Sjfv reg = IXGBE_READ_REG(hw, IXGBE_EERD); 1696200239Sjfv else 1697200239Sjfv reg = IXGBE_READ_REG(hw, IXGBE_EEWR); 1698200239Sjfv 1699200239Sjfv if (reg & IXGBE_EEPROM_RW_REG_DONE) { 1700171384Sjfv status = IXGBE_SUCCESS; 1701171384Sjfv break; 1702171384Sjfv } 1703171384Sjfv usec_delay(5); 1704171384Sjfv } 1705251964Sjfv 1706251964Sjfv if (i == IXGBE_EERD_EEWR_ATTEMPTS) 1707251964Sjfv ERROR_REPORT1(IXGBE_ERROR_POLLING, 1708251964Sjfv "EEPROM read/write done polling timed out"); 1709251964Sjfv 1710171384Sjfv return status; 1711171384Sjfv} 1712171384Sjfv 1713171384Sjfv/** 1714171384Sjfv * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang 1715171384Sjfv * @hw: pointer to hardware structure 1716171384Sjfv * 1717171384Sjfv * Prepares EEPROM for access using bit-bang method. This function should 1718171384Sjfv * be called before issuing a command to the EEPROM. 1719171384Sjfv **/ 1720171384Sjfvstatic s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw) 1721171384Sjfv{ 1722171384Sjfv s32 status = IXGBE_SUCCESS; 1723171384Sjfv u32 eec; 1724171384Sjfv u32 i; 1725171384Sjfv 1726200239Sjfv DEBUGFUNC("ixgbe_acquire_eeprom"); 1727200239Sjfv 1728230775Sjfv if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) 1729230775Sjfv != IXGBE_SUCCESS) 1730171384Sjfv status = IXGBE_ERR_SWFW_SYNC; 1731171384Sjfv 1732171384Sjfv if (status == IXGBE_SUCCESS) { 1733171384Sjfv eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1734171384Sjfv 1735171384Sjfv /* Request EEPROM Access */ 1736171384Sjfv eec |= IXGBE_EEC_REQ; 1737171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1738171384Sjfv 1739171384Sjfv for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) { 1740171384Sjfv eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1741171384Sjfv if (eec & IXGBE_EEC_GNT) 1742171384Sjfv break; 1743171384Sjfv usec_delay(5); 1744171384Sjfv } 1745171384Sjfv 1746179055Sjfv /* Release if grant not acquired */ 1747171384Sjfv if (!(eec & IXGBE_EEC_GNT)) { 1748171384Sjfv eec &= ~IXGBE_EEC_REQ; 1749171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1750171384Sjfv DEBUGOUT("Could not acquire EEPROM grant\n"); 1751171384Sjfv 1752230775Sjfv hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 1753171384Sjfv status = IXGBE_ERR_EEPROM; 1754171384Sjfv } 1755171384Sjfv 1756215911Sjfv /* Setup EEPROM for Read/Write */ 1757215911Sjfv if (status == IXGBE_SUCCESS) { 1758215911Sjfv /* Clear CS and SK */ 1759215911Sjfv eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK); 1760215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1761215911Sjfv IXGBE_WRITE_FLUSH(hw); 1762215911Sjfv usec_delay(1); 1763215911Sjfv } 1764171384Sjfv } 1765171384Sjfv return status; 1766171384Sjfv} 1767171384Sjfv 1768171384Sjfv/** 1769171384Sjfv * ixgbe_get_eeprom_semaphore - Get hardware semaphore 1770171384Sjfv * @hw: pointer to hardware structure 1771171384Sjfv * 1772171384Sjfv * Sets the hardware semaphores so EEPROM access can occur for bit-bang method 1773171384Sjfv **/ 1774171384Sjfvstatic s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw) 1775171384Sjfv{ 1776171384Sjfv s32 status = IXGBE_ERR_EEPROM; 1777194875Sjfv u32 timeout = 2000; 1778171384Sjfv u32 i; 1779171384Sjfv u32 swsm; 1780171384Sjfv 1781200239Sjfv DEBUGFUNC("ixgbe_get_eeprom_semaphore"); 1782200239Sjfv 1783215911Sjfv 1784171384Sjfv /* Get SMBI software semaphore between device drivers first */ 1785171384Sjfv for (i = 0; i < timeout; i++) { 1786171384Sjfv /* 1787171384Sjfv * If the SMBI bit is 0 when we read it, then the bit will be 1788171384Sjfv * set and we have the semaphore 1789171384Sjfv */ 1790171384Sjfv swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1791171384Sjfv if (!(swsm & IXGBE_SWSM_SMBI)) { 1792171384Sjfv status = IXGBE_SUCCESS; 1793171384Sjfv break; 1794171384Sjfv } 1795190873Sjfv usec_delay(50); 1796171384Sjfv } 1797171384Sjfv 1798230775Sjfv if (i == timeout) { 1799230775Sjfv DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore " 1800230775Sjfv "not granted.\n"); 1801230775Sjfv /* 1802230775Sjfv * this release is particularly important because our attempts 1803230775Sjfv * above to get the semaphore may have succeeded, and if there 1804230775Sjfv * was a timeout, we should unconditionally clear the semaphore 1805230775Sjfv * bits to free the driver to make progress 1806230775Sjfv */ 1807230775Sjfv ixgbe_release_eeprom_semaphore(hw); 1808230775Sjfv 1809230775Sjfv usec_delay(50); 1810230775Sjfv /* 1811230775Sjfv * one last try 1812230775Sjfv * If the SMBI bit is 0 when we read it, then the bit will be 1813230775Sjfv * set and we have the semaphore 1814230775Sjfv */ 1815230775Sjfv swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1816230775Sjfv if (!(swsm & IXGBE_SWSM_SMBI)) 1817230775Sjfv status = IXGBE_SUCCESS; 1818230775Sjfv } 1819230775Sjfv 1820171384Sjfv /* Now get the semaphore between SW/FW through the SWESMBI bit */ 1821171384Sjfv if (status == IXGBE_SUCCESS) { 1822171384Sjfv for (i = 0; i < timeout; i++) { 1823171384Sjfv swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1824171384Sjfv 1825171384Sjfv /* Set the SW EEPROM semaphore bit to request access */ 1826171384Sjfv swsm |= IXGBE_SWSM_SWESMBI; 1827171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 1828171384Sjfv 1829171384Sjfv /* 1830171384Sjfv * If we set the bit successfully then we got the 1831171384Sjfv * semaphore. 1832171384Sjfv */ 1833171384Sjfv swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1834171384Sjfv if (swsm & IXGBE_SWSM_SWESMBI) 1835171384Sjfv break; 1836171384Sjfv 1837171384Sjfv usec_delay(50); 1838171384Sjfv } 1839171384Sjfv 1840171384Sjfv /* 1841171384Sjfv * Release semaphores and return error if SW EEPROM semaphore 1842171384Sjfv * was not granted because we don't have access to the EEPROM 1843171384Sjfv */ 1844171384Sjfv if (i >= timeout) { 1845251964Sjfv ERROR_REPORT1(IXGBE_ERROR_POLLING, 1846251964Sjfv "SWESMBI Software EEPROM semaphore not granted.\n"); 1847171384Sjfv ixgbe_release_eeprom_semaphore(hw); 1848171384Sjfv status = IXGBE_ERR_EEPROM; 1849171384Sjfv } 1850190873Sjfv } else { 1851251964Sjfv ERROR_REPORT1(IXGBE_ERROR_POLLING, 1852251964Sjfv "Software semaphore SMBI between device drivers " 1853251964Sjfv "not granted.\n"); 1854171384Sjfv } 1855171384Sjfv 1856171384Sjfv return status; 1857171384Sjfv} 1858171384Sjfv 1859171384Sjfv/** 1860171384Sjfv * ixgbe_release_eeprom_semaphore - Release hardware semaphore 1861171384Sjfv * @hw: pointer to hardware structure 1862171384Sjfv * 1863171384Sjfv * This function clears hardware semaphore bits. 1864171384Sjfv **/ 1865171384Sjfvstatic void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw) 1866171384Sjfv{ 1867171384Sjfv u32 swsm; 1868171384Sjfv 1869200239Sjfv DEBUGFUNC("ixgbe_release_eeprom_semaphore"); 1870200239Sjfv 1871171384Sjfv swsm = IXGBE_READ_REG(hw, IXGBE_SWSM); 1872171384Sjfv 1873171384Sjfv /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */ 1874171384Sjfv swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI); 1875171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm); 1876179055Sjfv IXGBE_WRITE_FLUSH(hw); 1877171384Sjfv} 1878171384Sjfv 1879171384Sjfv/** 1880171384Sjfv * ixgbe_ready_eeprom - Polls for EEPROM ready 1881171384Sjfv * @hw: pointer to hardware structure 1882171384Sjfv **/ 1883171384Sjfvstatic s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw) 1884171384Sjfv{ 1885171384Sjfv s32 status = IXGBE_SUCCESS; 1886171384Sjfv u16 i; 1887171384Sjfv u8 spi_stat_reg; 1888171384Sjfv 1889200239Sjfv DEBUGFUNC("ixgbe_ready_eeprom"); 1890200239Sjfv 1891171384Sjfv /* 1892171384Sjfv * Read "Status Register" repeatedly until the LSB is cleared. The 1893171384Sjfv * EEPROM will signal that the command has been completed by clearing 1894171384Sjfv * bit 0 of the internal status register. If it's not cleared within 1895171384Sjfv * 5 milliseconds, then error out. 1896171384Sjfv */ 1897171384Sjfv for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) { 1898171384Sjfv ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI, 1899230775Sjfv IXGBE_EEPROM_OPCODE_BITS); 1900171384Sjfv spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8); 1901171384Sjfv if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI)) 1902171384Sjfv break; 1903171384Sjfv 1904171384Sjfv usec_delay(5); 1905171384Sjfv ixgbe_standby_eeprom(hw); 1906171384Sjfv }; 1907171384Sjfv 1908171384Sjfv /* 1909171384Sjfv * On some parts, SPI write time could vary from 0-20mSec on 3.3V 1910171384Sjfv * devices (and only 0-5mSec on 5V devices) 1911171384Sjfv */ 1912171384Sjfv if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) { 1913171384Sjfv DEBUGOUT("SPI EEPROM Status error\n"); 1914171384Sjfv status = IXGBE_ERR_EEPROM; 1915171384Sjfv } 1916171384Sjfv 1917171384Sjfv return status; 1918171384Sjfv} 1919171384Sjfv 1920171384Sjfv/** 1921171384Sjfv * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state 1922171384Sjfv * @hw: pointer to hardware structure 1923171384Sjfv **/ 1924171384Sjfvstatic void ixgbe_standby_eeprom(struct ixgbe_hw *hw) 1925171384Sjfv{ 1926171384Sjfv u32 eec; 1927171384Sjfv 1928200239Sjfv DEBUGFUNC("ixgbe_standby_eeprom"); 1929200239Sjfv 1930171384Sjfv eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1931171384Sjfv 1932171384Sjfv /* Toggle CS to flush commands */ 1933171384Sjfv eec |= IXGBE_EEC_CS; 1934171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1935171384Sjfv IXGBE_WRITE_FLUSH(hw); 1936171384Sjfv usec_delay(1); 1937171384Sjfv eec &= ~IXGBE_EEC_CS; 1938171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1939171384Sjfv IXGBE_WRITE_FLUSH(hw); 1940171384Sjfv usec_delay(1); 1941171384Sjfv} 1942171384Sjfv 1943171384Sjfv/** 1944171384Sjfv * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM. 1945171384Sjfv * @hw: pointer to hardware structure 1946171384Sjfv * @data: data to send to the EEPROM 1947171384Sjfv * @count: number of bits to shift out 1948171384Sjfv **/ 1949171384Sjfvstatic void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data, 1950230775Sjfv u16 count) 1951171384Sjfv{ 1952171384Sjfv u32 eec; 1953171384Sjfv u32 mask; 1954171384Sjfv u32 i; 1955171384Sjfv 1956200239Sjfv DEBUGFUNC("ixgbe_shift_out_eeprom_bits"); 1957200239Sjfv 1958171384Sjfv eec = IXGBE_READ_REG(hw, IXGBE_EEC); 1959171384Sjfv 1960171384Sjfv /* 1961171384Sjfv * Mask is used to shift "count" bits of "data" out to the EEPROM 1962171384Sjfv * one bit at a time. Determine the starting bit based on count 1963171384Sjfv */ 1964171384Sjfv mask = 0x01 << (count - 1); 1965171384Sjfv 1966171384Sjfv for (i = 0; i < count; i++) { 1967171384Sjfv /* 1968171384Sjfv * A "1" is shifted out to the EEPROM by setting bit "DI" to a 1969171384Sjfv * "1", and then raising and then lowering the clock (the SK 1970171384Sjfv * bit controls the clock input to the EEPROM). A "0" is 1971171384Sjfv * shifted out to the EEPROM by setting "DI" to "0" and then 1972171384Sjfv * raising and then lowering the clock. 1973171384Sjfv */ 1974171384Sjfv if (data & mask) 1975171384Sjfv eec |= IXGBE_EEC_DI; 1976171384Sjfv else 1977171384Sjfv eec &= ~IXGBE_EEC_DI; 1978171384Sjfv 1979171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1980171384Sjfv IXGBE_WRITE_FLUSH(hw); 1981171384Sjfv 1982171384Sjfv usec_delay(1); 1983171384Sjfv 1984171384Sjfv ixgbe_raise_eeprom_clk(hw, &eec); 1985171384Sjfv ixgbe_lower_eeprom_clk(hw, &eec); 1986171384Sjfv 1987171384Sjfv /* 1988171384Sjfv * Shift mask to signify next bit of data to shift in to the 1989171384Sjfv * EEPROM 1990171384Sjfv */ 1991171384Sjfv mask = mask >> 1; 1992171384Sjfv }; 1993171384Sjfv 1994171384Sjfv /* We leave the "DI" bit set to "0" when we leave this routine. */ 1995171384Sjfv eec &= ~IXGBE_EEC_DI; 1996171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 1997171384Sjfv IXGBE_WRITE_FLUSH(hw); 1998171384Sjfv} 1999171384Sjfv 2000171384Sjfv/** 2001171384Sjfv * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM 2002171384Sjfv * @hw: pointer to hardware structure 2003171384Sjfv **/ 2004171384Sjfvstatic u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count) 2005171384Sjfv{ 2006171384Sjfv u32 eec; 2007171384Sjfv u32 i; 2008171384Sjfv u16 data = 0; 2009171384Sjfv 2010200239Sjfv DEBUGFUNC("ixgbe_shift_in_eeprom_bits"); 2011200239Sjfv 2012171384Sjfv /* 2013171384Sjfv * In order to read a register from the EEPROM, we need to shift 2014171384Sjfv * 'count' bits in from the EEPROM. Bits are "shifted in" by raising 2015171384Sjfv * the clock input to the EEPROM (setting the SK bit), and then reading 2016171384Sjfv * the value of the "DO" bit. During this "shifting in" process the 2017171384Sjfv * "DI" bit should always be clear. 2018171384Sjfv */ 2019171384Sjfv eec = IXGBE_READ_REG(hw, IXGBE_EEC); 2020171384Sjfv 2021171384Sjfv eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI); 2022171384Sjfv 2023171384Sjfv for (i = 0; i < count; i++) { 2024171384Sjfv data = data << 1; 2025171384Sjfv ixgbe_raise_eeprom_clk(hw, &eec); 2026171384Sjfv 2027171384Sjfv eec = IXGBE_READ_REG(hw, IXGBE_EEC); 2028171384Sjfv 2029171384Sjfv eec &= ~(IXGBE_EEC_DI); 2030171384Sjfv if (eec & IXGBE_EEC_DO) 2031171384Sjfv data |= 1; 2032171384Sjfv 2033171384Sjfv ixgbe_lower_eeprom_clk(hw, &eec); 2034171384Sjfv } 2035171384Sjfv 2036171384Sjfv return data; 2037171384Sjfv} 2038171384Sjfv 2039171384Sjfv/** 2040171384Sjfv * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input. 2041171384Sjfv * @hw: pointer to hardware structure 2042171384Sjfv * @eec: EEC register's current value 2043171384Sjfv **/ 2044171384Sjfvstatic void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 2045171384Sjfv{ 2046200239Sjfv DEBUGFUNC("ixgbe_raise_eeprom_clk"); 2047200239Sjfv 2048171384Sjfv /* 2049171384Sjfv * Raise the clock input to the EEPROM 2050171384Sjfv * (setting the SK bit), then delay 2051171384Sjfv */ 2052171384Sjfv *eec = *eec | IXGBE_EEC_SK; 2053171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 2054171384Sjfv IXGBE_WRITE_FLUSH(hw); 2055171384Sjfv usec_delay(1); 2056171384Sjfv} 2057171384Sjfv 2058171384Sjfv/** 2059171384Sjfv * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input. 2060171384Sjfv * @hw: pointer to hardware structure 2061171384Sjfv * @eecd: EECD's current value 2062171384Sjfv **/ 2063171384Sjfvstatic void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec) 2064171384Sjfv{ 2065200239Sjfv DEBUGFUNC("ixgbe_lower_eeprom_clk"); 2066200239Sjfv 2067171384Sjfv /* 2068171384Sjfv * Lower the clock input to the EEPROM (clearing the SK bit), then 2069171384Sjfv * delay 2070171384Sjfv */ 2071171384Sjfv *eec = *eec & ~IXGBE_EEC_SK; 2072171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec); 2073171384Sjfv IXGBE_WRITE_FLUSH(hw); 2074171384Sjfv usec_delay(1); 2075171384Sjfv} 2076171384Sjfv 2077171384Sjfv/** 2078171384Sjfv * ixgbe_release_eeprom - Release EEPROM, release semaphores 2079171384Sjfv * @hw: pointer to hardware structure 2080171384Sjfv **/ 2081171384Sjfvstatic void ixgbe_release_eeprom(struct ixgbe_hw *hw) 2082171384Sjfv{ 2083171384Sjfv u32 eec; 2084171384Sjfv 2085200239Sjfv DEBUGFUNC("ixgbe_release_eeprom"); 2086200239Sjfv 2087171384Sjfv eec = IXGBE_READ_REG(hw, IXGBE_EEC); 2088171384Sjfv 2089171384Sjfv eec |= IXGBE_EEC_CS; /* Pull CS high */ 2090171384Sjfv eec &= ~IXGBE_EEC_SK; /* Lower SCK */ 2091171384Sjfv 2092171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 2093171384Sjfv IXGBE_WRITE_FLUSH(hw); 2094171384Sjfv 2095171384Sjfv usec_delay(1); 2096171384Sjfv 2097171384Sjfv /* Stop requesting EEPROM access */ 2098171384Sjfv eec &= ~IXGBE_EEC_REQ; 2099171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_EEC, eec); 2100171384Sjfv 2101230775Sjfv hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2102194875Sjfv 2103194875Sjfv /* Delay before attempt to obtain semaphore again to allow FW access */ 2104194875Sjfv msec_delay(hw->eeprom.semaphore_delay); 2105171384Sjfv} 2106171384Sjfv 2107171384Sjfv/** 2108200239Sjfv * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum 2109171384Sjfv * @hw: pointer to hardware structure 2110171384Sjfv **/ 2111200239Sjfvu16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw) 2112171384Sjfv{ 2113171384Sjfv u16 i; 2114171384Sjfv u16 j; 2115171384Sjfv u16 checksum = 0; 2116171384Sjfv u16 length = 0; 2117171384Sjfv u16 pointer = 0; 2118171384Sjfv u16 word = 0; 2119171384Sjfv 2120200239Sjfv DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic"); 2121200239Sjfv 2122171384Sjfv /* Include 0x0-0x3F in the checksum */ 2123171384Sjfv for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 2124179055Sjfv if (hw->eeprom.ops.read(hw, i, &word) != IXGBE_SUCCESS) { 2125171384Sjfv DEBUGOUT("EEPROM read failed\n"); 2126171384Sjfv break; 2127171384Sjfv } 2128171384Sjfv checksum += word; 2129171384Sjfv } 2130171384Sjfv 2131171384Sjfv /* Include all data from pointers except for the fw pointer */ 2132171384Sjfv for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) { 2133179055Sjfv hw->eeprom.ops.read(hw, i, &pointer); 2134171384Sjfv 2135171384Sjfv /* Make sure the pointer seems valid */ 2136171384Sjfv if (pointer != 0xFFFF && pointer != 0) { 2137179055Sjfv hw->eeprom.ops.read(hw, pointer, &length); 2138171384Sjfv 2139171384Sjfv if (length != 0xFFFF && length != 0) { 2140171384Sjfv for (j = pointer+1; j <= pointer+length; j++) { 2141179055Sjfv hw->eeprom.ops.read(hw, j, &word); 2142171384Sjfv checksum += word; 2143171384Sjfv } 2144171384Sjfv } 2145171384Sjfv } 2146171384Sjfv } 2147171384Sjfv 2148171384Sjfv checksum = (u16)IXGBE_EEPROM_SUM - checksum; 2149171384Sjfv 2150171384Sjfv return checksum; 2151171384Sjfv} 2152171384Sjfv 2153171384Sjfv/** 2154171384Sjfv * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum 2155171384Sjfv * @hw: pointer to hardware structure 2156171384Sjfv * @checksum_val: calculated checksum 2157171384Sjfv * 2158171384Sjfv * Performs checksum calculation and validates the EEPROM checksum. If the 2159171384Sjfv * caller does not need checksum_val, the value can be NULL. 2160171384Sjfv **/ 2161171384Sjfvs32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw, 2162230775Sjfv u16 *checksum_val) 2163171384Sjfv{ 2164171384Sjfv s32 status; 2165171384Sjfv u16 checksum; 2166171384Sjfv u16 read_checksum = 0; 2167171384Sjfv 2168200239Sjfv DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic"); 2169200239Sjfv 2170171384Sjfv /* 2171171384Sjfv * Read the first word from the EEPROM. If this times out or fails, do 2172171384Sjfv * not continue or we could be in for a very long wait while every 2173171384Sjfv * EEPROM read fails 2174171384Sjfv */ 2175179055Sjfv status = hw->eeprom.ops.read(hw, 0, &checksum); 2176171384Sjfv 2177171384Sjfv if (status == IXGBE_SUCCESS) { 2178200239Sjfv checksum = hw->eeprom.ops.calc_checksum(hw); 2179171384Sjfv 2180179055Sjfv hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum); 2181171384Sjfv 2182171384Sjfv /* 2183171384Sjfv * Verify read checksum from EEPROM is the same as 2184171384Sjfv * calculated checksum 2185171384Sjfv */ 2186179055Sjfv if (read_checksum != checksum) 2187171384Sjfv status = IXGBE_ERR_EEPROM_CHECKSUM; 2188171384Sjfv 2189171384Sjfv /* If the user cares, return the calculated checksum */ 2190179055Sjfv if (checksum_val) 2191171384Sjfv *checksum_val = checksum; 2192171384Sjfv } else { 2193171384Sjfv DEBUGOUT("EEPROM read failed\n"); 2194171384Sjfv } 2195171384Sjfv 2196171384Sjfv return status; 2197171384Sjfv} 2198171384Sjfv 2199171384Sjfv/** 2200179055Sjfv * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum 2201171384Sjfv * @hw: pointer to hardware structure 2202171384Sjfv **/ 2203171384Sjfvs32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw) 2204171384Sjfv{ 2205171384Sjfv s32 status; 2206171384Sjfv u16 checksum; 2207171384Sjfv 2208200239Sjfv DEBUGFUNC("ixgbe_update_eeprom_checksum_generic"); 2209200239Sjfv 2210171384Sjfv /* 2211171384Sjfv * Read the first word from the EEPROM. If this times out or fails, do 2212171384Sjfv * not continue or we could be in for a very long wait while every 2213171384Sjfv * EEPROM read fails 2214171384Sjfv */ 2215179055Sjfv status = hw->eeprom.ops.read(hw, 0, &checksum); 2216171384Sjfv 2217171384Sjfv if (status == IXGBE_SUCCESS) { 2218200239Sjfv checksum = hw->eeprom.ops.calc_checksum(hw); 2219179055Sjfv status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, 2220230775Sjfv checksum); 2221171384Sjfv } else { 2222171384Sjfv DEBUGOUT("EEPROM read failed\n"); 2223171384Sjfv } 2224171384Sjfv 2225171384Sjfv return status; 2226171384Sjfv} 2227171384Sjfv 2228171384Sjfv/** 2229171384Sjfv * ixgbe_validate_mac_addr - Validate MAC address 2230171384Sjfv * @mac_addr: pointer to MAC address. 2231171384Sjfv * 2232171384Sjfv * Tests a MAC address to ensure it is a valid Individual Address 2233171384Sjfv **/ 2234171384Sjfvs32 ixgbe_validate_mac_addr(u8 *mac_addr) 2235171384Sjfv{ 2236171384Sjfv s32 status = IXGBE_SUCCESS; 2237171384Sjfv 2238200239Sjfv DEBUGFUNC("ixgbe_validate_mac_addr"); 2239200239Sjfv 2240171384Sjfv /* Make sure it is not a multicast address */ 2241171384Sjfv if (IXGBE_IS_MULTICAST(mac_addr)) { 2242171384Sjfv DEBUGOUT("MAC address is multicast\n"); 2243171384Sjfv status = IXGBE_ERR_INVALID_MAC_ADDR; 2244171384Sjfv /* Not a broadcast address */ 2245171384Sjfv } else if (IXGBE_IS_BROADCAST(mac_addr)) { 2246171384Sjfv DEBUGOUT("MAC address is broadcast\n"); 2247171384Sjfv status = IXGBE_ERR_INVALID_MAC_ADDR; 2248171384Sjfv /* Reject the zero address */ 2249171384Sjfv } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 && 2250230775Sjfv mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) { 2251171384Sjfv DEBUGOUT("MAC address is all zeros\n"); 2252171384Sjfv status = IXGBE_ERR_INVALID_MAC_ADDR; 2253171384Sjfv } 2254171384Sjfv return status; 2255171384Sjfv} 2256171384Sjfv 2257171384Sjfv/** 2258179055Sjfv * ixgbe_set_rar_generic - Set Rx address register 2259171384Sjfv * @hw: pointer to hardware structure 2260179055Sjfv * @index: Receive address register to write 2261171384Sjfv * @addr: Address to put into receive address register 2262179055Sjfv * @vmdq: VMDq "set" or "pool" index 2263171384Sjfv * @enable_addr: set flag that address is active 2264171384Sjfv * 2265171384Sjfv * Puts an ethernet address into a receive address register. 2266171384Sjfv **/ 2267179055Sjfvs32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 2268230775Sjfv u32 enable_addr) 2269171384Sjfv{ 2270171384Sjfv u32 rar_low, rar_high; 2271179055Sjfv u32 rar_entries = hw->mac.num_rar_entries; 2272171384Sjfv 2273200239Sjfv DEBUGFUNC("ixgbe_set_rar_generic"); 2274200239Sjfv 2275215911Sjfv /* Make sure we are using a valid rar index range */ 2276215911Sjfv if (index >= rar_entries) { 2277251964Sjfv ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 2278251964Sjfv "RAR index %d is out of range.\n", index); 2279215911Sjfv return IXGBE_ERR_INVALID_ARGUMENT; 2280215911Sjfv } 2281215911Sjfv 2282179055Sjfv /* setup VMDq pool selection before this RAR gets enabled */ 2283179055Sjfv hw->mac.ops.set_vmdq(hw, index, vmdq); 2284171384Sjfv 2285215911Sjfv /* 2286215911Sjfv * HW expects these in little endian so we reverse the byte 2287215911Sjfv * order from network order (big endian) to little endian 2288215911Sjfv */ 2289215911Sjfv rar_low = ((u32)addr[0] | 2290230775Sjfv ((u32)addr[1] << 8) | 2291230775Sjfv ((u32)addr[2] << 16) | 2292230775Sjfv ((u32)addr[3] << 24)); 2293215911Sjfv /* 2294215911Sjfv * Some parts put the VMDq setting in the extra RAH bits, 2295215911Sjfv * so save everything except the lower 16 bits that hold part 2296215911Sjfv * of the address and the address valid bit. 2297215911Sjfv */ 2298215911Sjfv rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 2299215911Sjfv rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 2300215911Sjfv rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8)); 2301171384Sjfv 2302215911Sjfv if (enable_addr != 0) 2303215911Sjfv rar_high |= IXGBE_RAH_AV; 2304171384Sjfv 2305215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low); 2306215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 2307171384Sjfv 2308171384Sjfv return IXGBE_SUCCESS; 2309171384Sjfv} 2310171384Sjfv 2311171384Sjfv/** 2312181003Sjfv * ixgbe_clear_rar_generic - Remove Rx address register 2313181003Sjfv * @hw: pointer to hardware structure 2314181003Sjfv * @index: Receive address register to write 2315181003Sjfv * 2316181003Sjfv * Clears an ethernet address from a receive address register. 2317181003Sjfv **/ 2318181003Sjfvs32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index) 2319181003Sjfv{ 2320181003Sjfv u32 rar_high; 2321181003Sjfv u32 rar_entries = hw->mac.num_rar_entries; 2322181003Sjfv 2323200239Sjfv DEBUGFUNC("ixgbe_clear_rar_generic"); 2324200239Sjfv 2325181003Sjfv /* Make sure we are using a valid rar index range */ 2326215911Sjfv if (index >= rar_entries) { 2327251964Sjfv ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 2328251964Sjfv "RAR index %d is out of range.\n", index); 2329215911Sjfv return IXGBE_ERR_INVALID_ARGUMENT; 2330181003Sjfv } 2331181003Sjfv 2332215911Sjfv /* 2333215911Sjfv * Some parts put the VMDq setting in the extra RAH bits, 2334215911Sjfv * so save everything except the lower 16 bits that hold part 2335215911Sjfv * of the address and the address valid bit. 2336215911Sjfv */ 2337215911Sjfv rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index)); 2338215911Sjfv rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV); 2339215911Sjfv 2340215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0); 2341215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high); 2342215911Sjfv 2343181003Sjfv /* clear VMDq pool/queue selection for this RAR */ 2344181003Sjfv hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL); 2345181003Sjfv 2346181003Sjfv return IXGBE_SUCCESS; 2347181003Sjfv} 2348181003Sjfv 2349181003Sjfv/** 2350171384Sjfv * ixgbe_init_rx_addrs_generic - Initializes receive address filters. 2351171384Sjfv * @hw: pointer to hardware structure 2352171384Sjfv * 2353171384Sjfv * Places the MAC address in receive address register 0 and clears the rest 2354179055Sjfv * of the receive address registers. Clears the multicast table. Assumes 2355171384Sjfv * the receiver is in reset when the routine is called. 2356171384Sjfv **/ 2357171384Sjfvs32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw) 2358171384Sjfv{ 2359171384Sjfv u32 i; 2360179055Sjfv u32 rar_entries = hw->mac.num_rar_entries; 2361171384Sjfv 2362200239Sjfv DEBUGFUNC("ixgbe_init_rx_addrs_generic"); 2363200239Sjfv 2364171384Sjfv /* 2365171384Sjfv * If the current mac address is valid, assume it is a software override 2366171384Sjfv * to the permanent address. 2367171384Sjfv * Otherwise, use the permanent address from the eeprom. 2368171384Sjfv */ 2369171384Sjfv if (ixgbe_validate_mac_addr(hw->mac.addr) == 2370171384Sjfv IXGBE_ERR_INVALID_MAC_ADDR) { 2371171384Sjfv /* Get the MAC address from the RAR0 for later reference */ 2372179055Sjfv hw->mac.ops.get_mac_addr(hw, hw->mac.addr); 2373171384Sjfv 2374171384Sjfv DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ", 2375230775Sjfv hw->mac.addr[0], hw->mac.addr[1], 2376230775Sjfv hw->mac.addr[2]); 2377171384Sjfv DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 2378230775Sjfv hw->mac.addr[4], hw->mac.addr[5]); 2379171384Sjfv } else { 2380171384Sjfv /* Setup the receive address. */ 2381171384Sjfv DEBUGOUT("Overriding MAC Address in RAR[0]\n"); 2382171384Sjfv DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ", 2383230775Sjfv hw->mac.addr[0], hw->mac.addr[1], 2384230775Sjfv hw->mac.addr[2]); 2385171384Sjfv DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3], 2386230775Sjfv hw->mac.addr[4], hw->mac.addr[5]); 2387171384Sjfv 2388179055Sjfv hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV); 2389217593Sjfv 2390217593Sjfv /* clear VMDq pool/queue selection for RAR 0 */ 2391217593Sjfv hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL); 2392171384Sjfv } 2393179055Sjfv hw->addr_ctrl.overflow_promisc = 0; 2394171384Sjfv 2395171384Sjfv hw->addr_ctrl.rar_used_count = 1; 2396171384Sjfv 2397171384Sjfv /* Zero out the other receive addresses. */ 2398179055Sjfv DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1); 2399171384Sjfv for (i = 1; i < rar_entries; i++) { 2400171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0); 2401171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0); 2402171384Sjfv } 2403171384Sjfv 2404171384Sjfv /* Clear the MTA */ 2405171384Sjfv hw->addr_ctrl.mta_in_use = 0; 2406171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2407171384Sjfv 2408171384Sjfv DEBUGOUT(" Clearing MTA\n"); 2409179055Sjfv for (i = 0; i < hw->mac.mcft_size; i++) 2410171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0); 2411171384Sjfv 2412181003Sjfv ixgbe_init_uta_tables(hw); 2413181003Sjfv 2414171384Sjfv return IXGBE_SUCCESS; 2415171384Sjfv} 2416171384Sjfv 2417171384Sjfv/** 2418179055Sjfv * ixgbe_add_uc_addr - Adds a secondary unicast address. 2419179055Sjfv * @hw: pointer to hardware structure 2420179055Sjfv * @addr: new address 2421179055Sjfv * 2422179055Sjfv * Adds it to unused receive address register or goes into promiscuous mode. 2423179055Sjfv **/ 2424179055Sjfvvoid ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 2425179055Sjfv{ 2426179055Sjfv u32 rar_entries = hw->mac.num_rar_entries; 2427179055Sjfv u32 rar; 2428179055Sjfv 2429200239Sjfv DEBUGFUNC("ixgbe_add_uc_addr"); 2430200239Sjfv 2431179055Sjfv DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n", 2432230775Sjfv addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); 2433179055Sjfv 2434179055Sjfv /* 2435179055Sjfv * Place this address in the RAR if there is room, 2436179055Sjfv * else put the controller into promiscuous mode 2437179055Sjfv */ 2438179055Sjfv if (hw->addr_ctrl.rar_used_count < rar_entries) { 2439190873Sjfv rar = hw->addr_ctrl.rar_used_count; 2440179055Sjfv hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 2441179055Sjfv DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar); 2442179055Sjfv hw->addr_ctrl.rar_used_count++; 2443179055Sjfv } else { 2444179055Sjfv hw->addr_ctrl.overflow_promisc++; 2445179055Sjfv } 2446179055Sjfv 2447179055Sjfv DEBUGOUT("ixgbe_add_uc_addr Complete\n"); 2448179055Sjfv} 2449179055Sjfv 2450179055Sjfv/** 2451179055Sjfv * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses 2452179055Sjfv * @hw: pointer to hardware structure 2453179055Sjfv * @addr_list: the list of new addresses 2454179055Sjfv * @addr_count: number of addresses 2455179055Sjfv * @next: iterator function to walk the address list 2456179055Sjfv * 2457179055Sjfv * The given list replaces any existing list. Clears the secondary addrs from 2458179055Sjfv * receive address registers. Uses unused receive address registers for the 2459179055Sjfv * first secondary addresses, and falls back to promiscuous mode as needed. 2460179055Sjfv * 2461179055Sjfv * Drivers using secondary unicast addresses must set user_set_promisc when 2462179055Sjfv * manually putting the device into promiscuous mode. 2463179055Sjfv **/ 2464179055Sjfvs32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list, 2465230775Sjfv u32 addr_count, ixgbe_mc_addr_itr next) 2466179055Sjfv{ 2467179055Sjfv u8 *addr; 2468179055Sjfv u32 i; 2469179055Sjfv u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc; 2470179055Sjfv u32 uc_addr_in_use; 2471179055Sjfv u32 fctrl; 2472179055Sjfv u32 vmdq; 2473179055Sjfv 2474200239Sjfv DEBUGFUNC("ixgbe_update_uc_addr_list_generic"); 2475200239Sjfv 2476179055Sjfv /* 2477179055Sjfv * Clear accounting of old secondary address list, 2478179055Sjfv * don't count RAR[0] 2479179055Sjfv */ 2480190873Sjfv uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1; 2481179055Sjfv hw->addr_ctrl.rar_used_count -= uc_addr_in_use; 2482179055Sjfv hw->addr_ctrl.overflow_promisc = 0; 2483179055Sjfv 2484179055Sjfv /* Zero out the other receive addresses */ 2485200239Sjfv DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1); 2486200239Sjfv for (i = 0; i < uc_addr_in_use; i++) { 2487200239Sjfv IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0); 2488200239Sjfv IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0); 2489179055Sjfv } 2490179055Sjfv 2491179055Sjfv /* Add the new addresses */ 2492179055Sjfv for (i = 0; i < addr_count; i++) { 2493179055Sjfv DEBUGOUT(" Adding the secondary addresses:\n"); 2494179055Sjfv addr = next(hw, &addr_list, &vmdq); 2495179055Sjfv ixgbe_add_uc_addr(hw, addr, vmdq); 2496179055Sjfv } 2497179055Sjfv 2498179055Sjfv if (hw->addr_ctrl.overflow_promisc) { 2499179055Sjfv /* enable promisc if not already in overflow or set by user */ 2500179055Sjfv if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 2501185352Sjfv DEBUGOUT(" Entering address overflow promisc mode\n"); 2502179055Sjfv fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 2503179055Sjfv fctrl |= IXGBE_FCTRL_UPE; 2504179055Sjfv IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 2505179055Sjfv } 2506179055Sjfv } else { 2507179055Sjfv /* only disable if set by overflow, not by user */ 2508179055Sjfv if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) { 2509179055Sjfv DEBUGOUT(" Leaving address overflow promisc mode\n"); 2510179055Sjfv fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL); 2511179055Sjfv fctrl &= ~IXGBE_FCTRL_UPE; 2512179055Sjfv IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl); 2513179055Sjfv } 2514179055Sjfv } 2515179055Sjfv 2516179055Sjfv DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n"); 2517179055Sjfv return IXGBE_SUCCESS; 2518179055Sjfv} 2519179055Sjfv 2520179055Sjfv/** 2521171384Sjfv * ixgbe_mta_vector - Determines bit-vector in multicast table to set 2522171384Sjfv * @hw: pointer to hardware structure 2523171384Sjfv * @mc_addr: the multicast address 2524171384Sjfv * 2525171384Sjfv * Extracts the 12 bits, from a multicast address, to determine which 2526171384Sjfv * bit-vector to set in the multicast table. The hardware uses 12 bits, from 2527171384Sjfv * incoming rx multicast addresses, to determine the bit-vector to check in 2528171384Sjfv * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 2529179055Sjfv * by the MO field of the MCSTCTRL. The MO field is set during initialization 2530171384Sjfv * to mc_filter_type. 2531171384Sjfv **/ 2532171384Sjfvstatic s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr) 2533171384Sjfv{ 2534171384Sjfv u32 vector = 0; 2535171384Sjfv 2536200239Sjfv DEBUGFUNC("ixgbe_mta_vector"); 2537200239Sjfv 2538171384Sjfv switch (hw->mac.mc_filter_type) { 2539179055Sjfv case 0: /* use bits [47:36] of the address */ 2540171384Sjfv vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 2541171384Sjfv break; 2542179055Sjfv case 1: /* use bits [46:35] of the address */ 2543171384Sjfv vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 2544171384Sjfv break; 2545179055Sjfv case 2: /* use bits [45:34] of the address */ 2546171384Sjfv vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 2547171384Sjfv break; 2548179055Sjfv case 3: /* use bits [43:32] of the address */ 2549171384Sjfv vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 2550171384Sjfv break; 2551179055Sjfv default: /* Invalid mc_filter_type */ 2552171384Sjfv DEBUGOUT("MC filter type param set incorrectly\n"); 2553171384Sjfv ASSERT(0); 2554171384Sjfv break; 2555171384Sjfv } 2556171384Sjfv 2557171384Sjfv /* vector can only be 12-bits or boundary will be exceeded */ 2558171384Sjfv vector &= 0xFFF; 2559171384Sjfv return vector; 2560171384Sjfv} 2561171384Sjfv 2562171384Sjfv/** 2563171384Sjfv * ixgbe_set_mta - Set bit-vector in multicast table 2564171384Sjfv * @hw: pointer to hardware structure 2565171384Sjfv * @hash_value: Multicast address hash value 2566171384Sjfv * 2567171384Sjfv * Sets the bit-vector in the multicast table. 2568171384Sjfv **/ 2569171384Sjfvvoid ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr) 2570171384Sjfv{ 2571171384Sjfv u32 vector; 2572171384Sjfv u32 vector_bit; 2573171384Sjfv u32 vector_reg; 2574171384Sjfv 2575200239Sjfv DEBUGFUNC("ixgbe_set_mta"); 2576200239Sjfv 2577171384Sjfv hw->addr_ctrl.mta_in_use++; 2578171384Sjfv 2579171384Sjfv vector = ixgbe_mta_vector(hw, mc_addr); 2580171384Sjfv DEBUGOUT1(" bit-vector = 0x%03X\n", vector); 2581171384Sjfv 2582171384Sjfv /* 2583171384Sjfv * The MTA is a register array of 128 32-bit registers. It is treated 2584171384Sjfv * like an array of 4096 bits. We want to set bit 2585171384Sjfv * BitArray[vector_value]. So we figure out what register the bit is 2586171384Sjfv * in, read it, OR in the new bit, then write back the new value. The 2587171384Sjfv * register is determined by the upper 7 bits of the vector value and 2588171384Sjfv * the bit within that register are determined by the lower 5 bits of 2589171384Sjfv * the value. 2590171384Sjfv */ 2591171384Sjfv vector_reg = (vector >> 5) & 0x7F; 2592171384Sjfv vector_bit = vector & 0x1F; 2593215911Sjfv hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit); 2594171384Sjfv} 2595171384Sjfv 2596171384Sjfv/** 2597171384Sjfv * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses 2598171384Sjfv * @hw: pointer to hardware structure 2599171384Sjfv * @mc_addr_list: the list of new multicast addresses 2600171384Sjfv * @mc_addr_count: number of addresses 2601179055Sjfv * @next: iterator function to walk the multicast address list 2602230775Sjfv * @clear: flag, when set clears the table beforehand 2603171384Sjfv * 2604230775Sjfv * When the clear flag is set, the given list replaces any existing list. 2605230775Sjfv * Hashes the given addresses into the multicast table. 2606171384Sjfv **/ 2607171384Sjfvs32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list, 2608230775Sjfv u32 mc_addr_count, ixgbe_mc_addr_itr next, 2609230775Sjfv bool clear) 2610171384Sjfv{ 2611171384Sjfv u32 i; 2612179055Sjfv u32 vmdq; 2613171384Sjfv 2614200239Sjfv DEBUGFUNC("ixgbe_update_mc_addr_list_generic"); 2615200239Sjfv 2616171384Sjfv /* 2617171384Sjfv * Set the new number of MC addresses that we are being requested to 2618171384Sjfv * use. 2619171384Sjfv */ 2620171384Sjfv hw->addr_ctrl.num_mc_addrs = mc_addr_count; 2621171384Sjfv hw->addr_ctrl.mta_in_use = 0; 2622171384Sjfv 2623215911Sjfv /* Clear mta_shadow */ 2624230775Sjfv if (clear) { 2625230775Sjfv DEBUGOUT(" Clearing MTA\n"); 2626230775Sjfv memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 2627230775Sjfv } 2628171384Sjfv 2629215911Sjfv /* Update mta_shadow */ 2630171384Sjfv for (i = 0; i < mc_addr_count; i++) { 2631171384Sjfv DEBUGOUT(" Adding the multicast addresses:\n"); 2632190873Sjfv ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq)); 2633171384Sjfv } 2634171384Sjfv 2635171384Sjfv /* Enable mta */ 2636215911Sjfv for (i = 0; i < hw->mac.mcft_size; i++) 2637215911Sjfv IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i, 2638215911Sjfv hw->mac.mta_shadow[i]); 2639215911Sjfv 2640171384Sjfv if (hw->addr_ctrl.mta_in_use > 0) 2641171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, 2642230775Sjfv IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type); 2643171384Sjfv 2644171384Sjfv DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n"); 2645171384Sjfv return IXGBE_SUCCESS; 2646171384Sjfv} 2647171384Sjfv 2648171384Sjfv/** 2649171384Sjfv * ixgbe_enable_mc_generic - Enable multicast address in RAR 2650171384Sjfv * @hw: pointer to hardware structure 2651171384Sjfv * 2652171384Sjfv * Enables multicast address in RAR and the use of the multicast hash table. 2653171384Sjfv **/ 2654171384Sjfvs32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw) 2655171384Sjfv{ 2656171384Sjfv struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2657171384Sjfv 2658200239Sjfv DEBUGFUNC("ixgbe_enable_mc_generic"); 2659200239Sjfv 2660171384Sjfv if (a->mta_in_use > 0) 2661171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE | 2662230775Sjfv hw->mac.mc_filter_type); 2663171384Sjfv 2664171384Sjfv return IXGBE_SUCCESS; 2665171384Sjfv} 2666171384Sjfv 2667171384Sjfv/** 2668179055Sjfv * ixgbe_disable_mc_generic - Disable multicast address in RAR 2669171384Sjfv * @hw: pointer to hardware structure 2670171384Sjfv * 2671171384Sjfv * Disables multicast address in RAR and the use of the multicast hash table. 2672171384Sjfv **/ 2673171384Sjfvs32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw) 2674171384Sjfv{ 2675171384Sjfv struct ixgbe_addr_filter_info *a = &hw->addr_ctrl; 2676171384Sjfv 2677200239Sjfv DEBUGFUNC("ixgbe_disable_mc_generic"); 2678200239Sjfv 2679171384Sjfv if (a->mta_in_use > 0) 2680171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type); 2681171384Sjfv 2682171384Sjfv return IXGBE_SUCCESS; 2683171384Sjfv} 2684171384Sjfv 2685171384Sjfv/** 2686190873Sjfv * ixgbe_fc_enable_generic - Enable flow control 2687185352Sjfv * @hw: pointer to hardware structure 2688185352Sjfv * 2689190873Sjfv * Enable flow control according to the current settings. 2690185352Sjfv **/ 2691238149Sjfvs32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw) 2692185352Sjfv{ 2693185352Sjfv s32 ret_val = IXGBE_SUCCESS; 2694190873Sjfv u32 mflcn_reg, fccfg_reg; 2695190873Sjfv u32 reg; 2696215911Sjfv u32 fcrtl, fcrth; 2697238149Sjfv int i; 2698185352Sjfv 2699190873Sjfv DEBUGFUNC("ixgbe_fc_enable_generic"); 2700185352Sjfv 2701238149Sjfv /* Validate the water mark configuration */ 2702238149Sjfv if (!hw->fc.pause_time) { 2703238149Sjfv ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2704190873Sjfv goto out; 2705238149Sjfv } 2706185352Sjfv 2707238149Sjfv /* Low water mark of zero causes XOFF floods */ 2708238149Sjfv for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 2709238149Sjfv if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2710238149Sjfv hw->fc.high_water[i]) { 2711238149Sjfv if (!hw->fc.low_water[i] || 2712238149Sjfv hw->fc.low_water[i] >= hw->fc.high_water[i]) { 2713238149Sjfv DEBUGOUT("Invalid water mark configuration\n"); 2714238149Sjfv ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2715238149Sjfv goto out; 2716238149Sjfv } 2717238149Sjfv } 2718238149Sjfv } 2719238149Sjfv 2720238149Sjfv /* Negotiate the fc mode to use */ 2721238149Sjfv ixgbe_fc_autoneg(hw); 2722238149Sjfv 2723190873Sjfv /* Disable any previous flow control settings */ 2724190873Sjfv mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN); 2725238149Sjfv mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE); 2726190873Sjfv 2727190873Sjfv fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG); 2728190873Sjfv fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY); 2729190873Sjfv 2730185352Sjfv /* 2731185352Sjfv * The possible values of fc.current_mode are: 2732190873Sjfv * 0: Flow control is completely disabled 2733190873Sjfv * 1: Rx flow control is enabled (we can receive pause frames, 2734190873Sjfv * but not send pause frames). 2735190873Sjfv * 2: Tx flow control is enabled (we can send pause frames but 2736190873Sjfv * we do not support receiving pause frames). 2737190873Sjfv * 3: Both Rx and Tx flow control (symmetric) are enabled. 2738185352Sjfv * other: Invalid. 2739185352Sjfv */ 2740185352Sjfv switch (hw->fc.current_mode) { 2741185352Sjfv case ixgbe_fc_none: 2742215911Sjfv /* 2743215911Sjfv * Flow control is disabled by software override or autoneg. 2744190873Sjfv * The code below will actually disable it in the HW. 2745190873Sjfv */ 2746185352Sjfv break; 2747185352Sjfv case ixgbe_fc_rx_pause: 2748185352Sjfv /* 2749185352Sjfv * Rx Flow control is enabled and Tx Flow control is 2750185352Sjfv * disabled by software override. Since there really 2751185352Sjfv * isn't a way to advertise that we are capable of RX 2752185352Sjfv * Pause ONLY, we will advertise that we support both 2753185352Sjfv * symmetric and asymmetric Rx PAUSE. Later, we will 2754185352Sjfv * disable the adapter's ability to send PAUSE frames. 2755185352Sjfv */ 2756190873Sjfv mflcn_reg |= IXGBE_MFLCN_RFCE; 2757185352Sjfv break; 2758185352Sjfv case ixgbe_fc_tx_pause: 2759185352Sjfv /* 2760185352Sjfv * Tx Flow control is enabled, and Rx Flow control is 2761185352Sjfv * disabled by software override. 2762185352Sjfv */ 2763190873Sjfv fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2764185352Sjfv break; 2765185352Sjfv case ixgbe_fc_full: 2766185352Sjfv /* Flow control (both Rx and Tx) is enabled by SW override. */ 2767190873Sjfv mflcn_reg |= IXGBE_MFLCN_RFCE; 2768190873Sjfv fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X; 2769185352Sjfv break; 2770185352Sjfv default: 2771251964Sjfv ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 2772251964Sjfv "Flow control param set incorrectly\n"); 2773200239Sjfv ret_val = IXGBE_ERR_CONFIG; 2774185352Sjfv goto out; 2775185352Sjfv break; 2776185352Sjfv } 2777185352Sjfv 2778190873Sjfv /* Set 802.3x based flow control settings. */ 2779190873Sjfv mflcn_reg |= IXGBE_MFLCN_DPF; 2780190873Sjfv IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg); 2781190873Sjfv IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg); 2782185352Sjfv 2783194875Sjfv 2784238149Sjfv /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 2785238149Sjfv for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) { 2786238149Sjfv if ((hw->fc.current_mode & ixgbe_fc_tx_pause) && 2787238149Sjfv hw->fc.high_water[i]) { 2788238149Sjfv fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE; 2789238149Sjfv IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl); 2790238149Sjfv fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN; 2791238149Sjfv } else { 2792238149Sjfv IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0); 2793238149Sjfv /* 2794238149Sjfv * In order to prevent Tx hangs when the internal Tx 2795238149Sjfv * switch is enabled we must set the high water mark 2796238149Sjfv * to the maximum FCRTH value. This allows the Tx 2797238149Sjfv * switch to function even under heavy Rx workloads. 2798238149Sjfv */ 2799238149Sjfv fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32; 2800238149Sjfv } 2801238149Sjfv 2802238149Sjfv IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth); 2803190873Sjfv } 2804185352Sjfv 2805190873Sjfv /* Configure pause time (2 TCs per register) */ 2806238149Sjfv reg = hw->fc.pause_time * 0x00010001; 2807238149Sjfv for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++) 2808238149Sjfv IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg); 2809185352Sjfv 2810238149Sjfv /* Configure flow control refresh threshold value */ 2811238149Sjfv IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2); 2812185352Sjfv 2813190873Sjfvout: 2814190873Sjfv return ret_val; 2815190873Sjfv} 2816190873Sjfv 2817190873Sjfv/** 2818238149Sjfv * ixgbe_negotiate_fc - Negotiate flow control 2819190873Sjfv * @hw: pointer to hardware structure 2820238149Sjfv * @adv_reg: flow control advertised settings 2821238149Sjfv * @lp_reg: link partner's flow control settings 2822238149Sjfv * @adv_sym: symmetric pause bit in advertisement 2823238149Sjfv * @adv_asm: asymmetric pause bit in advertisement 2824238149Sjfv * @lp_sym: symmetric pause bit in link partner advertisement 2825238149Sjfv * @lp_asm: asymmetric pause bit in link partner advertisement 2826190873Sjfv * 2827238149Sjfv * Find the intersection between advertised settings and link partner's 2828238149Sjfv * advertised settings 2829190873Sjfv **/ 2830238149Sjfvstatic s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg, 2831238149Sjfv u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm) 2832190873Sjfv{ 2833251964Sjfv if ((!(adv_reg)) || (!(lp_reg))) { 2834251964Sjfv ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED, 2835251964Sjfv "Local or link partner's advertised flow control " 2836251964Sjfv "settings are NULL. Local: %x, link partner: %x\n", 2837251964Sjfv adv_reg, lp_reg); 2838238149Sjfv return IXGBE_ERR_FC_NOT_NEGOTIATED; 2839251964Sjfv } 2840190873Sjfv 2841238149Sjfv if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) { 2842238149Sjfv /* 2843238149Sjfv * Now we need to check if the user selected Rx ONLY 2844238149Sjfv * of pause frames. In this case, we had to advertise 2845238149Sjfv * FULL flow control because we could not advertise RX 2846238149Sjfv * ONLY. Hence, we must now check to see if we need to 2847238149Sjfv * turn OFF the TRANSMISSION of PAUSE frames. 2848238149Sjfv */ 2849238149Sjfv if (hw->fc.requested_mode == ixgbe_fc_full) { 2850238149Sjfv hw->fc.current_mode = ixgbe_fc_full; 2851238149Sjfv DEBUGOUT("Flow Control = FULL.\n"); 2852238149Sjfv } else { 2853238149Sjfv hw->fc.current_mode = ixgbe_fc_rx_pause; 2854238149Sjfv DEBUGOUT("Flow Control=RX PAUSE frames only\n"); 2855238149Sjfv } 2856238149Sjfv } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) && 2857238149Sjfv (lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2858238149Sjfv hw->fc.current_mode = ixgbe_fc_tx_pause; 2859238149Sjfv DEBUGOUT("Flow Control = TX PAUSE frames only.\n"); 2860238149Sjfv } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) && 2861238149Sjfv !(lp_reg & lp_sym) && (lp_reg & lp_asm)) { 2862238149Sjfv hw->fc.current_mode = ixgbe_fc_rx_pause; 2863238149Sjfv DEBUGOUT("Flow Control = RX PAUSE frames only.\n"); 2864215911Sjfv } else { 2865238149Sjfv hw->fc.current_mode = ixgbe_fc_none; 2866238149Sjfv DEBUGOUT("Flow Control = NONE.\n"); 2867185352Sjfv } 2868238149Sjfv return IXGBE_SUCCESS; 2869215911Sjfv} 2870185352Sjfv 2871215911Sjfv/** 2872215911Sjfv * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber 2873215911Sjfv * @hw: pointer to hardware structure 2874215911Sjfv * 2875215911Sjfv * Enable flow control according on 1 gig fiber. 2876215911Sjfv **/ 2877215911Sjfvstatic s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw) 2878215911Sjfv{ 2879215911Sjfv u32 pcs_anadv_reg, pcs_lpab_reg, linkstat; 2880238149Sjfv s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 2881200239Sjfv 2882200239Sjfv /* 2883200239Sjfv * On multispeed fiber at 1g, bail out if 2884200239Sjfv * - link is up but AN did not complete, or if 2885200239Sjfv * - link is up and AN completed but timed out 2886200239Sjfv */ 2887215911Sjfv 2888215911Sjfv linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA); 2889230775Sjfv if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) || 2890251964Sjfv (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) { 2891251964Sjfv ERROR_REPORT1(IXGBE_ERROR_POLLING, 2892251964Sjfv "Auto-Negotiation did not complete or timed out"); 2893215911Sjfv goto out; 2894251964Sjfv } 2895200239Sjfv 2896215911Sjfv pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA); 2897215911Sjfv pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP); 2898215911Sjfv 2899215911Sjfv ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg, 2900230775Sjfv pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE, 2901230775Sjfv IXGBE_PCS1GANA_ASM_PAUSE, 2902230775Sjfv IXGBE_PCS1GANA_SYM_PAUSE, 2903230775Sjfv IXGBE_PCS1GANA_ASM_PAUSE); 2904215911Sjfv 2905215911Sjfvout: 2906215911Sjfv return ret_val; 2907215911Sjfv} 2908215911Sjfv 2909215911Sjfv/** 2910215911Sjfv * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37 2911215911Sjfv * @hw: pointer to hardware structure 2912215911Sjfv * 2913215911Sjfv * Enable flow control according to IEEE clause 37. 2914215911Sjfv **/ 2915215911Sjfvstatic s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw) 2916215911Sjfv{ 2917215911Sjfv u32 links2, anlp1_reg, autoc_reg, links; 2918238149Sjfv s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 2919215911Sjfv 2920200239Sjfv /* 2921215911Sjfv * On backplane, bail out if 2922215911Sjfv * - backplane autoneg was not completed, or if 2923215911Sjfv * - we are 82599 and link partner is not AN enabled 2924200239Sjfv */ 2925215911Sjfv links = IXGBE_READ_REG(hw, IXGBE_LINKS); 2926251964Sjfv if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) { 2927251964Sjfv ERROR_REPORT1(IXGBE_ERROR_POLLING, 2928251964Sjfv "Auto-Negotiation did not complete"); 2929200239Sjfv goto out; 2930251964Sjfv } 2931200239Sjfv 2932215911Sjfv if (hw->mac.type == ixgbe_mac_82599EB) { 2933215911Sjfv links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2); 2934251964Sjfv if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) { 2935251964Sjfv ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 2936251964Sjfv "Link partner is not AN enabled"); 2937215911Sjfv goto out; 2938251964Sjfv } 2939215911Sjfv } 2940200239Sjfv /* 2941215911Sjfv * Read the 10g AN autoc and LP ability registers and resolve 2942185352Sjfv * local flow control settings accordingly 2943185352Sjfv */ 2944215911Sjfv autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 2945215911Sjfv anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1); 2946200239Sjfv 2947215911Sjfv ret_val = ixgbe_negotiate_fc(hw, autoc_reg, 2948215911Sjfv anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE, 2949215911Sjfv IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE); 2950215911Sjfv 2951215911Sjfvout: 2952215911Sjfv return ret_val; 2953215911Sjfv} 2954215911Sjfv 2955215911Sjfv/** 2956215911Sjfv * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37 2957215911Sjfv * @hw: pointer to hardware structure 2958215911Sjfv * 2959215911Sjfv * Enable flow control according to IEEE clause 37. 2960215911Sjfv **/ 2961215911Sjfvstatic s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw) 2962215911Sjfv{ 2963215911Sjfv u16 technology_ability_reg = 0; 2964215911Sjfv u16 lp_technology_ability_reg = 0; 2965215911Sjfv 2966215911Sjfv hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT, 2967215911Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2968215911Sjfv &technology_ability_reg); 2969215911Sjfv hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP, 2970215911Sjfv IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2971215911Sjfv &lp_technology_ability_reg); 2972215911Sjfv 2973215911Sjfv return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg, 2974215911Sjfv (u32)lp_technology_ability_reg, 2975215911Sjfv IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE, 2976215911Sjfv IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE); 2977215911Sjfv} 2978215911Sjfv 2979215911Sjfv/** 2980238149Sjfv * ixgbe_fc_autoneg - Configure flow control 2981215911Sjfv * @hw: pointer to hardware structure 2982215911Sjfv * 2983238149Sjfv * Compares our advertised flow control capabilities to those advertised by 2984238149Sjfv * our link partner, and determines the proper flow control mode to use. 2985215911Sjfv **/ 2986238149Sjfvvoid ixgbe_fc_autoneg(struct ixgbe_hw *hw) 2987215911Sjfv{ 2988238149Sjfv s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED; 2989238149Sjfv ixgbe_link_speed speed; 2990238149Sjfv bool link_up; 2991215911Sjfv 2992238149Sjfv DEBUGFUNC("ixgbe_fc_autoneg"); 2993185352Sjfv 2994190873Sjfv /* 2995238149Sjfv * AN should have completed when the cable was plugged in. 2996238149Sjfv * Look for reasons to bail out. Bail out if: 2997238149Sjfv * - FC autoneg is disabled, or if 2998238149Sjfv * - link is not up. 2999190873Sjfv */ 3000251964Sjfv if (hw->fc.disable_fc_autoneg) { 3001251964Sjfv ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 3002251964Sjfv "Flow control autoneg is disabled"); 3003190873Sjfv goto out; 3004251964Sjfv } 3005190873Sjfv 3006238149Sjfv hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 3007251964Sjfv if (!link_up) { 3008251964Sjfv ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down"); 3009190873Sjfv goto out; 3010251964Sjfv } 3011190873Sjfv 3012215911Sjfv switch (hw->phy.media_type) { 3013238149Sjfv /* Autoneg flow control on fiber adapters */ 3014247822Sjfv case ixgbe_media_type_fiber_fixed: 3015215911Sjfv case ixgbe_media_type_fiber: 3016238149Sjfv if (speed == IXGBE_LINK_SPEED_1GB_FULL) 3017238149Sjfv ret_val = ixgbe_fc_autoneg_fiber(hw); 3018238149Sjfv break; 3019238149Sjfv 3020238149Sjfv /* Autoneg flow control on backplane adapters */ 3021215911Sjfv case ixgbe_media_type_backplane: 3022238149Sjfv ret_val = ixgbe_fc_autoneg_backplane(hw); 3023215911Sjfv break; 3024215911Sjfv 3025238149Sjfv /* Autoneg flow control on copper adapters */ 3026215911Sjfv case ixgbe_media_type_copper: 3027251964Sjfv if (ixgbe_device_supports_autoneg_fc(hw)) 3028238149Sjfv ret_val = ixgbe_fc_autoneg_copper(hw); 3029215911Sjfv break; 3030215911Sjfv 3031215911Sjfv default: 3032190873Sjfv break; 3033190873Sjfv } 3034190873Sjfv 3035238149Sjfvout: 3036238149Sjfv if (ret_val == IXGBE_SUCCESS) { 3037238149Sjfv hw->fc.fc_was_autonegged = TRUE; 3038238149Sjfv } else { 3039238149Sjfv hw->fc.fc_was_autonegged = FALSE; 3040238149Sjfv hw->fc.current_mode = hw->fc.requested_mode; 3041230775Sjfv } 3042190873Sjfv} 3043190873Sjfv 3044251964Sjfv/* 3045251964Sjfv * ixgbe_pcie_timeout_poll - Return number of times to poll for completion 3046251964Sjfv * @hw: pointer to hardware structure 3047251964Sjfv * 3048251964Sjfv * System-wide timeout range is encoded in PCIe Device Control2 register. 3049251964Sjfv * 3050251964Sjfv * Add 10% to specified maximum and return the number of times to poll for 3051251964Sjfv * completion timeout, in units of 100 microsec. Never return less than 3052251964Sjfv * 800 = 80 millisec. 3053251964Sjfv */ 3054251964Sjfvstatic u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw) 3055251964Sjfv{ 3056251964Sjfv s16 devctl2; 3057251964Sjfv u32 pollcnt; 3058251964Sjfv 3059251964Sjfv devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2); 3060251964Sjfv devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK; 3061251964Sjfv 3062251964Sjfv switch (devctl2) { 3063251964Sjfv case IXGBE_PCIDEVCTRL2_65_130ms: 3064251964Sjfv pollcnt = 1300; /* 130 millisec */ 3065251964Sjfv break; 3066251964Sjfv case IXGBE_PCIDEVCTRL2_260_520ms: 3067251964Sjfv pollcnt = 5200; /* 520 millisec */ 3068251964Sjfv break; 3069251964Sjfv case IXGBE_PCIDEVCTRL2_1_2s: 3070251964Sjfv pollcnt = 20000; /* 2 sec */ 3071251964Sjfv break; 3072251964Sjfv case IXGBE_PCIDEVCTRL2_4_8s: 3073251964Sjfv pollcnt = 80000; /* 8 sec */ 3074251964Sjfv break; 3075251964Sjfv case IXGBE_PCIDEVCTRL2_17_34s: 3076251964Sjfv pollcnt = 34000; /* 34 sec */ 3077251964Sjfv break; 3078251964Sjfv case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */ 3079251964Sjfv case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */ 3080251964Sjfv case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */ 3081251964Sjfv case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */ 3082251964Sjfv default: 3083251964Sjfv pollcnt = 800; /* 80 millisec minimum */ 3084251964Sjfv break; 3085251964Sjfv } 3086251964Sjfv 3087251964Sjfv /* add 10% to spec maximum */ 3088251964Sjfv return (pollcnt * 11) / 10; 3089251964Sjfv} 3090251964Sjfv 3091185352Sjfv/** 3092171384Sjfv * ixgbe_disable_pcie_master - Disable PCI-express master access 3093171384Sjfv * @hw: pointer to hardware structure 3094171384Sjfv * 3095171384Sjfv * Disables PCI-Express master access and verifies there are no pending 3096171384Sjfv * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable 3097171384Sjfv * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS 3098171384Sjfv * is returned signifying master requests disabled. 3099171384Sjfv **/ 3100171384Sjfvs32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw) 3101171384Sjfv{ 3102230775Sjfv s32 status = IXGBE_SUCCESS; 3103251964Sjfv u32 i, poll; 3104171384Sjfv 3105200239Sjfv DEBUGFUNC("ixgbe_disable_pcie_master"); 3106200239Sjfv 3107230775Sjfv /* Always set this bit to ensure any future transactions are blocked */ 3108230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS); 3109230775Sjfv 3110251964Sjfv /* Exit if master requests are blocked */ 3111205720Sjfv if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) 3112205720Sjfv goto out; 3113205720Sjfv 3114230775Sjfv /* Poll for master request bit to clear */ 3115171384Sjfv for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { 3116230775Sjfv usec_delay(100); 3117205720Sjfv if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO)) 3118230775Sjfv goto out; 3119205720Sjfv } 3120205720Sjfv 3121230775Sjfv /* 3122230775Sjfv * Two consecutive resets are required via CTRL.RST per datasheet 3123230775Sjfv * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine 3124230775Sjfv * of this need. The first reset prevents new master requests from 3125230775Sjfv * being issued by our device. We then must wait 1usec or more for any 3126230775Sjfv * remaining completions from the PCIe bus to trickle in, and then reset 3127230775Sjfv * again to clear out any effects they may have had on our device. 3128230775Sjfv */ 3129205720Sjfv DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n"); 3130230775Sjfv hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 3131205720Sjfv 3132205720Sjfv /* 3133217593Sjfv * Before proceeding, make sure that the PCIe block does not have 3134217593Sjfv * transactions pending. 3135205720Sjfv */ 3136251964Sjfv poll = ixgbe_pcie_timeout_poll(hw); 3137251964Sjfv for (i = 0; i < poll; i++) { 3138230775Sjfv usec_delay(100); 3139205720Sjfv if (!(IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS) & 3140230775Sjfv IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING)) 3141230775Sjfv goto out; 3142171384Sjfv } 3143171384Sjfv 3144251964Sjfv ERROR_REPORT1(IXGBE_ERROR_POLLING, 3145251964Sjfv "PCIe transaction pending bit also did not clear.\n"); 3146230775Sjfv status = IXGBE_ERR_MASTER_REQUESTS_PENDING; 3147205720Sjfv 3148205720Sjfvout: 3149171384Sjfv return status; 3150171384Sjfv} 3151171384Sjfv 3152171384Sjfv/** 3153179055Sjfv * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore 3154171384Sjfv * @hw: pointer to hardware structure 3155179055Sjfv * @mask: Mask to specify which semaphore to acquire 3156171384Sjfv * 3157230775Sjfv * Acquires the SWFW semaphore through the GSSR register for the specified 3158171384Sjfv * function (CSR, PHY0, PHY1, EEPROM, Flash) 3159171384Sjfv **/ 3160171384Sjfvs32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask) 3161171384Sjfv{ 3162251964Sjfv u32 gssr = 0; 3163171384Sjfv u32 swmask = mask; 3164171384Sjfv u32 fwmask = mask << 5; 3165251964Sjfv u32 timeout = 200; 3166251964Sjfv u32 i; 3167171384Sjfv 3168200239Sjfv DEBUGFUNC("ixgbe_acquire_swfw_sync"); 3169200239Sjfv 3170251964Sjfv for (i = 0; i < timeout; i++) { 3171190873Sjfv /* 3172251964Sjfv * SW NVM semaphore bit is used for access to all 3173251964Sjfv * SW_FW_SYNC bits (not just NVM) 3174190873Sjfv */ 3175171384Sjfv if (ixgbe_get_eeprom_semaphore(hw)) 3176200239Sjfv return IXGBE_ERR_SWFW_SYNC; 3177171384Sjfv 3178171384Sjfv gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 3179251964Sjfv if (!(gssr & (fwmask | swmask))) { 3180251964Sjfv gssr |= swmask; 3181251964Sjfv IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 3182251964Sjfv ixgbe_release_eeprom_semaphore(hw); 3183251964Sjfv return IXGBE_SUCCESS; 3184251964Sjfv } else { 3185251964Sjfv /* Resource is currently in use by FW or SW */ 3186251964Sjfv ixgbe_release_eeprom_semaphore(hw); 3187251964Sjfv msec_delay(5); 3188251964Sjfv } 3189171384Sjfv } 3190171384Sjfv 3191251964Sjfv /* If time expired clear the bits holding the lock and retry */ 3192251964Sjfv if (gssr & (fwmask | swmask)) 3193251964Sjfv ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask)); 3194171384Sjfv 3195251964Sjfv msec_delay(5); 3196251964Sjfv return IXGBE_ERR_SWFW_SYNC; 3197171384Sjfv} 3198171384Sjfv 3199171384Sjfv/** 3200171384Sjfv * ixgbe_release_swfw_sync - Release SWFW semaphore 3201171384Sjfv * @hw: pointer to hardware structure 3202179055Sjfv * @mask: Mask to specify which semaphore to release 3203171384Sjfv * 3204230775Sjfv * Releases the SWFW semaphore through the GSSR register for the specified 3205171384Sjfv * function (CSR, PHY0, PHY1, EEPROM, Flash) 3206171384Sjfv **/ 3207171384Sjfvvoid ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask) 3208171384Sjfv{ 3209171384Sjfv u32 gssr; 3210171384Sjfv u32 swmask = mask; 3211171384Sjfv 3212200239Sjfv DEBUGFUNC("ixgbe_release_swfw_sync"); 3213200239Sjfv 3214171384Sjfv ixgbe_get_eeprom_semaphore(hw); 3215171384Sjfv 3216171384Sjfv gssr = IXGBE_READ_REG(hw, IXGBE_GSSR); 3217171384Sjfv gssr &= ~swmask; 3218171384Sjfv IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr); 3219171384Sjfv 3220171384Sjfv ixgbe_release_eeprom_semaphore(hw); 3221171384Sjfv} 3222171384Sjfv 3223190873Sjfv/** 3224230775Sjfv * ixgbe_disable_sec_rx_path_generic - Stops the receive data path 3225230775Sjfv * @hw: pointer to hardware structure 3226230775Sjfv * 3227230775Sjfv * Stops the receive data path and waits for the HW to internally empty 3228230775Sjfv * the Rx security block 3229230775Sjfv **/ 3230230775Sjfvs32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw) 3231230775Sjfv{ 3232230775Sjfv#define IXGBE_MAX_SECRX_POLL 40 3233230775Sjfv 3234230775Sjfv int i; 3235230775Sjfv int secrxreg; 3236230775Sjfv 3237230775Sjfv DEBUGFUNC("ixgbe_disable_sec_rx_path_generic"); 3238230775Sjfv 3239230775Sjfv 3240230775Sjfv secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 3241230775Sjfv secrxreg |= IXGBE_SECRXCTRL_RX_DIS; 3242230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 3243230775Sjfv for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) { 3244230775Sjfv secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT); 3245230775Sjfv if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY) 3246230775Sjfv break; 3247230775Sjfv else 3248230775Sjfv /* Use interrupt-safe sleep just in case */ 3249230775Sjfv usec_delay(1000); 3250230775Sjfv } 3251230775Sjfv 3252230775Sjfv /* For informational purposes only */ 3253230775Sjfv if (i >= IXGBE_MAX_SECRX_POLL) 3254230775Sjfv DEBUGOUT("Rx unit being enabled before security " 3255230775Sjfv "path fully disabled. Continuing with init.\n"); 3256230775Sjfv 3257230775Sjfv return IXGBE_SUCCESS; 3258230775Sjfv} 3259230775Sjfv 3260230775Sjfv/** 3261230775Sjfv * ixgbe_enable_sec_rx_path_generic - Enables the receive data path 3262230775Sjfv * @hw: pointer to hardware structure 3263230775Sjfv * 3264230775Sjfv * Enables the receive data path. 3265230775Sjfv **/ 3266230775Sjfvs32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw) 3267230775Sjfv{ 3268230775Sjfv int secrxreg; 3269230775Sjfv 3270230775Sjfv DEBUGFUNC("ixgbe_enable_sec_rx_path_generic"); 3271230775Sjfv 3272230775Sjfv secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL); 3273230775Sjfv secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS; 3274230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg); 3275230775Sjfv IXGBE_WRITE_FLUSH(hw); 3276230775Sjfv 3277230775Sjfv return IXGBE_SUCCESS; 3278230775Sjfv} 3279230775Sjfv 3280230775Sjfv/** 3281190873Sjfv * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit 3282190873Sjfv * @hw: pointer to hardware structure 3283190873Sjfv * @regval: register value to write to RXCTRL 3284190873Sjfv * 3285190873Sjfv * Enables the Rx DMA unit 3286190873Sjfv **/ 3287190873Sjfvs32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval) 3288190873Sjfv{ 3289200239Sjfv DEBUGFUNC("ixgbe_enable_rx_dma_generic"); 3290200239Sjfv 3291190873Sjfv IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval); 3292190873Sjfv 3293190873Sjfv return IXGBE_SUCCESS; 3294190873Sjfv} 3295190873Sjfv 3296190873Sjfv/** 3297190873Sjfv * ixgbe_blink_led_start_generic - Blink LED based on index. 3298190873Sjfv * @hw: pointer to hardware structure 3299190873Sjfv * @index: led number to blink 3300190873Sjfv **/ 3301190873Sjfvs32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index) 3302190873Sjfv{ 3303190873Sjfv ixgbe_link_speed speed = 0; 3304190873Sjfv bool link_up = 0; 3305190873Sjfv u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 3306190873Sjfv u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 3307247822Sjfv s32 ret_val = IXGBE_SUCCESS; 3308190873Sjfv 3309200239Sjfv DEBUGFUNC("ixgbe_blink_led_start_generic"); 3310200239Sjfv 3311190873Sjfv /* 3312190873Sjfv * Link must be up to auto-blink the LEDs; 3313190873Sjfv * Force it if link is down. 3314190873Sjfv */ 3315190873Sjfv hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 3316190873Sjfv 3317190873Sjfv if (!link_up) { 3318247822Sjfv /* Need the SW/FW semaphore around AUTOC writes if 82599 and 3319247822Sjfv * LESM is on. 3320247822Sjfv */ 3321247822Sjfv bool got_lock = FALSE; 3322247822Sjfv if ((hw->mac.type == ixgbe_mac_82599EB) && 3323247822Sjfv ixgbe_verify_lesm_fw_enabled_82599(hw)) { 3324247822Sjfv ret_val = hw->mac.ops.acquire_swfw_sync(hw, 3325247822Sjfv IXGBE_GSSR_MAC_CSR_SM); 3326247822Sjfv if (ret_val != IXGBE_SUCCESS) { 3327247822Sjfv ret_val = IXGBE_ERR_SWFW_SYNC; 3328247822Sjfv goto out; 3329247822Sjfv } 3330247822Sjfv got_lock = TRUE; 3331247822Sjfv } 3332247822Sjfv 3333194875Sjfv autoc_reg |= IXGBE_AUTOC_AN_RESTART; 3334190873Sjfv autoc_reg |= IXGBE_AUTOC_FLU; 3335190873Sjfv IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 3336230775Sjfv IXGBE_WRITE_FLUSH(hw); 3337247822Sjfv 3338247822Sjfv if (got_lock) 3339247822Sjfv hw->mac.ops.release_swfw_sync(hw, 3340247822Sjfv IXGBE_GSSR_MAC_CSR_SM); 3341190873Sjfv msec_delay(10); 3342190873Sjfv } 3343190873Sjfv 3344190873Sjfv led_reg &= ~IXGBE_LED_MODE_MASK(index); 3345190873Sjfv led_reg |= IXGBE_LED_BLINK(index); 3346190873Sjfv IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 3347190873Sjfv IXGBE_WRITE_FLUSH(hw); 3348190873Sjfv 3349247822Sjfvout: 3350247822Sjfv return ret_val; 3351190873Sjfv} 3352190873Sjfv 3353190873Sjfv/** 3354190873Sjfv * ixgbe_blink_led_stop_generic - Stop blinking LED based on index. 3355190873Sjfv * @hw: pointer to hardware structure 3356190873Sjfv * @index: led number to stop blinking 3357190873Sjfv **/ 3358190873Sjfvs32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index) 3359190873Sjfv{ 3360190873Sjfv u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC); 3361190873Sjfv u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 3362247822Sjfv s32 ret_val = IXGBE_SUCCESS; 3363247822Sjfv bool got_lock = FALSE; 3364190873Sjfv 3365200239Sjfv DEBUGFUNC("ixgbe_blink_led_stop_generic"); 3366247822Sjfv /* Need the SW/FW semaphore around AUTOC writes if 82599 and 3367247822Sjfv * LESM is on. 3368247822Sjfv */ 3369247822Sjfv if ((hw->mac.type == ixgbe_mac_82599EB) && 3370247822Sjfv ixgbe_verify_lesm_fw_enabled_82599(hw)) { 3371247822Sjfv ret_val = hw->mac.ops.acquire_swfw_sync(hw, 3372247822Sjfv IXGBE_GSSR_MAC_CSR_SM); 3373247822Sjfv if (ret_val != IXGBE_SUCCESS) { 3374247822Sjfv ret_val = IXGBE_ERR_SWFW_SYNC; 3375247822Sjfv goto out; 3376247822Sjfv } 3377247822Sjfv got_lock = TRUE; 3378247822Sjfv } 3379194875Sjfv 3380200239Sjfv 3381190873Sjfv autoc_reg &= ~IXGBE_AUTOC_FLU; 3382190873Sjfv autoc_reg |= IXGBE_AUTOC_AN_RESTART; 3383190873Sjfv IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg); 3384190873Sjfv 3385247822Sjfv if (hw->mac.type == ixgbe_mac_82599EB) 3386247822Sjfv ixgbe_reset_pipeline_82599(hw); 3387247822Sjfv 3388247822Sjfv if (got_lock) 3389247822Sjfv hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM); 3390247822Sjfv 3391190873Sjfv led_reg &= ~IXGBE_LED_MODE_MASK(index); 3392190873Sjfv led_reg &= ~IXGBE_LED_BLINK(index); 3393190873Sjfv led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 3394190873Sjfv IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg); 3395190873Sjfv IXGBE_WRITE_FLUSH(hw); 3396190873Sjfv 3397247822Sjfvout: 3398247822Sjfv return ret_val; 3399190873Sjfv} 3400190873Sjfv 3401200239Sjfv/** 3402200239Sjfv * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM 3403200239Sjfv * @hw: pointer to hardware structure 3404200239Sjfv * @san_mac_offset: SAN MAC address offset 3405200239Sjfv * 3406200239Sjfv * This function will read the EEPROM location for the SAN MAC address 3407200239Sjfv * pointer, and returns the value at that location. This is used in both 3408200239Sjfv * get and set mac_addr routines. 3409200239Sjfv **/ 3410200239Sjfvstatic s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw, 3411230775Sjfv u16 *san_mac_offset) 3412200239Sjfv{ 3413251964Sjfv s32 ret_val; 3414251964Sjfv 3415200239Sjfv DEBUGFUNC("ixgbe_get_san_mac_addr_offset"); 3416200239Sjfv 3417200239Sjfv /* 3418200239Sjfv * First read the EEPROM pointer to see if the MAC addresses are 3419200239Sjfv * available. 3420200239Sjfv */ 3421251964Sjfv ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, 3422251964Sjfv san_mac_offset); 3423251964Sjfv if (ret_val) { 3424251964Sjfv ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 3425251964Sjfv "eeprom at offset %d failed", 3426251964Sjfv IXGBE_SAN_MAC_ADDR_PTR); 3427251964Sjfv } 3428200239Sjfv 3429251964Sjfv return ret_val; 3430200239Sjfv} 3431200239Sjfv 3432200239Sjfv/** 3433200239Sjfv * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM 3434200239Sjfv * @hw: pointer to hardware structure 3435200239Sjfv * @san_mac_addr: SAN MAC address 3436200239Sjfv * 3437200239Sjfv * Reads the SAN MAC address from the EEPROM, if it's available. This is 3438200239Sjfv * per-port, so set_lan_id() must be called before reading the addresses. 3439200239Sjfv * set_lan_id() is called by identify_sfp(), but this cannot be relied 3440200239Sjfv * upon for non-SFP connections, so we must call it here. 3441200239Sjfv **/ 3442200239Sjfvs32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 3443200239Sjfv{ 3444200239Sjfv u16 san_mac_data, san_mac_offset; 3445200239Sjfv u8 i; 3446251964Sjfv s32 ret_val; 3447200239Sjfv 3448200239Sjfv DEBUGFUNC("ixgbe_get_san_mac_addr_generic"); 3449200239Sjfv 3450200239Sjfv /* 3451200239Sjfv * First read the EEPROM pointer to see if the MAC addresses are 3452200239Sjfv * available. If they're not, no point in calling set_lan_id() here. 3453200239Sjfv */ 3454251964Sjfv ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 3455251964Sjfv if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) 3456200239Sjfv goto san_mac_addr_out; 3457200239Sjfv 3458200239Sjfv /* make sure we know which port we need to program */ 3459200239Sjfv hw->mac.ops.set_lan_id(hw); 3460200239Sjfv /* apply the port offset to the address offset */ 3461200239Sjfv (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 3462230775Sjfv (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 3463200239Sjfv for (i = 0; i < 3; i++) { 3464251964Sjfv ret_val = hw->eeprom.ops.read(hw, san_mac_offset, 3465251964Sjfv &san_mac_data); 3466251964Sjfv if (ret_val) { 3467251964Sjfv ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 3468251964Sjfv "eeprom read at offset %d failed", 3469251964Sjfv san_mac_offset); 3470251964Sjfv goto san_mac_addr_out; 3471251964Sjfv } 3472200239Sjfv san_mac_addr[i * 2] = (u8)(san_mac_data); 3473200239Sjfv san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8); 3474200239Sjfv san_mac_offset++; 3475200239Sjfv } 3476251964Sjfv return IXGBE_SUCCESS; 3477200239Sjfv 3478200239Sjfvsan_mac_addr_out: 3479251964Sjfv /* 3480251964Sjfv * No addresses available in this EEPROM. It's not an 3481251964Sjfv * error though, so just wipe the local address and return. 3482251964Sjfv */ 3483251964Sjfv for (i = 0; i < 6; i++) 3484251964Sjfv san_mac_addr[i] = 0xFF; 3485200239Sjfv return IXGBE_SUCCESS; 3486200239Sjfv} 3487200239Sjfv 3488200239Sjfv/** 3489200239Sjfv * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM 3490200239Sjfv * @hw: pointer to hardware structure 3491200239Sjfv * @san_mac_addr: SAN MAC address 3492200239Sjfv * 3493200239Sjfv * Write a SAN MAC address to the EEPROM. 3494200239Sjfv **/ 3495200239Sjfvs32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr) 3496200239Sjfv{ 3497251964Sjfv s32 ret_val; 3498200239Sjfv u16 san_mac_data, san_mac_offset; 3499200239Sjfv u8 i; 3500200239Sjfv 3501200239Sjfv DEBUGFUNC("ixgbe_set_san_mac_addr_generic"); 3502200239Sjfv 3503200239Sjfv /* Look for SAN mac address pointer. If not defined, return */ 3504251964Sjfv ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset); 3505251964Sjfv if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF) 3506251964Sjfv return IXGBE_ERR_NO_SAN_ADDR_PTR; 3507200239Sjfv 3508200239Sjfv /* Make sure we know which port we need to write */ 3509200239Sjfv hw->mac.ops.set_lan_id(hw); 3510200239Sjfv /* Apply the port offset to the address offset */ 3511200239Sjfv (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) : 3512230775Sjfv (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET); 3513200239Sjfv 3514200239Sjfv for (i = 0; i < 3; i++) { 3515200239Sjfv san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8); 3516200239Sjfv san_mac_data |= (u16)(san_mac_addr[i * 2]); 3517200239Sjfv hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data); 3518200239Sjfv san_mac_offset++; 3519200239Sjfv } 3520200239Sjfv 3521251964Sjfv return IXGBE_SUCCESS; 3522200239Sjfv} 3523200239Sjfv 3524200239Sjfv/** 3525200239Sjfv * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count 3526200239Sjfv * @hw: pointer to hardware structure 3527200239Sjfv * 3528200239Sjfv * Read PCIe configuration space, and get the MSI-X vector count from 3529200239Sjfv * the capabilities table. 3530200239Sjfv **/ 3531238149Sjfvu16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw) 3532200239Sjfv{ 3533238149Sjfv u16 msix_count = 1; 3534238149Sjfv u16 max_msix_count; 3535238149Sjfv u16 pcie_offset; 3536200239Sjfv 3537238149Sjfv switch (hw->mac.type) { 3538238149Sjfv case ixgbe_mac_82598EB: 3539238149Sjfv pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS; 3540238149Sjfv max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598; 3541238149Sjfv break; 3542238149Sjfv case ixgbe_mac_82599EB: 3543238149Sjfv case ixgbe_mac_X540: 3544238149Sjfv pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS; 3545238149Sjfv max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599; 3546238149Sjfv break; 3547238149Sjfv default: 3548238149Sjfv return msix_count; 3549238149Sjfv } 3550238149Sjfv 3551200239Sjfv DEBUGFUNC("ixgbe_get_pcie_msix_count_generic"); 3552238149Sjfv msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset); 3553238149Sjfv msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK; 3554200239Sjfv 3555238149Sjfv /* MSI-X count is zero-based in HW */ 3556238149Sjfv msix_count++; 3557200239Sjfv 3558238149Sjfv if (msix_count > max_msix_count) 3559238149Sjfv msix_count = max_msix_count; 3560238149Sjfv 3561200239Sjfv return msix_count; 3562200239Sjfv} 3563200239Sjfv 3564200239Sjfv/** 3565200239Sjfv * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address 3566200239Sjfv * @hw: pointer to hardware structure 3567200239Sjfv * @addr: Address to put into receive address register 3568200239Sjfv * @vmdq: VMDq pool to assign 3569200239Sjfv * 3570200239Sjfv * Puts an ethernet address into a receive address register, or 3571200239Sjfv * finds the rar that it is aleady in; adds to the pool list 3572200239Sjfv **/ 3573200239Sjfvs32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 3574200239Sjfv{ 3575200239Sjfv static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF; 3576200239Sjfv u32 first_empty_rar = NO_EMPTY_RAR_FOUND; 3577200239Sjfv u32 rar; 3578200239Sjfv u32 rar_low, rar_high; 3579200239Sjfv u32 addr_low, addr_high; 3580200239Sjfv 3581200239Sjfv DEBUGFUNC("ixgbe_insert_mac_addr_generic"); 3582200239Sjfv 3583200239Sjfv /* swap bytes for HW little endian */ 3584200239Sjfv addr_low = addr[0] | (addr[1] << 8) 3585200239Sjfv | (addr[2] << 16) 3586200239Sjfv | (addr[3] << 24); 3587200239Sjfv addr_high = addr[4] | (addr[5] << 8); 3588200239Sjfv 3589200239Sjfv /* 3590200239Sjfv * Either find the mac_id in rar or find the first empty space. 3591200239Sjfv * rar_highwater points to just after the highest currently used 3592200239Sjfv * rar in order to shorten the search. It grows when we add a new 3593200239Sjfv * rar to the top. 3594200239Sjfv */ 3595200239Sjfv for (rar = 0; rar < hw->mac.rar_highwater; rar++) { 3596200239Sjfv rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar)); 3597200239Sjfv 3598200239Sjfv if (((IXGBE_RAH_AV & rar_high) == 0) 3599200239Sjfv && first_empty_rar == NO_EMPTY_RAR_FOUND) { 3600200239Sjfv first_empty_rar = rar; 3601200239Sjfv } else if ((rar_high & 0xFFFF) == addr_high) { 3602200239Sjfv rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar)); 3603200239Sjfv if (rar_low == addr_low) 3604200239Sjfv break; /* found it already in the rars */ 3605200239Sjfv } 3606200239Sjfv } 3607200239Sjfv 3608200239Sjfv if (rar < hw->mac.rar_highwater) { 3609200239Sjfv /* already there so just add to the pool bits */ 3610200239Sjfv ixgbe_set_vmdq(hw, rar, vmdq); 3611200239Sjfv } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) { 3612200239Sjfv /* stick it into first empty RAR slot we found */ 3613200239Sjfv rar = first_empty_rar; 3614200239Sjfv ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 3615200239Sjfv } else if (rar == hw->mac.rar_highwater) { 3616200239Sjfv /* add it to the top of the list and inc the highwater mark */ 3617200239Sjfv ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV); 3618200239Sjfv hw->mac.rar_highwater++; 3619200239Sjfv } else if (rar >= hw->mac.num_rar_entries) { 3620200239Sjfv return IXGBE_ERR_INVALID_MAC_ADDR; 3621200239Sjfv } 3622200239Sjfv 3623200239Sjfv /* 3624200239Sjfv * If we found rar[0], make sure the default pool bit (we use pool 0) 3625200239Sjfv * remains cleared to be sure default pool packets will get delivered 3626200239Sjfv */ 3627200239Sjfv if (rar == 0) 3628200239Sjfv ixgbe_clear_vmdq(hw, rar, 0); 3629200239Sjfv 3630200239Sjfv return rar; 3631200239Sjfv} 3632200239Sjfv 3633200239Sjfv/** 3634200239Sjfv * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address 3635200239Sjfv * @hw: pointer to hardware struct 3636200239Sjfv * @rar: receive address register index to disassociate 3637200239Sjfv * @vmdq: VMDq pool index to remove from the rar 3638200239Sjfv **/ 3639200239Sjfvs32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 3640200239Sjfv{ 3641200239Sjfv u32 mpsar_lo, mpsar_hi; 3642200239Sjfv u32 rar_entries = hw->mac.num_rar_entries; 3643200239Sjfv 3644200239Sjfv DEBUGFUNC("ixgbe_clear_vmdq_generic"); 3645200239Sjfv 3646215911Sjfv /* Make sure we are using a valid rar index range */ 3647215911Sjfv if (rar >= rar_entries) { 3648251964Sjfv ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 3649251964Sjfv "RAR index %d is out of range.\n", rar); 3650215911Sjfv return IXGBE_ERR_INVALID_ARGUMENT; 3651215911Sjfv } 3652200239Sjfv 3653215911Sjfv mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3654215911Sjfv mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3655200239Sjfv 3656215911Sjfv if (!mpsar_lo && !mpsar_hi) 3657215911Sjfv goto done; 3658215911Sjfv 3659215911Sjfv if (vmdq == IXGBE_CLEAR_VMDQ_ALL) { 3660215911Sjfv if (mpsar_lo) { 3661215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 3662215911Sjfv mpsar_lo = 0; 3663200239Sjfv } 3664215911Sjfv if (mpsar_hi) { 3665215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3666215911Sjfv mpsar_hi = 0; 3667215911Sjfv } 3668215911Sjfv } else if (vmdq < 32) { 3669215911Sjfv mpsar_lo &= ~(1 << vmdq); 3670215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo); 3671200239Sjfv } else { 3672215911Sjfv mpsar_hi &= ~(1 << (vmdq - 32)); 3673215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi); 3674200239Sjfv } 3675200239Sjfv 3676215911Sjfv /* was that the last pool using this rar? */ 3677215911Sjfv if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0) 3678215911Sjfv hw->mac.ops.clear_rar(hw, rar); 3679200239Sjfvdone: 3680200239Sjfv return IXGBE_SUCCESS; 3681200239Sjfv} 3682200239Sjfv 3683200239Sjfv/** 3684200239Sjfv * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address 3685200239Sjfv * @hw: pointer to hardware struct 3686200239Sjfv * @rar: receive address register index to associate with a VMDq index 3687200239Sjfv * @vmdq: VMDq pool index 3688200239Sjfv **/ 3689200239Sjfvs32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 3690200239Sjfv{ 3691200239Sjfv u32 mpsar; 3692200239Sjfv u32 rar_entries = hw->mac.num_rar_entries; 3693200239Sjfv 3694200239Sjfv DEBUGFUNC("ixgbe_set_vmdq_generic"); 3695200239Sjfv 3696215911Sjfv /* Make sure we are using a valid rar index range */ 3697215911Sjfv if (rar >= rar_entries) { 3698251964Sjfv ERROR_REPORT2(IXGBE_ERROR_ARGUMENT, 3699251964Sjfv "RAR index %d is out of range.\n", rar); 3700215911Sjfv return IXGBE_ERR_INVALID_ARGUMENT; 3701200239Sjfv } 3702215911Sjfv 3703215911Sjfv if (vmdq < 32) { 3704215911Sjfv mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar)); 3705215911Sjfv mpsar |= 1 << vmdq; 3706215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar); 3707215911Sjfv } else { 3708215911Sjfv mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar)); 3709215911Sjfv mpsar |= 1 << (vmdq - 32); 3710215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar); 3711215911Sjfv } 3712200239Sjfv return IXGBE_SUCCESS; 3713200239Sjfv} 3714200239Sjfv 3715200239Sjfv/** 3716238149Sjfv * This function should only be involved in the IOV mode. 3717238149Sjfv * In IOV mode, Default pool is next pool after the number of 3718238149Sjfv * VFs advertized and not 0. 3719238149Sjfv * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index] 3720238149Sjfv * 3721238149Sjfv * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address 3722238149Sjfv * @hw: pointer to hardware struct 3723238149Sjfv * @vmdq: VMDq pool index 3724238149Sjfv **/ 3725238149Sjfvs32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq) 3726238149Sjfv{ 3727238149Sjfv u32 rar = hw->mac.san_mac_rar_index; 3728238149Sjfv 3729238149Sjfv DEBUGFUNC("ixgbe_set_vmdq_san_mac"); 3730238149Sjfv 3731238149Sjfv if (vmdq < 32) { 3732238149Sjfv IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq); 3733238149Sjfv IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0); 3734238149Sjfv } else { 3735238149Sjfv IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0); 3736238149Sjfv IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32)); 3737238149Sjfv } 3738238149Sjfv 3739238149Sjfv return IXGBE_SUCCESS; 3740238149Sjfv} 3741238149Sjfv 3742238149Sjfv/** 3743200239Sjfv * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array 3744200239Sjfv * @hw: pointer to hardware structure 3745200239Sjfv **/ 3746200239Sjfvs32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw) 3747200239Sjfv{ 3748200239Sjfv int i; 3749200239Sjfv 3750200239Sjfv DEBUGFUNC("ixgbe_init_uta_tables_generic"); 3751200239Sjfv DEBUGOUT(" Clearing UTA\n"); 3752200239Sjfv 3753200239Sjfv for (i = 0; i < 128; i++) 3754200239Sjfv IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0); 3755200239Sjfv 3756200239Sjfv return IXGBE_SUCCESS; 3757200239Sjfv} 3758200239Sjfv 3759200239Sjfv/** 3760200239Sjfv * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot 3761200239Sjfv * @hw: pointer to hardware structure 3762200239Sjfv * @vlan: VLAN id to write to VLAN filter 3763200239Sjfv * 3764200239Sjfv * return the VLVF index where this VLAN id should be placed 3765200239Sjfv * 3766200239Sjfv **/ 3767200239Sjfvs32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan) 3768200239Sjfv{ 3769200239Sjfv u32 bits = 0; 3770200239Sjfv u32 first_empty_slot = 0; 3771200239Sjfv s32 regindex; 3772200239Sjfv 3773205720Sjfv /* short cut the special case */ 3774205720Sjfv if (vlan == 0) 3775205720Sjfv return 0; 3776205720Sjfv 3777200239Sjfv /* 3778200239Sjfv * Search for the vlan id in the VLVF entries. Save off the first empty 3779200239Sjfv * slot found along the way 3780200239Sjfv */ 3781200239Sjfv for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) { 3782200239Sjfv bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex)); 3783200239Sjfv if (!bits && !(first_empty_slot)) 3784200239Sjfv first_empty_slot = regindex; 3785200239Sjfv else if ((bits & 0x0FFF) == vlan) 3786200239Sjfv break; 3787200239Sjfv } 3788200239Sjfv 3789200239Sjfv /* 3790200239Sjfv * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan 3791200239Sjfv * in the VLVF. Else use the first empty VLVF register for this 3792200239Sjfv * vlan id. 3793200239Sjfv */ 3794200239Sjfv if (regindex >= IXGBE_VLVF_ENTRIES) { 3795200239Sjfv if (first_empty_slot) 3796200239Sjfv regindex = first_empty_slot; 3797200239Sjfv else { 3798251964Sjfv ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, 3799251964Sjfv "No space in VLVF.\n"); 3800205720Sjfv regindex = IXGBE_ERR_NO_SPACE; 3801200239Sjfv } 3802200239Sjfv } 3803200239Sjfv 3804200239Sjfv return regindex; 3805200239Sjfv} 3806200239Sjfv 3807200239Sjfv/** 3808200239Sjfv * ixgbe_set_vfta_generic - Set VLAN filter table 3809200239Sjfv * @hw: pointer to hardware structure 3810200239Sjfv * @vlan: VLAN id to write to VLAN filter 3811200239Sjfv * @vind: VMDq output index that maps queue to VLAN id in VFVFB 3812200239Sjfv * @vlan_on: boolean flag to turn on/off VLAN in VFVF 3813200239Sjfv * 3814200239Sjfv * Turn on/off specified VLAN in the VLAN filter table. 3815200239Sjfv **/ 3816200239Sjfvs32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 3817230775Sjfv bool vlan_on) 3818200239Sjfv{ 3819200239Sjfv s32 regindex; 3820200239Sjfv u32 bitindex; 3821205720Sjfv u32 vfta; 3822205720Sjfv u32 targetbit; 3823230775Sjfv s32 ret_val = IXGBE_SUCCESS; 3824205720Sjfv bool vfta_changed = FALSE; 3825200239Sjfv 3826200239Sjfv DEBUGFUNC("ixgbe_set_vfta_generic"); 3827200239Sjfv 3828200239Sjfv if (vlan > 4095) 3829200239Sjfv return IXGBE_ERR_PARAM; 3830200239Sjfv 3831200239Sjfv /* 3832200239Sjfv * this is a 2 part operation - first the VFTA, then the 3833200239Sjfv * VLVF and VLVFB if VT Mode is set 3834205720Sjfv * We don't write the VFTA until we know the VLVF part succeeded. 3835200239Sjfv */ 3836200239Sjfv 3837200239Sjfv /* Part 1 3838200239Sjfv * The VFTA is a bitstring made up of 128 32-bit registers 3839200239Sjfv * that enable the particular VLAN id, much like the MTA: 3840200239Sjfv * bits[11-5]: which register 3841200239Sjfv * bits[4-0]: which bit in the register 3842200239Sjfv */ 3843200239Sjfv regindex = (vlan >> 5) & 0x7F; 3844200239Sjfv bitindex = vlan & 0x1F; 3845205720Sjfv targetbit = (1 << bitindex); 3846205720Sjfv vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex)); 3847200239Sjfv 3848205720Sjfv if (vlan_on) { 3849205720Sjfv if (!(vfta & targetbit)) { 3850205720Sjfv vfta |= targetbit; 3851205720Sjfv vfta_changed = TRUE; 3852205720Sjfv } 3853205720Sjfv } else { 3854205720Sjfv if ((vfta & targetbit)) { 3855205720Sjfv vfta &= ~targetbit; 3856205720Sjfv vfta_changed = TRUE; 3857205720Sjfv } 3858205720Sjfv } 3859200239Sjfv 3860200239Sjfv /* Part 2 3861230775Sjfv * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF 3862230775Sjfv */ 3863230775Sjfv ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on, 3864230775Sjfv &vfta_changed); 3865230775Sjfv if (ret_val != IXGBE_SUCCESS) 3866230775Sjfv return ret_val; 3867230775Sjfv 3868230775Sjfv if (vfta_changed) 3869230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta); 3870230775Sjfv 3871230775Sjfv return IXGBE_SUCCESS; 3872230775Sjfv} 3873230775Sjfv 3874230775Sjfv/** 3875230775Sjfv * ixgbe_set_vlvf_generic - Set VLAN Pool Filter 3876230775Sjfv * @hw: pointer to hardware structure 3877230775Sjfv * @vlan: VLAN id to write to VLAN filter 3878230775Sjfv * @vind: VMDq output index that maps queue to VLAN id in VFVFB 3879230775Sjfv * @vlan_on: boolean flag to turn on/off VLAN in VFVF 3880230775Sjfv * @vfta_changed: pointer to boolean flag which indicates whether VFTA 3881230775Sjfv * should be changed 3882230775Sjfv * 3883230775Sjfv * Turn on/off specified bit in VLVF table. 3884230775Sjfv **/ 3885230775Sjfvs32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind, 3886230775Sjfv bool vlan_on, bool *vfta_changed) 3887230775Sjfv{ 3888230775Sjfv u32 vt; 3889230775Sjfv 3890230775Sjfv DEBUGFUNC("ixgbe_set_vlvf_generic"); 3891230775Sjfv 3892230775Sjfv if (vlan > 4095) 3893230775Sjfv return IXGBE_ERR_PARAM; 3894230775Sjfv 3895230775Sjfv /* If VT Mode is set 3896200239Sjfv * Either vlan_on 3897200239Sjfv * make sure the vlan is in VLVF 3898200239Sjfv * set the vind bit in the matching VLVFB 3899200239Sjfv * Or !vlan_on 3900200239Sjfv * clear the pool bit and possibly the vind 3901200239Sjfv */ 3902200239Sjfv vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL); 3903200239Sjfv if (vt & IXGBE_VT_CTL_VT_ENABLE) { 3904205720Sjfv s32 vlvf_index; 3905230775Sjfv u32 bits; 3906200239Sjfv 3907205720Sjfv vlvf_index = ixgbe_find_vlvf_slot(hw, vlan); 3908205720Sjfv if (vlvf_index < 0) 3909205720Sjfv return vlvf_index; 3910205720Sjfv 3911200239Sjfv if (vlan_on) { 3912200239Sjfv /* set the pool bit */ 3913200239Sjfv if (vind < 32) { 3914200239Sjfv bits = IXGBE_READ_REG(hw, 3915230775Sjfv IXGBE_VLVFB(vlvf_index * 2)); 3916200239Sjfv bits |= (1 << vind); 3917200239Sjfv IXGBE_WRITE_REG(hw, 3918230775Sjfv IXGBE_VLVFB(vlvf_index * 2), 3919200239Sjfv bits); 3920200239Sjfv } else { 3921200239Sjfv bits = IXGBE_READ_REG(hw, 3922230775Sjfv IXGBE_VLVFB((vlvf_index * 2) + 1)); 3923230775Sjfv bits |= (1 << (vind - 32)); 3924200239Sjfv IXGBE_WRITE_REG(hw, 3925230775Sjfv IXGBE_VLVFB((vlvf_index * 2) + 1), 3926230775Sjfv bits); 3927200239Sjfv } 3928200239Sjfv } else { 3929200239Sjfv /* clear the pool bit */ 3930200239Sjfv if (vind < 32) { 3931200239Sjfv bits = IXGBE_READ_REG(hw, 3932230775Sjfv IXGBE_VLVFB(vlvf_index * 2)); 3933200239Sjfv bits &= ~(1 << vind); 3934200239Sjfv IXGBE_WRITE_REG(hw, 3935230775Sjfv IXGBE_VLVFB(vlvf_index * 2), 3936200239Sjfv bits); 3937200239Sjfv bits |= IXGBE_READ_REG(hw, 3938230775Sjfv IXGBE_VLVFB((vlvf_index * 2) + 1)); 3939200239Sjfv } else { 3940200239Sjfv bits = IXGBE_READ_REG(hw, 3941230775Sjfv IXGBE_VLVFB((vlvf_index * 2) + 1)); 3942230775Sjfv bits &= ~(1 << (vind - 32)); 3943200239Sjfv IXGBE_WRITE_REG(hw, 3944230775Sjfv IXGBE_VLVFB((vlvf_index * 2) + 1), 3945230775Sjfv bits); 3946200239Sjfv bits |= IXGBE_READ_REG(hw, 3947230775Sjfv IXGBE_VLVFB(vlvf_index * 2)); 3948200239Sjfv } 3949200239Sjfv } 3950200239Sjfv 3951205720Sjfv /* 3952205720Sjfv * If there are still bits set in the VLVFB registers 3953205720Sjfv * for the VLAN ID indicated we need to see if the 3954205720Sjfv * caller is requesting that we clear the VFTA entry bit. 3955205720Sjfv * If the caller has requested that we clear the VFTA 3956205720Sjfv * entry bit but there are still pools/VFs using this VLAN 3957205720Sjfv * ID entry then ignore the request. We're not worried 3958205720Sjfv * about the case where we're turning the VFTA VLAN ID 3959205720Sjfv * entry bit on, only when requested to turn it off as 3960205720Sjfv * there may be multiple pools and/or VFs using the 3961205720Sjfv * VLAN ID entry. In that case we cannot clear the 3962205720Sjfv * VFTA bit until all pools/VFs using that VLAN ID have also 3963205720Sjfv * been cleared. This will be indicated by "bits" being 3964205720Sjfv * zero. 3965205720Sjfv */ 3966205720Sjfv if (bits) { 3967205720Sjfv IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 3968200239Sjfv (IXGBE_VLVF_VIEN | vlan)); 3969230775Sjfv if ((!vlan_on) && (vfta_changed != NULL)) { 3970205720Sjfv /* someone wants to clear the vfta entry 3971205720Sjfv * but some pools/VFs are still using it. 3972205720Sjfv * Ignore it. */ 3973230775Sjfv *vfta_changed = FALSE; 3974205720Sjfv } 3975230775Sjfv } else 3976205720Sjfv IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0); 3977200239Sjfv } 3978205720Sjfv 3979200239Sjfv return IXGBE_SUCCESS; 3980200239Sjfv} 3981200239Sjfv 3982200239Sjfv/** 3983200239Sjfv * ixgbe_clear_vfta_generic - Clear VLAN filter table 3984200239Sjfv * @hw: pointer to hardware structure 3985200239Sjfv * 3986200239Sjfv * Clears the VLAN filer table, and the VMDq index associated with the filter 3987200239Sjfv **/ 3988200239Sjfvs32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw) 3989200239Sjfv{ 3990200239Sjfv u32 offset; 3991200239Sjfv 3992200239Sjfv DEBUGFUNC("ixgbe_clear_vfta_generic"); 3993200239Sjfv 3994200239Sjfv for (offset = 0; offset < hw->mac.vft_size; offset++) 3995200239Sjfv IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0); 3996200239Sjfv 3997200239Sjfv for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) { 3998200239Sjfv IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0); 3999230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0); 4000230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0); 4001200239Sjfv } 4002200239Sjfv 4003200239Sjfv return IXGBE_SUCCESS; 4004200239Sjfv} 4005200239Sjfv 4006200239Sjfv/** 4007200239Sjfv * ixgbe_check_mac_link_generic - Determine link and speed status 4008200239Sjfv * @hw: pointer to hardware structure 4009200239Sjfv * @speed: pointer to link speed 4010200239Sjfv * @link_up: TRUE when link is up 4011200239Sjfv * @link_up_wait_to_complete: bool used to wait for link up or not 4012200239Sjfv * 4013200239Sjfv * Reads the links register to determine if link is up and the current speed 4014200239Sjfv **/ 4015200239Sjfvs32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 4016230775Sjfv bool *link_up, bool link_up_wait_to_complete) 4017200239Sjfv{ 4018205720Sjfv u32 links_reg, links_orig; 4019200239Sjfv u32 i; 4020200239Sjfv 4021200239Sjfv DEBUGFUNC("ixgbe_check_mac_link_generic"); 4022200239Sjfv 4023205720Sjfv /* clear the old state */ 4024205720Sjfv links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS); 4025205720Sjfv 4026200239Sjfv links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 4027205720Sjfv 4028205720Sjfv if (links_orig != links_reg) { 4029205720Sjfv DEBUGOUT2("LINKS changed from %08X to %08X\n", 4030230775Sjfv links_orig, links_reg); 4031205720Sjfv } 4032205720Sjfv 4033200239Sjfv if (link_up_wait_to_complete) { 4034200239Sjfv for (i = 0; i < IXGBE_LINK_UP_TIME; i++) { 4035200239Sjfv if (links_reg & IXGBE_LINKS_UP) { 4036200239Sjfv *link_up = TRUE; 4037200239Sjfv break; 4038200239Sjfv } else { 4039200239Sjfv *link_up = FALSE; 4040200239Sjfv } 4041200239Sjfv msec_delay(100); 4042200239Sjfv links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS); 4043200239Sjfv } 4044200239Sjfv } else { 4045200239Sjfv if (links_reg & IXGBE_LINKS_UP) 4046200239Sjfv *link_up = TRUE; 4047200239Sjfv else 4048200239Sjfv *link_up = FALSE; 4049200239Sjfv } 4050200239Sjfv 4051200239Sjfv if ((links_reg & IXGBE_LINKS_SPEED_82599) == 4052200239Sjfv IXGBE_LINKS_SPEED_10G_82599) 4053200239Sjfv *speed = IXGBE_LINK_SPEED_10GB_FULL; 4054200239Sjfv else if ((links_reg & IXGBE_LINKS_SPEED_82599) == 4055230775Sjfv IXGBE_LINKS_SPEED_1G_82599) 4056200239Sjfv *speed = IXGBE_LINK_SPEED_1GB_FULL; 4057215911Sjfv else if ((links_reg & IXGBE_LINKS_SPEED_82599) == 4058230775Sjfv IXGBE_LINKS_SPEED_100_82599) 4059215911Sjfv *speed = IXGBE_LINK_SPEED_100_FULL; 4060200239Sjfv else 4061215911Sjfv *speed = IXGBE_LINK_SPEED_UNKNOWN; 4062200239Sjfv 4063200239Sjfv return IXGBE_SUCCESS; 4064200239Sjfv} 4065200239Sjfv 4066200239Sjfv/** 4067200239Sjfv * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from 4068200239Sjfv * the EEPROM 4069200239Sjfv * @hw: pointer to hardware structure 4070200239Sjfv * @wwnn_prefix: the alternative WWNN prefix 4071200239Sjfv * @wwpn_prefix: the alternative WWPN prefix 4072200239Sjfv * 4073200239Sjfv * This function will read the EEPROM from the alternative SAN MAC address 4074200239Sjfv * block to check the support for the alternative WWNN/WWPN prefix support. 4075200239Sjfv **/ 4076200239Sjfvs32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix, 4077230775Sjfv u16 *wwpn_prefix) 4078200239Sjfv{ 4079200239Sjfv u16 offset, caps; 4080200239Sjfv u16 alt_san_mac_blk_offset; 4081200239Sjfv 4082200239Sjfv DEBUGFUNC("ixgbe_get_wwn_prefix_generic"); 4083200239Sjfv 4084200239Sjfv /* clear output first */ 4085200239Sjfv *wwnn_prefix = 0xFFFF; 4086200239Sjfv *wwpn_prefix = 0xFFFF; 4087200239Sjfv 4088200239Sjfv /* check if alternative SAN MAC is supported */ 4089251964Sjfv offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR; 4090251964Sjfv if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset)) 4091251964Sjfv goto wwn_prefix_err; 4092200239Sjfv 4093200239Sjfv if ((alt_san_mac_blk_offset == 0) || 4094200239Sjfv (alt_san_mac_blk_offset == 0xFFFF)) 4095200239Sjfv goto wwn_prefix_out; 4096200239Sjfv 4097200239Sjfv /* check capability in alternative san mac address block */ 4098200239Sjfv offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET; 4099251964Sjfv if (hw->eeprom.ops.read(hw, offset, &caps)) 4100251964Sjfv goto wwn_prefix_err; 4101200239Sjfv if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN)) 4102200239Sjfv goto wwn_prefix_out; 4103200239Sjfv 4104200239Sjfv /* get the corresponding prefix for WWNN/WWPN */ 4105200239Sjfv offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET; 4106251964Sjfv if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) { 4107251964Sjfv ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 4108251964Sjfv "eeprom read at offset %d failed", offset); 4109251964Sjfv } 4110200239Sjfv 4111200239Sjfv offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET; 4112251964Sjfv if (hw->eeprom.ops.read(hw, offset, wwpn_prefix)) 4113251964Sjfv goto wwn_prefix_err; 4114200239Sjfv 4115200239Sjfvwwn_prefix_out: 4116200239Sjfv return IXGBE_SUCCESS; 4117251964Sjfv 4118251964Sjfvwwn_prefix_err: 4119251964Sjfv ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 4120251964Sjfv "eeprom read at offset %d failed", offset); 4121251964Sjfv return IXGBE_SUCCESS; 4122200239Sjfv} 4123215911Sjfv 4124215911Sjfv/** 4125215911Sjfv * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM 4126215911Sjfv * @hw: pointer to hardware structure 4127215911Sjfv * @bs: the fcoe boot status 4128215911Sjfv * 4129215911Sjfv * This function will read the FCOE boot status from the iSCSI FCOE block 4130215911Sjfv **/ 4131215911Sjfvs32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs) 4132215911Sjfv{ 4133215911Sjfv u16 offset, caps, flags; 4134215911Sjfv s32 status; 4135215911Sjfv 4136215911Sjfv DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic"); 4137215911Sjfv 4138215911Sjfv /* clear output first */ 4139215911Sjfv *bs = ixgbe_fcoe_bootstatus_unavailable; 4140215911Sjfv 4141215911Sjfv /* check if FCOE IBA block is present */ 4142215911Sjfv offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR; 4143215911Sjfv status = hw->eeprom.ops.read(hw, offset, &caps); 4144215911Sjfv if (status != IXGBE_SUCCESS) 4145215911Sjfv goto out; 4146215911Sjfv 4147215911Sjfv if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE)) 4148215911Sjfv goto out; 4149215911Sjfv 4150215911Sjfv /* check if iSCSI FCOE block is populated */ 4151215911Sjfv status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset); 4152215911Sjfv if (status != IXGBE_SUCCESS) 4153215911Sjfv goto out; 4154215911Sjfv 4155215911Sjfv if ((offset == 0) || (offset == 0xFFFF)) 4156215911Sjfv goto out; 4157215911Sjfv 4158215911Sjfv /* read fcoe flags in iSCSI FCOE block */ 4159215911Sjfv offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET; 4160215911Sjfv status = hw->eeprom.ops.read(hw, offset, &flags); 4161215911Sjfv if (status != IXGBE_SUCCESS) 4162215911Sjfv goto out; 4163215911Sjfv 4164215911Sjfv if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE) 4165215911Sjfv *bs = ixgbe_fcoe_bootstatus_enabled; 4166215911Sjfv else 4167215911Sjfv *bs = ixgbe_fcoe_bootstatus_disabled; 4168215911Sjfv 4169215911Sjfvout: 4170215911Sjfv return status; 4171215911Sjfv} 4172215911Sjfv 4173215911Sjfv/** 4174215911Sjfv * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing 4175215911Sjfv * @hw: pointer to hardware structure 4176215911Sjfv * @enable: enable or disable switch for anti-spoofing 4177215911Sjfv * @pf: Physical Function pool - do not enable anti-spoofing for the PF 4178215911Sjfv * 4179215911Sjfv **/ 4180215911Sjfvvoid ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf) 4181215911Sjfv{ 4182215911Sjfv int j; 4183215911Sjfv int pf_target_reg = pf >> 3; 4184215911Sjfv int pf_target_shift = pf % 8; 4185215911Sjfv u32 pfvfspoof = 0; 4186215911Sjfv 4187215911Sjfv if (hw->mac.type == ixgbe_mac_82598EB) 4188215911Sjfv return; 4189215911Sjfv 4190215911Sjfv if (enable) 4191215911Sjfv pfvfspoof = IXGBE_SPOOF_MACAS_MASK; 4192215911Sjfv 4193215911Sjfv /* 4194215911Sjfv * PFVFSPOOF register array is size 8 with 8 bits assigned to 4195215911Sjfv * MAC anti-spoof enables in each register array element. 4196215911Sjfv */ 4197238149Sjfv for (j = 0; j < pf_target_reg; j++) 4198215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof); 4199215911Sjfv 4200215911Sjfv /* 4201215911Sjfv * The PF should be allowed to spoof so that it can support 4202238149Sjfv * emulation mode NICs. Do not set the bits assigned to the PF 4203215911Sjfv */ 4204238149Sjfv pfvfspoof &= (1 << pf_target_shift) - 1; 4205238149Sjfv IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof); 4206238149Sjfv 4207238149Sjfv /* 4208238149Sjfv * Remaining pools belong to the PF so they do not need to have 4209238149Sjfv * anti-spoofing enabled. 4210238149Sjfv */ 4211238149Sjfv for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++) 4212238149Sjfv IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0); 4213215911Sjfv} 4214215911Sjfv 4215215911Sjfv/** 4216215911Sjfv * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing 4217215911Sjfv * @hw: pointer to hardware structure 4218215911Sjfv * @enable: enable or disable switch for VLAN anti-spoofing 4219215911Sjfv * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing 4220215911Sjfv * 4221215911Sjfv **/ 4222215911Sjfvvoid ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 4223215911Sjfv{ 4224215911Sjfv int vf_target_reg = vf >> 3; 4225215911Sjfv int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT; 4226215911Sjfv u32 pfvfspoof; 4227215911Sjfv 4228215911Sjfv if (hw->mac.type == ixgbe_mac_82598EB) 4229215911Sjfv return; 4230215911Sjfv 4231215911Sjfv pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 4232215911Sjfv if (enable) 4233215911Sjfv pfvfspoof |= (1 << vf_target_shift); 4234215911Sjfv else 4235215911Sjfv pfvfspoof &= ~(1 << vf_target_shift); 4236215911Sjfv IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 4237215911Sjfv} 4238217593Sjfv 4239217593Sjfv/** 4240217593Sjfv * ixgbe_get_device_caps_generic - Get additional device capabilities 4241217593Sjfv * @hw: pointer to hardware structure 4242217593Sjfv * @device_caps: the EEPROM word with the extra device capabilities 4243217593Sjfv * 4244217593Sjfv * This function will read the EEPROM location for the device capabilities, 4245217593Sjfv * and return the word through device_caps. 4246217593Sjfv **/ 4247217593Sjfvs32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps) 4248217593Sjfv{ 4249217593Sjfv DEBUGFUNC("ixgbe_get_device_caps_generic"); 4250217593Sjfv 4251217593Sjfv hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps); 4252217593Sjfv 4253217593Sjfv return IXGBE_SUCCESS; 4254217593Sjfv} 4255217593Sjfv 4256217593Sjfv/** 4257217593Sjfv * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering 4258217593Sjfv * @hw: pointer to hardware structure 4259217593Sjfv * 4260217593Sjfv **/ 4261217593Sjfvvoid ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw) 4262217593Sjfv{ 4263217593Sjfv u32 regval; 4264217593Sjfv u32 i; 4265217593Sjfv 4266217593Sjfv DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2"); 4267217593Sjfv 4268217593Sjfv /* Enable relaxed ordering */ 4269217593Sjfv for (i = 0; i < hw->mac.max_tx_queues; i++) { 4270217593Sjfv regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i)); 4271238149Sjfv regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN; 4272217593Sjfv IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval); 4273217593Sjfv } 4274217593Sjfv 4275217593Sjfv for (i = 0; i < hw->mac.max_rx_queues; i++) { 4276217593Sjfv regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i)); 4277238149Sjfv regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN | 4278238149Sjfv IXGBE_DCA_RXCTRL_HEAD_WRO_EN; 4279217593Sjfv IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval); 4280217593Sjfv } 4281217593Sjfv 4282217593Sjfv} 4283230775Sjfv 4284230775Sjfv/** 4285230775Sjfv * ixgbe_calculate_checksum - Calculate checksum for buffer 4286230775Sjfv * @buffer: pointer to EEPROM 4287230775Sjfv * @length: size of EEPROM to calculate a checksum for 4288230775Sjfv * Calculates the checksum for some buffer on a specified length. The 4289230775Sjfv * checksum calculated is returned. 4290230775Sjfv **/ 4291247822Sjfvu8 ixgbe_calculate_checksum(u8 *buffer, u32 length) 4292230775Sjfv{ 4293230775Sjfv u32 i; 4294230775Sjfv u8 sum = 0; 4295230775Sjfv 4296230775Sjfv DEBUGFUNC("ixgbe_calculate_checksum"); 4297230775Sjfv 4298230775Sjfv if (!buffer) 4299230775Sjfv return 0; 4300230775Sjfv 4301230775Sjfv for (i = 0; i < length; i++) 4302230775Sjfv sum += buffer[i]; 4303230775Sjfv 4304230775Sjfv return (u8) (0 - sum); 4305230775Sjfv} 4306230775Sjfv 4307230775Sjfv/** 4308230775Sjfv * ixgbe_host_interface_command - Issue command to manageability block 4309230775Sjfv * @hw: pointer to the HW structure 4310230775Sjfv * @buffer: contains the command to write and where the return status will 4311230775Sjfv * be placed 4312238149Sjfv * @length: length of buffer, must be multiple of 4 bytes 4313230775Sjfv * 4314230775Sjfv * Communicates with the manageability block. On success return IXGBE_SUCCESS 4315230775Sjfv * else return IXGBE_ERR_HOST_INTERFACE_COMMAND. 4316230775Sjfv **/ 4317247822Sjfvs32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer, 4318247822Sjfv u32 length) 4319230775Sjfv{ 4320230775Sjfv u32 hicr, i, bi; 4321230775Sjfv u32 hdr_size = sizeof(struct ixgbe_hic_hdr); 4322230775Sjfv u8 buf_len, dword_len; 4323230775Sjfv 4324230775Sjfv s32 ret_val = IXGBE_SUCCESS; 4325230775Sjfv 4326230775Sjfv DEBUGFUNC("ixgbe_host_interface_command"); 4327230775Sjfv 4328230775Sjfv if (length == 0 || length & 0x3 || 4329230775Sjfv length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) { 4330230775Sjfv DEBUGOUT("Buffer length failure.\n"); 4331230775Sjfv ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 4332230775Sjfv goto out; 4333230775Sjfv } 4334230775Sjfv 4335230775Sjfv /* Check that the host interface is enabled. */ 4336230775Sjfv hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 4337230775Sjfv if ((hicr & IXGBE_HICR_EN) == 0) { 4338230775Sjfv DEBUGOUT("IXGBE_HOST_EN bit disabled.\n"); 4339230775Sjfv ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 4340230775Sjfv goto out; 4341230775Sjfv } 4342230775Sjfv 4343230775Sjfv /* Calculate length in DWORDs */ 4344230775Sjfv dword_len = length >> 2; 4345230775Sjfv 4346230775Sjfv /* 4347230775Sjfv * The device driver writes the relevant command block 4348230775Sjfv * into the ram area. 4349230775Sjfv */ 4350230775Sjfv for (i = 0; i < dword_len; i++) 4351230775Sjfv IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG, 4352230775Sjfv i, IXGBE_CPU_TO_LE32(buffer[i])); 4353230775Sjfv 4354230775Sjfv /* Setting this bit tells the ARC that a new command is pending. */ 4355230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C); 4356230775Sjfv 4357230775Sjfv for (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) { 4358230775Sjfv hicr = IXGBE_READ_REG(hw, IXGBE_HICR); 4359230775Sjfv if (!(hicr & IXGBE_HICR_C)) 4360230775Sjfv break; 4361230775Sjfv msec_delay(1); 4362230775Sjfv } 4363230775Sjfv 4364230775Sjfv /* Check command successful completion. */ 4365230775Sjfv if (i == IXGBE_HI_COMMAND_TIMEOUT || 4366230775Sjfv (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) { 4367230775Sjfv DEBUGOUT("Command has failed with no status valid.\n"); 4368230775Sjfv ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 4369230775Sjfv goto out; 4370230775Sjfv } 4371230775Sjfv 4372230775Sjfv /* Calculate length in DWORDs */ 4373230775Sjfv dword_len = hdr_size >> 2; 4374230775Sjfv 4375230775Sjfv /* first pull in the header so we know the buffer length */ 4376230775Sjfv for (bi = 0; bi < dword_len; bi++) { 4377230775Sjfv buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 4378230775Sjfv IXGBE_LE32_TO_CPUS(&buffer[bi]); 4379230775Sjfv } 4380230775Sjfv 4381230775Sjfv /* If there is any thing in data position pull it in */ 4382230775Sjfv buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len; 4383230775Sjfv if (buf_len == 0) 4384230775Sjfv goto out; 4385230775Sjfv 4386230775Sjfv if (length < (buf_len + hdr_size)) { 4387230775Sjfv DEBUGOUT("Buffer not large enough for reply message.\n"); 4388230775Sjfv ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 4389230775Sjfv goto out; 4390230775Sjfv } 4391230775Sjfv 4392230775Sjfv /* Calculate length in DWORDs, add 3 for odd lengths */ 4393230775Sjfv dword_len = (buf_len + 3) >> 2; 4394230775Sjfv 4395230775Sjfv /* Pull in the rest of the buffer (bi is where we left off)*/ 4396230775Sjfv for (; bi <= dword_len; bi++) { 4397230775Sjfv buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi); 4398230775Sjfv IXGBE_LE32_TO_CPUS(&buffer[bi]); 4399230775Sjfv } 4400230775Sjfv 4401230775Sjfvout: 4402230775Sjfv return ret_val; 4403230775Sjfv} 4404230775Sjfv 4405230775Sjfv/** 4406230775Sjfv * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware 4407230775Sjfv * @hw: pointer to the HW structure 4408230775Sjfv * @maj: driver version major number 4409230775Sjfv * @min: driver version minor number 4410230775Sjfv * @build: driver version build number 4411230775Sjfv * @sub: driver version sub build number 4412230775Sjfv * 4413230775Sjfv * Sends driver version number to firmware through the manageability 4414230775Sjfv * block. On success return IXGBE_SUCCESS 4415230775Sjfv * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring 4416230775Sjfv * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails. 4417230775Sjfv **/ 4418230775Sjfvs32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min, 4419230775Sjfv u8 build, u8 sub) 4420230775Sjfv{ 4421230775Sjfv struct ixgbe_hic_drv_info fw_cmd; 4422230775Sjfv int i; 4423230775Sjfv s32 ret_val = IXGBE_SUCCESS; 4424230775Sjfv 4425230775Sjfv DEBUGFUNC("ixgbe_set_fw_drv_ver_generic"); 4426230775Sjfv 4427230775Sjfv if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM) 4428230775Sjfv != IXGBE_SUCCESS) { 4429230775Sjfv ret_val = IXGBE_ERR_SWFW_SYNC; 4430230775Sjfv goto out; 4431230775Sjfv } 4432230775Sjfv 4433230775Sjfv fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO; 4434230775Sjfv fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN; 4435230775Sjfv fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 4436230775Sjfv fw_cmd.port_num = (u8)hw->bus.func; 4437230775Sjfv fw_cmd.ver_maj = maj; 4438230775Sjfv fw_cmd.ver_min = min; 4439230775Sjfv fw_cmd.ver_build = build; 4440230775Sjfv fw_cmd.ver_sub = sub; 4441230775Sjfv fw_cmd.hdr.checksum = 0; 4442230775Sjfv fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd, 4443230775Sjfv (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len)); 4444230775Sjfv fw_cmd.pad = 0; 4445230775Sjfv fw_cmd.pad2 = 0; 4446230775Sjfv 4447230775Sjfv for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) { 4448230775Sjfv ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 4449230775Sjfv sizeof(fw_cmd)); 4450230775Sjfv if (ret_val != IXGBE_SUCCESS) 4451230775Sjfv continue; 4452230775Sjfv 4453230775Sjfv if (fw_cmd.hdr.cmd_or_resp.ret_status == 4454230775Sjfv FW_CEM_RESP_STATUS_SUCCESS) 4455230775Sjfv ret_val = IXGBE_SUCCESS; 4456230775Sjfv else 4457230775Sjfv ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND; 4458230775Sjfv 4459230775Sjfv break; 4460230775Sjfv } 4461230775Sjfv 4462230775Sjfv hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM); 4463230775Sjfvout: 4464230775Sjfv return ret_val; 4465230775Sjfv} 4466230775Sjfv 4467230775Sjfv/** 4468230775Sjfv * ixgbe_set_rxpba_generic - Initialize Rx packet buffer 4469230775Sjfv * @hw: pointer to hardware structure 4470230775Sjfv * @num_pb: number of packet buffers to allocate 4471230775Sjfv * @headroom: reserve n KB of headroom 4472230775Sjfv * @strategy: packet buffer allocation strategy 4473230775Sjfv **/ 4474230775Sjfvvoid ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom, 4475230775Sjfv int strategy) 4476230775Sjfv{ 4477230775Sjfv u32 pbsize = hw->mac.rx_pb_size; 4478230775Sjfv int i = 0; 4479230775Sjfv u32 rxpktsize, txpktsize, txpbthresh; 4480230775Sjfv 4481230775Sjfv /* Reserve headroom */ 4482230775Sjfv pbsize -= headroom; 4483230775Sjfv 4484230775Sjfv if (!num_pb) 4485230775Sjfv num_pb = 1; 4486230775Sjfv 4487230775Sjfv /* Divide remaining packet buffer space amongst the number of packet 4488230775Sjfv * buffers requested using supplied strategy. 4489230775Sjfv */ 4490230775Sjfv switch (strategy) { 4491238149Sjfv case PBA_STRATEGY_WEIGHTED: 4492230775Sjfv /* ixgbe_dcb_pba_80_48 strategy weight first half of packet 4493230775Sjfv * buffer with 5/8 of the packet buffer space. 4494230775Sjfv */ 4495238149Sjfv rxpktsize = (pbsize * 5) / (num_pb * 4); 4496230775Sjfv pbsize -= rxpktsize * (num_pb / 2); 4497230775Sjfv rxpktsize <<= IXGBE_RXPBSIZE_SHIFT; 4498230775Sjfv for (; i < (num_pb / 2); i++) 4499230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 4500230775Sjfv /* Fall through to configure remaining packet buffers */ 4501238149Sjfv case PBA_STRATEGY_EQUAL: 4502230775Sjfv rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT; 4503230775Sjfv for (; i < num_pb; i++) 4504230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize); 4505230775Sjfv break; 4506230775Sjfv default: 4507230775Sjfv break; 4508230775Sjfv } 4509230775Sjfv 4510230775Sjfv /* Only support an equally distributed Tx packet buffer strategy. */ 4511230775Sjfv txpktsize = IXGBE_TXPBSIZE_MAX / num_pb; 4512230775Sjfv txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX; 4513230775Sjfv for (i = 0; i < num_pb; i++) { 4514230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize); 4515230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh); 4516230775Sjfv } 4517230775Sjfv 4518230775Sjfv /* Clear unused TCs, if any, to zero buffer size*/ 4519230775Sjfv for (; i < IXGBE_MAX_PB; i++) { 4520230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0); 4521230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0); 4522230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0); 4523230775Sjfv } 4524230775Sjfv} 4525230775Sjfv 4526230775Sjfv/** 4527230775Sjfv * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo 4528230775Sjfv * @hw: pointer to the hardware structure 4529230775Sjfv * 4530230775Sjfv * The 82599 and x540 MACs can experience issues if TX work is still pending 4531230775Sjfv * when a reset occurs. This function prevents this by flushing the PCIe 4532230775Sjfv * buffers on the system. 4533230775Sjfv **/ 4534230775Sjfvvoid ixgbe_clear_tx_pending(struct ixgbe_hw *hw) 4535230775Sjfv{ 4536230775Sjfv u32 gcr_ext, hlreg0; 4537230775Sjfv 4538230775Sjfv /* 4539230775Sjfv * If double reset is not requested then all transactions should 4540230775Sjfv * already be clear and as such there is no work to do 4541230775Sjfv */ 4542230775Sjfv if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED)) 4543230775Sjfv return; 4544230775Sjfv 4545230775Sjfv /* 4546230775Sjfv * Set loopback enable to prevent any transmits from being sent 4547230775Sjfv * should the link come up. This assumes that the RXCTRL.RXEN bit 4548230775Sjfv * has already been cleared. 4549230775Sjfv */ 4550230775Sjfv hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 4551230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK); 4552230775Sjfv 4553230775Sjfv /* initiate cleaning flow for buffers in the PCIe transaction layer */ 4554230775Sjfv gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT); 4555230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, 4556230775Sjfv gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR); 4557230775Sjfv 4558230775Sjfv /* Flush all writes and allow 20usec for all transactions to clear */ 4559230775Sjfv IXGBE_WRITE_FLUSH(hw); 4560230775Sjfv usec_delay(20); 4561230775Sjfv 4562230775Sjfv /* restore previous register values */ 4563230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext); 4564230775Sjfv IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 4565230775Sjfv} 4566230775Sjfv 4567251964Sjfv 4568251964Sjfv/** 4569251964Sjfv * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg 4570251964Sjfv * @hw: pointer to hardware structure 4571251964Sjfv * @map: pointer to u8 arr for returning map 4572251964Sjfv * 4573251964Sjfv * Read the rtrup2tc HW register and resolve its content into map 4574251964Sjfv **/ 4575251964Sjfvvoid ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map) 4576251964Sjfv{ 4577251964Sjfv u32 reg, i; 4578251964Sjfv 4579251964Sjfv reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC); 4580251964Sjfv for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++) 4581251964Sjfv map[i] = IXGBE_RTRUP2TC_UP_MASK & 4582251964Sjfv (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT)); 4583251964Sjfv return; 4584251964Sjfv} 4585