1233539Sjchandra/*- 2233539Sjchandra * Copyright (c) 2003-2012 Broadcom Corporation 3233539Sjchandra * All Rights Reserved 4233539Sjchandra * 5233539Sjchandra * Redistribution and use in source and binary forms, with or without 6233539Sjchandra * modification, are permitted provided that the following conditions 7233539Sjchandra * are met: 8233539Sjchandra * 9233539Sjchandra * 1. Redistributions of source code must retain the above copyright 10233539Sjchandra * notice, this list of conditions and the following disclaimer. 11233539Sjchandra * 2. Redistributions in binary form must reproduce the above copyright 12233539Sjchandra * notice, this list of conditions and the following disclaimer in 13233539Sjchandra * the documentation and/or other materials provided with the 14233539Sjchandra * distribution. 15233539Sjchandra * 16233539Sjchandra * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR 17233539Sjchandra * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18233539Sjchandra * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19233539Sjchandra * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE 20233539Sjchandra * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21233539Sjchandra * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22233539Sjchandra * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 23233539Sjchandra * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24233539Sjchandra * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 25233539Sjchandra * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 26233539Sjchandra * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27233539Sjchandra * 28233539Sjchandra * $FreeBSD$ 29233539Sjchandra */ 30233539Sjchandra 31233539Sjchandra#ifndef __OPENCORE_I2C_H__ 32233539Sjchandra#define __OPENCORE_I2C_H__ 33233539Sjchandra 34233539Sjchandra/* I2C specific registers */ 35233539Sjchandra#define OC_I2C_PRESCALE_LO_REG 0x00 36233539Sjchandra#define OC_I2C_PRESCALE_HI_REG 0x01 37233539Sjchandra#define OC_I2C_CTRL_REG 0x02 38233539Sjchandra#define OC_I2C_TRANSMIT_REG 0x03 /* tx and rx - same reg */ 39233539Sjchandra#define OC_I2C_RECV_REG 0x03 /* tx and rx - same reg */ 40233539Sjchandra#define OC_I2C_DATA_REG 0x03 /* tx and rx - same reg */ 41233539Sjchandra#define OC_I2C_CMD_REG 0x04 /* cmd and status - same reg */ 42233539Sjchandra#define OC_I2C_STATUS_REG 0x04 /* cmd and status - same reg */ 43233539Sjchandra 44233539Sjchandra#define XLP_I2C_CLKFREQ 133333333 /* XLP 133 MHz IO clock */ 45233539Sjchandra#define XLP_I2C_FREQ 100000 /* default 100kHz */ 46233539Sjchandra#define I2C_TIMEOUT 500000 47233539Sjchandra 48233539Sjchandra/* 49233539Sjchandra * These defines pertain to the OpenCores 50233539Sjchandra * I2C Master Host Controller used in XLP 51233539Sjchandra */ 52233539Sjchandra 53233539Sjchandra#define OC_PRESCALER_LO 0 54233539Sjchandra#define OC_PRESCALER_HI 1 55233539Sjchandra 56233539Sjchandra#define OC_CONTROL 2 57233539Sjchandra#define OC_CONTROL_EN 0x80 58233539Sjchandra#define OC_CONTROL_IEN 0x40 59233539Sjchandra 60233539Sjchandra#define OC_DATA 3 /* Data TX & RX Reg */ 61233539Sjchandra 62233539Sjchandra#define OC_COMMAND 4 63233539Sjchandra#define OC_COMMAND_START 0x90 64233539Sjchandra#define OC_COMMAND_STOP 0x40 65233539Sjchandra#define OC_COMMAND_READ 0x20 66233539Sjchandra#define OC_COMMAND_WRITE 0x10 67233539Sjchandra#define OC_COMMAND_RDACK 0x20 68233539Sjchandra#define OC_COMMAND_RDNACK 0x28 69233539Sjchandra#define OC_COMMAND_IACK 0x01 /* Not used */ 70233539Sjchandra 71233539Sjchandra#define OC_STATUS 4 /* Same as 'command' */ 72233539Sjchandra#define OC_STATUS_NACK 0x80 /* Did not get an ACK */ 73233539Sjchandra#define OC_STATUS_BUSY 0x40 74233539Sjchandra#define OC_STATUS_AL 0x20 /* Arbitration Lost */ 75233539Sjchandra#define OC_STATUS_TIP 0x02 /* Transfer in Progress */ 76233539Sjchandra#define OC_STATUS_IF 0x01 /* Intr. Pending Flag */ 77233539Sjchandra 78233539Sjchandra#endif 79