fwohcireg.h revision 125239 
1/*
2 * Copyright (c) 2003 Hidetoshi Shimokawa
3 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 *    must display the acknowledgement as bellow:
16 *
17 *    This product includes software developed by K. Kobayashi and H. Shimokawa
18 *
19 * 4. The name of the author may not be used to endorse or promote products
20 *    derived from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
32 * POSSIBILITY OF SUCH DAMAGE.
33 *
34 * $FreeBSD: head/sys/dev/firewire/fwohcireg.h 125239 2004-01-30 14:30:19Z simokawa $
35 *
36 */
37#define		PCI_CBMEM		0x10
38
39#define		FW_VENDORID_NEC		0x1033
40#define		FW_VENDORID_TI		0x104c
41#define		FW_VENDORID_SONY	0x104d
42#define		FW_VENDORID_VIA		0x1106
43#define		FW_VENDORID_RICOH	0x1180
44#define		FW_VENDORID_APPLE	0x106b
45#define		FW_VENDORID_LUCENT	0x11c1
46
47#define		FW_DEVICE_UPD861	(0x0063 << 16)
48#define		FW_DEVICE_UPD871	(0x00ce << 16)
49#define		FW_DEVICE_UPD72870	(0x00cd << 16)
50#define		FW_DEVICE_UPD72873	(0x00e7 << 16)
51#define		FW_DEVICE_UPD72874	(0x00f2 << 16)
52#define		FW_DEVICE_TITSB22	(0x8009 << 16)
53#define		FW_DEVICE_TITSB23	(0x8019 << 16)
54#define		FW_DEVICE_TITSB26	(0x8020 << 16)
55#define		FW_DEVICE_TITSB43	(0x8021 << 16)
56#define		FW_DEVICE_TITSB43A	(0x8023 << 16)
57#define		FW_DEVICE_TITSB43AB23	(0x8024 << 16)
58#define		FW_DEVICE_TITSB82AA2	(0x8025 << 16)
59#define		FW_DEVICE_TIPCI4410A	(0x8017 << 16)
60#define		FW_DEVICE_TIPCI4450	(0x8011 << 16)
61#define		FW_DEVICE_TIPCI4451	(0x8027 << 16)
62#define		FW_DEVICE_CX3022	(0x8039 << 16)
63#define		FW_DEVICE_VT6306	(0x3044 << 16)
64#define		FW_DEVICE_R5C551	(0x0551 << 16)
65#define		FW_DEVICE_R5C552	(0x0552 << 16)
66#define		FW_DEVICE_PANGEA	(0x0030 << 16)
67#define		FW_DEVICE_UNINORTH	(0x0031 << 16)
68#define		FW_DEVICE_FW322		(0x5811 << 16)
69
70#define PCI_INTERFACE_OHCI	0x10
71
72#define FW_OHCI_BASE_REG	0x10
73
74#define		OHCI_DMA_ITCH		0x20
75#define		OHCI_DMA_IRCH		0x20
76
77#define		OHCI_MAX_DMA_CH		(0x4 + OHCI_DMA_ITCH + OHCI_DMA_IRCH)
78
79
80typedef u_int32_t 	fwohcireg_t;
81
82/* for PCI */
83#if BYTE_ORDER == BIG_ENDIAN
84#define FWOHCI_DMA_WRITE(x, y)	((x) = htole32(y))
85#define FWOHCI_DMA_READ(x)	le32toh(x)
86#define FWOHCI_DMA_SET(x, y)	((x) |= htole32(y))
87#define FWOHCI_DMA_CLEAR(x, y)	((x) &= htole32(~(y)))
88#else
89#define FWOHCI_DMA_WRITE(x, y)	((x) = (y))
90#define FWOHCI_DMA_READ(x)	(x)
91#define FWOHCI_DMA_SET(x, y)	((x) |= (y))
92#define FWOHCI_DMA_CLEAR(x, y)	((x) &= ~(y))
93#endif
94
95struct fwohcidb {
96	union {
97		struct {
98			u_int32_t cmd;
99			u_int32_t addr;
100			u_int32_t depend;
101			u_int32_t res;
102		} desc;
103		u_int32_t immed[4];
104	} db;
105#define OHCI_STATUS_SHIFT	16
106#define OHCI_COUNT_MASK		0xffff
107#define OHCI_OUTPUT_MORE	(0 << 28)
108#define OHCI_OUTPUT_LAST	(1 << 28)
109#define OHCI_INPUT_MORE		(2 << 28)
110#define OHCI_INPUT_LAST		(3 << 28)
111#define OHCI_STORE_QUAD		(4 << 28)
112#define OHCI_LOAD_QUAD		(5 << 28)
113#define OHCI_NOP		(6 << 28)
114#define OHCI_STOP		(7 << 28)
115#define OHCI_STORE		(8 << 28)
116#define OHCI_CMD_MASK		(0xf << 28)
117
118#define	OHCI_UPDATE		(1 << 27)
119
120#define OHCI_KEY_ST0		(0 << 24)
121#define OHCI_KEY_ST1		(1 << 24)
122#define OHCI_KEY_ST2		(2 << 24)
123#define OHCI_KEY_ST3		(3 << 24)
124#define OHCI_KEY_REGS		(5 << 24)
125#define OHCI_KEY_SYS		(6 << 24)
126#define OHCI_KEY_DEVICE		(7 << 24)
127#define OHCI_KEY_MASK		(7 << 24)
128
129#define OHCI_INTERRUPT_NEVER	(0 << 20)
130#define OHCI_INTERRUPT_TRUE	(1 << 20)
131#define OHCI_INTERRUPT_FALSE	(2 << 20)
132#define OHCI_INTERRUPT_ALWAYS	(3 << 20)
133
134#define OHCI_BRANCH_NEVER	(0 << 18)
135#define OHCI_BRANCH_TRUE	(1 << 18)
136#define OHCI_BRANCH_FALSE	(2 << 18)
137#define OHCI_BRANCH_ALWAYS	(3 << 18)
138#define OHCI_BRANCH_MASK	(3 << 18)
139
140#define OHCI_WAIT_NEVER		(0 << 16)
141#define OHCI_WAIT_TRUE		(1 << 16)
142#define OHCI_WAIT_FALSE		(2 << 16)
143#define OHCI_WAIT_ALWAYS	(3 << 16)
144};
145
146#define OHCI_SPD_S100 0x4
147#define OHCI_SPD_S200 0x1
148#define OHCI_SPD_S400 0x2
149
150
151#define FWOHCIEV_NOSTAT 0
152#define FWOHCIEV_LONGP 2
153#define FWOHCIEV_MISSACK 3
154#define FWOHCIEV_UNDRRUN 4
155#define FWOHCIEV_OVRRUN 5
156#define FWOHCIEV_DESCERR 6
157#define FWOHCIEV_DTRDERR 7
158#define FWOHCIEV_DTWRERR 8
159#define FWOHCIEV_BUSRST 9
160#define FWOHCIEV_TIMEOUT 0xa
161#define FWOHCIEV_TCODERR 0xb
162#define FWOHCIEV_UNKNOWN 0xe
163#define FWOHCIEV_FLUSHED 0xf
164#define FWOHCIEV_ACKCOMPL 0x11
165#define FWOHCIEV_ACKPEND 0x12
166#define FWOHCIEV_ACKBSX 0x14
167#define FWOHCIEV_ACKBSA 0x15
168#define FWOHCIEV_ACKBSB 0x16
169#define FWOHCIEV_ACKTARD 0x1b
170#define FWOHCIEV_ACKDERR 0x1d
171#define FWOHCIEV_ACKTERR 0x1e
172
173#define FWOHCIEV_MASK 0x1f
174
175struct ohci_dma{
176	fwohcireg_t	cntl;
177
178#define	OHCI_CNTL_CYCMATCH_S	(0x1 << 31)
179
180#define	OHCI_CNTL_BUFFIL	(0x1 << 31)
181#define	OHCI_CNTL_ISOHDR	(0x1 << 30)
182#define	OHCI_CNTL_CYCMATCH_R	(0x1 << 29)
183#define	OHCI_CNTL_MULTICH	(0x1 << 28)
184
185#define	OHCI_CNTL_DMA_RUN	(0x1 << 15)
186#define	OHCI_CNTL_DMA_WAKE	(0x1 << 12)
187#define	OHCI_CNTL_DMA_DEAD	(0x1 << 11)
188#define	OHCI_CNTL_DMA_ACTIVE	(0x1 << 10)
189#define	OHCI_CNTL_DMA_BT	(0x1 << 8)
190#define	OHCI_CNTL_DMA_BAD	(0x1 << 7)
191#define	OHCI_CNTL_DMA_STAT	(0xff)
192
193	fwohcireg_t	cntl_clr;
194	fwohcireg_t	dummy0;
195	fwohcireg_t	cmd;
196	fwohcireg_t	match;
197	fwohcireg_t	dummy1;
198	fwohcireg_t	dummy2;
199	fwohcireg_t	dummy3;
200};
201
202struct ohci_itdma{
203	fwohcireg_t	cntl;
204	fwohcireg_t	cntl_clr;
205	fwohcireg_t	dummy0;
206	fwohcireg_t	cmd;
207};
208
209struct ohci_registers {
210	fwohcireg_t	ver;		/* Version No. 0x0 */
211	fwohcireg_t	guid;		/* GUID_ROM No. 0x4 */
212	fwohcireg_t	retry;		/* AT retries 0x8 */
213#define FWOHCI_RETRY	0x8
214	fwohcireg_t	csr_data;	/* CSR data   0xc */
215	fwohcireg_t	csr_cmp;	/* CSR compare 0x10 */
216	fwohcireg_t	csr_cntl;	/* CSR compare 0x14 */
217	fwohcireg_t	rom_hdr;	/* config ROM ptr. 0x18 */
218	fwohcireg_t	bus_id;		/* BUS_ID 0x1c */
219	fwohcireg_t	bus_opt;	/* BUS option 0x20 */
220#define	FWOHCIGUID_H	0x24
221#define	FWOHCIGUID_L	0x28
222	fwohcireg_t	guid_hi;	/* GUID hi 0x24 */
223	fwohcireg_t	guid_lo;	/* GUID lo 0x28 */
224	fwohcireg_t	dummy0[2];	/* dummy 0x2c-0x30 */
225	fwohcireg_t	config_rom;	/* config ROM map 0x34 */
226	fwohcireg_t	post_wr_lo;	/* post write addr lo 0x38 */
227	fwohcireg_t	post_wr_hi;	/* post write addr hi 0x3c */
228	fwohcireg_t	vender;		/* vender ID 0x40 */
229	fwohcireg_t	dummy1[3];	/* dummy 0x44-0x4c */
230	fwohcireg_t	hcc_cntl_set;	/* HCC control set 0x50 */
231	fwohcireg_t	hcc_cntl_clr;	/* HCC control clr 0x54 */
232#define	OHCI_HCC_BIBIV	(1 << 31)	/* BIBimage Valid */
233#define	OHCI_HCC_BIGEND	(1 << 30)	/* noByteSwapData */
234#define	OHCI_HCC_PRPHY	(1 << 23)	/* programPhyEnable */
235#define	OHCI_HCC_PHYEN	(1 << 22)	/* aPhyEnhanceEnable */
236#define	OHCI_HCC_LPS	(1 << 19)	/* LPS */
237#define	OHCI_HCC_POSTWR	(1 << 18)	/* postedWriteEnable */
238#define	OHCI_HCC_LINKEN	(1 << 17)	/* linkEnable */
239#define	OHCI_HCC_RESET	(1 << 16)	/* softReset */
240	fwohcireg_t	dummy2[2];	/* dummy 0x58-0x5c */
241	fwohcireg_t	dummy3[1];	/* dummy 0x60 */
242	fwohcireg_t	sid_buf;	/* self id buffer 0x64 */
243	fwohcireg_t	sid_cnt;	/* self id count 0x68 */
244	fwohcireg_t	dummy4[1];	/* dummy 0x6c */
245	fwohcireg_t	ir_mask_hi_set;	/* ir mask hi set 0x70 */
246	fwohcireg_t	ir_mask_hi_clr;	/* ir mask hi set 0x74 */
247	fwohcireg_t	ir_mask_lo_set;	/* ir mask hi set 0x78 */
248	fwohcireg_t	ir_mask_lo_clr;	/* ir mask hi set 0x7c */
249#define	FWOHCI_INTSTAT		0x80
250#define	FWOHCI_INTSTATCLR	0x84
251#define	FWOHCI_INTMASK		0x88
252#define	FWOHCI_INTMASKCLR	0x8c
253	fwohcireg_t	int_stat;   /*       0x80 */
254	fwohcireg_t	int_clear;  /*       0x84 */
255	fwohcireg_t	int_mask;   /*       0x88 */
256	fwohcireg_t	int_mask_clear;   /*       0x8c */
257	fwohcireg_t	it_int_stat;   /*       0x90 */
258	fwohcireg_t	it_int_clear;  /*       0x94 */
259	fwohcireg_t	it_int_mask;   /*       0x98 */
260	fwohcireg_t	it_mask_clear;   /*       0x9c */
261	fwohcireg_t	ir_int_stat;   /*       0xa0 */
262	fwohcireg_t	ir_int_clear;  /*       0xa4 */
263	fwohcireg_t	ir_int_mask;   /*       0xa8 */
264	fwohcireg_t	ir_mask_clear;   /*       0xac */
265	fwohcireg_t	dummy5[11];	/* dummy 0xb0-d8 */
266	fwohcireg_t	fairness;   /* fairness control      0xdc */
267	fwohcireg_t	link_cntl;		/* Chip control 0xe0*/
268	fwohcireg_t	link_cntl_clr;	/* Chip control clear 0xe4*/
269#define FWOHCI_NODEID	0xe8
270	fwohcireg_t	node;		/* Node ID 0xe8 */
271#define	OHCI_NODE_VALID	(1 << 31)
272#define	OHCI_NODE_ROOT	(1 << 30)
273
274#define	OHCI_ASYSRCBUS	1
275
276	fwohcireg_t	phy_access;	/* PHY cntl 0xec */
277#define	PHYDEV_RDDONE		(1<<31)
278#define	PHYDEV_RDCMD		(1<<15)
279#define	PHYDEV_WRCMD		(1<<14)
280#define	PHYDEV_REGADDR		8
281#define	PHYDEV_WRDATA		0
282#define	PHYDEV_RDADDR		24
283#define	PHYDEV_RDDATA		16
284
285	fwohcireg_t	cycle_timer;	/* Cycle Timer 0xf0 */
286	fwohcireg_t	dummy6[3];	/* dummy 0xf4-fc */
287	fwohcireg_t	areq_hi;	/* Async req. filter hi 0x100 */
288	fwohcireg_t	areq_hi_clr;	/* Async req. filter hi 0x104 */
289	fwohcireg_t	areq_lo;	/* Async req. filter lo 0x108 */
290	fwohcireg_t	areq_lo_clr;	/* Async req. filter lo 0x10c */
291	fwohcireg_t	preq_hi;	/* Async req. filter hi 0x110 */
292	fwohcireg_t	preq_hi_clr;	/* Async req. filter hi 0x114 */
293	fwohcireg_t	preq_lo;	/* Async req. filter lo 0x118 */
294	fwohcireg_t	preq_lo_clr;	/* Async req. filter lo 0x11c */
295
296	fwohcireg_t	pys_upper;	/* Physical Upper bound 0x120 */
297
298	fwohcireg_t	dummy7[23];	/* dummy 0x124-0x17c */
299
300	/*       0x180, 0x184, 0x188, 0x18c */
301	/*       0x190, 0x194, 0x198, 0x19c */
302	/*       0x1a0, 0x1a4, 0x1a8, 0x1ac */
303	/*       0x1b0, 0x1b4, 0x1b8, 0x1bc */
304	/*       0x1c0, 0x1c4, 0x1c8, 0x1cc */
305	/*       0x1d0, 0x1d4, 0x1d8, 0x1dc */
306	/*       0x1e0, 0x1e4, 0x1e8, 0x1ec */
307	/*       0x1f0, 0x1f4, 0x1f8, 0x1fc */
308	struct ohci_dma dma_ch[0x4];
309
310	/*       0x200, 0x204, 0x208, 0x20c */
311	/*       0x210, 0x204, 0x208, 0x20c */
312	struct ohci_itdma dma_itch[0x20];
313
314	/*       0x400, 0x404, 0x408, 0x40c */
315	/*       0x410, 0x404, 0x408, 0x40c */
316	struct ohci_dma dma_irch[0x20];
317};
318
319struct fwohcidb_tr{
320	STAILQ_ENTRY(fwohcidb_tr) link;
321	struct fw_xfer *xfer;
322	struct fwohcidb *db;
323	bus_dmamap_t dma_map;
324	caddr_t buf;
325	bus_addr_t bus_addr;
326	int dbcnt;
327};
328
329/*
330 * OHCI info structure.
331 */
332struct fwohci_txpkthdr{
333	union{
334		u_int32_t ld[4];
335		struct {
336#if BYTE_ORDER == BIG_ENDIAN
337			u_int32_t spd:16, /* XXX include reserved field */
338				  :8,
339				  tcode:4,
340				  :4;
341#else
342			u_int32_t :4,
343				  tcode:4,
344				  :8,
345				  spd:16; /* XXX include reserved fields */
346#endif
347		}common;
348		struct {
349#if BYTE_ORDER == BIG_ENDIAN
350			u_int32_t :8,
351				  srcbus:1,
352				  :4,
353				  spd:3,
354				  tlrt:8,
355				  tcode:4,
356				  :4;
357#else
358			u_int32_t :4,
359				  tcode:4,
360				  tlrt:8,
361				  spd:3,
362				  :4,
363				  srcbus:1,
364				  :8;
365#endif
366			BIT16x2(dst, );
367		}asycomm;
368		struct {
369#if BYTE_ORDER == BIG_ENDIAN
370			u_int32_t :13,
371			          spd:3,
372				  chtag:8,
373				  tcode:4,
374				  sy:4;
375#else
376			u_int32_t sy:4,
377				  tcode:4,
378				  chtag:8,
379			          spd:3,
380				  :13;
381#endif
382			BIT16x2(len, );
383		}stream;
384	}mode;
385};
386struct fwohci_trailer{
387	u_int32_t time:16,
388		  stat:16;
389};
390
391#define	OHCI_CNTL_CYCSRC	(0x1 << 22)
392#define	OHCI_CNTL_CYCMTR	(0x1 << 21)
393#define	OHCI_CNTL_CYCTIMER	(0x1 << 20)
394#define	OHCI_CNTL_PHYPKT	(0x1 << 10)
395#define	OHCI_CNTL_SID		(0x1 << 9)
396
397#define OHCI_INT_DMA_ATRQ	(0x1 << 0)
398#define OHCI_INT_DMA_ATRS	(0x1 << 1)
399#define OHCI_INT_DMA_ARRQ	(0x1 << 2)
400#define OHCI_INT_DMA_ARRS	(0x1 << 3)
401#define OHCI_INT_DMA_PRRQ	(0x1 << 4)
402#define OHCI_INT_DMA_PRRS	(0x1 << 5)
403#define OHCI_INT_DMA_IT	(0x1 << 6)
404#define OHCI_INT_DMA_IR	(0x1 << 7)
405#define OHCI_INT_PW_ERR	(0x1 << 8)
406#define OHCI_INT_LR_ERR	(0x1 << 9)
407
408#define OHCI_INT_PHY_SID	(0x1 << 16)
409#define OHCI_INT_PHY_BUS_R	(0x1 << 17)
410
411#define OHCI_INT_REG_FAIL	(0x1 << 18)
412
413#define OHCI_INT_PHY_INT	(0x1 << 19)
414#define OHCI_INT_CYC_START	(0x1 << 20)
415#define OHCI_INT_CYC_64SECOND	(0x1 << 21)
416#define OHCI_INT_CYC_LOST	(0x1 << 22)
417#define OHCI_INT_CYC_ERR	(0x1 << 23)
418
419#define OHCI_INT_ERR		(0x1 << 24)
420#define OHCI_INT_CYC_LONG	(0x1 << 25)
421#define OHCI_INT_PHY_REG	(0x1 << 26)
422
423#define OHCI_INT_EN		(0x1 << 31)
424
425#define IP_CHANNELS             0x0234
426#define FWOHCI_MAXREC		2048
427
428#define	OHCI_ISORA		0x02
429#define	OHCI_ISORB		0x04
430
431#define FWOHCITCODE_PHY		0xe
432