fwohcireg.h revision 108662
1103285Sikob/* 2103285Sikob * Copyright (c) 1998-2001 Katsushi Kobayashi and Hidetoshi Shimokawa 3103285Sikob * All rights reserved. 4103285Sikob * 5103285Sikob * Redistribution and use in source and binary forms, with or without 6103285Sikob * modification, are permitted provided that the following conditions 7103285Sikob * are met: 8103285Sikob * 1. Redistributions of source code must retain the above copyright 9103285Sikob * notice, this list of conditions and the following disclaimer. 10103285Sikob * 2. Redistributions in binary form must reproduce the above copyright 11103285Sikob * notice, this list of conditions and the following disclaimer in the 12103285Sikob * documentation and/or other materials provided with the distribution. 13103285Sikob * 3. All advertising materials mentioning features or use of this software 14103285Sikob * must display the acknowledgement as bellow: 15103285Sikob * 16103285Sikob * This product includes software developed by K. Kobayashi and H. Shimokawa 17103285Sikob * 18103285Sikob * 4. The name of the author may not be used to endorse or promote products 19103285Sikob * derived from this software without specific prior written permission. 20103285Sikob * 21103285Sikob * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22103285Sikob * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23103285Sikob * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24103285Sikob * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 25103285Sikob * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26103285Sikob * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 27103285Sikob * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28103285Sikob * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 29103285Sikob * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 30103285Sikob * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31103285Sikob * POSSIBILITY OF SUCH DAMAGE. 32103285Sikob * 33103285Sikob * $FreeBSD: head/sys/dev/firewire/fwohcireg.h 108662 2003-01-04 16:03:50Z simokawa $ 34103285Sikob * 35103285Sikob */ 36103285Sikob#define PCI_CBMEM 0x10 37103285Sikob 38108504Ssimokawa#define FW_VENDORID_NEC (0x1033 << 16) 39108504Ssimokawa#define FW_VENDORID_TI (0x104c << 16) 40108504Ssimokawa#define FW_VENDORID_SONY (0x104d << 16) 41108504Ssimokawa#define FW_VENDORID_VIA (0x1106 << 16) 42108504Ssimokawa#define FW_VENDORID_RICOH (0x1180 << 16) 43108504Ssimokawa#define FW_VENDORID_APPLE (0x106b << 16) 44108504Ssimokawa#define FW_VENDORID_LUCENT (0x11c1 << 16) 45103285Sikob 46103285Sikob#define FW_DEVICE_UPD861 0x0063 47103285Sikob#define FW_DEVICE_TITSB22 0x8009 48103285Sikob#define FW_DEVICE_TITSB23 0x8019 49103285Sikob#define FW_DEVICE_TITSB26 0x8020 50103285Sikob#define FW_DEVICE_TITSB43 0x8021 51108504Ssimokawa#define FW_DEVICE_TITSB43A 0x8023 52108504Ssimokawa#define FW_DEVICE_TIPCI4450 0x8011 53108504Ssimokawa#define FW_DEVICE_TIPCI4410A 0x8017 54103285Sikob#define FW_DEVICE_CX3022 0x8039 55103285Sikob#define FW_DEVICE_VT6306 0x3044 56108504Ssimokawa#define FW_DEVICE_R5C552 0x0552 57103485Sikob#define FW_DEVICE_PANGEA 0x0030 58103485Sikob#define FW_DEVICE_UNINORTH 0x0031 59103485Sikob#define FW_DEVICE_FW322 0x5811 60103285Sikob 61103285Sikob#define PCI_INTERFACE_OHCI 0x10 62103285Sikob 63103285Sikob#define FW_OHCI_BASE_REG 0x10 64103285Sikob 65103285Sikob#define OHCI_DMA_ITCH 0x20 66103285Sikob#define OHCI_DMA_IRCH 0x20 67103285Sikob 68103285Sikob#define OHCI_MAX_DMA_CH (0x4 + OHCI_DMA_ITCH + OHCI_DMA_IRCH) 69103285Sikob 70103285Sikob 71103285Sikobtypedef volatile u_int32_t fwohcireg_t; 72103285Sikob 73103285Sikobstruct fwohcidb { 74103285Sikob union { 75103285Sikob struct { 76103285Sikob volatile u_int32_t cmd; 77103285Sikob volatile u_int32_t addr; 78103285Sikob volatile u_int32_t depend; 79103285Sikob volatile u_int32_t count:16, 80103285Sikob status:16; 81103285Sikob } desc; 82103285Sikob volatile u_int32_t immed[4]; 83103285Sikob } db; 84103285Sikob#define OHCI_OUTPUT_MORE (0 << 28) 85103285Sikob#define OHCI_OUTPUT_LAST (1 << 28) 86103285Sikob#define OHCI_INPUT_MORE (2 << 28) 87103285Sikob#define OHCI_INPUT_LAST (3 << 28) 88103285Sikob#define OHCI_STORE_QUAD (4 << 28) 89103285Sikob#define OHCI_LOAD_QUAD (5 << 28) 90103285Sikob#define OHCI_NOP (6 << 28) 91103285Sikob#define OHCI_STOP (7 << 28) 92103285Sikob#define OHCI_STORE (8 << 28) 93103285Sikob#define OHCI_CMD_MASK (0xf << 28) 94103285Sikob 95103285Sikob#define OHCI_UPDATE (1 << 27) 96103285Sikob 97103285Sikob#define OHCI_KEY_ST0 (0 << 24) 98103285Sikob#define OHCI_KEY_ST1 (1 << 24) 99103285Sikob#define OHCI_KEY_ST2 (2 << 24) 100103285Sikob#define OHCI_KEY_ST3 (3 << 24) 101103285Sikob#define OHCI_KEY_REGS (5 << 24) 102103285Sikob#define OHCI_KEY_SYS (6 << 24) 103103285Sikob#define OHCI_KEY_DEVICE (7 << 24) 104103285Sikob#define OHCI_KEY_MASK (7 << 24) 105103285Sikob 106103285Sikob#define OHCI_INTERRUPT_NEVER (0 << 20) 107103285Sikob#define OHCI_INTERRUPT_TRUE (1 << 20) 108103285Sikob#define OHCI_INTERRUPT_FALSE (2 << 20) 109103285Sikob#define OHCI_INTERRUPT_ALWAYS (3 << 20) 110103285Sikob 111103285Sikob#define OHCI_BRANCH_NEVER (0 << 18) 112103285Sikob#define OHCI_BRANCH_TRUE (1 << 18) 113103285Sikob#define OHCI_BRANCH_FALSE (2 << 18) 114103285Sikob#define OHCI_BRANCH_ALWAYS (3 << 18) 115103285Sikob#define OHCI_BRANCH_MASK (3 << 18) 116103285Sikob 117103285Sikob#define OHCI_WAIT_NEVER (0 << 16) 118103285Sikob#define OHCI_WAIT_TRUE (1 << 16) 119103285Sikob#define OHCI_WAIT_FALSE (2 << 16) 120103285Sikob#define OHCI_WAIT_ALWAYS (3 << 16) 121103285Sikob}; 122103285Sikob 123103285Sikob#define OHCI_SPD_S100 0x4 124103285Sikob#define OHCI_SPD_S200 0x1 125103285Sikob#define OHCI_SPD_S400 0x2 126103285Sikob 127103285Sikob 128103285Sikob#define FWOHCIEV_NOSTAT 0 129103285Sikob#define FWOHCIEV_LONGP 2 130103285Sikob#define FWOHCIEV_MISSACK 3 131103285Sikob#define FWOHCIEV_UNDRRUN 4 132103285Sikob#define FWOHCIEV_OVRRUN 5 133103285Sikob#define FWOHCIEV_DESCERR 6 134103285Sikob#define FWOHCIEV_DTRDERR 7 135103285Sikob#define FWOHCIEV_DTWRERR 8 136103285Sikob#define FWOHCIEV_BUSRST 9 137103285Sikob#define FWOHCIEV_TIMEOUT 0xa 138103285Sikob#define FWOHCIEV_TCODERR 0xb 139103285Sikob#define FWOHCIEV_UNKNOWN 0xe 140103285Sikob#define FWOHCIEV_FLUSHED 0xf 141103285Sikob#define FWOHCIEV_ACKCOMPL 0x11 142103285Sikob#define FWOHCIEV_ACKPEND 0x12 143103285Sikob#define FWOHCIEV_ACKBSX 0x14 144103285Sikob#define FWOHCIEV_ACKBSA 0x15 145103285Sikob#define FWOHCIEV_ACKBSB 0x16 146103285Sikob#define FWOHCIEV_ACKTARD 0x1b 147103285Sikob#define FWOHCIEV_ACKDERR 0x1d 148103285Sikob#define FWOHCIEV_ACKTERR 0x1e 149103285Sikob 150103285Sikob#define FWOHCIEV_MASK 0x1f 151103285Sikob 152103285Sikobstruct ohci_registers { 153103285Sikob fwohcireg_t ver; /* Version No. 0x0 */ 154103285Sikob fwohcireg_t guid; /* GUID_ROM No. 0x4 */ 155103285Sikob fwohcireg_t retry; /* AT retries 0x8 */ 156103285Sikob#define FWOHCI_RETRY 0x8 157103285Sikob fwohcireg_t csr_data; /* CSR data 0xc */ 158103285Sikob fwohcireg_t csr_cmp; /* CSR compare 0x10 */ 159103285Sikob fwohcireg_t csr_cntl; /* CSR compare 0x14 */ 160103285Sikob fwohcireg_t rom_hdr; /* config ROM ptr. 0x18 */ 161103285Sikob fwohcireg_t bus_id; /* BUS_ID 0x1c */ 162103285Sikob fwohcireg_t bus_opt; /* BUS option 0x20 */ 163103285Sikob#define FWOHCIGUID_H 0x24 164103285Sikob#define FWOHCIGUID_L 0x28 165103285Sikob fwohcireg_t guid_hi; /* GUID hi 0x24 */ 166103285Sikob fwohcireg_t guid_lo; /* GUID lo 0x28 */ 167103285Sikob fwohcireg_t dummy0[2]; /* dummy 0x2c-0x30 */ 168103285Sikob fwohcireg_t config_rom; /* config ROM map 0x34 */ 169103285Sikob fwohcireg_t post_wr_lo; /* post write addr lo 0x38 */ 170103285Sikob fwohcireg_t post_wr_hi; /* post write addr hi 0x3c */ 171103285Sikob fwohcireg_t vender; /* vender ID 0x40 */ 172103285Sikob fwohcireg_t dummy1[3]; /* dummy 0x44-0x4c */ 173103285Sikob fwohcireg_t hcc_cntl_set; /* HCC control set 0x50 */ 174103285Sikob fwohcireg_t hcc_cntl_clr; /* HCC control clr 0x54 */ 175108662Ssimokawa#define OHCI_HCC_BIBIV (1 << 31) /* BIBimage Valid */ 176108662Ssimokawa#define OHCI_HCC_BIGEND (1 << 30) /* noByteSwapData */ 177108662Ssimokawa#define OHCI_HCC_PRPHY (1 << 23) /* programPhyEnable */ 178108662Ssimokawa#define OHCI_HCC_PHYEN (1 << 22) /* aPhyEnhanceEnable */ 179108662Ssimokawa#define OHCI_HCC_LPS (1 << 19) /* LPS */ 180108662Ssimokawa#define OHCI_HCC_POSTWR (1 << 18) /* postedWriteEnable */ 181108662Ssimokawa#define OHCI_HCC_LINKEN (1 << 17) /* linkEnable */ 182108662Ssimokawa#define OHCI_HCC_RESET (1 << 16) /* softReset */ 183103285Sikob fwohcireg_t dummy2[2]; /* dummy 0x58-0x5c */ 184103285Sikob fwohcireg_t dummy3[1]; /* dummy 0x60 */ 185103285Sikob fwohcireg_t sid_buf; /* self id buffer 0x64 */ 186103285Sikob fwohcireg_t sid_cnt; /* self id count 0x68 */ 187103285Sikob fwohcireg_t dummy4[1]; /* dummy 0x6c */ 188103285Sikob fwohcireg_t ir_mask_hi_set; /* ir mask hi set 0x70 */ 189103285Sikob fwohcireg_t ir_mask_hi_clr; /* ir mask hi set 0x74 */ 190103285Sikob fwohcireg_t ir_mask_lo_set; /* ir mask hi set 0x78 */ 191103285Sikob fwohcireg_t ir_mask_lo_clr; /* ir mask hi set 0x7c */ 192103285Sikob#define FWOHCI_INTSTAT 0x80 193103285Sikob#define FWOHCI_INTSTATCLR 0x84 194103285Sikob#define FWOHCI_INTMASK 0x88 195103285Sikob#define FWOHCI_INTMASKCLR 0x8c 196103285Sikob fwohcireg_t int_stat; /* 0x80 */ 197103285Sikob fwohcireg_t int_clear; /* 0x84 */ 198103285Sikob fwohcireg_t int_mask; /* 0x88 */ 199103285Sikob fwohcireg_t int_mask_clear; /* 0x8c */ 200103285Sikob fwohcireg_t it_int_stat; /* 0x90 */ 201103285Sikob fwohcireg_t it_int_clear; /* 0x94 */ 202103285Sikob fwohcireg_t it_int_mask; /* 0x98 */ 203103285Sikob fwohcireg_t it_mask_clear; /* 0x9c */ 204103285Sikob fwohcireg_t ir_int_stat; /* 0xa0 */ 205103285Sikob fwohcireg_t ir_int_clear; /* 0xa4 */ 206103285Sikob fwohcireg_t ir_int_mask; /* 0xa8 */ 207103285Sikob fwohcireg_t ir_mask_clear; /* 0xac */ 208103285Sikob fwohcireg_t dummy5[11]; /* dummy 0xb0-d8 */ 209103285Sikob fwohcireg_t fairness; /* fairness control 0xdc */ 210103285Sikob fwohcireg_t link_cntl; /* Chip control 0xe0*/ 211103285Sikob fwohcireg_t link_cntl_clr; /* Chip control clear 0xe4*/ 212103285Sikob#define FWOHCI_NODEID 0xe8 213103285Sikob fwohcireg_t node; /* Node ID 0xe8 */ 214103285Sikob#define OHCI_NODE_VALID (1 << 31) 215103285Sikob#define OHCI_NODE_ROOT (1 << 30) 216103285Sikob 217103285Sikob#define OHCI_ASYSRCBUS 1 218103285Sikob 219103285Sikob fwohcireg_t phy_access; /* PHY cntl 0xec */ 220103285Sikob#define PHYDEV_RDDONE (1<<31) 221103285Sikob#define PHYDEV_RDCMD (1<<15) 222103285Sikob#define PHYDEV_WRCMD (1<<14) 223103285Sikob#define PHYDEV_REGADDR 8 224103285Sikob#define PHYDEV_WRDATA 0 225103285Sikob#define PHYDEV_RDADDR 24 226103285Sikob#define PHYDEV_RDDATA 16 227103285Sikob 228103285Sikob fwohcireg_t cycle_timer; /* Cycle Timer 0xf0 */ 229103285Sikob fwohcireg_t dummy6[3]; /* dummy 0xf4-fc */ 230103285Sikob fwohcireg_t areq_hi; /* Async req. filter hi 0x100 */ 231103285Sikob fwohcireg_t areq_hi_clr; /* Async req. filter hi 0x104 */ 232103285Sikob fwohcireg_t areq_lo; /* Async req. filter lo 0x108 */ 233103285Sikob fwohcireg_t areq_lo_clr; /* Async req. filter lo 0x10c */ 234103285Sikob fwohcireg_t preq_hi; /* Async req. filter hi 0x110 */ 235103285Sikob fwohcireg_t preq_hi_clr; /* Async req. filter hi 0x114 */ 236103285Sikob fwohcireg_t preq_lo; /* Async req. filter lo 0x118 */ 237103285Sikob fwohcireg_t preq_lo_clr; /* Async req. filter lo 0x11c */ 238103285Sikob 239103285Sikob fwohcireg_t pys_upper; /* Physical Upper bound 0x120 */ 240103285Sikob 241103285Sikob fwohcireg_t dummy7[23]; /* dummy 0x124-0x17c */ 242103285Sikob 243103285Sikob struct ohci_dma{ 244103285Sikob fwohcireg_t cntl; 245103285Sikob 246103285Sikob#define OHCI_CNTL_CYCMATCH_S (0x1 << 31) 247103285Sikob 248103285Sikob#define OHCI_CNTL_BUFFIL (0x1 << 31) 249103285Sikob#define OHCI_CNTL_ISOHDR (0x1 << 30) 250103285Sikob#define OHCI_CNTL_CYCMATCH_R (0x1 << 29) 251103285Sikob#define OHCI_CNTL_MULTICH (0x1 << 28) 252103285Sikob 253103285Sikob#define OHCI_CNTL_DMA_RUN (0x1 << 15) 254103285Sikob#define OHCI_CNTL_DMA_WAKE (0x1 << 12) 255103285Sikob#define OHCI_CNTL_DMA_DEAD (0x1 << 11) 256103285Sikob#define OHCI_CNTL_DMA_ACTIVE (0x1 << 10) 257103285Sikob#define OHCI_CNTL_DMA_BT (0x1 << 8) 258103285Sikob#define OHCI_CNTL_DMA_BAD (0x1 << 7) 259103285Sikob#define OHCI_CNTL_DMA_STAT (0xff) 260103285Sikob 261103285Sikob fwohcireg_t cntl_clr; 262103285Sikob fwohcireg_t dummy0; 263103285Sikob fwohcireg_t cmd; 264103285Sikob fwohcireg_t match; 265103285Sikob fwohcireg_t dummy1; 266103285Sikob fwohcireg_t dummy2; 267103285Sikob fwohcireg_t dummy3; 268103285Sikob }; 269103285Sikob /* 0x180, 0x184, 0x188, 0x18c */ 270103285Sikob /* 0x190, 0x194, 0x198, 0x19c */ 271103285Sikob /* 0x1a0, 0x1a4, 0x1a8, 0x1ac */ 272103285Sikob /* 0x1b0, 0x1b4, 0x1b8, 0x1bc */ 273103285Sikob /* 0x1c0, 0x1c4, 0x1c8, 0x1cc */ 274103285Sikob /* 0x1d0, 0x1d4, 0x1d8, 0x1dc */ 275103285Sikob /* 0x1e0, 0x1e4, 0x1e8, 0x1ec */ 276103285Sikob /* 0x1f0, 0x1f4, 0x1f8, 0x1fc */ 277103285Sikob struct ohci_dma dma_ch[0x4]; 278103285Sikob 279103285Sikob /* 0x200, 0x204, 0x208, 0x20c */ 280103285Sikob /* 0x210, 0x204, 0x208, 0x20c */ 281103285Sikob struct ohci_itdma{ 282103285Sikob fwohcireg_t cntl; 283103285Sikob fwohcireg_t cntl_clr; 284103285Sikob fwohcireg_t dummy0; 285103285Sikob fwohcireg_t cmd; 286103285Sikob }; 287103285Sikob struct ohci_itdma dma_itch[0x20]; 288103285Sikob 289103285Sikob /* 0x400, 0x404, 0x408, 0x40c */ 290103285Sikob /* 0x410, 0x404, 0x408, 0x40c */ 291103285Sikob 292103285Sikob struct ohci_dma dma_irch[0x20]; 293103285Sikob}; 294103285Sikob 295103285Sikobstruct fwohcidb_tr{ 296103285Sikob STAILQ_ENTRY(fwohcidb_tr) link; 297103285Sikob struct fw_xfer *xfer; 298103285Sikob volatile struct fwohcidb *db; 299103285Sikob caddr_t buf; 300103285Sikob caddr_t dummy; 301103285Sikob int dbcnt; 302103285Sikob}; 303103285Sikob 304103285Sikob/* 305103285Sikob * OHCI info structure. 306103285Sikob */ 307103285Sikobstruct fwohci_txpkthdr{ 308103285Sikob union{ 309103285Sikob u_int32_t ld[4]; 310103285Sikob struct { 311103285Sikob u_int32_t res3:4, 312103285Sikob tcode:4, 313103285Sikob res2:8, 314103285Sikob spd:3, 315103285Sikob res1:13; 316103285Sikob }common; 317103285Sikob struct { 318103285Sikob u_int32_t res3:4, 319103285Sikob tcode:4, 320103285Sikob tlrt:8, 321103285Sikob spd:3, 322103285Sikob res2:4, 323103285Sikob srcbus:1, 324103285Sikob res1:8; 325103285Sikob u_int32_t res4:16, 326103285Sikob dst:16; 327103285Sikob }asycomm; 328103285Sikob struct { 329103285Sikob u_int32_t sy:4, 330103285Sikob tcode:4, 331103285Sikob chtag:8, 332103285Sikob spd:3, 333103285Sikob res1:13; 334103285Sikob u_int32_t res2:16, 335103285Sikob len:16; 336103285Sikob }stream; 337103285Sikob }mode; 338103285Sikob}; 339103285Sikobstruct fwohci_trailer{ 340103285Sikob u_int32_t time:16, 341103285Sikob stat:16; 342103285Sikob}; 343103285Sikob 344103285Sikob#define OHCI_CNTL_CYCSRC (0x1 << 22) 345103285Sikob#define OHCI_CNTL_CYCMTR (0x1 << 21) 346103285Sikob#define OHCI_CNTL_CYCTIMER (0x1 << 20) 347103285Sikob#define OHCI_CNTL_PHYPKT (0x1 << 10) 348103285Sikob#define OHCI_CNTL_SID (0x1 << 9) 349103285Sikob 350103285Sikob#define OHCI_INT_DMA_ATRQ (0x1 << 0) 351103285Sikob#define OHCI_INT_DMA_ATRS (0x1 << 1) 352103285Sikob#define OHCI_INT_DMA_ARRQ (0x1 << 2) 353103285Sikob#define OHCI_INT_DMA_ARRS (0x1 << 3) 354103285Sikob#define OHCI_INT_DMA_PRRQ (0x1 << 4) 355103285Sikob#define OHCI_INT_DMA_PRRS (0x1 << 5) 356103285Sikob#define OHCI_INT_DMA_IT (0x1 << 6) 357103285Sikob#define OHCI_INT_DMA_IR (0x1 << 7) 358103285Sikob#define OHCI_INT_PW_ERR (0x1 << 8) 359103285Sikob#define OHCI_INT_LR_ERR (0x1 << 9) 360103285Sikob 361103285Sikob#define OHCI_INT_PHY_SID (0x1 << 16) 362103285Sikob#define OHCI_INT_PHY_BUS_R (0x1 << 17) 363103285Sikob 364108276Ssimokawa#define OHCI_INT_REG_FAIL (0x1 << 18) 365108276Ssimokawa 366103285Sikob#define OHCI_INT_PHY_INT (0x1 << 19) 367103285Sikob#define OHCI_INT_CYC_START (0x1 << 20) 368103285Sikob#define OHCI_INT_CYC_64SECOND (0x1 << 21) 369103285Sikob#define OHCI_INT_CYC_LOST (0x1 << 22) 370103285Sikob#define OHCI_INT_CYC_ERR (0x1 << 23) 371103285Sikob 372103285Sikob#define OHCI_INT_ERR (0x1 << 24) 373103285Sikob#define OHCI_INT_CYC_LONG (0x1 << 25) 374103285Sikob#define OHCI_INT_PHY_REG (0x1 << 26) 375103285Sikob 376103285Sikob#define OHCI_INT_EN (0x1 << 31) 377103285Sikob 378103285Sikob#define IP_CHANNELS 0x0234 379103285Sikob#define FWOHCI_MAXREC 2048 380103285Sikob 381103285Sikob#define OHCI_ISORA 0x02 382103285Sikob#define OHCI_ISORB 0x04 383103285Sikob 384103285Sikob#define FWOHCITCODE_PHY 0xe 385