1254885Sdumbbell/* 2254885Sdumbbell * Copyright 2008-2009 Advanced Micro Devices, Inc. 3254885Sdumbbell * Copyright 2008 Red Hat Inc. 4254885Sdumbbell * 5254885Sdumbbell * Permission is hereby granted, free of charge, to any person obtaining a 6254885Sdumbbell * copy of this software and associated documentation files (the "Software"), 7254885Sdumbbell * to deal in the Software without restriction, including without limitation 8254885Sdumbbell * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9254885Sdumbbell * and/or sell copies of the Software, and to permit persons to whom the 10254885Sdumbbell * Software is furnished to do so, subject to the following conditions: 11254885Sdumbbell * 12254885Sdumbbell * The above copyright notice and this permission notice (including the next 13254885Sdumbbell * paragraph) shall be included in all copies or substantial portions of the 14254885Sdumbbell * Software. 15254885Sdumbbell * 16254885Sdumbbell * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17254885Sdumbbell * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18254885Sdumbbell * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19254885Sdumbbell * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 20254885Sdumbbell * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21254885Sdumbbell * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22254885Sdumbbell * DEALINGS IN THE SOFTWARE. 23254885Sdumbbell * 24254885Sdumbbell * Authors: 25254885Sdumbbell * Dave Airlie <airlied@redhat.com> 26254885Sdumbbell * Alex Deucher <alexander.deucher@amd.com> 27254885Sdumbbell */ 28254885Sdumbbell 29254885Sdumbbell#include <sys/cdefs.h> 30254885Sdumbbell__FBSDID("$FreeBSD$"); 31254885Sdumbbell 32254885Sdumbbell#include <sys/param.h> 33254885Sdumbbell#include <sys/systm.h> 34254885Sdumbbell#include <sys/linker.h> 35254885Sdumbbell#include <sys/firmware.h> 36254885Sdumbbell 37254885Sdumbbell#include <dev/drm2/drmP.h> 38254885Sdumbbell#include <dev/drm2/radeon/radeon_drm.h> 39254885Sdumbbell#include "radeon_drv.h" 40254885Sdumbbell#include "r600_cp.h" 41254885Sdumbbell 42254885Sdumbbell#define PFP_UCODE_SIZE 576 43254885Sdumbbell#define PM4_UCODE_SIZE 1792 44254885Sdumbbell#define R700_PFP_UCODE_SIZE 848 45254885Sdumbbell#define R700_PM4_UCODE_SIZE 1360 46254885Sdumbbell 47254885Sdumbbell# define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */ 48254885Sdumbbell# define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1)) 49254885Sdumbbell 50254885Sdumbbell#define R600_PTE_VALID (1 << 0) 51254885Sdumbbell#define R600_PTE_SYSTEM (1 << 1) 52254885Sdumbbell#define R600_PTE_SNOOPED (1 << 2) 53254885Sdumbbell#define R600_PTE_READABLE (1 << 5) 54254885Sdumbbell#define R600_PTE_WRITEABLE (1 << 6) 55254885Sdumbbell 56254885Sdumbbell/* MAX values used for gfx init */ 57254885Sdumbbell#define R6XX_MAX_SH_GPRS 256 58254885Sdumbbell#define R6XX_MAX_TEMP_GPRS 16 59254885Sdumbbell#define R6XX_MAX_SH_THREADS 256 60254885Sdumbbell#define R6XX_MAX_SH_STACK_ENTRIES 4096 61254885Sdumbbell#define R6XX_MAX_BACKENDS 8 62254885Sdumbbell#define R6XX_MAX_BACKENDS_MASK 0xff 63254885Sdumbbell#define R6XX_MAX_SIMDS 8 64254885Sdumbbell#define R6XX_MAX_SIMDS_MASK 0xff 65254885Sdumbbell#define R6XX_MAX_PIPES 8 66254885Sdumbbell#define R6XX_MAX_PIPES_MASK 0xff 67254885Sdumbbell 68254885Sdumbbell#define R7XX_MAX_SH_GPRS 256 69254885Sdumbbell#define R7XX_MAX_TEMP_GPRS 16 70254885Sdumbbell#define R7XX_MAX_SH_THREADS 256 71254885Sdumbbell#define R7XX_MAX_SH_STACK_ENTRIES 4096 72254885Sdumbbell#define R7XX_MAX_BACKENDS 8 73254885Sdumbbell#define R7XX_MAX_BACKENDS_MASK 0xff 74254885Sdumbbell#define R7XX_MAX_SIMDS 16 75254885Sdumbbell#define R7XX_MAX_SIMDS_MASK 0xffff 76254885Sdumbbell#define R7XX_MAX_PIPES 8 77254885Sdumbbell#define R7XX_MAX_PIPES_MASK 0xff 78254885Sdumbbell 79254885Sdumbbellstatic int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries) 80254885Sdumbbell{ 81254885Sdumbbell int i; 82254885Sdumbbell 83254885Sdumbbell dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 84254885Sdumbbell 85254885Sdumbbell for (i = 0; i < dev_priv->usec_timeout; i++) { 86254885Sdumbbell int slots; 87254885Sdumbbell if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) 88254885Sdumbbell slots = (RADEON_READ(R600_GRBM_STATUS) 89254885Sdumbbell & R700_CMDFIFO_AVAIL_MASK); 90254885Sdumbbell else 91254885Sdumbbell slots = (RADEON_READ(R600_GRBM_STATUS) 92254885Sdumbbell & R600_CMDFIFO_AVAIL_MASK); 93254885Sdumbbell if (slots >= entries) 94254885Sdumbbell return 0; 95254885Sdumbbell DRM_UDELAY(1); 96254885Sdumbbell } 97254885Sdumbbell DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n", 98254885Sdumbbell RADEON_READ(R600_GRBM_STATUS), 99254885Sdumbbell RADEON_READ(R600_GRBM_STATUS2)); 100254885Sdumbbell 101254885Sdumbbell return -EBUSY; 102254885Sdumbbell} 103254885Sdumbbell 104254885Sdumbbellstatic int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv) 105254885Sdumbbell{ 106254885Sdumbbell int i, ret; 107254885Sdumbbell 108254885Sdumbbell dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE; 109254885Sdumbbell 110254885Sdumbbell if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) 111254885Sdumbbell ret = r600_do_wait_for_fifo(dev_priv, 8); 112254885Sdumbbell else 113254885Sdumbbell ret = r600_do_wait_for_fifo(dev_priv, 16); 114254885Sdumbbell if (ret) 115254885Sdumbbell return ret; 116254885Sdumbbell for (i = 0; i < dev_priv->usec_timeout; i++) { 117254885Sdumbbell if (!(RADEON_READ(R600_GRBM_STATUS) & R600_GUI_ACTIVE)) 118254885Sdumbbell return 0; 119254885Sdumbbell DRM_UDELAY(1); 120254885Sdumbbell } 121254885Sdumbbell DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n", 122254885Sdumbbell RADEON_READ(R600_GRBM_STATUS), 123254885Sdumbbell RADEON_READ(R600_GRBM_STATUS2)); 124254885Sdumbbell 125254885Sdumbbell return -EBUSY; 126254885Sdumbbell} 127254885Sdumbbell 128254885Sdumbbellvoid r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info) 129254885Sdumbbell{ 130254885Sdumbbell struct drm_sg_mem *entry = dev->sg; 131254885Sdumbbell#ifdef __linux__ 132254885Sdumbbell int max_pages; 133254885Sdumbbell int pages; 134254885Sdumbbell int i; 135254885Sdumbbell#endif 136254885Sdumbbell 137254885Sdumbbell if (!entry) 138254885Sdumbbell return; 139254885Sdumbbell 140254885Sdumbbell if (gart_info->bus_addr) { 141254885Sdumbbell#ifdef __linux__ 142254885Sdumbbell max_pages = (gart_info->table_size / sizeof(u64)); 143254885Sdumbbell pages = (entry->pages <= max_pages) 144254885Sdumbbell ? entry->pages : max_pages; 145254885Sdumbbell 146254885Sdumbbell for (i = 0; i < pages; i++) { 147254885Sdumbbell if (!entry->busaddr[i]) 148254885Sdumbbell break; 149254885Sdumbbell pci_unmap_page(dev->pdev, entry->busaddr[i], 150254885Sdumbbell PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); 151254885Sdumbbell } 152254885Sdumbbell#endif 153254885Sdumbbell if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) 154254885Sdumbbell gart_info->bus_addr = 0; 155254885Sdumbbell } 156254885Sdumbbell} 157254885Sdumbbell 158254885Sdumbbell/* R600 has page table setup */ 159254885Sdumbbellint r600_page_table_init(struct drm_device *dev) 160254885Sdumbbell{ 161254885Sdumbbell drm_radeon_private_t *dev_priv = dev->dev_private; 162254885Sdumbbell struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info; 163254885Sdumbbell struct drm_local_map *map = &gart_info->mapping; 164254885Sdumbbell struct drm_sg_mem *entry = dev->sg; 165254885Sdumbbell int ret = 0; 166254885Sdumbbell int i, j; 167254885Sdumbbell int pages; 168254885Sdumbbell u64 page_base; 169254885Sdumbbell dma_addr_t entry_addr; 170254885Sdumbbell int max_ati_pages, max_real_pages, gart_idx; 171254885Sdumbbell 172254885Sdumbbell /* okay page table is available - lets rock */ 173254885Sdumbbell max_ati_pages = (gart_info->table_size / sizeof(u64)); 174254885Sdumbbell max_real_pages = max_ati_pages / (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); 175254885Sdumbbell 176254885Sdumbbell pages = (entry->pages <= max_real_pages) ? 177254885Sdumbbell entry->pages : max_real_pages; 178254885Sdumbbell 179254885Sdumbbell memset_io((void __iomem *)map->handle, 0, max_ati_pages * sizeof(u64)); 180254885Sdumbbell 181254885Sdumbbell gart_idx = 0; 182254885Sdumbbell for (i = 0; i < pages; i++) { 183254885Sdumbbell#ifdef __linux__ 184254885Sdumbbell entry->busaddr[i] = pci_map_page(dev->pdev, 185254885Sdumbbell entry->pagelist[i], 0, 186254885Sdumbbell PAGE_SIZE, 187254885Sdumbbell PCI_DMA_BIDIRECTIONAL); 188254885Sdumbbell if (pci_dma_mapping_error(dev->pdev, entry->busaddr[i])) { 189254885Sdumbbell DRM_ERROR("unable to map PCIGART pages!\n"); 190254885Sdumbbell r600_page_table_cleanup(dev, gart_info); 191254885Sdumbbell goto done; 192254885Sdumbbell } 193254885Sdumbbell#endif 194254885Sdumbbell entry_addr = entry->busaddr[i]; 195254885Sdumbbell for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) { 196254885Sdumbbell page_base = (u64) entry_addr & ATI_PCIGART_PAGE_MASK; 197254885Sdumbbell page_base |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED; 198254885Sdumbbell page_base |= R600_PTE_READABLE | R600_PTE_WRITEABLE; 199254885Sdumbbell 200254885Sdumbbell DRM_WRITE64(map, gart_idx * sizeof(u64), page_base); 201254885Sdumbbell 202254885Sdumbbell gart_idx++; 203254885Sdumbbell 204254885Sdumbbell if ((i % 128) == 0) 205254885Sdumbbell DRM_DEBUG("page entry %d: 0x%016llx\n", 206254885Sdumbbell i, (unsigned long long)page_base); 207254885Sdumbbell entry_addr += ATI_PCIGART_PAGE_SIZE; 208254885Sdumbbell } 209254885Sdumbbell } 210254885Sdumbbell ret = 1; 211254885Sdumbbell#ifdef __linux__ 212254885Sdumbbelldone: 213254885Sdumbbell#endif 214254885Sdumbbell return ret; 215254885Sdumbbell} 216254885Sdumbbell 217254885Sdumbbellstatic void r600_vm_flush_gart_range(struct drm_device *dev) 218254885Sdumbbell{ 219254885Sdumbbell drm_radeon_private_t *dev_priv = dev->dev_private; 220254885Sdumbbell u32 resp, countdown = 1000; 221254885Sdumbbell RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12); 222254885Sdumbbell RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 223254885Sdumbbell RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE, 2); 224254885Sdumbbell 225254885Sdumbbell do { 226254885Sdumbbell resp = RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE); 227254885Sdumbbell countdown--; 228254885Sdumbbell DRM_UDELAY(1); 229254885Sdumbbell } while (((resp & 0xf0) == 0) && countdown); 230254885Sdumbbell} 231254885Sdumbbell 232254885Sdumbbellstatic void r600_vm_init(struct drm_device *dev) 233254885Sdumbbell{ 234254885Sdumbbell drm_radeon_private_t *dev_priv = dev->dev_private; 235254885Sdumbbell /* initialise the VM to use the page table we constructed up there */ 236254885Sdumbbell u32 vm_c0, i; 237254885Sdumbbell u32 mc_rd_a; 238254885Sdumbbell u32 vm_l2_cntl, vm_l2_cntl3; 239254885Sdumbbell /* okay set up the PCIE aperture type thingo */ 240254885Sdumbbell RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12); 241254885Sdumbbell RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 242254885Sdumbbell RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); 243254885Sdumbbell 244254885Sdumbbell /* setup MC RD a */ 245254885Sdumbbell mc_rd_a = R600_MCD_L1_TLB | R600_MCD_L1_FRAG_PROC | R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS | 246254885Sdumbbell R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | R600_MCD_EFFECTIVE_L1_TLB_SIZE(5) | 247254885Sdumbbell R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(5) | R600_MCD_WAIT_L2_QUERY; 248254885Sdumbbell 249254885Sdumbbell RADEON_WRITE(R600_MCD_RD_A_CNTL, mc_rd_a); 250254885Sdumbbell RADEON_WRITE(R600_MCD_RD_B_CNTL, mc_rd_a); 251254885Sdumbbell 252254885Sdumbbell RADEON_WRITE(R600_MCD_WR_A_CNTL, mc_rd_a); 253254885Sdumbbell RADEON_WRITE(R600_MCD_WR_B_CNTL, mc_rd_a); 254254885Sdumbbell 255254885Sdumbbell RADEON_WRITE(R600_MCD_RD_GFX_CNTL, mc_rd_a); 256254885Sdumbbell RADEON_WRITE(R600_MCD_WR_GFX_CNTL, mc_rd_a); 257254885Sdumbbell 258254885Sdumbbell RADEON_WRITE(R600_MCD_RD_SYS_CNTL, mc_rd_a); 259254885Sdumbbell RADEON_WRITE(R600_MCD_WR_SYS_CNTL, mc_rd_a); 260254885Sdumbbell 261254885Sdumbbell RADEON_WRITE(R600_MCD_RD_HDP_CNTL, mc_rd_a | R600_MCD_L1_STRICT_ORDERING); 262254885Sdumbbell RADEON_WRITE(R600_MCD_WR_HDP_CNTL, mc_rd_a /*| R600_MCD_L1_STRICT_ORDERING*/); 263254885Sdumbbell 264254885Sdumbbell RADEON_WRITE(R600_MCD_RD_PDMA_CNTL, mc_rd_a); 265254885Sdumbbell RADEON_WRITE(R600_MCD_WR_PDMA_CNTL, mc_rd_a); 266254885Sdumbbell 267254885Sdumbbell RADEON_WRITE(R600_MCD_RD_SEM_CNTL, mc_rd_a | R600_MCD_SEMAPHORE_MODE); 268254885Sdumbbell RADEON_WRITE(R600_MCD_WR_SEM_CNTL, mc_rd_a); 269254885Sdumbbell 270254885Sdumbbell vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W; 271254885Sdumbbell vm_l2_cntl |= R600_VM_L2_CNTL_QUEUE_SIZE(7); 272254885Sdumbbell RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl); 273254885Sdumbbell 274254885Sdumbbell RADEON_WRITE(R600_VM_L2_CNTL2, 0); 275254885Sdumbbell vm_l2_cntl3 = (R600_VM_L2_CNTL3_BANK_SELECT_0(0) | 276254885Sdumbbell R600_VM_L2_CNTL3_BANK_SELECT_1(1) | 277254885Sdumbbell R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(2)); 278254885Sdumbbell RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3); 279254885Sdumbbell 280254885Sdumbbell vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT; 281254885Sdumbbell 282254885Sdumbbell RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0); 283254885Sdumbbell 284254885Sdumbbell vm_c0 &= ~R600_VM_ENABLE_CONTEXT; 285254885Sdumbbell 286254885Sdumbbell /* disable all other contexts */ 287254885Sdumbbell for (i = 1; i < 8; i++) 288254885Sdumbbell RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0); 289254885Sdumbbell 290254885Sdumbbell RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12); 291254885Sdumbbell RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12); 292254885Sdumbbell RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 293254885Sdumbbell 294254885Sdumbbell r600_vm_flush_gart_range(dev); 295254885Sdumbbell} 296254885Sdumbbell 297254885Sdumbbellstatic int r600_cp_init_microcode(drm_radeon_private_t *dev_priv) 298254885Sdumbbell{ 299254885Sdumbbell const char *chip_name; 300254885Sdumbbell size_t pfp_req_size, me_req_size; 301254885Sdumbbell char fw_name[30]; 302254885Sdumbbell int err; 303254885Sdumbbell 304254885Sdumbbell switch (dev_priv->flags & RADEON_FAMILY_MASK) { 305254885Sdumbbell case CHIP_R600: chip_name = "R600"; break; 306254885Sdumbbell case CHIP_RV610: chip_name = "RV610"; break; 307254885Sdumbbell case CHIP_RV630: chip_name = "RV630"; break; 308254885Sdumbbell case CHIP_RV620: chip_name = "RV620"; break; 309254885Sdumbbell case CHIP_RV635: chip_name = "RV635"; break; 310254885Sdumbbell case CHIP_RV670: chip_name = "RV670"; break; 311254885Sdumbbell case CHIP_RS780: 312254885Sdumbbell case CHIP_RS880: chip_name = "RS780"; break; 313254885Sdumbbell case CHIP_RV770: chip_name = "RV770"; break; 314254885Sdumbbell case CHIP_RV730: 315254885Sdumbbell case CHIP_RV740: chip_name = "RV730"; break; 316254885Sdumbbell case CHIP_RV710: chip_name = "RV710"; break; 317254885Sdumbbell default: panic("%s: Unsupported family %d", __func__, dev_priv->flags & RADEON_FAMILY_MASK); 318254885Sdumbbell } 319254885Sdumbbell 320254885Sdumbbell if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) { 321254885Sdumbbell pfp_req_size = R700_PFP_UCODE_SIZE * 4; 322254885Sdumbbell me_req_size = R700_PM4_UCODE_SIZE * 4; 323254885Sdumbbell } else { 324254885Sdumbbell pfp_req_size = PFP_UCODE_SIZE * 4; 325254885Sdumbbell me_req_size = PM4_UCODE_SIZE * 12; 326254885Sdumbbell } 327254885Sdumbbell 328254885Sdumbbell DRM_INFO("Loading %s CP Microcode\n", chip_name); 329254885Sdumbbell err = 0; 330254885Sdumbbell 331254885Sdumbbell snprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_pfp", chip_name); 332254885Sdumbbell dev_priv->pfp_fw = firmware_get(fw_name); 333254885Sdumbbell if (dev_priv->pfp_fw == NULL) { 334254885Sdumbbell err = -ENOENT; 335254885Sdumbbell goto out; 336254885Sdumbbell } 337254885Sdumbbell if (dev_priv->pfp_fw->datasize != pfp_req_size) { 338254885Sdumbbell DRM_ERROR( 339254885Sdumbbell "r600_cp: Bogus length %zu in firmware \"%s\"\n", 340254885Sdumbbell dev_priv->pfp_fw->datasize, fw_name); 341254885Sdumbbell err = -EINVAL; 342254885Sdumbbell goto out; 343254885Sdumbbell } 344254885Sdumbbell 345254885Sdumbbell snprintf(fw_name, sizeof(fw_name), "radeonkmsfw_%s_me", chip_name); 346254885Sdumbbell dev_priv->me_fw = firmware_get(fw_name); 347254885Sdumbbell if (dev_priv->me_fw == NULL) { 348254885Sdumbbell err = -ENOENT; 349254885Sdumbbell goto out; 350254885Sdumbbell } 351254885Sdumbbell if (dev_priv->me_fw->datasize != me_req_size) { 352254885Sdumbbell DRM_ERROR( 353254885Sdumbbell "r600_cp: Bogus length %zu in firmware \"%s\"\n", 354254885Sdumbbell dev_priv->me_fw->datasize, fw_name); 355254885Sdumbbell err = -EINVAL; 356254885Sdumbbell } 357254885Sdumbbellout: 358254885Sdumbbell if (err) { 359254885Sdumbbell if (err != -EINVAL) 360254885Sdumbbell DRM_ERROR( 361254885Sdumbbell "r600_cp: Failed to load firmware \"%s\"\n", 362254885Sdumbbell fw_name); 363254885Sdumbbell if (dev_priv->pfp_fw != NULL) { 364254885Sdumbbell firmware_put(dev_priv->pfp_fw, FIRMWARE_UNLOAD); 365254885Sdumbbell dev_priv->pfp_fw = NULL; 366254885Sdumbbell } 367254885Sdumbbell if (dev_priv->me_fw != NULL) { 368254885Sdumbbell firmware_put(dev_priv->me_fw, FIRMWARE_UNLOAD); 369254885Sdumbbell dev_priv->me_fw = NULL; 370254885Sdumbbell } 371254885Sdumbbell } 372254885Sdumbbell return err; 373254885Sdumbbell} 374254885Sdumbbell 375254885Sdumbbellstatic void r600_cp_load_microcode(drm_radeon_private_t *dev_priv) 376254885Sdumbbell{ 377254885Sdumbbell const __be32 *fw_data; 378254885Sdumbbell int i; 379254885Sdumbbell 380254885Sdumbbell if (!dev_priv->me_fw || !dev_priv->pfp_fw) 381254885Sdumbbell return; 382254885Sdumbbell 383254885Sdumbbell r600_do_cp_stop(dev_priv); 384254885Sdumbbell 385254885Sdumbbell RADEON_WRITE(R600_CP_RB_CNTL, 386254885Sdumbbell#ifdef __BIG_ENDIAN 387254885Sdumbbell R600_BUF_SWAP_32BIT | 388254885Sdumbbell#endif 389254885Sdumbbell R600_RB_NO_UPDATE | 390254885Sdumbbell R600_RB_BLKSZ(15) | 391254885Sdumbbell R600_RB_BUFSZ(3)); 392254885Sdumbbell 393254885Sdumbbell RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); 394254885Sdumbbell RADEON_READ(R600_GRBM_SOFT_RESET); 395254885Sdumbbell DRM_MDELAY(15); 396254885Sdumbbell RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 397254885Sdumbbell 398254885Sdumbbell fw_data = (const __be32 *)dev_priv->me_fw->data; 399254885Sdumbbell RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 400254885Sdumbbell for (i = 0; i < PM4_UCODE_SIZE * 3; i++) 401254885Sdumbbell RADEON_WRITE(R600_CP_ME_RAM_DATA, 402254885Sdumbbell be32_to_cpup(fw_data++)); 403254885Sdumbbell 404254885Sdumbbell fw_data = (const __be32 *)dev_priv->pfp_fw->data; 405254885Sdumbbell RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 406254885Sdumbbell for (i = 0; i < PFP_UCODE_SIZE; i++) 407254885Sdumbbell RADEON_WRITE(R600_CP_PFP_UCODE_DATA, 408254885Sdumbbell be32_to_cpup(fw_data++)); 409254885Sdumbbell 410254885Sdumbbell RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 411254885Sdumbbell RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 412254885Sdumbbell RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0); 413254885Sdumbbell 414254885Sdumbbell} 415254885Sdumbbell 416254885Sdumbbellstatic void r700_vm_init(struct drm_device *dev) 417254885Sdumbbell{ 418254885Sdumbbell drm_radeon_private_t *dev_priv = dev->dev_private; 419254885Sdumbbell /* initialise the VM to use the page table we constructed up there */ 420254885Sdumbbell u32 vm_c0, i; 421254885Sdumbbell u32 mc_vm_md_l1; 422254885Sdumbbell u32 vm_l2_cntl, vm_l2_cntl3; 423254885Sdumbbell /* okay set up the PCIE aperture type thingo */ 424254885Sdumbbell RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12); 425254885Sdumbbell RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 426254885Sdumbbell RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); 427254885Sdumbbell 428254885Sdumbbell mc_vm_md_l1 = R700_ENABLE_L1_TLB | 429254885Sdumbbell R700_ENABLE_L1_FRAGMENT_PROCESSING | 430254885Sdumbbell R700_SYSTEM_ACCESS_MODE_IN_SYS | 431254885Sdumbbell R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 432254885Sdumbbell R700_EFFECTIVE_L1_TLB_SIZE(5) | 433254885Sdumbbell R700_EFFECTIVE_L1_QUEUE_SIZE(5); 434254885Sdumbbell 435254885Sdumbbell RADEON_WRITE(R700_MC_VM_MD_L1_TLB0_CNTL, mc_vm_md_l1); 436254885Sdumbbell RADEON_WRITE(R700_MC_VM_MD_L1_TLB1_CNTL, mc_vm_md_l1); 437254885Sdumbbell RADEON_WRITE(R700_MC_VM_MD_L1_TLB2_CNTL, mc_vm_md_l1); 438254885Sdumbbell RADEON_WRITE(R700_MC_VM_MB_L1_TLB0_CNTL, mc_vm_md_l1); 439254885Sdumbbell RADEON_WRITE(R700_MC_VM_MB_L1_TLB1_CNTL, mc_vm_md_l1); 440254885Sdumbbell RADEON_WRITE(R700_MC_VM_MB_L1_TLB2_CNTL, mc_vm_md_l1); 441254885Sdumbbell RADEON_WRITE(R700_MC_VM_MB_L1_TLB3_CNTL, mc_vm_md_l1); 442254885Sdumbbell 443254885Sdumbbell vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W; 444254885Sdumbbell vm_l2_cntl |= R700_VM_L2_CNTL_QUEUE_SIZE(7); 445254885Sdumbbell RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl); 446254885Sdumbbell 447254885Sdumbbell RADEON_WRITE(R600_VM_L2_CNTL2, 0); 448254885Sdumbbell vm_l2_cntl3 = R700_VM_L2_CNTL3_BANK_SELECT(0) | R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(2); 449254885Sdumbbell RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3); 450254885Sdumbbell 451254885Sdumbbell vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT; 452254885Sdumbbell 453254885Sdumbbell RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0); 454254885Sdumbbell 455254885Sdumbbell vm_c0 &= ~R600_VM_ENABLE_CONTEXT; 456254885Sdumbbell 457254885Sdumbbell /* disable all other contexts */ 458254885Sdumbbell for (i = 1; i < 8; i++) 459254885Sdumbbell RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0); 460254885Sdumbbell 461254885Sdumbbell RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12); 462254885Sdumbbell RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12); 463254885Sdumbbell RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12); 464254885Sdumbbell 465254885Sdumbbell r600_vm_flush_gart_range(dev); 466254885Sdumbbell} 467254885Sdumbbell 468254885Sdumbbellstatic void r700_cp_load_microcode(drm_radeon_private_t *dev_priv) 469254885Sdumbbell{ 470254885Sdumbbell const __be32 *fw_data; 471254885Sdumbbell int i; 472254885Sdumbbell 473254885Sdumbbell if (!dev_priv->me_fw || !dev_priv->pfp_fw) 474254885Sdumbbell return; 475254885Sdumbbell 476254885Sdumbbell r600_do_cp_stop(dev_priv); 477254885Sdumbbell 478254885Sdumbbell RADEON_WRITE(R600_CP_RB_CNTL, 479254885Sdumbbell#ifdef __BIG_ENDIAN 480254885Sdumbbell R600_BUF_SWAP_32BIT | 481254885Sdumbbell#endif 482254885Sdumbbell R600_RB_NO_UPDATE | 483254885Sdumbbell R600_RB_BLKSZ(15) | 484254885Sdumbbell R600_RB_BUFSZ(3)); 485254885Sdumbbell 486254885Sdumbbell RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); 487254885Sdumbbell RADEON_READ(R600_GRBM_SOFT_RESET); 488254885Sdumbbell DRM_MDELAY(15); 489254885Sdumbbell RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 490254885Sdumbbell 491254885Sdumbbell fw_data = (const __be32 *)dev_priv->pfp_fw->data; 492254885Sdumbbell RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 493254885Sdumbbell for (i = 0; i < R700_PFP_UCODE_SIZE; i++) 494254885Sdumbbell RADEON_WRITE(R600_CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); 495254885Sdumbbell RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 496254885Sdumbbell 497254885Sdumbbell fw_data = (const __be32 *)dev_priv->me_fw->data; 498254885Sdumbbell RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 499254885Sdumbbell for (i = 0; i < R700_PM4_UCODE_SIZE; i++) 500254885Sdumbbell RADEON_WRITE(R600_CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); 501254885Sdumbbell RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 502254885Sdumbbell 503254885Sdumbbell RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0); 504254885Sdumbbell RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0); 505254885Sdumbbell RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0); 506254885Sdumbbell 507254885Sdumbbell} 508254885Sdumbbell 509254885Sdumbbellstatic void r600_test_writeback(drm_radeon_private_t *dev_priv) 510254885Sdumbbell{ 511254885Sdumbbell u32 tmp; 512254885Sdumbbell 513254885Sdumbbell /* Start with assuming that writeback doesn't work */ 514254885Sdumbbell dev_priv->writeback_works = 0; 515254885Sdumbbell 516254885Sdumbbell /* Writeback doesn't seem to work everywhere, test it here and possibly 517254885Sdumbbell * enable it if it appears to work 518254885Sdumbbell */ 519254885Sdumbbell radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0); 520254885Sdumbbell 521254885Sdumbbell RADEON_WRITE(R600_SCRATCH_REG1, 0xdeadbeef); 522254885Sdumbbell 523254885Sdumbbell for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) { 524254885Sdumbbell u32 val; 525254885Sdumbbell 526254885Sdumbbell val = radeon_read_ring_rptr(dev_priv, R600_SCRATCHOFF(1)); 527254885Sdumbbell if (val == 0xdeadbeef) 528254885Sdumbbell break; 529254885Sdumbbell DRM_UDELAY(1); 530254885Sdumbbell } 531254885Sdumbbell 532254885Sdumbbell if (tmp < dev_priv->usec_timeout) { 533254885Sdumbbell dev_priv->writeback_works = 1; 534254885Sdumbbell DRM_INFO("writeback test succeeded in %d usecs\n", tmp); 535254885Sdumbbell } else { 536254885Sdumbbell dev_priv->writeback_works = 0; 537254885Sdumbbell DRM_INFO("writeback test failed\n"); 538254885Sdumbbell } 539254885Sdumbbell if (radeon_no_wb == 1) { 540254885Sdumbbell dev_priv->writeback_works = 0; 541254885Sdumbbell DRM_INFO("writeback forced off\n"); 542254885Sdumbbell } 543254885Sdumbbell 544254885Sdumbbell if (!dev_priv->writeback_works) { 545254885Sdumbbell /* Disable writeback to avoid unnecessary bus master transfer */ 546254885Sdumbbell RADEON_WRITE(R600_CP_RB_CNTL, 547254885Sdumbbell#ifdef __BIG_ENDIAN 548254885Sdumbbell R600_BUF_SWAP_32BIT | 549254885Sdumbbell#endif 550254885Sdumbbell RADEON_READ(R600_CP_RB_CNTL) | 551254885Sdumbbell R600_RB_NO_UPDATE); 552254885Sdumbbell RADEON_WRITE(R600_SCRATCH_UMSK, 0); 553254885Sdumbbell } 554254885Sdumbbell} 555254885Sdumbbell 556254885Sdumbbellint r600_do_engine_reset(struct drm_device *dev) 557254885Sdumbbell{ 558254885Sdumbbell drm_radeon_private_t *dev_priv = dev->dev_private; 559254885Sdumbbell u32 cp_ptr, cp_me_cntl, cp_rb_cntl; 560254885Sdumbbell 561254885Sdumbbell DRM_INFO("Resetting GPU\n"); 562254885Sdumbbell 563254885Sdumbbell cp_ptr = RADEON_READ(R600_CP_RB_WPTR); 564254885Sdumbbell cp_me_cntl = RADEON_READ(R600_CP_ME_CNTL); 565254885Sdumbbell RADEON_WRITE(R600_CP_ME_CNTL, R600_CP_ME_HALT); 566254885Sdumbbell 567254885Sdumbbell RADEON_WRITE(R600_GRBM_SOFT_RESET, 0x7fff); 568254885Sdumbbell RADEON_READ(R600_GRBM_SOFT_RESET); 569254885Sdumbbell DRM_UDELAY(50); 570254885Sdumbbell RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 571254885Sdumbbell RADEON_READ(R600_GRBM_SOFT_RESET); 572254885Sdumbbell 573254885Sdumbbell RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0); 574254885Sdumbbell cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL); 575254885Sdumbbell RADEON_WRITE(R600_CP_RB_CNTL, 576254885Sdumbbell#ifdef __BIG_ENDIAN 577254885Sdumbbell R600_BUF_SWAP_32BIT | 578254885Sdumbbell#endif 579254885Sdumbbell R600_RB_RPTR_WR_ENA); 580254885Sdumbbell 581254885Sdumbbell RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr); 582254885Sdumbbell RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr); 583254885Sdumbbell RADEON_WRITE(R600_CP_RB_CNTL, cp_rb_cntl); 584254885Sdumbbell RADEON_WRITE(R600_CP_ME_CNTL, cp_me_cntl); 585254885Sdumbbell 586254885Sdumbbell /* Reset the CP ring */ 587254885Sdumbbell r600_do_cp_reset(dev_priv); 588254885Sdumbbell 589254885Sdumbbell /* The CP is no longer running after an engine reset */ 590254885Sdumbbell dev_priv->cp_running = 0; 591254885Sdumbbell 592254885Sdumbbell /* Reset any pending vertex, indirect buffers */ 593254885Sdumbbell radeon_freelist_reset(dev); 594254885Sdumbbell 595254885Sdumbbell return 0; 596254885Sdumbbell 597254885Sdumbbell} 598254885Sdumbbell 599254885Sdumbbellstatic u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes, 600254885Sdumbbell u32 num_backends, 601254885Sdumbbell u32 backend_disable_mask) 602254885Sdumbbell{ 603254885Sdumbbell u32 backend_map = 0; 604254885Sdumbbell u32 enabled_backends_mask; 605254885Sdumbbell u32 enabled_backends_count; 606254885Sdumbbell u32 cur_pipe; 607254885Sdumbbell u32 swizzle_pipe[R6XX_MAX_PIPES]; 608254885Sdumbbell u32 cur_backend; 609254885Sdumbbell u32 i; 610254885Sdumbbell 611254885Sdumbbell if (num_tile_pipes > R6XX_MAX_PIPES) 612254885Sdumbbell num_tile_pipes = R6XX_MAX_PIPES; 613254885Sdumbbell if (num_tile_pipes < 1) 614254885Sdumbbell num_tile_pipes = 1; 615254885Sdumbbell if (num_backends > R6XX_MAX_BACKENDS) 616254885Sdumbbell num_backends = R6XX_MAX_BACKENDS; 617254885Sdumbbell if (num_backends < 1) 618254885Sdumbbell num_backends = 1; 619254885Sdumbbell 620254885Sdumbbell enabled_backends_mask = 0; 621254885Sdumbbell enabled_backends_count = 0; 622254885Sdumbbell for (i = 0; i < R6XX_MAX_BACKENDS; ++i) { 623254885Sdumbbell if (((backend_disable_mask >> i) & 1) == 0) { 624254885Sdumbbell enabled_backends_mask |= (1 << i); 625254885Sdumbbell ++enabled_backends_count; 626254885Sdumbbell } 627254885Sdumbbell if (enabled_backends_count == num_backends) 628254885Sdumbbell break; 629254885Sdumbbell } 630254885Sdumbbell 631254885Sdumbbell if (enabled_backends_count == 0) { 632254885Sdumbbell enabled_backends_mask = 1; 633254885Sdumbbell enabled_backends_count = 1; 634254885Sdumbbell } 635254885Sdumbbell 636254885Sdumbbell if (enabled_backends_count != num_backends) 637254885Sdumbbell num_backends = enabled_backends_count; 638254885Sdumbbell 639254885Sdumbbell memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES); 640254885Sdumbbell switch (num_tile_pipes) { 641254885Sdumbbell case 1: 642254885Sdumbbell swizzle_pipe[0] = 0; 643254885Sdumbbell break; 644254885Sdumbbell case 2: 645254885Sdumbbell swizzle_pipe[0] = 0; 646254885Sdumbbell swizzle_pipe[1] = 1; 647254885Sdumbbell break; 648254885Sdumbbell case 3: 649254885Sdumbbell swizzle_pipe[0] = 0; 650254885Sdumbbell swizzle_pipe[1] = 1; 651254885Sdumbbell swizzle_pipe[2] = 2; 652254885Sdumbbell break; 653254885Sdumbbell case 4: 654254885Sdumbbell swizzle_pipe[0] = 0; 655254885Sdumbbell swizzle_pipe[1] = 1; 656254885Sdumbbell swizzle_pipe[2] = 2; 657254885Sdumbbell swizzle_pipe[3] = 3; 658254885Sdumbbell break; 659254885Sdumbbell case 5: 660254885Sdumbbell swizzle_pipe[0] = 0; 661254885Sdumbbell swizzle_pipe[1] = 1; 662254885Sdumbbell swizzle_pipe[2] = 2; 663254885Sdumbbell swizzle_pipe[3] = 3; 664254885Sdumbbell swizzle_pipe[4] = 4; 665254885Sdumbbell break; 666254885Sdumbbell case 6: 667254885Sdumbbell swizzle_pipe[0] = 0; 668254885Sdumbbell swizzle_pipe[1] = 2; 669254885Sdumbbell swizzle_pipe[2] = 4; 670254885Sdumbbell swizzle_pipe[3] = 5; 671254885Sdumbbell swizzle_pipe[4] = 1; 672254885Sdumbbell swizzle_pipe[5] = 3; 673254885Sdumbbell break; 674254885Sdumbbell case 7: 675254885Sdumbbell swizzle_pipe[0] = 0; 676254885Sdumbbell swizzle_pipe[1] = 2; 677254885Sdumbbell swizzle_pipe[2] = 4; 678254885Sdumbbell swizzle_pipe[3] = 6; 679254885Sdumbbell swizzle_pipe[4] = 1; 680254885Sdumbbell swizzle_pipe[5] = 3; 681254885Sdumbbell swizzle_pipe[6] = 5; 682254885Sdumbbell break; 683254885Sdumbbell case 8: 684254885Sdumbbell swizzle_pipe[0] = 0; 685254885Sdumbbell swizzle_pipe[1] = 2; 686254885Sdumbbell swizzle_pipe[2] = 4; 687254885Sdumbbell swizzle_pipe[3] = 6; 688254885Sdumbbell swizzle_pipe[4] = 1; 689254885Sdumbbell swizzle_pipe[5] = 3; 690254885Sdumbbell swizzle_pipe[6] = 5; 691254885Sdumbbell swizzle_pipe[7] = 7; 692254885Sdumbbell break; 693254885Sdumbbell } 694254885Sdumbbell 695254885Sdumbbell cur_backend = 0; 696254885Sdumbbell for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 697254885Sdumbbell while (((1 << cur_backend) & enabled_backends_mask) == 0) 698254885Sdumbbell cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; 699254885Sdumbbell 700254885Sdumbbell backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); 701254885Sdumbbell 702254885Sdumbbell cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS; 703254885Sdumbbell } 704254885Sdumbbell 705254885Sdumbbell return backend_map; 706254885Sdumbbell} 707254885Sdumbbell 708254885Sdumbbellstatic int r600_count_pipe_bits(uint32_t val) 709254885Sdumbbell{ 710254885Sdumbbell return hweight32(val); 711254885Sdumbbell} 712254885Sdumbbell 713254885Sdumbbellstatic void r600_gfx_init(struct drm_device *dev, 714254885Sdumbbell drm_radeon_private_t *dev_priv) 715254885Sdumbbell{ 716254885Sdumbbell int i, j, num_qd_pipes; 717254885Sdumbbell u32 sx_debug_1; 718254885Sdumbbell u32 tc_cntl; 719254885Sdumbbell u32 arb_pop; 720254885Sdumbbell u32 num_gs_verts_per_thread; 721254885Sdumbbell u32 vgt_gs_per_es; 722254885Sdumbbell u32 gs_prim_buffer_depth = 0; 723254885Sdumbbell u32 sq_ms_fifo_sizes; 724254885Sdumbbell u32 sq_config; 725254885Sdumbbell u32 sq_gpr_resource_mgmt_1 = 0; 726254885Sdumbbell u32 sq_gpr_resource_mgmt_2 = 0; 727254885Sdumbbell u32 sq_thread_resource_mgmt = 0; 728254885Sdumbbell u32 sq_stack_resource_mgmt_1 = 0; 729254885Sdumbbell u32 sq_stack_resource_mgmt_2 = 0; 730254885Sdumbbell u32 hdp_host_path_cntl; 731254885Sdumbbell u32 backend_map; 732254885Sdumbbell u32 gb_tiling_config = 0; 733254885Sdumbbell u32 cc_rb_backend_disable; 734254885Sdumbbell u32 cc_gc_shader_pipe_config; 735254885Sdumbbell u32 ramcfg; 736254885Sdumbbell 737254885Sdumbbell /* setup chip specs */ 738254885Sdumbbell switch (dev_priv->flags & RADEON_FAMILY_MASK) { 739254885Sdumbbell case CHIP_R600: 740254885Sdumbbell dev_priv->r600_max_pipes = 4; 741254885Sdumbbell dev_priv->r600_max_tile_pipes = 8; 742254885Sdumbbell dev_priv->r600_max_simds = 4; 743254885Sdumbbell dev_priv->r600_max_backends = 4; 744254885Sdumbbell dev_priv->r600_max_gprs = 256; 745254885Sdumbbell dev_priv->r600_max_threads = 192; 746254885Sdumbbell dev_priv->r600_max_stack_entries = 256; 747254885Sdumbbell dev_priv->r600_max_hw_contexts = 8; 748254885Sdumbbell dev_priv->r600_max_gs_threads = 16; 749254885Sdumbbell dev_priv->r600_sx_max_export_size = 128; 750254885Sdumbbell dev_priv->r600_sx_max_export_pos_size = 16; 751254885Sdumbbell dev_priv->r600_sx_max_export_smx_size = 128; 752254885Sdumbbell dev_priv->r600_sq_num_cf_insts = 2; 753254885Sdumbbell break; 754254885Sdumbbell case CHIP_RV630: 755254885Sdumbbell case CHIP_RV635: 756254885Sdumbbell dev_priv->r600_max_pipes = 2; 757254885Sdumbbell dev_priv->r600_max_tile_pipes = 2; 758254885Sdumbbell dev_priv->r600_max_simds = 3; 759254885Sdumbbell dev_priv->r600_max_backends = 1; 760254885Sdumbbell dev_priv->r600_max_gprs = 128; 761254885Sdumbbell dev_priv->r600_max_threads = 192; 762254885Sdumbbell dev_priv->r600_max_stack_entries = 128; 763254885Sdumbbell dev_priv->r600_max_hw_contexts = 8; 764254885Sdumbbell dev_priv->r600_max_gs_threads = 4; 765254885Sdumbbell dev_priv->r600_sx_max_export_size = 128; 766254885Sdumbbell dev_priv->r600_sx_max_export_pos_size = 16; 767254885Sdumbbell dev_priv->r600_sx_max_export_smx_size = 128; 768254885Sdumbbell dev_priv->r600_sq_num_cf_insts = 2; 769254885Sdumbbell break; 770254885Sdumbbell case CHIP_RV610: 771254885Sdumbbell case CHIP_RS780: 772254885Sdumbbell case CHIP_RS880: 773254885Sdumbbell case CHIP_RV620: 774254885Sdumbbell dev_priv->r600_max_pipes = 1; 775254885Sdumbbell dev_priv->r600_max_tile_pipes = 1; 776254885Sdumbbell dev_priv->r600_max_simds = 2; 777254885Sdumbbell dev_priv->r600_max_backends = 1; 778254885Sdumbbell dev_priv->r600_max_gprs = 128; 779254885Sdumbbell dev_priv->r600_max_threads = 192; 780254885Sdumbbell dev_priv->r600_max_stack_entries = 128; 781254885Sdumbbell dev_priv->r600_max_hw_contexts = 4; 782254885Sdumbbell dev_priv->r600_max_gs_threads = 4; 783254885Sdumbbell dev_priv->r600_sx_max_export_size = 128; 784254885Sdumbbell dev_priv->r600_sx_max_export_pos_size = 16; 785254885Sdumbbell dev_priv->r600_sx_max_export_smx_size = 128; 786254885Sdumbbell dev_priv->r600_sq_num_cf_insts = 1; 787254885Sdumbbell break; 788254885Sdumbbell case CHIP_RV670: 789254885Sdumbbell dev_priv->r600_max_pipes = 4; 790254885Sdumbbell dev_priv->r600_max_tile_pipes = 4; 791254885Sdumbbell dev_priv->r600_max_simds = 4; 792254885Sdumbbell dev_priv->r600_max_backends = 4; 793254885Sdumbbell dev_priv->r600_max_gprs = 192; 794254885Sdumbbell dev_priv->r600_max_threads = 192; 795254885Sdumbbell dev_priv->r600_max_stack_entries = 256; 796254885Sdumbbell dev_priv->r600_max_hw_contexts = 8; 797254885Sdumbbell dev_priv->r600_max_gs_threads = 16; 798254885Sdumbbell dev_priv->r600_sx_max_export_size = 128; 799254885Sdumbbell dev_priv->r600_sx_max_export_pos_size = 16; 800254885Sdumbbell dev_priv->r600_sx_max_export_smx_size = 128; 801254885Sdumbbell dev_priv->r600_sq_num_cf_insts = 2; 802254885Sdumbbell break; 803254885Sdumbbell default: 804254885Sdumbbell break; 805254885Sdumbbell } 806254885Sdumbbell 807254885Sdumbbell /* Initialize HDP */ 808254885Sdumbbell j = 0; 809254885Sdumbbell for (i = 0; i < 32; i++) { 810254885Sdumbbell RADEON_WRITE((0x2c14 + j), 0x00000000); 811254885Sdumbbell RADEON_WRITE((0x2c18 + j), 0x00000000); 812254885Sdumbbell RADEON_WRITE((0x2c1c + j), 0x00000000); 813254885Sdumbbell RADEON_WRITE((0x2c20 + j), 0x00000000); 814254885Sdumbbell RADEON_WRITE((0x2c24 + j), 0x00000000); 815254885Sdumbbell j += 0x18; 816254885Sdumbbell } 817254885Sdumbbell 818254885Sdumbbell RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff)); 819254885Sdumbbell 820254885Sdumbbell /* setup tiling, simd, pipe config */ 821254885Sdumbbell ramcfg = RADEON_READ(R600_RAMCFG); 822254885Sdumbbell 823254885Sdumbbell switch (dev_priv->r600_max_tile_pipes) { 824254885Sdumbbell case 1: 825254885Sdumbbell gb_tiling_config |= R600_PIPE_TILING(0); 826254885Sdumbbell break; 827254885Sdumbbell case 2: 828254885Sdumbbell gb_tiling_config |= R600_PIPE_TILING(1); 829254885Sdumbbell break; 830254885Sdumbbell case 4: 831254885Sdumbbell gb_tiling_config |= R600_PIPE_TILING(2); 832254885Sdumbbell break; 833254885Sdumbbell case 8: 834254885Sdumbbell gb_tiling_config |= R600_PIPE_TILING(3); 835254885Sdumbbell break; 836254885Sdumbbell default: 837254885Sdumbbell break; 838254885Sdumbbell } 839254885Sdumbbell 840254885Sdumbbell gb_tiling_config |= R600_BANK_TILING((ramcfg >> R600_NOOFBANK_SHIFT) & R600_NOOFBANK_MASK); 841254885Sdumbbell 842254885Sdumbbell gb_tiling_config |= R600_GROUP_SIZE(0); 843254885Sdumbbell 844254885Sdumbbell if (((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK) > 3) { 845254885Sdumbbell gb_tiling_config |= R600_ROW_TILING(3); 846254885Sdumbbell gb_tiling_config |= R600_SAMPLE_SPLIT(3); 847254885Sdumbbell } else { 848254885Sdumbbell gb_tiling_config |= 849254885Sdumbbell R600_ROW_TILING(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK)); 850254885Sdumbbell gb_tiling_config |= 851254885Sdumbbell R600_SAMPLE_SPLIT(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK)); 852254885Sdumbbell } 853254885Sdumbbell 854254885Sdumbbell gb_tiling_config |= R600_BANK_SWAPS(1); 855254885Sdumbbell 856254885Sdumbbell cc_rb_backend_disable = RADEON_READ(R600_CC_RB_BACKEND_DISABLE) & 0x00ff0000; 857254885Sdumbbell cc_rb_backend_disable |= 858254885Sdumbbell R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_MASK); 859254885Sdumbbell 860254885Sdumbbell cc_gc_shader_pipe_config = RADEON_READ(R600_CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; 861254885Sdumbbell cc_gc_shader_pipe_config |= 862254885Sdumbbell R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK); 863254885Sdumbbell cc_gc_shader_pipe_config |= 864254885Sdumbbell R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK); 865254885Sdumbbell 866254885Sdumbbell backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes, 867254885Sdumbbell (R6XX_MAX_BACKENDS - 868254885Sdumbbell r600_count_pipe_bits((cc_rb_backend_disable & 869254885Sdumbbell R6XX_MAX_BACKENDS_MASK) >> 16)), 870254885Sdumbbell (cc_rb_backend_disable >> 16)); 871254885Sdumbbell gb_tiling_config |= R600_BACKEND_MAP(backend_map); 872254885Sdumbbell 873254885Sdumbbell RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config); 874254885Sdumbbell RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 875254885Sdumbbell RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 876254885Sdumbbell if (gb_tiling_config & 0xc0) { 877254885Sdumbbell dev_priv->r600_group_size = 512; 878254885Sdumbbell } else { 879254885Sdumbbell dev_priv->r600_group_size = 256; 880254885Sdumbbell } 881254885Sdumbbell dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7); 882254885Sdumbbell if (gb_tiling_config & 0x30) { 883254885Sdumbbell dev_priv->r600_nbanks = 8; 884254885Sdumbbell } else { 885254885Sdumbbell dev_priv->r600_nbanks = 4; 886254885Sdumbbell } 887254885Sdumbbell 888254885Sdumbbell RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 889254885Sdumbbell RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 890254885Sdumbbell RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 891254885Sdumbbell 892254885Sdumbbell num_qd_pipes = 893254885Sdumbbell R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK) >> 8); 894254885Sdumbbell RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK); 895254885Sdumbbell RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK); 896254885Sdumbbell 897254885Sdumbbell /* set HW defaults for 3D engine */ 898254885Sdumbbell RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) | 899254885Sdumbbell R600_ROQ_IB2_START(0x2b))); 900254885Sdumbbell 901254885Sdumbbell RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, (R600_MEQ_END(0x40) | 902254885Sdumbbell R600_ROQ_END(0x40))); 903254885Sdumbbell 904254885Sdumbbell RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO | 905254885Sdumbbell R600_SYNC_GRADIENT | 906254885Sdumbbell R600_SYNC_WALKER | 907254885Sdumbbell R600_SYNC_ALIGNER)); 908254885Sdumbbell 909254885Sdumbbell if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) 910254885Sdumbbell RADEON_WRITE(R600_ARB_GDEC_RD_CNTL, 0x00000021); 911254885Sdumbbell 912254885Sdumbbell sx_debug_1 = RADEON_READ(R600_SX_DEBUG_1); 913254885Sdumbbell sx_debug_1 |= R600_SMX_EVENT_RELEASE; 914254885Sdumbbell if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600)) 915254885Sdumbbell sx_debug_1 |= R600_ENABLE_NEW_SMX_ADDRESS; 916254885Sdumbbell RADEON_WRITE(R600_SX_DEBUG_1, sx_debug_1); 917254885Sdumbbell 918254885Sdumbbell if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) || 919254885Sdumbbell ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) || 920254885Sdumbbell ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 921254885Sdumbbell ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 922254885Sdumbbell ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || 923254885Sdumbbell ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) 924254885Sdumbbell RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE); 925254885Sdumbbell else 926254885Sdumbbell RADEON_WRITE(R600_DB_DEBUG, 0); 927254885Sdumbbell 928254885Sdumbbell RADEON_WRITE(R600_DB_WATERMARKS, (R600_DEPTH_FREE(4) | 929254885Sdumbbell R600_DEPTH_FLUSH(16) | 930254885Sdumbbell R600_DEPTH_PENDING_FREE(4) | 931254885Sdumbbell R600_DEPTH_CACHELINE_FREE(16))); 932254885Sdumbbell RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 933254885Sdumbbell RADEON_WRITE(R600_VGT_NUM_INSTANCES, 0); 934254885Sdumbbell 935254885Sdumbbell RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0)); 936254885Sdumbbell RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(0)); 937254885Sdumbbell 938254885Sdumbbell sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES); 939254885Sdumbbell if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 940254885Sdumbbell ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 941254885Sdumbbell ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || 942254885Sdumbbell ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) { 943254885Sdumbbell sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) | 944254885Sdumbbell R600_FETCH_FIFO_HIWATER(0xa) | 945254885Sdumbbell R600_DONE_FIFO_HIWATER(0xe0) | 946254885Sdumbbell R600_ALU_UPDATE_FIFO_HIWATER(0x8)); 947254885Sdumbbell } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) || 948254885Sdumbbell ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) { 949254885Sdumbbell sq_ms_fifo_sizes &= ~R600_DONE_FIFO_HIWATER(0xff); 950254885Sdumbbell sq_ms_fifo_sizes |= R600_DONE_FIFO_HIWATER(0x4); 951254885Sdumbbell } 952254885Sdumbbell RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); 953254885Sdumbbell 954254885Sdumbbell /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 955254885Sdumbbell * should be adjusted as needed by the 2D/3D drivers. This just sets default values 956254885Sdumbbell */ 957254885Sdumbbell sq_config = RADEON_READ(R600_SQ_CONFIG); 958254885Sdumbbell sq_config &= ~(R600_PS_PRIO(3) | 959254885Sdumbbell R600_VS_PRIO(3) | 960254885Sdumbbell R600_GS_PRIO(3) | 961254885Sdumbbell R600_ES_PRIO(3)); 962254885Sdumbbell sq_config |= (R600_DX9_CONSTS | 963254885Sdumbbell R600_VC_ENABLE | 964254885Sdumbbell R600_PS_PRIO(0) | 965254885Sdumbbell R600_VS_PRIO(1) | 966254885Sdumbbell R600_GS_PRIO(2) | 967254885Sdumbbell R600_ES_PRIO(3)); 968254885Sdumbbell 969254885Sdumbbell if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) { 970254885Sdumbbell sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(124) | 971254885Sdumbbell R600_NUM_VS_GPRS(124) | 972254885Sdumbbell R600_NUM_CLAUSE_TEMP_GPRS(4)); 973254885Sdumbbell sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(0) | 974254885Sdumbbell R600_NUM_ES_GPRS(0)); 975254885Sdumbbell sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(136) | 976254885Sdumbbell R600_NUM_VS_THREADS(48) | 977254885Sdumbbell R600_NUM_GS_THREADS(4) | 978254885Sdumbbell R600_NUM_ES_THREADS(4)); 979254885Sdumbbell sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(128) | 980254885Sdumbbell R600_NUM_VS_STACK_ENTRIES(128)); 981254885Sdumbbell sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(0) | 982254885Sdumbbell R600_NUM_ES_STACK_ENTRIES(0)); 983254885Sdumbbell } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 984254885Sdumbbell ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 985254885Sdumbbell ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || 986254885Sdumbbell ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) { 987254885Sdumbbell /* no vertex cache */ 988254885Sdumbbell sq_config &= ~R600_VC_ENABLE; 989254885Sdumbbell 990254885Sdumbbell sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | 991254885Sdumbbell R600_NUM_VS_GPRS(44) | 992254885Sdumbbell R600_NUM_CLAUSE_TEMP_GPRS(2)); 993254885Sdumbbell sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) | 994254885Sdumbbell R600_NUM_ES_GPRS(17)); 995254885Sdumbbell sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | 996254885Sdumbbell R600_NUM_VS_THREADS(78) | 997254885Sdumbbell R600_NUM_GS_THREADS(4) | 998254885Sdumbbell R600_NUM_ES_THREADS(31)); 999254885Sdumbbell sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) | 1000254885Sdumbbell R600_NUM_VS_STACK_ENTRIES(40)); 1001254885Sdumbbell sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) | 1002254885Sdumbbell R600_NUM_ES_STACK_ENTRIES(16)); 1003254885Sdumbbell } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) || 1004254885Sdumbbell ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) { 1005254885Sdumbbell sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | 1006254885Sdumbbell R600_NUM_VS_GPRS(44) | 1007254885Sdumbbell R600_NUM_CLAUSE_TEMP_GPRS(2)); 1008254885Sdumbbell sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(18) | 1009254885Sdumbbell R600_NUM_ES_GPRS(18)); 1010254885Sdumbbell sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | 1011254885Sdumbbell R600_NUM_VS_THREADS(78) | 1012254885Sdumbbell R600_NUM_GS_THREADS(4) | 1013254885Sdumbbell R600_NUM_ES_THREADS(31)); 1014254885Sdumbbell sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) | 1015254885Sdumbbell R600_NUM_VS_STACK_ENTRIES(40)); 1016254885Sdumbbell sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) | 1017254885Sdumbbell R600_NUM_ES_STACK_ENTRIES(16)); 1018254885Sdumbbell } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) { 1019254885Sdumbbell sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) | 1020254885Sdumbbell R600_NUM_VS_GPRS(44) | 1021254885Sdumbbell R600_NUM_CLAUSE_TEMP_GPRS(2)); 1022254885Sdumbbell sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) | 1023254885Sdumbbell R600_NUM_ES_GPRS(17)); 1024254885Sdumbbell sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) | 1025254885Sdumbbell R600_NUM_VS_THREADS(78) | 1026254885Sdumbbell R600_NUM_GS_THREADS(4) | 1027254885Sdumbbell R600_NUM_ES_THREADS(31)); 1028254885Sdumbbell sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(64) | 1029254885Sdumbbell R600_NUM_VS_STACK_ENTRIES(64)); 1030254885Sdumbbell sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(64) | 1031254885Sdumbbell R600_NUM_ES_STACK_ENTRIES(64)); 1032254885Sdumbbell } 1033254885Sdumbbell 1034254885Sdumbbell RADEON_WRITE(R600_SQ_CONFIG, sq_config); 1035254885Sdumbbell RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); 1036254885Sdumbbell RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); 1037254885Sdumbbell RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 1038254885Sdumbbell RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); 1039254885Sdumbbell RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); 1040254885Sdumbbell 1041254885Sdumbbell if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) || 1042254885Sdumbbell ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) || 1043254885Sdumbbell ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) || 1044254885Sdumbbell ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) 1045254885Sdumbbell RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY)); 1046254885Sdumbbell else 1047254885Sdumbbell RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC)); 1048254885Sdumbbell 1049254885Sdumbbell RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_2S, (R600_S0_X(0xc) | 1050254885Sdumbbell R600_S0_Y(0x4) | 1051254885Sdumbbell R600_S1_X(0x4) | 1052254885Sdumbbell R600_S1_Y(0xc))); 1053254885Sdumbbell RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_4S, (R600_S0_X(0xe) | 1054254885Sdumbbell R600_S0_Y(0xe) | 1055254885Sdumbbell R600_S1_X(0x2) | 1056254885Sdumbbell R600_S1_Y(0x2) | 1057254885Sdumbbell R600_S2_X(0xa) | 1058254885Sdumbbell R600_S2_Y(0x6) | 1059254885Sdumbbell R600_S3_X(0x6) | 1060254885Sdumbbell R600_S3_Y(0xa))); 1061254885Sdumbbell RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0, (R600_S0_X(0xe) | 1062254885Sdumbbell R600_S0_Y(0xb) | 1063254885Sdumbbell R600_S1_X(0x4) | 1064254885Sdumbbell R600_S1_Y(0xc) | 1065254885Sdumbbell R600_S2_X(0x1) | 1066254885Sdumbbell R600_S2_Y(0x6) | 1067254885Sdumbbell R600_S3_X(0xa) | 1068254885Sdumbbell R600_S3_Y(0xe))); 1069254885Sdumbbell RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1, (R600_S4_X(0x6) | 1070254885Sdumbbell R600_S4_Y(0x1) | 1071254885Sdumbbell R600_S5_X(0x0) | 1072254885Sdumbbell R600_S5_Y(0x0) | 1073254885Sdumbbell R600_S6_X(0xb) | 1074254885Sdumbbell R600_S6_Y(0x4) | 1075254885Sdumbbell R600_S7_X(0x7) | 1076254885Sdumbbell R600_S7_Y(0x8))); 1077254885Sdumbbell 1078254885Sdumbbell 1079254885Sdumbbell switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1080254885Sdumbbell case CHIP_R600: 1081254885Sdumbbell case CHIP_RV630: 1082254885Sdumbbell case CHIP_RV635: 1083254885Sdumbbell gs_prim_buffer_depth = 0; 1084254885Sdumbbell break; 1085254885Sdumbbell case CHIP_RV610: 1086254885Sdumbbell case CHIP_RS780: 1087254885Sdumbbell case CHIP_RS880: 1088254885Sdumbbell case CHIP_RV620: 1089254885Sdumbbell gs_prim_buffer_depth = 32; 1090254885Sdumbbell break; 1091254885Sdumbbell case CHIP_RV670: 1092254885Sdumbbell gs_prim_buffer_depth = 128; 1093254885Sdumbbell break; 1094254885Sdumbbell default: 1095254885Sdumbbell break; 1096254885Sdumbbell } 1097254885Sdumbbell 1098254885Sdumbbell num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16; 1099254885Sdumbbell vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; 1100254885Sdumbbell /* Max value for this is 256 */ 1101254885Sdumbbell if (vgt_gs_per_es > 256) 1102254885Sdumbbell vgt_gs_per_es = 256; 1103254885Sdumbbell 1104254885Sdumbbell RADEON_WRITE(R600_VGT_ES_PER_GS, 128); 1105254885Sdumbbell RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es); 1106254885Sdumbbell RADEON_WRITE(R600_VGT_GS_PER_VS, 2); 1107254885Sdumbbell RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16); 1108254885Sdumbbell 1109254885Sdumbbell /* more default values. 2D/3D driver should adjust as needed */ 1110254885Sdumbbell RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0); 1111254885Sdumbbell RADEON_WRITE(R600_VGT_STRMOUT_EN, 0); 1112254885Sdumbbell RADEON_WRITE(R600_SX_MISC, 0); 1113254885Sdumbbell RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0); 1114254885Sdumbbell RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0); 1115254885Sdumbbell RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0); 1116254885Sdumbbell RADEON_WRITE(R600_SPI_INPUT_Z, 0); 1117254885Sdumbbell RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2)); 1118254885Sdumbbell RADEON_WRITE(R600_CB_COLOR7_FRAG, 0); 1119254885Sdumbbell 1120254885Sdumbbell /* clear render buffer base addresses */ 1121254885Sdumbbell RADEON_WRITE(R600_CB_COLOR0_BASE, 0); 1122254885Sdumbbell RADEON_WRITE(R600_CB_COLOR1_BASE, 0); 1123254885Sdumbbell RADEON_WRITE(R600_CB_COLOR2_BASE, 0); 1124254885Sdumbbell RADEON_WRITE(R600_CB_COLOR3_BASE, 0); 1125254885Sdumbbell RADEON_WRITE(R600_CB_COLOR4_BASE, 0); 1126254885Sdumbbell RADEON_WRITE(R600_CB_COLOR5_BASE, 0); 1127254885Sdumbbell RADEON_WRITE(R600_CB_COLOR6_BASE, 0); 1128254885Sdumbbell RADEON_WRITE(R600_CB_COLOR7_BASE, 0); 1129254885Sdumbbell 1130254885Sdumbbell switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1131254885Sdumbbell case CHIP_RV610: 1132254885Sdumbbell case CHIP_RS780: 1133254885Sdumbbell case CHIP_RS880: 1134254885Sdumbbell case CHIP_RV620: 1135254885Sdumbbell tc_cntl = R600_TC_L2_SIZE(8); 1136254885Sdumbbell break; 1137254885Sdumbbell case CHIP_RV630: 1138254885Sdumbbell case CHIP_RV635: 1139254885Sdumbbell tc_cntl = R600_TC_L2_SIZE(4); 1140254885Sdumbbell break; 1141254885Sdumbbell case CHIP_R600: 1142254885Sdumbbell tc_cntl = R600_TC_L2_SIZE(0) | R600_L2_DISABLE_LATE_HIT; 1143254885Sdumbbell break; 1144254885Sdumbbell default: 1145254885Sdumbbell tc_cntl = R600_TC_L2_SIZE(0); 1146254885Sdumbbell break; 1147254885Sdumbbell } 1148254885Sdumbbell 1149254885Sdumbbell RADEON_WRITE(R600_TC_CNTL, tc_cntl); 1150254885Sdumbbell 1151254885Sdumbbell hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL); 1152254885Sdumbbell RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1153254885Sdumbbell 1154254885Sdumbbell arb_pop = RADEON_READ(R600_ARB_POP); 1155254885Sdumbbell arb_pop |= R600_ENABLE_TC128; 1156254885Sdumbbell RADEON_WRITE(R600_ARB_POP, arb_pop); 1157254885Sdumbbell 1158254885Sdumbbell RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 1159254885Sdumbbell RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA | 1160254885Sdumbbell R600_NUM_CLIP_SEQ(3))); 1161254885Sdumbbell RADEON_WRITE(R600_PA_SC_ENHANCE, R600_FORCE_EOV_MAX_CLK_CNT(4095)); 1162254885Sdumbbell 1163254885Sdumbbell} 1164254885Sdumbbell 1165254885Sdumbbellstatic u32 r700_get_tile_pipe_to_backend_map(drm_radeon_private_t *dev_priv, 1166254885Sdumbbell u32 num_tile_pipes, 1167254885Sdumbbell u32 num_backends, 1168254885Sdumbbell u32 backend_disable_mask) 1169254885Sdumbbell{ 1170254885Sdumbbell u32 backend_map = 0; 1171254885Sdumbbell u32 enabled_backends_mask; 1172254885Sdumbbell u32 enabled_backends_count; 1173254885Sdumbbell u32 cur_pipe; 1174254885Sdumbbell u32 swizzle_pipe[R7XX_MAX_PIPES]; 1175254885Sdumbbell u32 cur_backend; 1176254885Sdumbbell u32 i; 1177254885Sdumbbell bool force_no_swizzle; 1178254885Sdumbbell 1179254885Sdumbbell if (num_tile_pipes > R7XX_MAX_PIPES) 1180254885Sdumbbell num_tile_pipes = R7XX_MAX_PIPES; 1181254885Sdumbbell if (num_tile_pipes < 1) 1182254885Sdumbbell num_tile_pipes = 1; 1183254885Sdumbbell if (num_backends > R7XX_MAX_BACKENDS) 1184254885Sdumbbell num_backends = R7XX_MAX_BACKENDS; 1185254885Sdumbbell if (num_backends < 1) 1186254885Sdumbbell num_backends = 1; 1187254885Sdumbbell 1188254885Sdumbbell enabled_backends_mask = 0; 1189254885Sdumbbell enabled_backends_count = 0; 1190254885Sdumbbell for (i = 0; i < R7XX_MAX_BACKENDS; ++i) { 1191254885Sdumbbell if (((backend_disable_mask >> i) & 1) == 0) { 1192254885Sdumbbell enabled_backends_mask |= (1 << i); 1193254885Sdumbbell ++enabled_backends_count; 1194254885Sdumbbell } 1195254885Sdumbbell if (enabled_backends_count == num_backends) 1196254885Sdumbbell break; 1197254885Sdumbbell } 1198254885Sdumbbell 1199254885Sdumbbell if (enabled_backends_count == 0) { 1200254885Sdumbbell enabled_backends_mask = 1; 1201254885Sdumbbell enabled_backends_count = 1; 1202254885Sdumbbell } 1203254885Sdumbbell 1204254885Sdumbbell if (enabled_backends_count != num_backends) 1205254885Sdumbbell num_backends = enabled_backends_count; 1206254885Sdumbbell 1207254885Sdumbbell switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1208254885Sdumbbell case CHIP_RV770: 1209254885Sdumbbell case CHIP_RV730: 1210254885Sdumbbell force_no_swizzle = false; 1211254885Sdumbbell break; 1212254885Sdumbbell case CHIP_RV710: 1213254885Sdumbbell case CHIP_RV740: 1214254885Sdumbbell default: 1215254885Sdumbbell force_no_swizzle = true; 1216254885Sdumbbell break; 1217254885Sdumbbell } 1218254885Sdumbbell 1219254885Sdumbbell memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES); 1220254885Sdumbbell switch (num_tile_pipes) { 1221254885Sdumbbell case 1: 1222254885Sdumbbell swizzle_pipe[0] = 0; 1223254885Sdumbbell break; 1224254885Sdumbbell case 2: 1225254885Sdumbbell swizzle_pipe[0] = 0; 1226254885Sdumbbell swizzle_pipe[1] = 1; 1227254885Sdumbbell break; 1228254885Sdumbbell case 3: 1229254885Sdumbbell if (force_no_swizzle) { 1230254885Sdumbbell swizzle_pipe[0] = 0; 1231254885Sdumbbell swizzle_pipe[1] = 1; 1232254885Sdumbbell swizzle_pipe[2] = 2; 1233254885Sdumbbell } else { 1234254885Sdumbbell swizzle_pipe[0] = 0; 1235254885Sdumbbell swizzle_pipe[1] = 2; 1236254885Sdumbbell swizzle_pipe[2] = 1; 1237254885Sdumbbell } 1238254885Sdumbbell break; 1239254885Sdumbbell case 4: 1240254885Sdumbbell if (force_no_swizzle) { 1241254885Sdumbbell swizzle_pipe[0] = 0; 1242254885Sdumbbell swizzle_pipe[1] = 1; 1243254885Sdumbbell swizzle_pipe[2] = 2; 1244254885Sdumbbell swizzle_pipe[3] = 3; 1245254885Sdumbbell } else { 1246254885Sdumbbell swizzle_pipe[0] = 0; 1247254885Sdumbbell swizzle_pipe[1] = 2; 1248254885Sdumbbell swizzle_pipe[2] = 3; 1249254885Sdumbbell swizzle_pipe[3] = 1; 1250254885Sdumbbell } 1251254885Sdumbbell break; 1252254885Sdumbbell case 5: 1253254885Sdumbbell if (force_no_swizzle) { 1254254885Sdumbbell swizzle_pipe[0] = 0; 1255254885Sdumbbell swizzle_pipe[1] = 1; 1256254885Sdumbbell swizzle_pipe[2] = 2; 1257254885Sdumbbell swizzle_pipe[3] = 3; 1258254885Sdumbbell swizzle_pipe[4] = 4; 1259254885Sdumbbell } else { 1260254885Sdumbbell swizzle_pipe[0] = 0; 1261254885Sdumbbell swizzle_pipe[1] = 2; 1262254885Sdumbbell swizzle_pipe[2] = 4; 1263254885Sdumbbell swizzle_pipe[3] = 1; 1264254885Sdumbbell swizzle_pipe[4] = 3; 1265254885Sdumbbell } 1266254885Sdumbbell break; 1267254885Sdumbbell case 6: 1268254885Sdumbbell if (force_no_swizzle) { 1269254885Sdumbbell swizzle_pipe[0] = 0; 1270254885Sdumbbell swizzle_pipe[1] = 1; 1271254885Sdumbbell swizzle_pipe[2] = 2; 1272254885Sdumbbell swizzle_pipe[3] = 3; 1273254885Sdumbbell swizzle_pipe[4] = 4; 1274254885Sdumbbell swizzle_pipe[5] = 5; 1275254885Sdumbbell } else { 1276254885Sdumbbell swizzle_pipe[0] = 0; 1277254885Sdumbbell swizzle_pipe[1] = 2; 1278254885Sdumbbell swizzle_pipe[2] = 4; 1279254885Sdumbbell swizzle_pipe[3] = 5; 1280254885Sdumbbell swizzle_pipe[4] = 3; 1281254885Sdumbbell swizzle_pipe[5] = 1; 1282254885Sdumbbell } 1283254885Sdumbbell break; 1284254885Sdumbbell case 7: 1285254885Sdumbbell if (force_no_swizzle) { 1286254885Sdumbbell swizzle_pipe[0] = 0; 1287254885Sdumbbell swizzle_pipe[1] = 1; 1288254885Sdumbbell swizzle_pipe[2] = 2; 1289254885Sdumbbell swizzle_pipe[3] = 3; 1290254885Sdumbbell swizzle_pipe[4] = 4; 1291254885Sdumbbell swizzle_pipe[5] = 5; 1292254885Sdumbbell swizzle_pipe[6] = 6; 1293254885Sdumbbell } else { 1294254885Sdumbbell swizzle_pipe[0] = 0; 1295254885Sdumbbell swizzle_pipe[1] = 2; 1296254885Sdumbbell swizzle_pipe[2] = 4; 1297254885Sdumbbell swizzle_pipe[3] = 6; 1298254885Sdumbbell swizzle_pipe[4] = 3; 1299254885Sdumbbell swizzle_pipe[5] = 1; 1300254885Sdumbbell swizzle_pipe[6] = 5; 1301254885Sdumbbell } 1302254885Sdumbbell break; 1303254885Sdumbbell case 8: 1304254885Sdumbbell if (force_no_swizzle) { 1305254885Sdumbbell swizzle_pipe[0] = 0; 1306254885Sdumbbell swizzle_pipe[1] = 1; 1307254885Sdumbbell swizzle_pipe[2] = 2; 1308254885Sdumbbell swizzle_pipe[3] = 3; 1309254885Sdumbbell swizzle_pipe[4] = 4; 1310254885Sdumbbell swizzle_pipe[5] = 5; 1311254885Sdumbbell swizzle_pipe[6] = 6; 1312254885Sdumbbell swizzle_pipe[7] = 7; 1313254885Sdumbbell } else { 1314254885Sdumbbell swizzle_pipe[0] = 0; 1315254885Sdumbbell swizzle_pipe[1] = 2; 1316254885Sdumbbell swizzle_pipe[2] = 4; 1317254885Sdumbbell swizzle_pipe[3] = 6; 1318254885Sdumbbell swizzle_pipe[4] = 3; 1319254885Sdumbbell swizzle_pipe[5] = 1; 1320254885Sdumbbell swizzle_pipe[6] = 7; 1321254885Sdumbbell swizzle_pipe[7] = 5; 1322254885Sdumbbell } 1323254885Sdumbbell break; 1324254885Sdumbbell } 1325254885Sdumbbell 1326254885Sdumbbell cur_backend = 0; 1327254885Sdumbbell for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { 1328254885Sdumbbell while (((1 << cur_backend) & enabled_backends_mask) == 0) 1329254885Sdumbbell cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; 1330254885Sdumbbell 1331254885Sdumbbell backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); 1332254885Sdumbbell 1333254885Sdumbbell cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; 1334254885Sdumbbell } 1335254885Sdumbbell 1336254885Sdumbbell return backend_map; 1337254885Sdumbbell} 1338254885Sdumbbell 1339254885Sdumbbellstatic void r700_gfx_init(struct drm_device *dev, 1340254885Sdumbbell drm_radeon_private_t *dev_priv) 1341254885Sdumbbell{ 1342254885Sdumbbell int i, j, num_qd_pipes; 1343254885Sdumbbell u32 ta_aux_cntl; 1344254885Sdumbbell u32 sx_debug_1; 1345254885Sdumbbell u32 smx_dc_ctl0; 1346254885Sdumbbell u32 db_debug3; 1347254885Sdumbbell u32 num_gs_verts_per_thread; 1348254885Sdumbbell u32 vgt_gs_per_es; 1349254885Sdumbbell u32 gs_prim_buffer_depth = 0; 1350254885Sdumbbell u32 sq_ms_fifo_sizes; 1351254885Sdumbbell u32 sq_config; 1352254885Sdumbbell u32 sq_thread_resource_mgmt; 1353254885Sdumbbell u32 hdp_host_path_cntl; 1354254885Sdumbbell u32 sq_dyn_gpr_size_simd_ab_0; 1355254885Sdumbbell u32 backend_map; 1356254885Sdumbbell u32 gb_tiling_config = 0; 1357254885Sdumbbell u32 cc_rb_backend_disable; 1358254885Sdumbbell u32 cc_gc_shader_pipe_config; 1359254885Sdumbbell u32 mc_arb_ramcfg; 1360254885Sdumbbell u32 db_debug4; 1361254885Sdumbbell 1362254885Sdumbbell /* setup chip specs */ 1363254885Sdumbbell switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1364254885Sdumbbell case CHIP_RV770: 1365254885Sdumbbell dev_priv->r600_max_pipes = 4; 1366254885Sdumbbell dev_priv->r600_max_tile_pipes = 8; 1367254885Sdumbbell dev_priv->r600_max_simds = 10; 1368254885Sdumbbell dev_priv->r600_max_backends = 4; 1369254885Sdumbbell dev_priv->r600_max_gprs = 256; 1370254885Sdumbbell dev_priv->r600_max_threads = 248; 1371254885Sdumbbell dev_priv->r600_max_stack_entries = 512; 1372254885Sdumbbell dev_priv->r600_max_hw_contexts = 8; 1373254885Sdumbbell dev_priv->r600_max_gs_threads = 16 * 2; 1374254885Sdumbbell dev_priv->r600_sx_max_export_size = 128; 1375254885Sdumbbell dev_priv->r600_sx_max_export_pos_size = 16; 1376254885Sdumbbell dev_priv->r600_sx_max_export_smx_size = 112; 1377254885Sdumbbell dev_priv->r600_sq_num_cf_insts = 2; 1378254885Sdumbbell 1379254885Sdumbbell dev_priv->r700_sx_num_of_sets = 7; 1380254885Sdumbbell dev_priv->r700_sc_prim_fifo_size = 0xF9; 1381254885Sdumbbell dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1382254885Sdumbbell dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 1383254885Sdumbbell break; 1384254885Sdumbbell case CHIP_RV730: 1385254885Sdumbbell dev_priv->r600_max_pipes = 2; 1386254885Sdumbbell dev_priv->r600_max_tile_pipes = 4; 1387254885Sdumbbell dev_priv->r600_max_simds = 8; 1388254885Sdumbbell dev_priv->r600_max_backends = 2; 1389254885Sdumbbell dev_priv->r600_max_gprs = 128; 1390254885Sdumbbell dev_priv->r600_max_threads = 248; 1391254885Sdumbbell dev_priv->r600_max_stack_entries = 256; 1392254885Sdumbbell dev_priv->r600_max_hw_contexts = 8; 1393254885Sdumbbell dev_priv->r600_max_gs_threads = 16 * 2; 1394254885Sdumbbell dev_priv->r600_sx_max_export_size = 256; 1395254885Sdumbbell dev_priv->r600_sx_max_export_pos_size = 32; 1396254885Sdumbbell dev_priv->r600_sx_max_export_smx_size = 224; 1397254885Sdumbbell dev_priv->r600_sq_num_cf_insts = 2; 1398254885Sdumbbell 1399254885Sdumbbell dev_priv->r700_sx_num_of_sets = 7; 1400254885Sdumbbell dev_priv->r700_sc_prim_fifo_size = 0xf9; 1401254885Sdumbbell dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1402254885Sdumbbell dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 1403254885Sdumbbell if (dev_priv->r600_sx_max_export_pos_size > 16) { 1404254885Sdumbbell dev_priv->r600_sx_max_export_pos_size -= 16; 1405254885Sdumbbell dev_priv->r600_sx_max_export_smx_size += 16; 1406254885Sdumbbell } 1407254885Sdumbbell break; 1408254885Sdumbbell case CHIP_RV710: 1409254885Sdumbbell dev_priv->r600_max_pipes = 2; 1410254885Sdumbbell dev_priv->r600_max_tile_pipes = 2; 1411254885Sdumbbell dev_priv->r600_max_simds = 2; 1412254885Sdumbbell dev_priv->r600_max_backends = 1; 1413254885Sdumbbell dev_priv->r600_max_gprs = 256; 1414254885Sdumbbell dev_priv->r600_max_threads = 192; 1415254885Sdumbbell dev_priv->r600_max_stack_entries = 256; 1416254885Sdumbbell dev_priv->r600_max_hw_contexts = 4; 1417254885Sdumbbell dev_priv->r600_max_gs_threads = 8 * 2; 1418254885Sdumbbell dev_priv->r600_sx_max_export_size = 128; 1419254885Sdumbbell dev_priv->r600_sx_max_export_pos_size = 16; 1420254885Sdumbbell dev_priv->r600_sx_max_export_smx_size = 112; 1421254885Sdumbbell dev_priv->r600_sq_num_cf_insts = 1; 1422254885Sdumbbell 1423254885Sdumbbell dev_priv->r700_sx_num_of_sets = 7; 1424254885Sdumbbell dev_priv->r700_sc_prim_fifo_size = 0x40; 1425254885Sdumbbell dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1426254885Sdumbbell dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 1427254885Sdumbbell break; 1428254885Sdumbbell case CHIP_RV740: 1429254885Sdumbbell dev_priv->r600_max_pipes = 4; 1430254885Sdumbbell dev_priv->r600_max_tile_pipes = 4; 1431254885Sdumbbell dev_priv->r600_max_simds = 8; 1432254885Sdumbbell dev_priv->r600_max_backends = 4; 1433254885Sdumbbell dev_priv->r600_max_gprs = 256; 1434254885Sdumbbell dev_priv->r600_max_threads = 248; 1435254885Sdumbbell dev_priv->r600_max_stack_entries = 512; 1436254885Sdumbbell dev_priv->r600_max_hw_contexts = 8; 1437254885Sdumbbell dev_priv->r600_max_gs_threads = 16 * 2; 1438254885Sdumbbell dev_priv->r600_sx_max_export_size = 256; 1439254885Sdumbbell dev_priv->r600_sx_max_export_pos_size = 32; 1440254885Sdumbbell dev_priv->r600_sx_max_export_smx_size = 224; 1441254885Sdumbbell dev_priv->r600_sq_num_cf_insts = 2; 1442254885Sdumbbell 1443254885Sdumbbell dev_priv->r700_sx_num_of_sets = 7; 1444254885Sdumbbell dev_priv->r700_sc_prim_fifo_size = 0x100; 1445254885Sdumbbell dev_priv->r700_sc_hiz_tile_fifo_size = 0x30; 1446254885Sdumbbell dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130; 1447254885Sdumbbell 1448254885Sdumbbell if (dev_priv->r600_sx_max_export_pos_size > 16) { 1449254885Sdumbbell dev_priv->r600_sx_max_export_pos_size -= 16; 1450254885Sdumbbell dev_priv->r600_sx_max_export_smx_size += 16; 1451254885Sdumbbell } 1452254885Sdumbbell break; 1453254885Sdumbbell default: 1454254885Sdumbbell break; 1455254885Sdumbbell } 1456254885Sdumbbell 1457254885Sdumbbell /* Initialize HDP */ 1458254885Sdumbbell j = 0; 1459254885Sdumbbell for (i = 0; i < 32; i++) { 1460254885Sdumbbell RADEON_WRITE((0x2c14 + j), 0x00000000); 1461254885Sdumbbell RADEON_WRITE((0x2c18 + j), 0x00000000); 1462254885Sdumbbell RADEON_WRITE((0x2c1c + j), 0x00000000); 1463254885Sdumbbell RADEON_WRITE((0x2c20 + j), 0x00000000); 1464254885Sdumbbell RADEON_WRITE((0x2c24 + j), 0x00000000); 1465254885Sdumbbell j += 0x18; 1466254885Sdumbbell } 1467254885Sdumbbell 1468254885Sdumbbell RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff)); 1469254885Sdumbbell 1470254885Sdumbbell /* setup tiling, simd, pipe config */ 1471254885Sdumbbell mc_arb_ramcfg = RADEON_READ(R700_MC_ARB_RAMCFG); 1472254885Sdumbbell 1473254885Sdumbbell switch (dev_priv->r600_max_tile_pipes) { 1474254885Sdumbbell case 1: 1475254885Sdumbbell gb_tiling_config |= R600_PIPE_TILING(0); 1476254885Sdumbbell break; 1477254885Sdumbbell case 2: 1478254885Sdumbbell gb_tiling_config |= R600_PIPE_TILING(1); 1479254885Sdumbbell break; 1480254885Sdumbbell case 4: 1481254885Sdumbbell gb_tiling_config |= R600_PIPE_TILING(2); 1482254885Sdumbbell break; 1483254885Sdumbbell case 8: 1484254885Sdumbbell gb_tiling_config |= R600_PIPE_TILING(3); 1485254885Sdumbbell break; 1486254885Sdumbbell default: 1487254885Sdumbbell break; 1488254885Sdumbbell } 1489254885Sdumbbell 1490254885Sdumbbell if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770) 1491254885Sdumbbell gb_tiling_config |= R600_BANK_TILING(1); 1492254885Sdumbbell else 1493254885Sdumbbell gb_tiling_config |= R600_BANK_TILING((mc_arb_ramcfg >> R700_NOOFBANK_SHIFT) & R700_NOOFBANK_MASK); 1494254885Sdumbbell 1495254885Sdumbbell gb_tiling_config |= R600_GROUP_SIZE(0); 1496254885Sdumbbell 1497254885Sdumbbell if (((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK) > 3) { 1498254885Sdumbbell gb_tiling_config |= R600_ROW_TILING(3); 1499254885Sdumbbell gb_tiling_config |= R600_SAMPLE_SPLIT(3); 1500254885Sdumbbell } else { 1501254885Sdumbbell gb_tiling_config |= 1502254885Sdumbbell R600_ROW_TILING(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK)); 1503254885Sdumbbell gb_tiling_config |= 1504254885Sdumbbell R600_SAMPLE_SPLIT(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK)); 1505254885Sdumbbell } 1506254885Sdumbbell 1507254885Sdumbbell gb_tiling_config |= R600_BANK_SWAPS(1); 1508254885Sdumbbell 1509254885Sdumbbell cc_rb_backend_disable = RADEON_READ(R600_CC_RB_BACKEND_DISABLE) & 0x00ff0000; 1510254885Sdumbbell cc_rb_backend_disable |= 1511254885Sdumbbell R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_MASK); 1512254885Sdumbbell 1513254885Sdumbbell cc_gc_shader_pipe_config = RADEON_READ(R600_CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00; 1514254885Sdumbbell cc_gc_shader_pipe_config |= 1515254885Sdumbbell R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK); 1516254885Sdumbbell cc_gc_shader_pipe_config |= 1517254885Sdumbbell R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK); 1518254885Sdumbbell 1519254885Sdumbbell if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV740) 1520254885Sdumbbell backend_map = 0x28; 1521254885Sdumbbell else 1522254885Sdumbbell backend_map = r700_get_tile_pipe_to_backend_map(dev_priv, 1523254885Sdumbbell dev_priv->r600_max_tile_pipes, 1524254885Sdumbbell (R7XX_MAX_BACKENDS - 1525254885Sdumbbell r600_count_pipe_bits((cc_rb_backend_disable & 1526254885Sdumbbell R7XX_MAX_BACKENDS_MASK) >> 16)), 1527254885Sdumbbell (cc_rb_backend_disable >> 16)); 1528254885Sdumbbell gb_tiling_config |= R600_BACKEND_MAP(backend_map); 1529254885Sdumbbell 1530254885Sdumbbell RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config); 1531254885Sdumbbell RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1532254885Sdumbbell RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); 1533254885Sdumbbell if (gb_tiling_config & 0xc0) { 1534254885Sdumbbell dev_priv->r600_group_size = 512; 1535254885Sdumbbell } else { 1536254885Sdumbbell dev_priv->r600_group_size = 256; 1537254885Sdumbbell } 1538254885Sdumbbell dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7); 1539254885Sdumbbell if (gb_tiling_config & 0x30) { 1540254885Sdumbbell dev_priv->r600_nbanks = 8; 1541254885Sdumbbell } else { 1542254885Sdumbbell dev_priv->r600_nbanks = 4; 1543254885Sdumbbell } 1544254885Sdumbbell 1545254885Sdumbbell RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); 1546254885Sdumbbell RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 1547254885Sdumbbell RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); 1548254885Sdumbbell 1549254885Sdumbbell RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); 1550254885Sdumbbell RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0); 1551254885Sdumbbell RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0); 1552254885Sdumbbell RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0); 1553254885Sdumbbell RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0); 1554254885Sdumbbell 1555254885Sdumbbell num_qd_pipes = 1556254885Sdumbbell R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK) >> 8); 1557254885Sdumbbell RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK); 1558254885Sdumbbell RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK); 1559254885Sdumbbell 1560254885Sdumbbell /* set HW defaults for 3D engine */ 1561254885Sdumbbell RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) | 1562254885Sdumbbell R600_ROQ_IB2_START(0x2b))); 1563254885Sdumbbell 1564254885Sdumbbell RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, R700_STQ_SPLIT(0x30)); 1565254885Sdumbbell 1566254885Sdumbbell ta_aux_cntl = RADEON_READ(R600_TA_CNTL_AUX); 1567254885Sdumbbell RADEON_WRITE(R600_TA_CNTL_AUX, ta_aux_cntl | R600_DISABLE_CUBE_ANISO); 1568254885Sdumbbell 1569254885Sdumbbell sx_debug_1 = RADEON_READ(R700_SX_DEBUG_1); 1570254885Sdumbbell sx_debug_1 |= R700_ENABLE_NEW_SMX_ADDRESS; 1571254885Sdumbbell RADEON_WRITE(R700_SX_DEBUG_1, sx_debug_1); 1572254885Sdumbbell 1573254885Sdumbbell smx_dc_ctl0 = RADEON_READ(R600_SMX_DC_CTL0); 1574254885Sdumbbell smx_dc_ctl0 &= ~R700_CACHE_DEPTH(0x1ff); 1575254885Sdumbbell smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1); 1576254885Sdumbbell RADEON_WRITE(R600_SMX_DC_CTL0, smx_dc_ctl0); 1577254885Sdumbbell 1578254885Sdumbbell if ((dev_priv->flags & RADEON_FAMILY_MASK) != CHIP_RV740) 1579254885Sdumbbell RADEON_WRITE(R700_SMX_EVENT_CTL, (R700_ES_FLUSH_CTL(4) | 1580254885Sdumbbell R700_GS_FLUSH_CTL(4) | 1581254885Sdumbbell R700_ACK_FLUSH_CTL(3) | 1582254885Sdumbbell R700_SYNC_FLUSH_CTL)); 1583254885Sdumbbell 1584254885Sdumbbell db_debug3 = RADEON_READ(R700_DB_DEBUG3); 1585254885Sdumbbell db_debug3 &= ~R700_DB_CLK_OFF_DELAY(0x1f); 1586254885Sdumbbell switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1587254885Sdumbbell case CHIP_RV770: 1588254885Sdumbbell case CHIP_RV740: 1589254885Sdumbbell db_debug3 |= R700_DB_CLK_OFF_DELAY(0x1f); 1590254885Sdumbbell break; 1591254885Sdumbbell case CHIP_RV710: 1592254885Sdumbbell case CHIP_RV730: 1593254885Sdumbbell default: 1594254885Sdumbbell db_debug3 |= R700_DB_CLK_OFF_DELAY(2); 1595254885Sdumbbell break; 1596254885Sdumbbell } 1597254885Sdumbbell RADEON_WRITE(R700_DB_DEBUG3, db_debug3); 1598254885Sdumbbell 1599254885Sdumbbell if ((dev_priv->flags & RADEON_FAMILY_MASK) != CHIP_RV770) { 1600254885Sdumbbell db_debug4 = RADEON_READ(RV700_DB_DEBUG4); 1601254885Sdumbbell db_debug4 |= RV700_DISABLE_TILE_COVERED_FOR_PS_ITER; 1602254885Sdumbbell RADEON_WRITE(RV700_DB_DEBUG4, db_debug4); 1603254885Sdumbbell } 1604254885Sdumbbell 1605254885Sdumbbell RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_size / 4) - 1) | 1606254885Sdumbbell R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) | 1607254885Sdumbbell R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1))); 1608254885Sdumbbell 1609254885Sdumbbell RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) | 1610254885Sdumbbell R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) | 1611254885Sdumbbell R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize))); 1612254885Sdumbbell 1613254885Sdumbbell RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 1614254885Sdumbbell 1615254885Sdumbbell RADEON_WRITE(R600_VGT_NUM_INSTANCES, 1); 1616254885Sdumbbell 1617254885Sdumbbell RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0)); 1618254885Sdumbbell 1619254885Sdumbbell RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(4)); 1620254885Sdumbbell 1621254885Sdumbbell RADEON_WRITE(R600_CP_PERFMON_CNTL, 0); 1622254885Sdumbbell 1623254885Sdumbbell sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) | 1624254885Sdumbbell R600_DONE_FIFO_HIWATER(0xe0) | 1625254885Sdumbbell R600_ALU_UPDATE_FIFO_HIWATER(0x8)); 1626254885Sdumbbell switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1627254885Sdumbbell case CHIP_RV770: 1628254885Sdumbbell case CHIP_RV730: 1629254885Sdumbbell case CHIP_RV710: 1630254885Sdumbbell sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x1); 1631254885Sdumbbell break; 1632254885Sdumbbell case CHIP_RV740: 1633254885Sdumbbell default: 1634254885Sdumbbell sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4); 1635254885Sdumbbell break; 1636254885Sdumbbell } 1637254885Sdumbbell RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); 1638254885Sdumbbell 1639254885Sdumbbell /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT 1640254885Sdumbbell * should be adjusted as needed by the 2D/3D drivers. This just sets default values 1641254885Sdumbbell */ 1642254885Sdumbbell sq_config = RADEON_READ(R600_SQ_CONFIG); 1643254885Sdumbbell sq_config &= ~(R600_PS_PRIO(3) | 1644254885Sdumbbell R600_VS_PRIO(3) | 1645254885Sdumbbell R600_GS_PRIO(3) | 1646254885Sdumbbell R600_ES_PRIO(3)); 1647254885Sdumbbell sq_config |= (R600_DX9_CONSTS | 1648254885Sdumbbell R600_VC_ENABLE | 1649254885Sdumbbell R600_EXPORT_SRC_C | 1650254885Sdumbbell R600_PS_PRIO(0) | 1651254885Sdumbbell R600_VS_PRIO(1) | 1652254885Sdumbbell R600_GS_PRIO(2) | 1653254885Sdumbbell R600_ES_PRIO(3)); 1654254885Sdumbbell if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710) 1655254885Sdumbbell /* no vertex cache */ 1656254885Sdumbbell sq_config &= ~R600_VC_ENABLE; 1657254885Sdumbbell 1658254885Sdumbbell RADEON_WRITE(R600_SQ_CONFIG, sq_config); 1659254885Sdumbbell 1660254885Sdumbbell RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) | 1661254885Sdumbbell R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) | 1662254885Sdumbbell R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2))); 1663254885Sdumbbell 1664254885Sdumbbell RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) | 1665254885Sdumbbell R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64))); 1666254885Sdumbbell 1667254885Sdumbbell sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) | 1668254885Sdumbbell R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) | 1669254885Sdumbbell R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8)); 1670254885Sdumbbell if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads) 1671254885Sdumbbell sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads); 1672254885Sdumbbell else 1673254885Sdumbbell sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8); 1674254885Sdumbbell RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); 1675254885Sdumbbell 1676254885Sdumbbell RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) | 1677254885Sdumbbell R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4))); 1678254885Sdumbbell 1679254885Sdumbbell RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) | 1680254885Sdumbbell R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4))); 1681254885Sdumbbell 1682254885Sdumbbell sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) | 1683254885Sdumbbell R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) | 1684254885Sdumbbell R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) | 1685254885Sdumbbell R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64)); 1686254885Sdumbbell 1687254885Sdumbbell RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0); 1688254885Sdumbbell RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0); 1689254885Sdumbbell RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0); 1690254885Sdumbbell RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0); 1691254885Sdumbbell RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0); 1692254885Sdumbbell RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0); 1693254885Sdumbbell RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0); 1694254885Sdumbbell RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0); 1695254885Sdumbbell 1696254885Sdumbbell RADEON_WRITE(R700_PA_SC_FORCE_EOV_MAX_CNTS, (R700_FORCE_EOV_MAX_CLK_CNT(4095) | 1697254885Sdumbbell R700_FORCE_EOV_MAX_REZ_CNT(255))); 1698254885Sdumbbell 1699254885Sdumbbell if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710) 1700254885Sdumbbell RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_TC_ONLY) | 1701254885Sdumbbell R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO))); 1702254885Sdumbbell else 1703254885Sdumbbell RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_VC_AND_TC) | 1704254885Sdumbbell R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO))); 1705254885Sdumbbell 1706254885Sdumbbell switch (dev_priv->flags & RADEON_FAMILY_MASK) { 1707254885Sdumbbell case CHIP_RV770: 1708254885Sdumbbell case CHIP_RV730: 1709254885Sdumbbell case CHIP_RV740: 1710254885Sdumbbell gs_prim_buffer_depth = 384; 1711254885Sdumbbell break; 1712254885Sdumbbell case CHIP_RV710: 1713254885Sdumbbell gs_prim_buffer_depth = 128; 1714254885Sdumbbell break; 1715254885Sdumbbell default: 1716254885Sdumbbell break; 1717254885Sdumbbell } 1718254885Sdumbbell 1719254885Sdumbbell num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16; 1720254885Sdumbbell vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; 1721254885Sdumbbell /* Max value for this is 256 */ 1722254885Sdumbbell if (vgt_gs_per_es > 256) 1723254885Sdumbbell vgt_gs_per_es = 256; 1724254885Sdumbbell 1725254885Sdumbbell RADEON_WRITE(R600_VGT_ES_PER_GS, 128); 1726254885Sdumbbell RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es); 1727254885Sdumbbell RADEON_WRITE(R600_VGT_GS_PER_VS, 2); 1728254885Sdumbbell 1729254885Sdumbbell /* more default values. 2D/3D driver should adjust as needed */ 1730254885Sdumbbell RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16); 1731254885Sdumbbell RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0); 1732254885Sdumbbell RADEON_WRITE(R600_VGT_STRMOUT_EN, 0); 1733254885Sdumbbell RADEON_WRITE(R600_SX_MISC, 0); 1734254885Sdumbbell RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0); 1735254885Sdumbbell RADEON_WRITE(R700_PA_SC_EDGERULE, 0xaaaaaaaa); 1736254885Sdumbbell RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0); 1737254885Sdumbbell RADEON_WRITE(R600_PA_SC_CLIPRECT_RULE, 0xffff); 1738254885Sdumbbell RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0); 1739254885Sdumbbell RADEON_WRITE(R600_SPI_INPUT_Z, 0); 1740254885Sdumbbell RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2)); 1741254885Sdumbbell RADEON_WRITE(R600_CB_COLOR7_FRAG, 0); 1742254885Sdumbbell 1743254885Sdumbbell /* clear render buffer base addresses */ 1744254885Sdumbbell RADEON_WRITE(R600_CB_COLOR0_BASE, 0); 1745254885Sdumbbell RADEON_WRITE(R600_CB_COLOR1_BASE, 0); 1746254885Sdumbbell RADEON_WRITE(R600_CB_COLOR2_BASE, 0); 1747254885Sdumbbell RADEON_WRITE(R600_CB_COLOR3_BASE, 0); 1748254885Sdumbbell RADEON_WRITE(R600_CB_COLOR4_BASE, 0); 1749254885Sdumbbell RADEON_WRITE(R600_CB_COLOR5_BASE, 0); 1750254885Sdumbbell RADEON_WRITE(R600_CB_COLOR6_BASE, 0); 1751254885Sdumbbell RADEON_WRITE(R600_CB_COLOR7_BASE, 0); 1752254885Sdumbbell 1753254885Sdumbbell RADEON_WRITE(R700_TCP_CNTL, 0); 1754254885Sdumbbell 1755254885Sdumbbell hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL); 1756254885Sdumbbell RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1757254885Sdumbbell 1758254885Sdumbbell RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0); 1759254885Sdumbbell 1760254885Sdumbbell RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA | 1761254885Sdumbbell R600_NUM_CLIP_SEQ(3))); 1762254885Sdumbbell 1763254885Sdumbbell} 1764254885Sdumbbell 1765254885Sdumbbellstatic void r600_cp_init_ring_buffer(struct drm_device *dev, 1766254885Sdumbbell drm_radeon_private_t *dev_priv, 1767254885Sdumbbell struct drm_file *file_priv) 1768254885Sdumbbell{ 1769254885Sdumbbell struct drm_radeon_master_private *master_priv; 1770254885Sdumbbell u32 ring_start; 1771254885Sdumbbell u64 rptr_addr; 1772254885Sdumbbell 1773254885Sdumbbell if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) 1774254885Sdumbbell r700_gfx_init(dev, dev_priv); 1775254885Sdumbbell else 1776254885Sdumbbell r600_gfx_init(dev, dev_priv); 1777254885Sdumbbell 1778254885Sdumbbell RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); 1779254885Sdumbbell RADEON_READ(R600_GRBM_SOFT_RESET); 1780254885Sdumbbell DRM_MDELAY(15); 1781254885Sdumbbell RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); 1782254885Sdumbbell 1783254885Sdumbbell 1784254885Sdumbbell /* Set ring buffer size */ 1785254885Sdumbbell#ifdef __BIG_ENDIAN 1786254885Sdumbbell RADEON_WRITE(R600_CP_RB_CNTL, 1787254885Sdumbbell R600_BUF_SWAP_32BIT | 1788254885Sdumbbell R600_RB_NO_UPDATE | 1789254885Sdumbbell (dev_priv->ring.rptr_update_l2qw << 8) | 1790254885Sdumbbell dev_priv->ring.size_l2qw); 1791254885Sdumbbell#else 1792254885Sdumbbell RADEON_WRITE(R600_CP_RB_CNTL, 1793254885Sdumbbell RADEON_RB_NO_UPDATE | 1794254885Sdumbbell (dev_priv->ring.rptr_update_l2qw << 8) | 1795254885Sdumbbell dev_priv->ring.size_l2qw); 1796254885Sdumbbell#endif 1797254885Sdumbbell 1798254885Sdumbbell RADEON_WRITE(R600_CP_SEM_WAIT_TIMER, 0x0); 1799254885Sdumbbell 1800254885Sdumbbell /* Set the write pointer delay */ 1801254885Sdumbbell RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0); 1802254885Sdumbbell 1803254885Sdumbbell#ifdef __BIG_ENDIAN 1804254885Sdumbbell RADEON_WRITE(R600_CP_RB_CNTL, 1805254885Sdumbbell R600_BUF_SWAP_32BIT | 1806254885Sdumbbell R600_RB_NO_UPDATE | 1807254885Sdumbbell R600_RB_RPTR_WR_ENA | 1808254885Sdumbbell (dev_priv->ring.rptr_update_l2qw << 8) | 1809254885Sdumbbell dev_priv->ring.size_l2qw); 1810254885Sdumbbell#else 1811254885Sdumbbell RADEON_WRITE(R600_CP_RB_CNTL, 1812254885Sdumbbell R600_RB_NO_UPDATE | 1813254885Sdumbbell R600_RB_RPTR_WR_ENA | 1814254885Sdumbbell (dev_priv->ring.rptr_update_l2qw << 8) | 1815254885Sdumbbell dev_priv->ring.size_l2qw); 1816254885Sdumbbell#endif 1817254885Sdumbbell 1818254885Sdumbbell /* Initialize the ring buffer's read and write pointers */ 1819254885Sdumbbell RADEON_WRITE(R600_CP_RB_RPTR_WR, 0); 1820254885Sdumbbell RADEON_WRITE(R600_CP_RB_WPTR, 0); 1821254885Sdumbbell SET_RING_HEAD(dev_priv, 0); 1822254885Sdumbbell dev_priv->ring.tail = 0; 1823254885Sdumbbell 1824254885Sdumbbell#if __OS_HAS_AGP 1825254885Sdumbbell if (dev_priv->flags & RADEON_IS_AGP) { 1826254885Sdumbbell rptr_addr = dev_priv->ring_rptr->offset 1827254885Sdumbbell - dev->agp->base + 1828254885Sdumbbell dev_priv->gart_vm_start; 1829254885Sdumbbell } else 1830254885Sdumbbell#endif 1831254885Sdumbbell { 1832254885Sdumbbell rptr_addr = dev_priv->ring_rptr->offset 1833254885Sdumbbell - ((unsigned long) dev->sg->vaddr) 1834254885Sdumbbell + dev_priv->gart_vm_start; 1835254885Sdumbbell } 1836254885Sdumbbell RADEON_WRITE(R600_CP_RB_RPTR_ADDR, (rptr_addr & 0xfffffffc)); 1837254885Sdumbbell RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI, upper_32_bits(rptr_addr)); 1838254885Sdumbbell 1839254885Sdumbbell#ifdef __BIG_ENDIAN 1840254885Sdumbbell RADEON_WRITE(R600_CP_RB_CNTL, 1841254885Sdumbbell RADEON_BUF_SWAP_32BIT | 1842254885Sdumbbell (dev_priv->ring.rptr_update_l2qw << 8) | 1843254885Sdumbbell dev_priv->ring.size_l2qw); 1844254885Sdumbbell#else 1845254885Sdumbbell RADEON_WRITE(R600_CP_RB_CNTL, 1846254885Sdumbbell (dev_priv->ring.rptr_update_l2qw << 8) | 1847254885Sdumbbell dev_priv->ring.size_l2qw); 1848254885Sdumbbell#endif 1849254885Sdumbbell 1850254885Sdumbbell#if __OS_HAS_AGP 1851254885Sdumbbell if (dev_priv->flags & RADEON_IS_AGP) { 1852254885Sdumbbell /* XXX */ 1853254885Sdumbbell radeon_write_agp_base(dev_priv, dev->agp->base); 1854254885Sdumbbell 1855254885Sdumbbell /* XXX */ 1856254885Sdumbbell radeon_write_agp_location(dev_priv, 1857254885Sdumbbell (((dev_priv->gart_vm_start - 1 + 1858254885Sdumbbell dev_priv->gart_size) & 0xffff0000) | 1859254885Sdumbbell (dev_priv->gart_vm_start >> 16))); 1860254885Sdumbbell 1861254885Sdumbbell ring_start = (dev_priv->cp_ring->offset 1862254885Sdumbbell - dev->agp->base 1863254885Sdumbbell + dev_priv->gart_vm_start); 1864254885Sdumbbell } else 1865254885Sdumbbell#endif 1866254885Sdumbbell ring_start = (dev_priv->cp_ring->offset 1867254885Sdumbbell - (unsigned long)dev->sg->vaddr> 1868254885Sdumbbell + dev_priv->gart_vm_start); 1869254885Sdumbbell 1870254885Sdumbbell RADEON_WRITE(R600_CP_RB_BASE, ring_start >> 8); 1871254885Sdumbbell 1872254885Sdumbbell RADEON_WRITE(R600_CP_ME_CNTL, 0xff); 1873254885Sdumbbell 1874254885Sdumbbell RADEON_WRITE(R600_CP_DEBUG, (1 << 27) | (1 << 28)); 1875254885Sdumbbell 1876254885Sdumbbell /* Initialize the scratch register pointer. This will cause 1877254885Sdumbbell * the scratch register values to be written out to memory 1878254885Sdumbbell * whenever they are updated. 1879254885Sdumbbell * 1880254885Sdumbbell * We simply put this behind the ring read pointer, this works 1881254885Sdumbbell * with PCI GART as well as (whatever kind of) AGP GART 1882254885Sdumbbell */ 1883254885Sdumbbell { 1884254885Sdumbbell u64 scratch_addr; 1885254885Sdumbbell 1886254885Sdumbbell scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR) & 0xFFFFFFFC; 1887254885Sdumbbell scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32; 1888254885Sdumbbell scratch_addr += R600_SCRATCH_REG_OFFSET; 1889254885Sdumbbell scratch_addr >>= 8; 1890254885Sdumbbell scratch_addr &= 0xffffffff; 1891254885Sdumbbell 1892254885Sdumbbell RADEON_WRITE(R600_SCRATCH_ADDR, (uint32_t)scratch_addr); 1893254885Sdumbbell } 1894254885Sdumbbell 1895254885Sdumbbell RADEON_WRITE(R600_SCRATCH_UMSK, 0x7); 1896254885Sdumbbell 1897254885Sdumbbell /* Turn on bus mastering */ 1898254885Sdumbbell radeon_enable_bm(dev_priv); 1899254885Sdumbbell 1900254885Sdumbbell radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(0), 0); 1901254885Sdumbbell RADEON_WRITE(R600_LAST_FRAME_REG, 0); 1902254885Sdumbbell 1903254885Sdumbbell radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0); 1904254885Sdumbbell RADEON_WRITE(R600_LAST_DISPATCH_REG, 0); 1905254885Sdumbbell 1906254885Sdumbbell radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(2), 0); 1907254885Sdumbbell RADEON_WRITE(R600_LAST_CLEAR_REG, 0); 1908254885Sdumbbell 1909254885Sdumbbell /* reset sarea copies of these */ 1910254885Sdumbbell master_priv = file_priv->masterp->driver_priv; 1911254885Sdumbbell if (master_priv->sarea_priv) { 1912254885Sdumbbell master_priv->sarea_priv->last_frame = 0; 1913254885Sdumbbell master_priv->sarea_priv->last_dispatch = 0; 1914254885Sdumbbell master_priv->sarea_priv->last_clear = 0; 1915254885Sdumbbell } 1916254885Sdumbbell 1917254885Sdumbbell r600_do_wait_for_idle(dev_priv); 1918254885Sdumbbell 1919254885Sdumbbell} 1920254885Sdumbbell 1921254885Sdumbbellint r600_do_cleanup_cp(struct drm_device *dev) 1922254885Sdumbbell{ 1923254885Sdumbbell drm_radeon_private_t *dev_priv = dev->dev_private; 1924254885Sdumbbell DRM_DEBUG("\n"); 1925254885Sdumbbell 1926254885Sdumbbell /* Make sure interrupts are disabled here because the uninstall ioctl 1927254885Sdumbbell * may not have been called from userspace and after dev_private 1928254885Sdumbbell * is freed, it's too late. 1929254885Sdumbbell */ 1930254885Sdumbbell if (dev->irq_enabled) 1931254885Sdumbbell drm_irq_uninstall(dev); 1932254885Sdumbbell 1933254885Sdumbbell#if __OS_HAS_AGP 1934254885Sdumbbell if (dev_priv->flags & RADEON_IS_AGP) { 1935254885Sdumbbell if (dev_priv->cp_ring != NULL) { 1936254885Sdumbbell drm_core_ioremapfree(dev_priv->cp_ring, dev); 1937254885Sdumbbell dev_priv->cp_ring = NULL; 1938254885Sdumbbell } 1939254885Sdumbbell if (dev_priv->ring_rptr != NULL) { 1940254885Sdumbbell drm_core_ioremapfree(dev_priv->ring_rptr, dev); 1941254885Sdumbbell dev_priv->ring_rptr = NULL; 1942254885Sdumbbell } 1943254885Sdumbbell if (dev->agp_buffer_map != NULL) { 1944254885Sdumbbell drm_core_ioremapfree(dev->agp_buffer_map, dev); 1945254885Sdumbbell dev->agp_buffer_map = NULL; 1946254885Sdumbbell } 1947254885Sdumbbell } else 1948254885Sdumbbell#endif 1949254885Sdumbbell { 1950254885Sdumbbell 1951254885Sdumbbell if (dev_priv->gart_info.bus_addr) 1952254885Sdumbbell r600_page_table_cleanup(dev, &dev_priv->gart_info); 1953254885Sdumbbell 1954254885Sdumbbell if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) { 1955254885Sdumbbell drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev); 1956254885Sdumbbell dev_priv->gart_info.addr = NULL; 1957254885Sdumbbell } 1958254885Sdumbbell } 1959254885Sdumbbell /* only clear to the start of flags */ 1960254885Sdumbbell memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags)); 1961254885Sdumbbell 1962254885Sdumbbell return 0; 1963254885Sdumbbell} 1964254885Sdumbbell 1965254885Sdumbbellint r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init, 1966254885Sdumbbell struct drm_file *file_priv) 1967254885Sdumbbell{ 1968254885Sdumbbell drm_radeon_private_t *dev_priv = dev->dev_private; 1969254885Sdumbbell struct drm_radeon_master_private *master_priv = file_priv->masterp->driver_priv; 1970254885Sdumbbell 1971254885Sdumbbell DRM_DEBUG("\n"); 1972254885Sdumbbell 1973254885Sdumbbell sx_init(&dev_priv->cs_mutex, "drm__radeon_private__cs_mutex"); 1974254885Sdumbbell r600_cs_legacy_init(); 1975254885Sdumbbell /* if we require new memory map but we don't have it fail */ 1976254885Sdumbbell if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) { 1977254885Sdumbbell DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n"); 1978254885Sdumbbell r600_do_cleanup_cp(dev); 1979254885Sdumbbell return -EINVAL; 1980254885Sdumbbell } 1981254885Sdumbbell 1982254885Sdumbbell if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) { 1983254885Sdumbbell DRM_DEBUG("Forcing AGP card to PCI mode\n"); 1984254885Sdumbbell dev_priv->flags &= ~RADEON_IS_AGP; 1985254885Sdumbbell /* The writeback test succeeds, but when writeback is enabled, 1986254885Sdumbbell * the ring buffer read ptr update fails after first 128 bytes. 1987254885Sdumbbell */ 1988254885Sdumbbell radeon_no_wb = 1; 1989254885Sdumbbell } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE)) 1990254885Sdumbbell && !init->is_pci) { 1991254885Sdumbbell DRM_DEBUG("Restoring AGP flag\n"); 1992254885Sdumbbell dev_priv->flags |= RADEON_IS_AGP; 1993254885Sdumbbell } 1994254885Sdumbbell 1995254885Sdumbbell dev_priv->usec_timeout = init->usec_timeout; 1996254885Sdumbbell if (dev_priv->usec_timeout < 1 || 1997254885Sdumbbell dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) { 1998254885Sdumbbell DRM_DEBUG("TIMEOUT problem!\n"); 1999254885Sdumbbell r600_do_cleanup_cp(dev); 2000254885Sdumbbell return -EINVAL; 2001254885Sdumbbell } 2002254885Sdumbbell 2003254885Sdumbbell /* Enable vblank on CRTC1 for older X servers 2004254885Sdumbbell */ 2005254885Sdumbbell dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1; 2006254885Sdumbbell dev_priv->do_boxes = 0; 2007254885Sdumbbell dev_priv->cp_mode = init->cp_mode; 2008254885Sdumbbell 2009254885Sdumbbell /* We don't support anything other than bus-mastering ring mode, 2010254885Sdumbbell * but the ring can be in either AGP or PCI space for the ring 2011254885Sdumbbell * read pointer. 2012254885Sdumbbell */ 2013254885Sdumbbell if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) && 2014254885Sdumbbell (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) { 2015254885Sdumbbell DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode); 2016254885Sdumbbell r600_do_cleanup_cp(dev); 2017254885Sdumbbell return -EINVAL; 2018254885Sdumbbell } 2019254885Sdumbbell 2020254885Sdumbbell switch (init->fb_bpp) { 2021254885Sdumbbell case 16: 2022254885Sdumbbell dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565; 2023254885Sdumbbell break; 2024254885Sdumbbell case 32: 2025254885Sdumbbell default: 2026254885Sdumbbell dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888; 2027254885Sdumbbell break; 2028254885Sdumbbell } 2029254885Sdumbbell dev_priv->front_offset = init->front_offset; 2030254885Sdumbbell dev_priv->front_pitch = init->front_pitch; 2031254885Sdumbbell dev_priv->back_offset = init->back_offset; 2032254885Sdumbbell dev_priv->back_pitch = init->back_pitch; 2033254885Sdumbbell 2034254885Sdumbbell dev_priv->ring_offset = init->ring_offset; 2035254885Sdumbbell dev_priv->ring_rptr_offset = init->ring_rptr_offset; 2036254885Sdumbbell dev_priv->buffers_offset = init->buffers_offset; 2037254885Sdumbbell dev_priv->gart_textures_offset = init->gart_textures_offset; 2038254885Sdumbbell 2039254885Sdumbbell master_priv->sarea = drm_getsarea(dev); 2040254885Sdumbbell if (!master_priv->sarea) { 2041254885Sdumbbell DRM_ERROR("could not find sarea!\n"); 2042254885Sdumbbell r600_do_cleanup_cp(dev); 2043254885Sdumbbell return -EINVAL; 2044254885Sdumbbell } 2045254885Sdumbbell 2046254885Sdumbbell dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset); 2047254885Sdumbbell if (!dev_priv->cp_ring) { 2048254885Sdumbbell DRM_ERROR("could not find cp ring region!\n"); 2049254885Sdumbbell r600_do_cleanup_cp(dev); 2050254885Sdumbbell return -EINVAL; 2051254885Sdumbbell } 2052254885Sdumbbell dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset); 2053254885Sdumbbell if (!dev_priv->ring_rptr) { 2054254885Sdumbbell DRM_ERROR("could not find ring read pointer!\n"); 2055254885Sdumbbell r600_do_cleanup_cp(dev); 2056254885Sdumbbell return -EINVAL; 2057254885Sdumbbell } 2058254885Sdumbbell dev->agp_buffer_token = init->buffers_offset; 2059254885Sdumbbell dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset); 2060254885Sdumbbell if (!dev->agp_buffer_map) { 2061254885Sdumbbell DRM_ERROR("could not find dma buffer region!\n"); 2062254885Sdumbbell r600_do_cleanup_cp(dev); 2063254885Sdumbbell return -EINVAL; 2064254885Sdumbbell } 2065254885Sdumbbell 2066254885Sdumbbell if (init->gart_textures_offset) { 2067254885Sdumbbell dev_priv->gart_textures = 2068254885Sdumbbell drm_core_findmap(dev, init->gart_textures_offset); 2069254885Sdumbbell if (!dev_priv->gart_textures) { 2070254885Sdumbbell DRM_ERROR("could not find GART texture region!\n"); 2071254885Sdumbbell r600_do_cleanup_cp(dev); 2072254885Sdumbbell return -EINVAL; 2073254885Sdumbbell } 2074254885Sdumbbell } 2075254885Sdumbbell 2076254885Sdumbbell#if __OS_HAS_AGP 2077254885Sdumbbell /* XXX */ 2078254885Sdumbbell if (dev_priv->flags & RADEON_IS_AGP) { 2079254885Sdumbbell drm_core_ioremap_wc(dev_priv->cp_ring, dev); 2080254885Sdumbbell drm_core_ioremap_wc(dev_priv->ring_rptr, dev); 2081254885Sdumbbell drm_core_ioremap_wc(dev->agp_buffer_map, dev); 2082254885Sdumbbell if (!dev_priv->cp_ring->handle || 2083254885Sdumbbell !dev_priv->ring_rptr->handle || 2084254885Sdumbbell !dev->agp_buffer_map->handle) { 2085254885Sdumbbell DRM_ERROR("could not find ioremap agp regions!\n"); 2086254885Sdumbbell r600_do_cleanup_cp(dev); 2087254885Sdumbbell return -EINVAL; 2088254885Sdumbbell } 2089254885Sdumbbell } else 2090254885Sdumbbell#endif 2091254885Sdumbbell { 2092254885Sdumbbell dev_priv->cp_ring->handle = (void *)(unsigned long)dev_priv->cp_ring->offset; 2093254885Sdumbbell dev_priv->ring_rptr->handle = 2094254885Sdumbbell (void *)(unsigned long)dev_priv->ring_rptr->offset; 2095254885Sdumbbell dev->agp_buffer_map->handle = 2096254885Sdumbbell (void *)(unsigned long)dev->agp_buffer_map->offset; 2097254885Sdumbbell 2098254885Sdumbbell DRM_DEBUG("dev_priv->cp_ring->handle %p\n", 2099254885Sdumbbell dev_priv->cp_ring->handle); 2100254885Sdumbbell DRM_DEBUG("dev_priv->ring_rptr->handle %p\n", 2101254885Sdumbbell dev_priv->ring_rptr->handle); 2102254885Sdumbbell DRM_DEBUG("dev->agp_buffer_map->handle %p\n", 2103254885Sdumbbell dev->agp_buffer_map->handle); 2104254885Sdumbbell } 2105254885Sdumbbell 2106254885Sdumbbell dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24; 2107254885Sdumbbell dev_priv->fb_size = 2108254885Sdumbbell (((radeon_read_fb_location(dev_priv) & 0xffff0000u) << 8) + 0x1000000) 2109254885Sdumbbell - dev_priv->fb_location; 2110254885Sdumbbell 2111254885Sdumbbell dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) | 2112254885Sdumbbell ((dev_priv->front_offset 2113254885Sdumbbell + dev_priv->fb_location) >> 10)); 2114254885Sdumbbell 2115254885Sdumbbell dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) | 2116254885Sdumbbell ((dev_priv->back_offset 2117254885Sdumbbell + dev_priv->fb_location) >> 10)); 2118254885Sdumbbell 2119254885Sdumbbell dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) | 2120254885Sdumbbell ((dev_priv->depth_offset 2121254885Sdumbbell + dev_priv->fb_location) >> 10)); 2122254885Sdumbbell 2123254885Sdumbbell dev_priv->gart_size = init->gart_size; 2124254885Sdumbbell 2125254885Sdumbbell /* New let's set the memory map ... */ 2126254885Sdumbbell if (dev_priv->new_memmap) { 2127254885Sdumbbell u32 base = 0; 2128254885Sdumbbell 2129254885Sdumbbell DRM_INFO("Setting GART location based on new memory map\n"); 2130254885Sdumbbell 2131254885Sdumbbell /* If using AGP, try to locate the AGP aperture at the same 2132254885Sdumbbell * location in the card and on the bus, though we have to 2133254885Sdumbbell * align it down. 2134254885Sdumbbell */ 2135254885Sdumbbell#if __OS_HAS_AGP 2136254885Sdumbbell /* XXX */ 2137254885Sdumbbell if (dev_priv->flags & RADEON_IS_AGP) { 2138254885Sdumbbell base = dev->agp->base; 2139254885Sdumbbell /* Check if valid */ 2140254885Sdumbbell if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location && 2141254885Sdumbbell base < (dev_priv->fb_location + dev_priv->fb_size - 1)) { 2142254885Sdumbbell DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n", 2143254885Sdumbbell dev->agp->base); 2144254885Sdumbbell base = 0; 2145254885Sdumbbell } 2146254885Sdumbbell } 2147254885Sdumbbell#endif 2148254885Sdumbbell /* If not or if AGP is at 0 (Macs), try to put it elsewhere */ 2149254885Sdumbbell if (base == 0) { 2150254885Sdumbbell base = dev_priv->fb_location + dev_priv->fb_size; 2151254885Sdumbbell if (base < dev_priv->fb_location || 2152254885Sdumbbell ((base + dev_priv->gart_size) & 0xfffffffful) < base) 2153254885Sdumbbell base = dev_priv->fb_location 2154254885Sdumbbell - dev_priv->gart_size; 2155254885Sdumbbell } 2156254885Sdumbbell dev_priv->gart_vm_start = base & 0xffc00000u; 2157254885Sdumbbell if (dev_priv->gart_vm_start != base) 2158254885Sdumbbell DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n", 2159254885Sdumbbell base, dev_priv->gart_vm_start); 2160254885Sdumbbell } 2161254885Sdumbbell 2162254885Sdumbbell#if __OS_HAS_AGP 2163254885Sdumbbell /* XXX */ 2164254885Sdumbbell if (dev_priv->flags & RADEON_IS_AGP) 2165254885Sdumbbell dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 2166254885Sdumbbell - dev->agp->base 2167254885Sdumbbell + dev_priv->gart_vm_start); 2168254885Sdumbbell else 2169254885Sdumbbell#endif 2170254885Sdumbbell dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset 2171254885Sdumbbell - (unsigned long)dev->sg->vaddr 2172254885Sdumbbell + dev_priv->gart_vm_start); 2173254885Sdumbbell 2174254885Sdumbbell DRM_DEBUG("fb 0x%08x size %d\n", 2175254885Sdumbbell (unsigned int) dev_priv->fb_location, 2176254885Sdumbbell (unsigned int) dev_priv->fb_size); 2177254885Sdumbbell DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size); 2178254885Sdumbbell DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n", 2179254885Sdumbbell (unsigned int) dev_priv->gart_vm_start); 2180254885Sdumbbell DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n", 2181254885Sdumbbell dev_priv->gart_buffers_offset); 2182254885Sdumbbell 2183254885Sdumbbell dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle; 2184254885Sdumbbell dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle 2185254885Sdumbbell + init->ring_size / sizeof(u32)); 2186254885Sdumbbell dev_priv->ring.size = init->ring_size; 2187254885Sdumbbell dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8); 2188254885Sdumbbell 2189254885Sdumbbell dev_priv->ring.rptr_update = /* init->rptr_update */ 4096; 2190254885Sdumbbell dev_priv->ring.rptr_update_l2qw = drm_order(/* init->rptr_update */ 4096 / 8); 2191254885Sdumbbell 2192254885Sdumbbell dev_priv->ring.fetch_size = /* init->fetch_size */ 32; 2193254885Sdumbbell dev_priv->ring.fetch_size_l2ow = drm_order(/* init->fetch_size */ 32 / 16); 2194254885Sdumbbell 2195254885Sdumbbell dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1; 2196254885Sdumbbell 2197254885Sdumbbell dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; 2198254885Sdumbbell 2199254885Sdumbbell#if __OS_HAS_AGP 2200254885Sdumbbell if (dev_priv->flags & RADEON_IS_AGP) { 2201254885Sdumbbell /* XXX turn off pcie gart */ 2202254885Sdumbbell } else 2203254885Sdumbbell#endif 2204254885Sdumbbell { 2205254885Sdumbbell dev_priv->gart_info.table_mask = DMA_BIT_MASK(32); 2206254885Sdumbbell /* if we have an offset set from userspace */ 2207254885Sdumbbell if (!dev_priv->pcigart_offset_set) { 2208254885Sdumbbell DRM_ERROR("Need gart offset from userspace\n"); 2209254885Sdumbbell r600_do_cleanup_cp(dev); 2210254885Sdumbbell return -EINVAL; 2211254885Sdumbbell } 2212254885Sdumbbell 2213254885Sdumbbell DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset); 2214254885Sdumbbell 2215254885Sdumbbell dev_priv->gart_info.bus_addr = 2216254885Sdumbbell dev_priv->pcigart_offset + dev_priv->fb_location; 2217254885Sdumbbell dev_priv->gart_info.mapping.offset = 2218254885Sdumbbell dev_priv->pcigart_offset + dev_priv->fb_aper_offset; 2219254885Sdumbbell dev_priv->gart_info.mapping.size = 2220254885Sdumbbell dev_priv->gart_info.table_size; 2221254885Sdumbbell 2222254885Sdumbbell drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev); 2223254885Sdumbbell if (!dev_priv->gart_info.mapping.handle) { 2224254885Sdumbbell DRM_ERROR("ioremap failed.\n"); 2225254885Sdumbbell r600_do_cleanup_cp(dev); 2226254885Sdumbbell return -EINVAL; 2227254885Sdumbbell } 2228254885Sdumbbell 2229254885Sdumbbell dev_priv->gart_info.addr = 2230254885Sdumbbell dev_priv->gart_info.mapping.handle; 2231254885Sdumbbell 2232254885Sdumbbell DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n", 2233254885Sdumbbell dev_priv->gart_info.addr, 2234254885Sdumbbell dev_priv->pcigart_offset); 2235254885Sdumbbell 2236254885Sdumbbell if (!r600_page_table_init(dev)) { 2237254885Sdumbbell DRM_ERROR("Failed to init GART table\n"); 2238254885Sdumbbell r600_do_cleanup_cp(dev); 2239254885Sdumbbell return -EINVAL; 2240254885Sdumbbell } 2241254885Sdumbbell 2242254885Sdumbbell if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) 2243254885Sdumbbell r700_vm_init(dev); 2244254885Sdumbbell else 2245254885Sdumbbell r600_vm_init(dev); 2246254885Sdumbbell } 2247254885Sdumbbell 2248254885Sdumbbell if (!dev_priv->me_fw || !dev_priv->pfp_fw) { 2249254885Sdumbbell int err = r600_cp_init_microcode(dev_priv); 2250254885Sdumbbell if (err) { 2251254885Sdumbbell DRM_ERROR("Failed to load firmware!\n"); 2252254885Sdumbbell r600_do_cleanup_cp(dev); 2253254885Sdumbbell return err; 2254254885Sdumbbell } 2255254885Sdumbbell } 2256254885Sdumbbell if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) 2257254885Sdumbbell r700_cp_load_microcode(dev_priv); 2258254885Sdumbbell else 2259254885Sdumbbell r600_cp_load_microcode(dev_priv); 2260254885Sdumbbell 2261254885Sdumbbell r600_cp_init_ring_buffer(dev, dev_priv, file_priv); 2262254885Sdumbbell 2263254885Sdumbbell dev_priv->last_buf = 0; 2264254885Sdumbbell 2265254885Sdumbbell r600_do_engine_reset(dev); 2266254885Sdumbbell r600_test_writeback(dev_priv); 2267254885Sdumbbell 2268254885Sdumbbell return 0; 2269254885Sdumbbell} 2270254885Sdumbbell 2271254885Sdumbbellint r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv) 2272254885Sdumbbell{ 2273254885Sdumbbell drm_radeon_private_t *dev_priv = dev->dev_private; 2274254885Sdumbbell 2275254885Sdumbbell DRM_DEBUG("\n"); 2276254885Sdumbbell if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) { 2277254885Sdumbbell r700_vm_init(dev); 2278254885Sdumbbell r700_cp_load_microcode(dev_priv); 2279254885Sdumbbell } else { 2280254885Sdumbbell r600_vm_init(dev); 2281254885Sdumbbell r600_cp_load_microcode(dev_priv); 2282254885Sdumbbell } 2283254885Sdumbbell r600_cp_init_ring_buffer(dev, dev_priv, file_priv); 2284254885Sdumbbell r600_do_engine_reset(dev); 2285254885Sdumbbell 2286254885Sdumbbell return 0; 2287254885Sdumbbell} 2288254885Sdumbbell 2289254885Sdumbbell/* Wait for the CP to go idle. 2290254885Sdumbbell */ 2291254885Sdumbbellint r600_do_cp_idle(drm_radeon_private_t *dev_priv) 2292254885Sdumbbell{ 2293254885Sdumbbell RING_LOCALS; 2294254885Sdumbbell DRM_DEBUG("\n"); 2295254885Sdumbbell 2296254885Sdumbbell BEGIN_RING(5); 2297254885Sdumbbell OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0)); 2298254885Sdumbbell OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT); 2299254885Sdumbbell /* wait for 3D idle clean */ 2300254885Sdumbbell OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); 2301254885Sdumbbell OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2); 2302254885Sdumbbell OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN); 2303254885Sdumbbell 2304254885Sdumbbell ADVANCE_RING(); 2305254885Sdumbbell COMMIT_RING(); 2306254885Sdumbbell 2307254885Sdumbbell return r600_do_wait_for_idle(dev_priv); 2308254885Sdumbbell} 2309254885Sdumbbell 2310254885Sdumbbell/* Start the Command Processor. 2311254885Sdumbbell */ 2312254885Sdumbbellvoid r600_do_cp_start(drm_radeon_private_t *dev_priv) 2313254885Sdumbbell{ 2314254885Sdumbbell u32 cp_me; 2315254885Sdumbbell RING_LOCALS; 2316254885Sdumbbell DRM_DEBUG("\n"); 2317254885Sdumbbell 2318254885Sdumbbell BEGIN_RING(7); 2319254885Sdumbbell OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5)); 2320254885Sdumbbell OUT_RING(0x00000001); 2321254885Sdumbbell if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770)) 2322254885Sdumbbell OUT_RING(0x00000003); 2323254885Sdumbbell else 2324254885Sdumbbell OUT_RING(0x00000000); 2325254885Sdumbbell OUT_RING((dev_priv->r600_max_hw_contexts - 1)); 2326254885Sdumbbell OUT_RING(R600_ME_INITIALIZE_DEVICE_ID(1)); 2327254885Sdumbbell OUT_RING(0x00000000); 2328254885Sdumbbell OUT_RING(0x00000000); 2329254885Sdumbbell ADVANCE_RING(); 2330254885Sdumbbell COMMIT_RING(); 2331254885Sdumbbell 2332254885Sdumbbell /* set the mux and reset the halt bit */ 2333254885Sdumbbell cp_me = 0xff; 2334254885Sdumbbell RADEON_WRITE(R600_CP_ME_CNTL, cp_me); 2335254885Sdumbbell 2336254885Sdumbbell dev_priv->cp_running = 1; 2337254885Sdumbbell 2338254885Sdumbbell} 2339254885Sdumbbell 2340254885Sdumbbellvoid r600_do_cp_reset(drm_radeon_private_t *dev_priv) 2341254885Sdumbbell{ 2342254885Sdumbbell u32 cur_read_ptr; 2343254885Sdumbbell DRM_DEBUG("\n"); 2344254885Sdumbbell 2345254885Sdumbbell cur_read_ptr = RADEON_READ(R600_CP_RB_RPTR); 2346254885Sdumbbell RADEON_WRITE(R600_CP_RB_WPTR, cur_read_ptr); 2347254885Sdumbbell SET_RING_HEAD(dev_priv, cur_read_ptr); 2348254885Sdumbbell dev_priv->ring.tail = cur_read_ptr; 2349254885Sdumbbell} 2350254885Sdumbbell 2351254885Sdumbbellvoid r600_do_cp_stop(drm_radeon_private_t *dev_priv) 2352254885Sdumbbell{ 2353254885Sdumbbell uint32_t cp_me; 2354254885Sdumbbell 2355254885Sdumbbell DRM_DEBUG("\n"); 2356254885Sdumbbell 2357254885Sdumbbell cp_me = 0xff | R600_CP_ME_HALT; 2358254885Sdumbbell 2359254885Sdumbbell RADEON_WRITE(R600_CP_ME_CNTL, cp_me); 2360254885Sdumbbell 2361254885Sdumbbell dev_priv->cp_running = 0; 2362254885Sdumbbell} 2363254885Sdumbbell 2364254885Sdumbbellint r600_cp_dispatch_indirect(struct drm_device *dev, 2365254885Sdumbbell struct drm_buf *buf, int start, int end) 2366254885Sdumbbell{ 2367254885Sdumbbell drm_radeon_private_t *dev_priv = dev->dev_private; 2368254885Sdumbbell RING_LOCALS; 2369254885Sdumbbell 2370254885Sdumbbell if (start != end) { 2371254885Sdumbbell unsigned long offset = (dev_priv->gart_buffers_offset 2372254885Sdumbbell + buf->offset + start); 2373254885Sdumbbell int dwords = (end - start + 3) / sizeof(u32); 2374254885Sdumbbell 2375254885Sdumbbell DRM_DEBUG("dwords:%d\n", dwords); 2376254885Sdumbbell DRM_DEBUG("offset 0x%lx\n", offset); 2377254885Sdumbbell 2378254885Sdumbbell 2379254885Sdumbbell /* Indirect buffer data must be a multiple of 16 dwords. 2380254885Sdumbbell * pad the data with a Type-2 CP packet. 2381254885Sdumbbell */ 2382254885Sdumbbell while (dwords & 0xf) { 2383254885Sdumbbell u32 *data = (u32 *) 2384254885Sdumbbell ((char *)dev->agp_buffer_map->handle 2385254885Sdumbbell + buf->offset + start); 2386254885Sdumbbell data[dwords++] = RADEON_CP_PACKET2; 2387254885Sdumbbell } 2388254885Sdumbbell 2389254885Sdumbbell /* Fire off the indirect buffer */ 2390254885Sdumbbell BEGIN_RING(4); 2391254885Sdumbbell OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER, 2)); 2392254885Sdumbbell OUT_RING((offset & 0xfffffffc)); 2393254885Sdumbbell OUT_RING((upper_32_bits(offset) & 0xff)); 2394254885Sdumbbell OUT_RING(dwords); 2395254885Sdumbbell ADVANCE_RING(); 2396254885Sdumbbell } 2397254885Sdumbbell 2398254885Sdumbbell return 0; 2399254885Sdumbbell} 2400254885Sdumbbell 2401254885Sdumbbellvoid r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv) 2402254885Sdumbbell{ 2403254885Sdumbbell drm_radeon_private_t *dev_priv = dev->dev_private; 2404254885Sdumbbell struct drm_master *master = file_priv->masterp; 2405254885Sdumbbell struct drm_radeon_master_private *master_priv = master->driver_priv; 2406254885Sdumbbell drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv; 2407254885Sdumbbell int nbox = sarea_priv->nbox; 2408254885Sdumbbell struct drm_clip_rect *pbox = sarea_priv->boxes; 2409254885Sdumbbell int i, cpp, src_pitch, dst_pitch; 2410254885Sdumbbell uint64_t src, dst; 2411254885Sdumbbell RING_LOCALS; 2412254885Sdumbbell DRM_DEBUG("\n"); 2413254885Sdumbbell 2414254885Sdumbbell if (dev_priv->color_fmt == RADEON_COLOR_FORMAT_ARGB8888) 2415254885Sdumbbell cpp = 4; 2416254885Sdumbbell else 2417254885Sdumbbell cpp = 2; 2418254885Sdumbbell 2419254885Sdumbbell if (sarea_priv->pfCurrentPage == 0) { 2420254885Sdumbbell src_pitch = dev_priv->back_pitch; 2421254885Sdumbbell dst_pitch = dev_priv->front_pitch; 2422254885Sdumbbell src = dev_priv->back_offset + dev_priv->fb_location; 2423254885Sdumbbell dst = dev_priv->front_offset + dev_priv->fb_location; 2424254885Sdumbbell } else { 2425254885Sdumbbell src_pitch = dev_priv->front_pitch; 2426254885Sdumbbell dst_pitch = dev_priv->back_pitch; 2427254885Sdumbbell src = dev_priv->front_offset + dev_priv->fb_location; 2428254885Sdumbbell dst = dev_priv->back_offset + dev_priv->fb_location; 2429254885Sdumbbell } 2430254885Sdumbbell 2431254885Sdumbbell if (r600_prepare_blit_copy(dev, file_priv)) { 2432254885Sdumbbell DRM_ERROR("unable to allocate vertex buffer for swap buffer\n"); 2433254885Sdumbbell return; 2434254885Sdumbbell } 2435254885Sdumbbell for (i = 0; i < nbox; i++) { 2436254885Sdumbbell int x = pbox[i].x1; 2437254885Sdumbbell int y = pbox[i].y1; 2438254885Sdumbbell int w = pbox[i].x2 - x; 2439254885Sdumbbell int h = pbox[i].y2 - y; 2440254885Sdumbbell 2441254885Sdumbbell DRM_DEBUG("%d,%d-%d,%d\n", x, y, w, h); 2442254885Sdumbbell 2443254885Sdumbbell r600_blit_swap(dev, 2444254885Sdumbbell src, dst, 2445254885Sdumbbell x, y, x, y, w, h, 2446254885Sdumbbell src_pitch, dst_pitch, cpp); 2447254885Sdumbbell } 2448254885Sdumbbell r600_done_blit_copy(dev); 2449254885Sdumbbell 2450254885Sdumbbell /* Increment the frame counter. The client-side 3D driver must 2451254885Sdumbbell * throttle the framerate by waiting for this value before 2452254885Sdumbbell * performing the swapbuffer ioctl. 2453254885Sdumbbell */ 2454254885Sdumbbell sarea_priv->last_frame++; 2455254885Sdumbbell 2456254885Sdumbbell BEGIN_RING(3); 2457254885Sdumbbell R600_FRAME_AGE(sarea_priv->last_frame); 2458254885Sdumbbell ADVANCE_RING(); 2459254885Sdumbbell} 2460254885Sdumbbell 2461254885Sdumbbellint r600_cp_dispatch_texture(struct drm_device *dev, 2462254885Sdumbbell struct drm_file *file_priv, 2463254885Sdumbbell drm_radeon_texture_t *tex, 2464254885Sdumbbell drm_radeon_tex_image_t *image) 2465254885Sdumbbell{ 2466254885Sdumbbell drm_radeon_private_t *dev_priv = dev->dev_private; 2467254885Sdumbbell struct drm_buf *buf; 2468254885Sdumbbell u32 *buffer; 2469254885Sdumbbell const u8 __user *data; 2470254885Sdumbbell int size, pass_size; 2471254885Sdumbbell u64 src_offset, dst_offset; 2472254885Sdumbbell 2473254885Sdumbbell if (!radeon_check_offset(dev_priv, tex->offset)) { 2474254885Sdumbbell DRM_ERROR("Invalid destination offset\n"); 2475254885Sdumbbell return -EINVAL; 2476254885Sdumbbell } 2477254885Sdumbbell 2478254885Sdumbbell /* this might fail for zero-sized uploads - are those illegal? */ 2479254885Sdumbbell if (!radeon_check_offset(dev_priv, tex->offset + tex->height * tex->pitch - 1)) { 2480254885Sdumbbell DRM_ERROR("Invalid final destination offset\n"); 2481254885Sdumbbell return -EINVAL; 2482254885Sdumbbell } 2483254885Sdumbbell 2484254885Sdumbbell size = tex->height * tex->pitch; 2485254885Sdumbbell 2486254885Sdumbbell if (size == 0) 2487254885Sdumbbell return 0; 2488254885Sdumbbell 2489254885Sdumbbell dst_offset = tex->offset; 2490254885Sdumbbell 2491254885Sdumbbell if (r600_prepare_blit_copy(dev, file_priv)) { 2492254885Sdumbbell DRM_ERROR("unable to allocate vertex buffer for swap buffer\n"); 2493254885Sdumbbell return -EAGAIN; 2494254885Sdumbbell } 2495254885Sdumbbell do { 2496254885Sdumbbell data = (const u8 __user *)image->data; 2497254885Sdumbbell pass_size = size; 2498254885Sdumbbell 2499254885Sdumbbell buf = radeon_freelist_get(dev); 2500254885Sdumbbell if (!buf) { 2501254885Sdumbbell DRM_DEBUG("EAGAIN\n"); 2502254885Sdumbbell if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image))) 2503254885Sdumbbell return -EFAULT; 2504254885Sdumbbell return -EAGAIN; 2505254885Sdumbbell } 2506254885Sdumbbell 2507254885Sdumbbell if (pass_size > buf->total) 2508254885Sdumbbell pass_size = buf->total; 2509254885Sdumbbell 2510254885Sdumbbell /* Dispatch the indirect buffer. 2511254885Sdumbbell */ 2512254885Sdumbbell buffer = 2513254885Sdumbbell (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset); 2514254885Sdumbbell 2515254885Sdumbbell if (DRM_COPY_FROM_USER(buffer, data, pass_size)) { 2516254885Sdumbbell DRM_ERROR("EFAULT on pad, %d bytes\n", pass_size); 2517254885Sdumbbell return -EFAULT; 2518254885Sdumbbell } 2519254885Sdumbbell 2520254885Sdumbbell buf->file_priv = file_priv; 2521254885Sdumbbell buf->used = pass_size; 2522254885Sdumbbell src_offset = dev_priv->gart_buffers_offset + buf->offset; 2523254885Sdumbbell 2524254885Sdumbbell r600_blit_copy(dev, src_offset, dst_offset, pass_size); 2525254885Sdumbbell 2526254885Sdumbbell radeon_cp_discard_buffer(dev, file_priv->masterp, buf); 2527254885Sdumbbell 2528254885Sdumbbell /* Update the input parameters for next time */ 2529254885Sdumbbell image->data = (const u8 __user *)image->data + pass_size; 2530254885Sdumbbell dst_offset += pass_size; 2531254885Sdumbbell size -= pass_size; 2532254885Sdumbbell } while (size > 0); 2533254885Sdumbbell r600_done_blit_copy(dev); 2534254885Sdumbbell 2535254885Sdumbbell return 0; 2536254885Sdumbbell} 2537254885Sdumbbell 2538254885Sdumbbell/* 2539254885Sdumbbell * Legacy cs ioctl 2540254885Sdumbbell */ 2541254885Sdumbbellstatic u32 radeon_cs_id_get(struct drm_radeon_private *radeon) 2542254885Sdumbbell{ 2543254885Sdumbbell /* FIXME: check if wrap affect last reported wrap & sequence */ 2544254885Sdumbbell radeon->cs_id_scnt = (radeon->cs_id_scnt + 1) & 0x00FFFFFF; 2545254885Sdumbbell if (!radeon->cs_id_scnt) { 2546254885Sdumbbell /* increment wrap counter */ 2547254885Sdumbbell radeon->cs_id_wcnt += 0x01000000; 2548254885Sdumbbell /* valid sequence counter start at 1 */ 2549254885Sdumbbell radeon->cs_id_scnt = 1; 2550254885Sdumbbell } 2551254885Sdumbbell return (radeon->cs_id_scnt | radeon->cs_id_wcnt); 2552254885Sdumbbell} 2553254885Sdumbbell 2554254885Sdumbbellstatic void r600_cs_id_emit(drm_radeon_private_t *dev_priv, u32 *id) 2555254885Sdumbbell{ 2556254885Sdumbbell RING_LOCALS; 2557254885Sdumbbell 2558254885Sdumbbell *id = radeon_cs_id_get(dev_priv); 2559254885Sdumbbell 2560254885Sdumbbell /* SCRATCH 2 */ 2561254885Sdumbbell BEGIN_RING(3); 2562254885Sdumbbell R600_CLEAR_AGE(*id); 2563254885Sdumbbell ADVANCE_RING(); 2564254885Sdumbbell COMMIT_RING(); 2565254885Sdumbbell} 2566254885Sdumbbell 2567254885Sdumbbellstatic int r600_ib_get(struct drm_device *dev, 2568254885Sdumbbell struct drm_file *fpriv, 2569254885Sdumbbell struct drm_buf **buffer) 2570254885Sdumbbell{ 2571254885Sdumbbell struct drm_buf *buf; 2572254885Sdumbbell 2573254885Sdumbbell *buffer = NULL; 2574254885Sdumbbell buf = radeon_freelist_get(dev); 2575254885Sdumbbell if (!buf) { 2576254885Sdumbbell return -EBUSY; 2577254885Sdumbbell } 2578254885Sdumbbell buf->file_priv = fpriv; 2579254885Sdumbbell *buffer = buf; 2580254885Sdumbbell return 0; 2581254885Sdumbbell} 2582254885Sdumbbell 2583254885Sdumbbellstatic void r600_ib_free(struct drm_device *dev, struct drm_buf *buf, 2584254885Sdumbbell struct drm_file *fpriv, int l, int r) 2585254885Sdumbbell{ 2586254885Sdumbbell drm_radeon_private_t *dev_priv = dev->dev_private; 2587254885Sdumbbell 2588254885Sdumbbell if (buf) { 2589254885Sdumbbell if (!r) 2590254885Sdumbbell r600_cp_dispatch_indirect(dev, buf, 0, l * 4); 2591254885Sdumbbell radeon_cp_discard_buffer(dev, fpriv->masterp, buf); 2592254885Sdumbbell COMMIT_RING(); 2593254885Sdumbbell } 2594254885Sdumbbell} 2595254885Sdumbbell 2596254885Sdumbbellint r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv) 2597254885Sdumbbell{ 2598254885Sdumbbell struct drm_radeon_private *dev_priv = dev->dev_private; 2599254885Sdumbbell struct drm_radeon_cs *cs = data; 2600254885Sdumbbell struct drm_buf *buf; 2601254885Sdumbbell unsigned family; 2602254885Sdumbbell int l, r = 0; 2603254885Sdumbbell u32 *ib, cs_id = 0; 2604254885Sdumbbell 2605254885Sdumbbell if (dev_priv == NULL) { 2606254885Sdumbbell DRM_ERROR("called with no initialization\n"); 2607254885Sdumbbell return -EINVAL; 2608254885Sdumbbell } 2609254885Sdumbbell family = dev_priv->flags & RADEON_FAMILY_MASK; 2610254885Sdumbbell if (family < CHIP_R600) { 2611254885Sdumbbell DRM_ERROR("cs ioctl valid only for R6XX & R7XX in legacy mode\n"); 2612254885Sdumbbell return -EINVAL; 2613254885Sdumbbell } 2614254885Sdumbbell sx_xlock(&dev_priv->cs_mutex); 2615254885Sdumbbell /* get ib */ 2616254885Sdumbbell l = 0; 2617254885Sdumbbell r = r600_ib_get(dev, fpriv, &buf); 2618254885Sdumbbell if (r) { 2619254885Sdumbbell DRM_ERROR("ib_get failed\n"); 2620254885Sdumbbell goto out; 2621254885Sdumbbell } 2622254885Sdumbbell ib = (u32 *)((uintptr_t)dev->agp_buffer_map->handle + buf->offset); 2623254885Sdumbbell /* now parse command stream */ 2624254885Sdumbbell r = r600_cs_legacy(dev, data, fpriv, family, ib, &l); 2625254885Sdumbbell if (r) { 2626254885Sdumbbell goto out; 2627254885Sdumbbell } 2628254885Sdumbbell 2629254885Sdumbbellout: 2630254885Sdumbbell r600_ib_free(dev, buf, fpriv, l, r); 2631254885Sdumbbell /* emit cs id sequence */ 2632254885Sdumbbell r600_cs_id_emit(dev_priv, &cs_id); 2633254885Sdumbbell cs->cs_id = cs_id; 2634254885Sdumbbell sx_xunlock(&dev_priv->cs_mutex); 2635254885Sdumbbell return r; 2636254885Sdumbbell} 2637254885Sdumbbell 2638254885Sdumbbellvoid r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size) 2639254885Sdumbbell{ 2640254885Sdumbbell struct drm_radeon_private *dev_priv = dev->dev_private; 2641254885Sdumbbell 2642254885Sdumbbell *npipes = dev_priv->r600_npipes; 2643254885Sdumbbell *nbanks = dev_priv->r600_nbanks; 2644254885Sdumbbell *group_size = dev_priv->r600_group_size; 2645254885Sdumbbell} 2646