1155192Srwatson/* 2188313Srwatson * Copyright �� 2006 Intel Corporation 3155192Srwatson * 4155192Srwatson * Permission is hereby granted, free of charge, to any person obtaining a 5155192Srwatson * copy of this software and associated documentation files (the "Software"), 6155192Srwatson * to deal in the Software without restriction, including without limitation 7155192Srwatson * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8155192Srwatson * and/or sell copies of the Software, and to permit persons to whom the 9155192Srwatson * Software is furnished to do so, subject to the following conditions: 10155192Srwatson * 11155192Srwatson * The above copyright notice and this permission notice (including the next 12155192Srwatson * paragraph) shall be included in all copies or substantial portions of the 13155192Srwatson * Software. 14180701Srwatson * 15155192Srwatson * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16155192Srwatson * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17155192Srwatson * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18155192Srwatson * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19155192Srwatson * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20155192Srwatson * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21155192Srwatson * SOFTWARE. 22155192Srwatson * 23155192Srwatson * Authors: 24155192Srwatson * Eric Anholt <eric@anholt.net> 25155192Srwatson * 26155192Srwatson * $FreeBSD$ 27155192Srwatson */ 28155192Srwatson 29155192Srwatson#ifndef _I830_BIOS_H_ 30155192Srwatson#define _I830_BIOS_H_ 31178186Srwatson 32178186Srwatson#include <dev/drm2/drmP.h> 33178186Srwatson 34155192Srwatsonstruct vbt_header { 35155192Srwatson u8 signature[20]; /**< Always starts with 'VBT$' */ 36155192Srwatson u16 version; /**< decimal */ 37155192Srwatson u16 header_size; /**< in bytes */ 38155192Srwatson u16 vbt_size; /**< in bytes */ 39155192Srwatson u8 vbt_checksum; 40155192Srwatson u8 reserved0; 41184482Srwatson u32 bdb_offset; /**< from beginning of VBT */ 42155192Srwatson u32 aim_offset[4]; /**< from beginning of VBT */ 43181060Scsjp} __attribute__((packed)); 44155192Srwatson 45155192Srwatsonstruct bdb_header { 46155192Srwatson u8 signature[16]; /**< Always 'BIOS_DATA_BLOCK' */ 47155192Srwatson u16 version; /**< decimal */ 48155192Srwatson u16 header_size; /**< in bytes */ 49155192Srwatson u16 bdb_size; /**< in bytes */ 50155192Srwatson}; 51155192Srwatson 52155192Srwatson/* strictly speaking, this is a "skip" block, but it has interesting info */ 53155192Srwatsonstruct vbios_data { 54155192Srwatson u8 type; /* 0 == desktop, 1 == mobile */ 55155192Srwatson u8 relstage; 56155192Srwatson u8 chipset; 57155192Srwatson u8 lvds_present:1; 58180735Srwatson u8 tv_present:1; 59155192Srwatson u8 rsvd2:6; /* finish byte */ 60155192Srwatson u8 rsvd3[4]; 61155192Srwatson u8 signon[155]; 62155192Srwatson u8 copyright[61]; 63155192Srwatson u16 code_segment; 64155192Srwatson u8 dos_boot_mode; 65155192Srwatson u8 bandwidth_percent; 66155192Srwatson u8 rsvd4; /* popup memory size */ 67155192Srwatson u8 resize_pci_bios; 68155192Srwatson u8 rsvd5; /* is crt already on ddc2 */ 69184482Srwatson} __attribute__((packed)); 70156889Srwatson 71155192Srwatson/* 72184482Srwatson * There are several types of BIOS data blocks (BDBs), each block has 73184482Srwatson * an ID and size in the first 3 bytes (ID in first, size in next 2). 74184482Srwatson * Known types are listed below. 75184482Srwatson */ 76184482Srwatson#define BDB_GENERAL_FEATURES 1 77184482Srwatson#define BDB_GENERAL_DEFINITIONS 2 78195925Srwatson#define BDB_OLD_TOGGLE_LIST 3 79195925Srwatson#define BDB_MODE_SUPPORT_LIST 4 80195925Srwatson#define BDB_GENERIC_MODE_TABLE 5 81195925Srwatson#define BDB_EXT_MMIO_REGS 6 82195925Srwatson#define BDB_SWF_IO 7 83195925Srwatson#define BDB_SWF_MMIO 8 84195925Srwatson#define BDB_DOT_CLOCK_TABLE 9 85195925Srwatson#define BDB_MODE_REMOVAL_TABLE 10 86195925Srwatson#define BDB_CHILD_DEVICE_TABLE 11 87195925Srwatson#define BDB_DRIVER_FEATURES 12 88195925Srwatson#define BDB_DRIVER_PERSISTENCE 13 89195925Srwatson#define BDB_EXT_TABLE_PTRS 14 90195925Srwatson#define BDB_DOT_CLOCK_OVERRIDE 15 91195925Srwatson#define BDB_DISPLAY_SELECT 16 92195925Srwatson/* 17 rsvd */ 93195925Srwatson#define BDB_DRIVER_ROTATION 18 94195925Srwatson#define BDB_DISPLAY_REMOVE 19 95195925Srwatson#define BDB_OEM_CUSTOM 20 96195925Srwatson#define BDB_EFP_LIST 21 /* workarounds for VGA hsync/vsync */ 97195925Srwatson#define BDB_SDVO_LVDS_OPTIONS 22 98195925Srwatson#define BDB_SDVO_PANEL_DTDS 23 99195925Srwatson#define BDB_SDVO_LVDS_PNP_IDS 24 100195925Srwatson#define BDB_SDVO_LVDS_POWER_SEQ 25 101195925Srwatson#define BDB_TV_OPTIONS 26 102195925Srwatson#define BDB_EDP 27 103195925Srwatson#define BDB_LVDS_OPTIONS 40 104195925Srwatson#define BDB_LVDS_LFP_DATA_PTRS 41 105195925Srwatson#define BDB_LVDS_LFP_DATA 42 106195925Srwatson#define BDB_LVDS_BACKLIGHT 43 107195925Srwatson#define BDB_LVDS_POWER 44 108195925Srwatson#define BDB_SKIP 254 /* VBIOS private block, ignore */ 109195925Srwatson 110195925Srwatsonstruct bdb_general_features { 111195925Srwatson /* bits 1 */ 112195925Srwatson u8 panel_fitting:2; 113195925Srwatson u8 flexaim:1; 114195925Srwatson u8 msg_enable:1; 115155192Srwatson u8 clear_screen:3; 116155192Srwatson u8 color_flip:1; 117155192Srwatson 118155192Srwatson /* bits 2 */ 119155192Srwatson u8 download_ext_vbt:1; 120155192Srwatson u8 enable_ssc:1; 121155192Srwatson u8 ssc_freq:1; 122155192Srwatson u8 enable_lfp_on_override:1; 123155192Srwatson u8 disable_ssc_ddt:1; 124155192Srwatson u8 rsvd7:1; 125184482Srwatson u8 display_clock_mode:1; 126155192Srwatson u8 rsvd8:1; /* finish byte */ 127173142Srwatson 128155192Srwatson /* bits 3 */ 129155192Srwatson u8 disable_smooth_vision:1; 130155192Srwatson u8 single_dvi:1; 131155192Srwatson u8 rsvd9:6; /* finish byte */ 132155192Srwatson 133155192Srwatson /* bits 4 */ 134155192Srwatson u8 legacy_monitor_detect; 135184482Srwatson 136155192Srwatson /* bits 5 */ 137155192Srwatson u8 int_crt_support:1; 138155192Srwatson u8 int_tv_support:1; 139156889Srwatson u8 int_efp_support:1; 140155192Srwatson u8 dp_ssc_enb:1; /* PCH attached eDP supports SSC */ 141155192Srwatson u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */ 142156889Srwatson u8 rsvd11:3; /* finish byte */ 143155192Srwatson} __attribute__((packed)); 144156889Srwatson 145155192Srwatson/* pre-915 */ 146155192Srwatson#define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */ 147156889Srwatson#define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */ 148155192Srwatson#define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */ 149155192Srwatson#define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */ 150155192Srwatson 151155192Srwatson/* Pre 915 */ 152155192Srwatson#define DEVICE_TYPE_NONE 0x00 153155192Srwatson#define DEVICE_TYPE_CRT 0x01 154155192Srwatson#define DEVICE_TYPE_TV 0x09 155155192Srwatson#define DEVICE_TYPE_EFP 0x12 156155192Srwatson#define DEVICE_TYPE_LFP 0x22 157155192Srwatson/* On 915+ */ 158184482Srwatson#define DEVICE_TYPE_CRT_DPMS 0x6001 159155192Srwatson#define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001 160155192Srwatson#define DEVICE_TYPE_TV_COMPOSITE 0x0209 161155192Srwatson#define DEVICE_TYPE_TV_MACROVISION 0x0289 162155192Srwatson#define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c 163184482Srwatson#define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609 164155192Srwatson#define DEVICE_TYPE_TV_SCART 0x0209 165155192Srwatson#define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009 166155192Srwatson#define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012 167155192Srwatson#define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052 168155192Srwatson#define DEVICE_TYPE_EFP_DVI_I 0x6053 169155192Srwatson#define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152 170155192Srwatson#define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2 171155192Srwatson#define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062 172184482Srwatson#define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162 173155192Srwatson#define DEVICE_TYPE_LFP_PANELLINK 0x5012 174155192Srwatson#define DEVICE_TYPE_LFP_CMOS_PWR 0x5042 175155192Srwatson#define DEVICE_TYPE_LFP_LVDS_PWR 0x5062 176156889Srwatson#define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162 177155192Srwatson#define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2 178155192Srwatson 179155192Srwatson#define DEVICE_CFG_NONE 0x00 180184482Srwatson#define DEVICE_CFG_12BIT_DVOB 0x01 181155192Srwatson#define DEVICE_CFG_12BIT_DVOC 0x02 182155192Srwatson#define DEVICE_CFG_24BIT_DVOBC 0x09 183155192Srwatson#define DEVICE_CFG_24BIT_DVOCB 0x0a 184155192Srwatson#define DEVICE_CFG_DUAL_DVOB 0x11 185155192Srwatson#define DEVICE_CFG_DUAL_DVOC 0x12 186155192Srwatson#define DEVICE_CFG_DUAL_DVOBC 0x13 187155192Srwatson#define DEVICE_CFG_DUAL_LINK_DVOBC 0x19 188155192Srwatson#define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a 189155192Srwatson 190155192Srwatson#define DEVICE_WIRE_NONE 0x00 191156889Srwatson#define DEVICE_WIRE_DVOB 0x01 192155192Srwatson#define DEVICE_WIRE_DVOC 0x02 193155192Srwatson#define DEVICE_WIRE_DVOBC 0x03 194173142Srwatson#define DEVICE_WIRE_DVOBB 0x05 195155192Srwatson#define DEVICE_WIRE_DVOCC 0x06 196155192Srwatson#define DEVICE_WIRE_DVOB_MASTER 0x0d 197155192Srwatson#define DEVICE_WIRE_DVOC_MASTER 0x0e 198155192Srwatson 199155192Srwatson#define DEVICE_PORT_DVOA 0x00 /* none on 845+ */ 200155192Srwatson#define DEVICE_PORT_DVOB 0x01 201155192Srwatson#define DEVICE_PORT_DVOC 0x02 202155192Srwatson 203159269Srwatsonstruct child_device_config { 204155192Srwatson u16 handle; 205155192Srwatson u16 device_type; 206155192Srwatson u8 device_id[10]; /* ascii string */ 207155192Srwatson u16 addin_offset; 208155192Srwatson u8 dvo_port; /* See Device_PORT_* above */ 209155192Srwatson u8 i2c_pin; 210156889Srwatson u8 slave_addr; 211155192Srwatson u8 ddc_pin; 212155192Srwatson u16 edid_ptr; 213155192Srwatson u8 dvo_cfg; /* See DEVICE_CFG_* above */ 214159269Srwatson u8 dvo2_port; 215156889Srwatson u8 i2c2_pin; 216155192Srwatson u8 slave2_addr; 217159269Srwatson u8 ddc2_pin; 218156889Srwatson u8 capabilities; 219155192Srwatson u8 dvo_wiring;/* See DEVICE_WIRE_* above */ 220155192Srwatson u8 dvo2_wiring; 221156889Srwatson u16 extended_type; 222155192Srwatson u8 dvo_function; 223155192Srwatson} __attribute__((packed)); 224155192Srwatson 225155192Srwatsonstruct bdb_general_definitions { 226156889Srwatson /* DDC GPIO */ 227155192Srwatson u8 crt_ddc_gmbus_pin; 228155192Srwatson 229176690Srwatson /* DPMS bits */ 230155192Srwatson u8 dpms_acpi:1; 231155192Srwatson u8 skip_boot_crt_detect:1; 232155192Srwatson u8 dpms_aim:1; 233156889Srwatson u8 rsvd1:5; /* finish byte */ 234155192Srwatson 235155192Srwatson /* boot device bits */ 236155192Srwatson u8 boot_display[2]; 237155192Srwatson u8 child_dev_size; 238155192Srwatson 239155192Srwatson /* 240155192Srwatson * Device info: 241155192Srwatson * If TV is present, it'll be at devices[0]. 242155192Srwatson * LVDS will be next, either devices[0] or [1], if present. 243155192Srwatson * On some platforms the number of device is 6. But could be as few as 244155192Srwatson * 4 if both TV and LVDS are missing. 245155192Srwatson * And the device num is related with the size of general definition 246155192Srwatson * block. It is obtained by using the following formula: 247155192Srwatson * number = (block_size - sizeof(bdb_general_definitions))/ 248155192Srwatson * sizeof(child_device_config); 249155192Srwatson */ 250155192Srwatson struct child_device_config devices[0]; 251155192Srwatson} __attribute__((packed)); 252155192Srwatson 253155192Srwatsonstruct bdb_lvds_options { 254155192Srwatson u8 panel_type; 255155192Srwatson u8 rsvd1; 256155192Srwatson /* LVDS capabilities, stored in a dword */ 257155192Srwatson u8 pfit_mode:2; 258155192Srwatson u8 pfit_text_mode_enhanced:1; 259155192Srwatson u8 pfit_gfx_mode_enhanced:1; 260155192Srwatson u8 pfit_ratio_auto:1; 261155192Srwatson u8 pixel_dither:1; 262155192Srwatson u8 lvds_edid:1; 263155192Srwatson u8 rsvd2:1; 264155192Srwatson u8 rsvd4; 265155192Srwatson} __attribute__((packed)); 266155192Srwatson 267155192Srwatson/* LFP pointer table contains entries to the struct below */ 268155192Srwatsonstruct bdb_lvds_lfp_data_ptr { 269155192Srwatson u16 fp_timing_offset; /* offsets are from start of bdb */ 270155192Srwatson u8 fp_table_size; 271155192Srwatson u16 dvo_timing_offset; 272155192Srwatson u8 dvo_table_size; 273155192Srwatson u16 panel_pnp_id_offset; 274155192Srwatson u8 pnp_table_size; 275155192Srwatson} __attribute__((packed)); 276155192Srwatson 277181053Srwatsonstruct bdb_lvds_lfp_data_ptrs { 278155192Srwatson u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */ 279155192Srwatson struct bdb_lvds_lfp_data_ptr ptr[16]; 280155192Srwatson} __attribute__((packed)); 281155192Srwatson 282155192Srwatson/* LFP data has 3 blocks per entry */ 283155192Srwatsonstruct lvds_fp_timing { 284155192Srwatson u16 x_res; 285155192Srwatson u16 y_res; 286156889Srwatson u32 lvds_reg; 287155192Srwatson u32 lvds_reg_val; 288155192Srwatson u32 pp_on_reg; 289155192Srwatson u32 pp_on_reg_val; 290176690Srwatson u32 pp_off_reg; 291156889Srwatson u32 pp_off_reg_val; 292195925Srwatson u32 pp_cycle_reg; 293155192Srwatson u32 pp_cycle_reg_val; 294156889Srwatson u32 pfit_reg; 295156889Srwatson u32 pfit_reg_val; 296156889Srwatson u16 terminator; 297155192Srwatson} __attribute__((packed)); 298195925Srwatson 299195925Srwatsonstruct lvds_dvo_timing { 300195925Srwatson u16 clock; /**< In 10khz */ 301195925Srwatson u8 hactive_lo; 302195925Srwatson u8 hblank_lo; 303195925Srwatson u8 hblank_hi:4; 304155192Srwatson u8 hactive_hi:4; 305195925Srwatson u8 vactive_lo; 306195925Srwatson u8 vblank_lo; 307195925Srwatson u8 vblank_hi:4; 308195925Srwatson u8 vactive_hi:4; 309155192Srwatson u8 hsync_off_lo; 310156889Srwatson u8 hsync_pulse_width; 311195925Srwatson u8 vsync_pulse_width:4; 312155192Srwatson u8 vsync_off:4; 313195925Srwatson u8 rsvd0:6; 314195925Srwatson u8 hsync_off_hi:2; 315195925Srwatson u8 h_image; 316195925Srwatson u8 v_image; 317155192Srwatson u8 max_hv; 318195925Srwatson u8 h_border; 319155192Srwatson u8 v_border; 320155192Srwatson u8 rsvd1:3; 321155192Srwatson u8 digital:2; 322155192Srwatson u8 vsync_positive:1; 323155192Srwatson u8 hsync_positive:1; 324188313Srwatson u8 rsvd2:1; 325176565Srwatson} __attribute__((packed)); 326155192Srwatson 327155192Srwatsonstruct lvds_pnp_id { 328155192Srwatson u16 mfg_name; 329155192Srwatson u16 product_code; 330155192Srwatson u32 serial; 331155192Srwatson u8 mfg_week; 332155192Srwatson u8 mfg_year; 333155192Srwatson} __attribute__((packed)); 334155192Srwatson 335155192Srwatsonstruct bdb_lvds_lfp_data_entry { 336155192Srwatson struct lvds_fp_timing fp_timing; 337155192Srwatson struct lvds_dvo_timing dvo_timing; 338155192Srwatson struct lvds_pnp_id pnp_id; 339170196Srwatson} __attribute__((packed)); 340155192Srwatson 341155192Srwatsonstruct bdb_lvds_lfp_data { 342155192Srwatson struct bdb_lvds_lfp_data_entry data[16]; 343155192Srwatson} __attribute__((packed)); 344155192Srwatson 345155192Srwatsonstruct aimdb_header { 346155192Srwatson char signature[16]; 347188313Srwatson char oem_device[20]; 348176565Srwatson u16 aimdb_version; 349155192Srwatson u16 aimdb_header_size; 350155192Srwatson u16 aimdb_size; 351155192Srwatson} __attribute__((packed)); 352155192Srwatson 353155192Srwatsonstruct aimdb_block { 354155192Srwatson u8 aimdb_id; 355155192Srwatson u16 aimdb_size; 356155192Srwatson} __attribute__((packed)); 357155192Srwatson 358155192Srwatsonstruct vch_panel_data { 359155192Srwatson u16 fp_timing_offset; 360155192Srwatson u8 fp_timing_size; 361155192Srwatson u16 dvo_timing_offset; 362155192Srwatson u8 dvo_timing_size; 363155192Srwatson u16 text_fitting_offset; 364155192Srwatson u8 text_fitting_size; 365155192Srwatson u16 graphics_fitting_offset; 366155192Srwatson u8 graphics_fitting_size; 367155192Srwatson} __attribute__((packed)); 368155192Srwatson 369155192Srwatsonstruct vch_bdb_22 { 370155192Srwatson struct aimdb_block aimdb_block; 371155192Srwatson struct vch_panel_data panels[16]; 372155192Srwatson} __attribute__((packed)); 373155192Srwatson 374155192Srwatsonstruct bdb_sdvo_lvds_options { 375155192Srwatson u8 panel_backlight; 376155192Srwatson u8 h40_set_panel_type; 377155192Srwatson u8 panel_type; 378155192Srwatson u8 ssc_clk_freq; 379155192Srwatson u16 als_low_trip; 380155192Srwatson u16 als_high_trip; 381155192Srwatson u8 sclalarcoeff_tab_row_num; 382155192Srwatson u8 sclalarcoeff_tab_row_size; 383181053Srwatson u8 coefficient[8]; 384155192Srwatson u8 panel_misc_bits_1; 385155192Srwatson u8 panel_misc_bits_2; 386155192Srwatson u8 panel_misc_bits_3; 387155192Srwatson u8 panel_misc_bits_4; 388155192Srwatson} __attribute__((packed)); 389155192Srwatson 390155192Srwatson 391188313Srwatson#define BDB_DRIVER_FEATURE_NO_LVDS 0 392155192Srwatson#define BDB_DRIVER_FEATURE_INT_LVDS 1 393155192Srwatson#define BDB_DRIVER_FEATURE_SDVO_LVDS 2 394155192Srwatson#define BDB_DRIVER_FEATURE_EDP 3 395155192Srwatson 396155192Srwatsonstruct bdb_driver_features { 397155192Srwatson u8 boot_dev_algorithm:1; 398155192Srwatson u8 block_display_switch:1; 399155192Srwatson u8 allow_display_switch:1; 400155192Srwatson u8 hotplug_dvo:1; 401155192Srwatson u8 dual_view_zoom:1; 402155192Srwatson u8 int15h_hook:1; 403155192Srwatson u8 sprite_in_clone:1; 404155192Srwatson u8 primary_lfp_id:1; 405155192Srwatson 406155192Srwatson u16 boot_mode_x; 407155192Srwatson u16 boot_mode_y; 408155192Srwatson u8 boot_mode_bpp; 409155192Srwatson u8 boot_mode_refresh; 410155192Srwatson 411155192Srwatson u16 enable_lfp_primary:1; 412155192Srwatson u16 selective_mode_pruning:1; 413155192Srwatson u16 dual_frequency:1; 414155192Srwatson u16 render_clock_freq:1; /* 0: high freq; 1: low freq */ 415155192Srwatson u16 nt_clone_support:1; 416155192Srwatson u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */ 417155192Srwatson u16 sprite_display_assign:1; /* 0: secondary; 1: primary */ 418155192Srwatson u16 cui_aspect_scaling:1; 419155192Srwatson u16 preserve_aspect_ratio:1; 420155192Srwatson u16 sdvo_device_power_down:1; 421155192Srwatson u16 crt_hotplug:1; 422155192Srwatson u16 lvds_config:2; 423155192Srwatson u16 tv_hotplug:1; 424155192Srwatson u16 hdmi_config:2; 425155192Srwatson 426155192Srwatson u8 static_display:1; 427155192Srwatson u8 reserved2:7; 428155192Srwatson u16 legacy_crt_max_x; 429155192Srwatson u16 legacy_crt_max_y; 430155192Srwatson u8 legacy_crt_max_refresh; 431155192Srwatson 432155192Srwatson u8 hdmi_termination; 433155192Srwatson u8 custom_vbt_version; 434155192Srwatson} __attribute__((packed)); 435155192Srwatson 436155192Srwatson#define EDP_18BPP 0 437155192Srwatson#define EDP_24BPP 1 438155192Srwatson#define EDP_30BPP 2 439155192Srwatson#define EDP_RATE_1_62 0 440155192Srwatson#define EDP_RATE_2_7 1 441155192Srwatson#define EDP_LANE_1 0 442155192Srwatson#define EDP_LANE_2 1 443155192Srwatson#define EDP_LANE_4 3 444155192Srwatson#define EDP_PREEMPHASIS_NONE 0 445155192Srwatson#define EDP_PREEMPHASIS_3_5dB 1 446155192Srwatson#define EDP_PREEMPHASIS_6dB 2 447155192Srwatson#define EDP_PREEMPHASIS_9_5dB 3 448155192Srwatson#define EDP_VSWING_0_4V 0 449155192Srwatson#define EDP_VSWING_0_6V 1 450155192Srwatson#define EDP_VSWING_0_8V 2 451155192Srwatson#define EDP_VSWING_1_2V 3 452155192Srwatson 453155192Srwatsonstruct edp_power_seq { 454155192Srwatson u16 t1_t3; 455155192Srwatson u16 t8; 456156889Srwatson u16 t9; 457156889Srwatson u16 t10; 458156889Srwatson u16 t11_t12; 459170196Srwatson} __attribute__ ((packed)); 460156889Srwatson 461156889Srwatsonstruct edp_link_params { 462155192Srwatson u8 rate:4; 463155192Srwatson u8 lanes:4; 464244324Spjd u8 preemphasis:4; 465155192Srwatson u8 vswing:4; 466181060Scsjp} __attribute__ ((packed)); 467181060Scsjp 468155192Srwatsonstruct bdb_edp { 469181060Scsjp struct edp_power_seq power_seqs[16]; 470244324Spjd u32 color_depth; 471155192Srwatson struct edp_link_params link_params[16]; 472181060Scsjp u32 sdrrs_msa_timing_delay; 473181060Scsjp 474165621Srwatson /* ith bit indicates enabled/disabled for (i+1)th panel */ 475181060Scsjp u16 edp_s3d_feature; 476181060Scsjp u16 edp_t3_optimization; 477155192Srwatson} __attribute__ ((packed)); 478168355Srwatson 479181060Scsjpvoid intel_setup_bios(struct drm_device *dev); 480181060Scsjpbool intel_parse_bios(struct drm_device *dev); 481181060Scsjp 482181060Scsjp/* 483181060Scsjp * Driver<->VBIOS interaction occurs through scratch bits in 484181060Scsjp * GR18 & SWF*. 485181060Scsjp */ 486155192Srwatson 487181060Scsjp/* GR18 bits are set on display switch and hotkey events */ 488181060Scsjp#define GR18_DRIVER_SWITCH_EN (1<<7) /* 0: VBIOS control, 1: driver control */ 489181060Scsjp#define GR18_HOTKEY_MASK 0x78 /* See also SWF4 15:0 */ 490181060Scsjp#define GR18_HK_NONE (0x0<<3) 491181060Scsjp#define GR18_HK_LFP_STRETCH (0x1<<3) 492181060Scsjp#define GR18_HK_TOGGLE_DISP (0x2<<3) 493244324Spjd#define GR18_HK_DISP_SWITCH (0x4<<3) /* see SWF14 15:0 for what to enable */ 494244324Spjd#define GR18_HK_POPUP_DISABLED (0x6<<3) 495244324Spjd#define GR18_HK_POPUP_ENABLED (0x7<<3) 496244324Spjd#define GR18_HK_PFIT (0x8<<3) 497244324Spjd#define GR18_HK_APM_CHANGE (0xa<<3) 498244324Spjd#define GR18_HK_MULTIPLE (0xc<<3) 499244324Spjd#define GR18_USER_INT_EN (1<<2) 500244324Spjd#define GR18_A0000_FLUSH_EN (1<<1) 501244324Spjd#define GR18_SMM_EN (1<<0) 502244324Spjd 503244324Spjd/* Set by driver, cleared by VBIOS */ 504244324Spjd#define SWF00_YRES_SHIFT 16 505244324Spjd#define SWF00_XRES_SHIFT 0 506244324Spjd#define SWF00_RES_MASK 0xffff 507244324Spjd 508244324Spjd/* Set by VBIOS at boot time and driver at runtime */ 509244324Spjd#define SWF01_TV2_FORMAT_SHIFT 8 510244324Spjd#define SWF01_TV1_FORMAT_SHIFT 0 511244324Spjd#define SWF01_TV_FORMAT_MASK 0xffff 512244324Spjd 513181060Scsjp#define SWF10_VBIOS_BLC_I2C_EN (1<<29) 514168355Srwatson#define SWF10_GTT_OVERRIDE_EN (1<<28) 515181060Scsjp#define SWF10_LFP_DPMS_OVR (1<<27) /* override DPMS on display switch */ 516181060Scsjp#define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24) 517181060Scsjp#define SWF10_OLD_TOGGLE 0x0 518181060Scsjp#define SWF10_TOGGLE_LIST_1 0x1 519181060Scsjp#define SWF10_TOGGLE_LIST_2 0x2 520181060Scsjp#define SWF10_TOGGLE_LIST_3 0x3 521181060Scsjp#define SWF10_TOGGLE_LIST_4 0x4 522181060Scsjp#define SWF10_PANNING_EN (1<<23) 523181060Scsjp#define SWF10_DRIVER_LOADED (1<<22) 524181060Scsjp#define SWF10_EXTENDED_DESKTOP (1<<21) 525181060Scsjp#define SWF10_EXCLUSIVE_MODE (1<<20) 526181060Scsjp#define SWF10_OVERLAY_EN (1<<19) 527181060Scsjp#define SWF10_PLANEB_HOLDOFF (1<<18) 528181060Scsjp#define SWF10_PLANEA_HOLDOFF (1<<17) 529181060Scsjp#define SWF10_VGA_HOLDOFF (1<<16) 530181060Scsjp#define SWF10_ACTIVE_DISP_MASK 0xffff 531181060Scsjp#define SWF10_PIPEB_LFP2 (1<<15) 532181060Scsjp#define SWF10_PIPEB_EFP2 (1<<14) 533181060Scsjp#define SWF10_PIPEB_TV2 (1<<13) 534184660Sjhb#define SWF10_PIPEB_CRT2 (1<<12) 535181060Scsjp#define SWF10_PIPEB_LFP (1<<11) 536181060Scsjp#define SWF10_PIPEB_EFP (1<<10) 537155192Srwatson#define SWF10_PIPEB_TV (1<<9) 538181060Scsjp#define SWF10_PIPEB_CRT (1<<8) 539181060Scsjp#define SWF10_PIPEA_LFP2 (1<<7) 540181060Scsjp#define SWF10_PIPEA_EFP2 (1<<6) 541181060Scsjp#define SWF10_PIPEA_TV2 (1<<5) 542181060Scsjp#define SWF10_PIPEA_CRT2 (1<<4) 543181060Scsjp#define SWF10_PIPEA_LFP (1<<3) 544181060Scsjp#define SWF10_PIPEA_EFP (1<<2) 545181060Scsjp#define SWF10_PIPEA_TV (1<<1) 546184660Sjhb#define SWF10_PIPEA_CRT (1<<0) 547181060Scsjp 548181060Scsjp#define SWF11_MEMORY_SIZE_SHIFT 16 549181060Scsjp#define SWF11_SV_TEST_EN (1<<15) 550181060Scsjp#define SWF11_IS_AGP (1<<14) 551181060Scsjp#define SWF11_DISPLAY_HOLDOFF (1<<13) 552181060Scsjp#define SWF11_DPMS_REDUCED (1<<12) 553181060Scsjp#define SWF11_IS_VBE_MODE (1<<11) 554181060Scsjp#define SWF11_PIPEB_ACCESS (1<<10) /* 0 here means pipe a */ 555244324Spjd#define SWF11_DPMS_MASK 0x07 556182090Scsjp#define SWF11_DPMS_OFF (1<<2) 557181060Scsjp#define SWF11_DPMS_SUSPEND (1<<1) 558181060Scsjp#define SWF11_DPMS_STANDBY (1<<0) 559181060Scsjp#define SWF11_DPMS_ON 0 560181060Scsjp 561181060Scsjp#define SWF14_GFX_PFIT_EN (1<<31) 562181060Scsjp#define SWF14_TEXT_PFIT_EN (1<<30) 563181060Scsjp#define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */ 564181060Scsjp#define SWF14_POPUP_EN (1<<28) 565181060Scsjp#define SWF14_DISPLAY_HOLDOFF (1<<27) 566181060Scsjp#define SWF14_DISP_DETECT_EN (1<<26) 567212425Smdf#define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */ 568181060Scsjp#define SWF14_DRIVER_STATUS (1<<24) 569181060Scsjp#define SWF14_OS_TYPE_WIN9X (1<<23) 570181060Scsjp#define SWF14_OS_TYPE_WINNT (1<<22) 571181060Scsjp/* 21:19 rsvd */ 572155192Srwatson#define SWF14_PM_TYPE_MASK 0x00070000 573#define SWF14_PM_ACPI_VIDEO (0x4 << 16) 574#define SWF14_PM_ACPI (0x3 << 16) 575#define SWF14_PM_APM_12 (0x2 << 16) 576#define SWF14_PM_APM_11 (0x1 << 16) 577#define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */ 578 /* if GR18 indicates a display switch */ 579#define SWF14_DS_PIPEB_LFP2_EN (1<<15) 580#define SWF14_DS_PIPEB_EFP2_EN (1<<14) 581#define SWF14_DS_PIPEB_TV2_EN (1<<13) 582#define SWF14_DS_PIPEB_CRT2_EN (1<<12) 583#define SWF14_DS_PIPEB_LFP_EN (1<<11) 584#define SWF14_DS_PIPEB_EFP_EN (1<<10) 585#define SWF14_DS_PIPEB_TV_EN (1<<9) 586#define SWF14_DS_PIPEB_CRT_EN (1<<8) 587#define SWF14_DS_PIPEA_LFP2_EN (1<<7) 588#define SWF14_DS_PIPEA_EFP2_EN (1<<6) 589#define SWF14_DS_PIPEA_TV2_EN (1<<5) 590#define SWF14_DS_PIPEA_CRT2_EN (1<<4) 591#define SWF14_DS_PIPEA_LFP_EN (1<<3) 592#define SWF14_DS_PIPEA_EFP_EN (1<<2) 593#define SWF14_DS_PIPEA_TV_EN (1<<1) 594#define SWF14_DS_PIPEA_CRT_EN (1<<0) 595 /* if GR18 indicates a panel fitting request */ 596#define SWF14_PFIT_EN (1<<0) /* 0 means disable */ 597 /* if GR18 indicates an APM change request */ 598#define SWF14_APM_HIBERNATE 0x4 599#define SWF14_APM_SUSPEND 0x3 600#define SWF14_APM_STANDBY 0x1 601#define SWF14_APM_RESTORE 0x0 602 603/* Add the device class for LFP, TV, HDMI */ 604#define DEVICE_TYPE_INT_LFP 0x1022 605#define DEVICE_TYPE_INT_TV 0x1009 606#define DEVICE_TYPE_HDMI 0x60D2 607#define DEVICE_TYPE_DP 0x68C6 608#define DEVICE_TYPE_eDP 0x78C6 609 610/* define the DVO port for HDMI output type */ 611#define DVO_B 1 612#define DVO_C 2 613#define DVO_D 3 614 615/* define the PORT for DP output type */ 616#define PORT_IDPB 7 617#define PORT_IDPC 8 618#define PORT_IDPD 9 619 620#endif /* _I830_BIOS_H_ */ 621