1235783Skib/* 2235783Skib * Copyright �� 2007-2008 Intel Corporation 3235783Skib * Jesse Barnes <jesse.barnes@intel.com> 4235783Skib * 5235783Skib * Permission is hereby granted, free of charge, to any person obtaining a 6235783Skib * copy of this software and associated documentation files (the "Software"), 7235783Skib * to deal in the Software without restriction, including without limitation 8235783Skib * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9235783Skib * and/or sell copies of the Software, and to permit persons to whom the 10235783Skib * Software is furnished to do so, subject to the following conditions: 11235783Skib * 12235783Skib * The above copyright notice and this permission notice shall be included in 13235783Skib * all copies or substantial portions of the Software. 14235783Skib * 15235783Skib * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16235783Skib * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17235783Skib * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18235783Skib * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19235783Skib * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20235783Skib * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21235783Skib * OTHER DEALINGS IN THE SOFTWARE. 22235783Skib * 23235783Skib * $FreeBSD$ 24235783Skib */ 25235783Skib#ifndef __DRM_EDID_H__ 26235783Skib#define __DRM_EDID_H__ 27235783Skib 28235783Skib#include <sys/types.h> 29235783Skib#include <dev/drm2/drmP.h> 30235783Skib 31235783Skib#define EDID_LENGTH 128 32235783Skib#define DDC_ADDR 0x50 33235783Skib 34235783Skib#define CEA_EXT 0x02 35235783Skib#define VTB_EXT 0x10 36235783Skib#define DI_EXT 0x40 37235783Skib#define LS_EXT 0x50 38235783Skib#define MI_EXT 0x60 39235783Skib 40235783Skibstruct est_timings { 41235783Skib u8 t1; 42235783Skib u8 t2; 43235783Skib u8 mfg_rsvd; 44235783Skib} __attribute__((packed)); 45235783Skib 46235783Skib/* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */ 47235783Skib#define EDID_TIMING_ASPECT_SHIFT 6 48235783Skib#define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT) 49235783Skib 50235783Skib/* need to add 60 */ 51235783Skib#define EDID_TIMING_VFREQ_SHIFT 0 52235783Skib#define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT) 53235783Skib 54235783Skibstruct std_timing { 55235783Skib u8 hsize; /* need to multiply by 8 then add 248 */ 56235783Skib u8 vfreq_aspect; 57235783Skib} __attribute__((packed)); 58235783Skib 59235783Skib#define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1) 60235783Skib#define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2) 61235783Skib#define DRM_EDID_PT_SEPARATE_SYNC (3 << 3) 62235783Skib#define DRM_EDID_PT_STEREO (1 << 5) 63235783Skib#define DRM_EDID_PT_INTERLACED (1 << 7) 64235783Skib 65235783Skib/* If detailed data is pixel timing */ 66235783Skibstruct detailed_pixel_timing { 67235783Skib u8 hactive_lo; 68235783Skib u8 hblank_lo; 69235783Skib u8 hactive_hblank_hi; 70235783Skib u8 vactive_lo; 71235783Skib u8 vblank_lo; 72235783Skib u8 vactive_vblank_hi; 73235783Skib u8 hsync_offset_lo; 74235783Skib u8 hsync_pulse_width_lo; 75235783Skib u8 vsync_offset_pulse_width_lo; 76235783Skib u8 hsync_vsync_offset_pulse_width_hi; 77235783Skib u8 width_mm_lo; 78235783Skib u8 height_mm_lo; 79235783Skib u8 width_height_mm_hi; 80235783Skib u8 hborder; 81235783Skib u8 vborder; 82235783Skib u8 misc; 83235783Skib} __attribute__((packed)); 84235783Skib 85235783Skib/* If it's not pixel timing, it'll be one of the below */ 86235783Skibstruct detailed_data_string { 87235783Skib u8 str[13]; 88235783Skib} __attribute__((packed)); 89235783Skib 90235783Skibstruct detailed_data_monitor_range { 91235783Skib u8 min_vfreq; 92235783Skib u8 max_vfreq; 93235783Skib u8 min_hfreq_khz; 94235783Skib u8 max_hfreq_khz; 95235783Skib u8 pixel_clock_mhz; /* need to multiply by 10 */ 96235783Skib u16 sec_gtf_toggle; /* A000=use above, 20=use below */ 97235783Skib u8 hfreq_start_khz; /* need to multiply by 2 */ 98235783Skib u8 c; /* need to divide by 2 */ 99235783Skib u16 m; 100235783Skib u8 k; 101235783Skib u8 j; /* need to divide by 2 */ 102235783Skib} __attribute__((packed)); 103235783Skib 104235783Skibstruct detailed_data_wpindex { 105235783Skib u8 white_yx_lo; /* Lower 2 bits each */ 106235783Skib u8 white_x_hi; 107235783Skib u8 white_y_hi; 108235783Skib u8 gamma; /* need to divide by 100 then add 1 */ 109235783Skib} __attribute__((packed)); 110235783Skib 111235783Skibstruct detailed_data_color_point { 112235783Skib u8 windex1; 113235783Skib u8 wpindex1[3]; 114235783Skib u8 windex2; 115235783Skib u8 wpindex2[3]; 116235783Skib} __attribute__((packed)); 117235783Skib 118235783Skibstruct cvt_timing { 119235783Skib u8 code[3]; 120235783Skib} __attribute__((packed)); 121235783Skib 122235783Skibstruct detailed_non_pixel { 123235783Skib u8 pad1; 124235783Skib u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name 125235783Skib fb=color point data, fa=standard timing data, 126235783Skib f9=undefined, f8=mfg. reserved */ 127235783Skib u8 pad2; 128235783Skib union { 129235783Skib struct detailed_data_string str; 130235783Skib struct detailed_data_monitor_range range; 131235783Skib struct detailed_data_wpindex color; 132235783Skib struct std_timing timings[6]; 133235783Skib struct cvt_timing cvt[4]; 134235783Skib } data; 135235783Skib} __attribute__((packed)); 136235783Skib 137235783Skib#define EDID_DETAIL_EST_TIMINGS 0xf7 138235783Skib#define EDID_DETAIL_CVT_3BYTE 0xf8 139235783Skib#define EDID_DETAIL_COLOR_MGMT_DATA 0xf9 140235783Skib#define EDID_DETAIL_STD_MODES 0xfa 141235783Skib#define EDID_DETAIL_MONITOR_CPDATA 0xfb 142235783Skib#define EDID_DETAIL_MONITOR_NAME 0xfc 143235783Skib#define EDID_DETAIL_MONITOR_RANGE 0xfd 144235783Skib#define EDID_DETAIL_MONITOR_STRING 0xfe 145235783Skib#define EDID_DETAIL_MONITOR_SERIAL 0xff 146235783Skib 147235783Skibstruct detailed_timing { 148235783Skib u16 pixel_clock; /* need to multiply by 10 KHz */ 149235783Skib union { 150235783Skib struct detailed_pixel_timing pixel_data; 151235783Skib struct detailed_non_pixel other_data; 152235783Skib } data; 153235783Skib} __attribute__((packed)); 154235783Skib 155235783Skib#define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0) 156235783Skib#define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1) 157235783Skib#define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2) 158235783Skib#define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3) 159235783Skib#define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4) 160235783Skib#define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5) 161235783Skib#define DRM_EDID_INPUT_DIGITAL (1 << 7) 162235783Skib#define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4) 163235783Skib#define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4) 164235783Skib#define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4) 165235783Skib#define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4) 166235783Skib#define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4) 167235783Skib#define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4) 168235783Skib#define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4) 169235783Skib#define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4) 170235783Skib#define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4) 171235783Skib#define DRM_EDID_DIGITAL_TYPE_UNDEF (0) 172235783Skib#define DRM_EDID_DIGITAL_TYPE_DVI (1) 173235783Skib#define DRM_EDID_DIGITAL_TYPE_HDMI_A (2) 174235783Skib#define DRM_EDID_DIGITAL_TYPE_HDMI_B (3) 175235783Skib#define DRM_EDID_DIGITAL_TYPE_MDDI (4) 176235783Skib#define DRM_EDID_DIGITAL_TYPE_DP (5) 177235783Skib 178235783Skib#define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0) 179235783Skib#define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1) 180235783Skib#define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2) 181235783Skib#define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */ 182235783Skib/* If digital */ 183235783Skib#define DRM_EDID_FEATURE_COLOR_MASK (3 << 3) 184235783Skib#define DRM_EDID_FEATURE_RGB (0 << 3) 185235783Skib#define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3) 186235783Skib#define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3) 187235783Skib#define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */ 188235783Skib 189235783Skib#define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5) 190235783Skib#define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6) 191235783Skib#define DRM_EDID_FEATURE_PM_STANDBY (1 << 7) 192235783Skib 193235783Skibstruct edid { 194235783Skib u8 header[8]; 195235783Skib /* Vendor & product info */ 196235783Skib u8 mfg_id[2]; 197235783Skib u8 prod_code[2]; 198235783Skib u32 serial; /* FIXME: byte order */ 199235783Skib u8 mfg_week; 200235783Skib u8 mfg_year; 201235783Skib /* EDID version */ 202235783Skib u8 version; 203235783Skib u8 revision; 204235783Skib /* Display info: */ 205235783Skib u8 input; 206235783Skib u8 width_cm; 207235783Skib u8 height_cm; 208235783Skib u8 gamma; 209235783Skib u8 features; 210235783Skib /* Color characteristics */ 211235783Skib u8 red_green_lo; 212235783Skib u8 black_white_lo; 213235783Skib u8 red_x; 214235783Skib u8 red_y; 215235783Skib u8 green_x; 216235783Skib u8 green_y; 217235783Skib u8 blue_x; 218235783Skib u8 blue_y; 219235783Skib u8 white_x; 220235783Skib u8 white_y; 221235783Skib /* Est. timings and mfg rsvd timings*/ 222235783Skib struct est_timings established_timings; 223235783Skib /* Standard timings 1-8*/ 224235783Skib struct std_timing standard_timings[8]; 225235783Skib /* Detailing timings 1-4 */ 226235783Skib struct detailed_timing detailed_timings[4]; 227235783Skib /* Number of 128 byte ext. blocks */ 228235783Skib u8 extensions; 229235783Skib /* Checksum */ 230235783Skib u8 checksum; 231235783Skib} __attribute__((packed)); 232235783Skib 233235783Skib#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) 234235783Skib 235235783Skibstruct drm_encoder; 236235783Skibstruct drm_connector; 237235783Skibstruct drm_display_mode; 238235783Skibvoid drm_edid_to_eld(struct drm_connector *connector, struct edid *edid); 239235783Skibint drm_av_sync_delay(struct drm_connector *connector, 240235783Skib struct drm_display_mode *mode); 241235783Skibstruct drm_connector *drm_select_eld(struct drm_encoder *encoder, 242235783Skib struct drm_display_mode *mode); 243235783Skib 244235783Skib#endif /* __DRM_EDID_H__ */ 245