1218885Sdim/*- 2218885Sdim * Defines for Cronyx-Sigma adapter driver. 3218885Sdim * 4218885Sdim * Copyright (C) 1994-2001 Cronyx Engineering. 5218885Sdim * Author: Serge Vakulenko, <vak@cronyx.ru> 6218885Sdim * 7218885Sdim * Copyright (C) 1998-2003 Cronyx Engineering. 8218885Sdim * Author: Roman Kurakin, <rik@cronyx.ru> 9218885Sdim * 10218885Sdim * This software is distributed with NO WARRANTIES, not even the implied 11218885Sdim * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 12218885Sdim * 13218885Sdim * Authors grant any other persons or organisations permission to use 14235633Sdim * or modify this software as long as this message is kept with the software, 15218885Sdim * all derivative works or modified versions. 16218885Sdim * 17218885Sdim * Cronyx Id: cxddk.h,v 1.1.2.1 2003/11/12 17:13:41 rik Exp $ 18218885Sdim * $FreeBSD$ 19218885Sdim */ 20218885Sdim 21245431Sdim#ifndef port_t 22245431Sdim# ifdef _M_ALPHA /* port address on Alpha under */ 23245431Sdim# define port_t unsigned long /* Windows NT is 32 bit long */ 24245431Sdim# else 25245431Sdim# define port_t unsigned short /* all other architectures */ 26245431Sdim# endif /* have 16-bit port addresses */ 27245431Sdim#endif 28245431Sdim 29245431Sdim#define NBRD 3 /* the max number of installed boards */ 30245431Sdim#define NPORT 32 /* the number of i/o ports per board */ 31245431Sdim#define DMABUFSZ 1600 32245431Sdim 33245431Sdim/* 34245431Sdim * Asynchronous channel mode ------------------------------------------------- 35245431Sdim */ 36245431Sdim 37245431Sdim/* Parity */ 38245431Sdim#define PAR_EVEN 0 /* even parity */ 39245431Sdim#define PAR_ODD 1 /* odd parity */ 40245431Sdim 41245431Sdim/* Parity mode */ 42245431Sdim#define PARM_NOPAR 0 /* no parity */ 43245431Sdim#define PARM_FORCE 1 /* force parity (odd = force 1, even = 0) */ 44245431Sdim#define PARM_NORMAL 2 /* normal parity */ 45245431Sdim 46245431Sdim/* Flow control transparency mode */ 47245431Sdim#define FLOWCC_PASS 0 /* pass flow ctl chars as exceptions */ 48245431Sdim#define FLOWCC_NOTPASS 1 /* don't pass flow ctl chars to the host */ 49245431Sdim 50245431Sdim/* Stop bit length */ 51245431Sdim#define STOPB_1 2 /* 1 stop bit */ 52235633Sdim#define STOPB_15 3 /* 1.5 stop bits */ 53235633Sdim#define STOPB_2 4 /* 2 stop bits */ 54245431Sdim 55245431Sdim/* Action on break condition */ 56245431Sdim#define BRK_INTR 0 /* generate an exception interrupt */ 57245431Sdim#define BRK_NULL 1 /* translate to a NULL character */ 58245431Sdim#define BRK_RESERVED 2 /* reserved */ 59245431Sdim#define BRK_DISCARD 3 /* discard character */ 60245431Sdim 61245431Sdim/* Parity/framing error actions */ 62235633Sdim#define PERR_INTR 0 /* generate an exception interrupt */ 63235633Sdim#define PERR_NULL 1 /* translate to a NULL character */ 64235633Sdim#define PERR_IGNORE 2 /* ignore error; char passed as good data */ 65235633Sdim#define PERR_DISCARD 3 /* discard error character */ 66245431Sdim#define PERR_FFNULL 5 /* translate to FF NULL char */ 67245431Sdim 68245431Sdimtypedef struct { /* async channel option register 1 */ 69245431Sdim unsigned charlen : 4; /* character length, 5..8 */ 70245431Sdim unsigned ignpar : 1; /* ignore parity */ 71245431Sdim unsigned parmode : 2; /* parity mode */ 72245431Sdim unsigned parity : 1; /* parity */ 73245431Sdim} cx_cor1_async_t; 74235633Sdim 75235633Sdimtypedef struct { /* async channel option register 2 */ 76235633Sdim unsigned dsrae : 1; /* DSR automatic enable */ 77235633Sdim unsigned ctsae : 1; /* CTS automatic enable */ 78235633Sdim unsigned rtsao : 1; /* RTS automatic output enable */ 79235633Sdim unsigned rlm : 1; /* remote loopback mode enable */ 80245431Sdim unsigned zero : 1; 81245431Sdim unsigned etc : 1; /* embedded transmitter cmd enable */ 82235633Sdim unsigned ixon : 1; /* in-band XON/XOFF enable */ 83235633Sdim unsigned ixany : 1; /* XON on any character */ 84245431Sdim} cx_cor2_async_t; 85245431Sdim 86245431Sdimtypedef struct { /* async channel option register 3 */ 87245431Sdim unsigned stopb : 3; /* stop bit length */ 88245431Sdim unsigned zero : 1; 89245431Sdim unsigned scde : 1; /* special char detection enable */ 90245431Sdim unsigned flowct : 1; /* flow control transparency mode */ 91245431Sdim unsigned rngde : 1; /* range detect enable */ 92245431Sdim unsigned escde : 1; /* extended spec. char detect enable */ 93245431Sdim} cx_cor3_async_t; 94245431Sdim 95245431Sdimtypedef struct { /* async channel option register 6 */ 96245431Sdim unsigned parerr : 3; /* parity/framing error actions */ 97245431Sdim unsigned brk : 2; /* action on break condition */ 98245431Sdim unsigned inlcr : 1; /* translate NL to CR on input */ 99245431Sdim unsigned icrnl : 1; /* translate CR to NL on input */ 100245431Sdim unsigned igncr : 1; /* discard CR on input */ 101245431Sdim} cx_cor6_async_t; 102235633Sdim 103235633Sdimtypedef struct { /* async channel option register 7 */ 104245431Sdim unsigned ocrnl : 1; /* translate CR to NL on output */ 105245431Sdim unsigned onlcr : 1; /* translate NL to CR on output */ 106235633Sdim unsigned zero : 3; 107235633Sdim unsigned fcerr : 1; /* process flow ctl err chars enable */ 108235633Sdim unsigned lnext : 1; /* LNext option enable */ 109235633Sdim unsigned istrip : 1; /* strip 8-bit on input */ 110235633Sdim} cx_cor7_async_t; 111235633Sdim 112235633Sdimtypedef struct { /* async channel options */ 113235633Sdim cx_cor1_async_t cor1; /* channel option register 1 */ 114235633Sdim cx_cor2_async_t cor2; /* channel option register 2 */ 115235633Sdim cx_cor3_async_t cor3; /* option register 3 */ 116235633Sdim cx_cor6_async_t cor6; /* channel option register 6 */ 117235633Sdim cx_cor7_async_t cor7; /* channel option register 7 */ 118235633Sdim unsigned char schr1; /* special character register 1 (XON) */ 119235633Sdim unsigned char schr2; /* special character register 2 (XOFF) */ 120245431Sdim unsigned char schr3; /* special character register 3 */ 121245431Sdim unsigned char schr4; /* special character register 4 */ 122235633Sdim unsigned char scrl; /* special character range low */ 123235633Sdim unsigned char scrh; /* special character range high */ 124245431Sdim unsigned char lnxt; /* LNext character */ 125245431Sdim} cx_opt_async_t; 126235633Sdim 127235633Sdim/* 128245431Sdim * HDLC channel mode --------------------------------------------------------- 129245431Sdim */ 130245431Sdim/* Address field length option */ 131245431Sdim#define AFLO_1OCT 0 /* address field is 1 octet in length */ 132245431Sdim#define AFLO_2OCT 1 /* address field is 2 octet in length */ 133245431Sdim 134235633Sdim/* Clear detect for X.21 data transfer phase */ 135235633Sdim#define CLRDET_DISABLE 0 /* clear detect disabled */ 136245431Sdim#define CLRDET_ENABLE 1 /* clear detect enabled */ 137245431Sdim 138235633Sdim/* Addressing mode */ 139235633Sdim#define ADMODE_NOADDR 0 /* no address */ 140245431Sdim#define ADMODE_4_1 1 /* 4 * 1 byte */ 141245431Sdim#define ADMODE_2_2 2 /* 2 * 2 byte */ 142245431Sdim 143245431Sdim/* FCS append */ 144235633Sdim#define FCS_NOTPASS 0 /* receive CRC is not passed to the host */ 145235633Sdim#define FCS_PASS 1 /* receive CRC is passed to the host */ 146245431Sdim 147245431Sdim/* CRC modes */ 148235633Sdim#define CRC_INVERT 0 /* CRC is transmitted inverted (CRC V.41) */ 149235633Sdim#define CRC_DONT_INVERT 1 /* CRC is not transmitted inverted (CRC-16) */ 150235633Sdim 151235633Sdim/* Send sync pattern */ 152245431Sdim#define SYNC_00 0 /* send 00h as pad char (NRZI encoding) */ 153245431Sdim#define SYNC_AA 1 /* send AAh (Manchester/NRZ encoding) */ 154235633Sdim 155235633Sdim/* FCS preset */ 156245431Sdim#define FCSP_ONES 0 /* FCS is preset to all ones (CRC V.41) */ 157245431Sdim#define FCSP_ZEROS 1 /* FCS is preset to all zeros (CRC-16) */ 158235633Sdim 159235633Sdim/* idle mode */ 160245431Sdim#define IDLE_FLAG 0 /* idle in flag */ 161245431Sdim#define IDLE_MARK 1 /* idle in mark */ 162235633Sdim 163235633Sdim/* CRC polynomial select */ 164235633Sdim#define POLY_V41 0 /* x^16+x^12+x^5+1 (HDLC, preset to 1) */ 165235633Sdim#define POLY_16 1 /* x^16+x^15+x^2+1 (bisync, preset to 0) */ 166245431Sdim 167245431Sdimtypedef struct { /* hdlc channel option register 1 */ 168235633Sdim unsigned ifflags : 4; /* number of inter-frame flags sent */ 169235633Sdim unsigned admode : 2; /* addressing mode */ 170245431Sdim unsigned clrdet : 1; /* clear detect for X.21 data transfer phase */ 171245431Sdim unsigned aflo : 1; /* address field length option */ 172235633Sdim} cx_cor1_hdlc_t; 173235633Sdim 174245431Sdimtypedef struct { /* hdlc channel option register 2 */ 175245431Sdim unsigned dsrae : 1; /* DSR automatic enable */ 176235633Sdim unsigned ctsae : 1; /* CTS automatic enable */ 177235633Sdim unsigned rtsao : 1; /* RTS automatic output enable */ 178235633Sdim unsigned zero1 : 1; 179235633Sdim unsigned crcninv : 1; /* CRC invertion option */ 180235633Sdim unsigned zero2 : 1; 181235633Sdim unsigned fcsapd : 1; /* FCS append */ 182235633Sdim unsigned zero3 : 1; 183235633Sdim} cx_cor2_hdlc_t; 184235633Sdim 185245431Sdimtypedef struct { /* hdlc channel option register 3 */ 186245431Sdim unsigned padcnt : 3; /* pad character count */ 187235633Sdim unsigned idle : 1; /* idle mode */ 188235633Sdim unsigned nofcs : 1; /* FCS disable */ 189235633Sdim unsigned fcspre : 1; /* FCS preset */ 190235633Sdim unsigned syncpat : 1; /* send sync pattern */ 191245431Sdim unsigned sndpad : 1; /* send pad characters before flag enable */ 192245431Sdim} cx_cor3_hdlc_t; 193235633Sdim 194235633Sdimtypedef struct { /* hdlc channel options */ 195245431Sdim cx_cor1_hdlc_t cor1; /* hdlc channel option register 1 */ 196245431Sdim cx_cor2_hdlc_t cor2; /* hdlc channel option register 2 */ 197245431Sdim cx_cor3_hdlc_t cor3; /* hdlc channel option register 3 */ 198245431Sdim unsigned char rfar1; /* receive frame address register 1 */ 199245431Sdim unsigned char rfar2; /* receive frame address register 2 */ 200245431Sdim unsigned char rfar3; /* receive frame address register 3 */ 201245431Sdim unsigned char rfar4; /* receive frame address register 4 */ 202245431Sdim unsigned char cpsr; /* CRC polynomial select */ 203245431Sdim} cx_opt_hdlc_t; 204245431Sdim 205245431Sdim/* 206245431Sdim * CD2400 channel state structure -------------------------------------------- 207245431Sdim */ 208245431Sdim 209245431Sdim/* Signal encoding */ 210245431Sdim#define ENCOD_NRZ 0 /* NRZ mode */ 211245431Sdim#define ENCOD_NRZI 1 /* NRZI mode */ 212245431Sdim#define ENCOD_MANCHESTER 2 /* Manchester mode */ 213245431Sdim 214245431Sdim/* Clock source */ 215245431Sdim#define CLK_0 0 /* clock 0 */ 216245431Sdim#define CLK_1 1 /* clock 1 */ 217235633Sdim#define CLK_2 2 /* clock 2 */ 218235633Sdim#define CLK_3 3 /* clock 3 */ 219235633Sdim#define CLK_4 4 /* clock 4 */ 220235633Sdim#define CLK_EXT 6 /* external clock */ 221218885Sdim#define CLK_RCV 7 /* receive clock */ 222218885Sdim 223218885Sdim/* Board type */ 224218885Sdim#define B_SIGMA_XXX 0 /* old Sigmas */ 225235633Sdim#define B_SIGMA_2X 1 /* Sigma-22 */ 226235633Sdim#define B_SIGMA_800 2 /* Sigma-800 */ 227235633Sdim 228235633Sdim/* Channel type */ 229235633Sdim#define T_NONE 0 /* no channel */ 230235633Sdim#define T_ASYNC 1 /* pure asynchronous RS-232 channel */ 231245431Sdim#define T_SYNC_RS232 2 /* pure synchronous RS-232 channel */ 232245431Sdim#define T_SYNC_V35 3 /* pure synchronous V.35 channel */ 233235633Sdim#define T_SYNC_RS449 4 /* pure synchronous RS-449 channel */ 234235633Sdim#define T_UNIV_RS232 5 /* sync/async RS-232 channel */ 235235633Sdim#define T_UNIV_RS449 6 /* sync/async RS-232/RS-449 channel */ 236235633Sdim#define T_UNIV_V35 7 /* sync/async RS-232/V.35 channel */ 237235633Sdim#define T_UNIV 8 /* sync/async, unknown interface */ 238235633Sdim 239245431Sdim#define M_ASYNC 0 /* asynchronous mode */ 240245431Sdim#define M_HDLC 1 /* bit-sync mode (HDLC) */ 241245431Sdim 242245431Sdimtypedef struct { /* channel option register 4 */ 243245431Sdim unsigned thr : 4; /* FIFO threshold */ 244245431Sdim unsigned zero : 1; 245245431Sdim unsigned cts_zd : 1; /* detect 1 to 0 transition on the CTS */ 246245431Sdim unsigned cd_zd : 1; /* detect 1 to 0 transition on the CD */ 247235633Sdim unsigned dsr_zd : 1; /* detect 1 to 0 transition on the DSR */ 248235633Sdim} cx_cor4_t; 249235633Sdim 250235633Sdimtypedef struct { /* channel option register 5 */ 251235633Sdim unsigned rx_thr : 4; /* receive flow control FIFO threshold */ 252235633Sdim unsigned zero : 1; 253235633Sdim unsigned cts_od : 1; /* detect 0 to 1 transition on the CTS */ 254235633Sdim unsigned cd_od : 1; /* detect 0 to 1 transition on the CD */ 255235633Sdim unsigned dsr_od : 1; /* detect 0 to 1 transition on the DSR */ 256235633Sdim} cx_cor5_t; 257235633Sdim 258235633Sdimtypedef struct { /* receive clock option register */ 259235633Sdim unsigned clk : 3; /* receive clock source */ 260235633Sdim unsigned encod : 2; /* signal encoding NRZ/NRZI/Manchester */ 261235633Sdim unsigned dpll : 1; /* DPLL enable */ 262235633Sdim unsigned zero : 1; 263235633Sdim unsigned tlval : 1; /* transmit line value */ 264235633Sdim} cx_rcor_t; 265245431Sdim 266245431Sdimtypedef struct { /* transmit clock option register */ 267235633Sdim unsigned zero1 : 1; 268235633Sdim unsigned llm : 1; /* local loopback mode */ 269245431Sdim unsigned zero2 : 1; 270245431Sdim unsigned ext1x : 1; /* external 1x clock mode */ 271221345Sdim unsigned zero3 : 1; 272221345Sdim unsigned clk : 3; /* transmit clock source */ 273235633Sdim} cx_tcor_t; 274235633Sdim 275245431Sdimtypedef struct { 276245431Sdim cx_cor4_t cor4; /* channel option register 4 */ 277235633Sdim cx_cor5_t cor5; /* channel option register 5 */ 278235633Sdim cx_rcor_t rcor; /* receive clock option register */ 279245431Sdim cx_tcor_t tcor; /* transmit clock option register */ 280245431Sdim} cx_chan_opt_t; 281245431Sdim 282245431Sdimtypedef enum { /* line break mode */ 283245431Sdim BRK_IDLE, /* normal line mode */ 284245431Sdim BRK_SEND, /* start sending break */ 285245431Sdim BRK_STOP, /* stop sending break */ 286245431Sdim} cx_break_t; 287245431Sdim 288245431Sdim#define BUS_NORMAL 0 /* normal bus timing */ 289245431Sdim#define BUS_FAST 1 /* fast bus timing (Sigma-22 and -800) */ 290245431Sdim#define BUS_FAST2 2 /* fast bus timing (Sigma-800) */ 291245431Sdim#define BUS_FAST3 3 /* fast bus timing (Sigma-800) */ 292245431Sdim 293245431Sdimtypedef struct { /* board options */ 294245431Sdim unsigned char fast; /* bus master timing (Sigma-22 and -800) */ 295245431Sdim} cx_board_opt_t; 296245431Sdim 297245431Sdim#define NCHIP 4 /* the number of controllers per board */ 298245431Sdim#define NCHAN 16 /* the number of channels on the board */ 299245431Sdim 300245431Sdimtypedef struct { 301245431Sdim unsigned char tbuffer [2] [DMABUFSZ]; 302245431Sdim unsigned char rbuffer [2] [DMABUFSZ]; 303245431Sdim} cx_buf_t; 304245431Sdim 305245431Sdimtypedef struct _cx_chan_t { 306245431Sdim struct _cx_board_t *board; /* board pointer */ 307245431Sdim unsigned char type; /* channel type */ 308245431Sdim unsigned char num; /* channel number, 0..15 */ 309245431Sdim port_t port; /* base port address */ 310245431Sdim unsigned long oscfreq; /* oscillator frequency in Hz */ 311245431Sdim unsigned long rxbaud; /* receiver speed */ 312245431Sdim unsigned long txbaud; /* transmitter speed */ 313245431Sdim unsigned char mode; /* channel mode */ 314245431Sdim cx_chan_opt_t opt; /* common channel options */ 315245431Sdim cx_opt_async_t aopt; /* async mode options */ 316245431Sdim cx_opt_hdlc_t hopt; /* hdlc mode options */ 317245431Sdim unsigned char *arbuf; /* receiver A dma buffer */ 318245431Sdim unsigned char *brbuf; /* receiver B dma buffer */ 319245431Sdim unsigned char *atbuf; /* transmitter A dma buffer */ 320245431Sdim unsigned char *btbuf; /* transmitter B dma buffer */ 321245431Sdim unsigned long arphys; /* receiver A phys address */ 322245431Sdim unsigned long brphys; /* receiver B phys address */ 323245431Sdim unsigned long atphys; /* transmitter A phys address */ 324245431Sdim unsigned long btphys; /* transmitter B phys address */ 325245431Sdim unsigned char dtr; /* DTR signal value */ 326245431Sdim unsigned char rts; /* RTS signal value */ 327245431Sdim 328235633Sdim unsigned long rintr; /* receive interrupts */ 329235633Sdim unsigned long tintr; /* transmit interrupts */ 330235633Sdim unsigned long mintr; /* modem interrupts */ 331235633Sdim unsigned long ibytes; /* input bytes */ 332235633Sdim unsigned long ipkts; /* input packets */ 333235633Sdim unsigned long ierrs; /* input errors */ 334245431Sdim unsigned long obytes; /* output bytes */ 335245431Sdim unsigned long opkts; /* output packets */ 336235633Sdim unsigned long oerrs; /* output errors */ 337235633Sdim 338245431Sdim void *sys; 339245431Sdim int debug; 340235633Sdim int debug_shadow; 341235633Sdim void *attach [2]; 342235633Sdim char *received_data; 343235633Sdim int received_len; 344235633Sdim int overflow; 345235633Sdim 346245431Sdim void (*call_on_rx) (struct _cx_chan_t*, char*, int); 347245431Sdim void (*call_on_tx) (struct _cx_chan_t*, void*, int); 348235633Sdim void (*call_on_msig) (struct _cx_chan_t*); 349218885Sdim void (*call_on_err) (struct _cx_chan_t*, int); 350218885Sdim 351218885Sdim} cx_chan_t; 352218885Sdim 353218885Sdimtypedef struct _cx_board_t { 354218885Sdim unsigned char type; /* board type */ 355218885Sdim unsigned char num; /* board number, 0..2 */ 356218885Sdim port_t port; /* base board port, 0..3f0 */ 357235633Sdim unsigned char irq; /* irq {3 5 7 10 11 12 15} */ 358235633Sdim unsigned char dma; /* DMA request {5 6 7} */ 359235633Sdim char name[16]; /* board version name */ 360235633Sdim unsigned char nuniv; /* number of universal channels */ 361235633Sdim unsigned char nsync; /* number of sync. channels */ 362235633Sdim unsigned char nasync; /* number of async. channels */ 363235633Sdim unsigned char if0type; /* chan0 interface RS-232/RS-449/V.35 */ 364235633Sdim unsigned char if8type; /* chan8 interface RS-232/RS-449/V.35 */ 365235633Sdim unsigned short bcr0; /* BCR0 image */ 366235633Sdim unsigned short bcr0b; /* BCR0b image */ 367235633Sdim unsigned short bcr1; /* BCR1 image */ 368235633Sdim unsigned short bcr1b; /* BCR1b image */ 369235633Sdim cx_board_opt_t opt; /* board options */ 370235633Sdim cx_chan_t chan[NCHAN]; /* channel structures */ 371235633Sdim void *sys; 372235633Sdim} cx_board_t; 373235633Sdim 374235633Sdimextern long cx_rxbaud, cx_txbaud; 375218885Sdimextern int cx_univ_mode, cx_sync_mode, cx_iftype; 376218885Sdim 377218885Sdimextern cx_chan_opt_t chan_opt_dflt; /* default mode-independent options */ 378218885Sdimextern cx_opt_async_t opt_async_dflt; /* default async options */ 379223017Sdimextern cx_opt_hdlc_t opt_hdlc_dflt; /* default hdlc options */ 380218885Sdimextern cx_board_opt_t board_opt_dflt; /* default board options */ 381245431Sdim 382245431Sdimstruct _cr_dat_tst; 383245431Sdimint cx_probe_board (port_t port, int irq, int dma); 384245431Sdimvoid cx_init (cx_board_t *b, int num, port_t port, int irq, int dma); 385218885Sdimvoid cx_init_board (cx_board_t *b, int num, port_t port, int irq, int dma, 386218885Sdim int chain, int rev, int osc, int mod, int rev2, int osc2, int mod2); 387218885Sdimvoid cx_init_2x (cx_board_t *b, int num, port_t port, int irq, int dma, 388235633Sdim int rev, int osc); 389218885Sdimvoid cx_init_800 (cx_board_t *b, int num, port_t port, int irq, int dma, 390218885Sdim int chain); 391245431Sdimint cx_download (port_t port, const unsigned char *firmware, long bits, 392245431Sdim const struct _cr_dat_tst *tst); 393245431Sdimint cx_setup_board (cx_board_t *b, const unsigned char *firmware, 394245431Sdim long bits, const struct _cr_dat_tst *tst); 395245431Sdimvoid cx_setup_chan (cx_chan_t *c); 396245431Sdimvoid cx_update_chan (cx_chan_t *c); 397245431Sdimvoid cx_set_dtr (cx_chan_t *c, int on); 398245431Sdimvoid cx_set_rts (cx_chan_t *c, int on); 399245431Sdimvoid cx_led (cx_board_t *b, int on); 400245431Sdimvoid cx_cmd (port_t base, int cmd); 401245431Sdimvoid cx_disable_dma (cx_board_t *b); 402245431Sdimvoid cx_reinit_board (cx_board_t *b); 403245431Sdimint cx_get_dsr (cx_chan_t *c); 404245431Sdimint cx_get_cts (cx_chan_t *c); 405245431Sdimint cx_get_cd (cx_chan_t *c); 406245431Sdimvoid cx_clock (long hz, long ba, int *clk, int *div); 407245431Sdim 408245431Sdim/* DDK errors */ 409245431Sdim#define CX_FRAME 1 410245431Sdim#define CX_CRC 2 411245431Sdim#define CX_OVERRUN 3 412245431Sdim#define CX_OVERFLOW 4 413245431Sdim#define CX_UNDERRUN 5 414245431Sdim#define CX_BREAK 6 415245431Sdim 416235633Sdim/* clock sources */ 417235633Sdim#define CX_CLK_INT 0 418235633Sdim#define CX_CLK_EXT 6 419235633Sdim#define CX_CLK_RCV 7 420235633Sdim#define CX_CLK_DPLL 8 421235633Sdim#define CX_CLK_DPLL_EXT 14 422235633Sdim 423235633Sdim/* functions dealing with interrupt vector in DOS */ 424235633Sdim#if defined (MSDOS) || defined (__MSDOS__) 425235633Sdimint ddk_int_alloc (int irq, void (*func)(), void *arg); 426218885Sdimint ddk_int_restore (int irq); 427218885Sdim#endif 428218885Sdim 429235633Sdimint cx_probe_irq (cx_board_t *b, int irq); 430218885Sdimvoid cx_int_handler (cx_board_t *b); 431218885Sdim 432218885Sdimint cx_find (port_t *board_ports); 433235633Sdimint cx_open_board (cx_board_t *b, int num, port_t port, int irq, int dma); 434218885Sdimvoid cx_close_board (cx_board_t *b); 435235633Sdim 436235633Sdimvoid cx_start_chan (cx_chan_t *c, cx_buf_t *cb, unsigned long phys); 437235633Sdim 438235633Sdim/* 439235633Sdim Set port type for old models of Sigma 440235633Sdim */ 441235633Sdimvoid cx_set_port (cx_chan_t *c, int iftype); 442235633Sdim 443235633Sdim/* 444235633Sdim Get port type for old models of Sigma 445235633Sdim -1 Fixed port type or auto detect 446218885Sdim 0 RS232 447218885Sdim 1 V35 448218885Sdim 2 RS449 449218885Sdim */ 450218885Sdimint cx_get_port (cx_chan_t *c); 451218885Sdim 452218885Sdimvoid cx_enable_receive (cx_chan_t *c, int on); 453218885Sdimvoid cx_enable_transmit (cx_chan_t *c, int on); 454int cx_receive_enabled (cx_chan_t *c); 455int cx_transmit_enabled (cx_chan_t *c); 456 457void cx_set_baud (cx_chan_t *, unsigned long baud); 458int cx_set_mode (cx_chan_t *c, int mode); 459void cx_set_loop (cx_chan_t *c, int on); 460void cx_set_nrzi (cx_chan_t *c, int nrzi); 461void cx_set_dpll (cx_chan_t *c, int on); 462 463unsigned long cx_get_baud (cx_chan_t *c); 464int cx_get_loop (cx_chan_t *c); 465int cx_get_nrzi (cx_chan_t *c); 466int cx_get_dpll (cx_chan_t *c); 467 468int cx_send_packet (cx_chan_t *c, char *data, int len, void *attachment); 469int cx_buf_free (cx_chan_t *c); 470 471void cx_register_transmit (cx_chan_t *c, 472 void (*func) (cx_chan_t *c, void *attachment, int len)); 473void cx_register_receive (cx_chan_t *c, 474 void (*func) (cx_chan_t *c, char *data, int len)); 475void cx_register_modem (cx_chan_t *c, void (*func) (cx_chan_t *c)); 476void cx_register_error (cx_chan_t *c, void (*func) (cx_chan_t *c, int data)); 477void cx_intr_off (cx_board_t *b); 478void cx_intr_on (cx_board_t *b); 479int cx_checkintr (cx_board_t *b); 480 481/* Async functions */ 482void cx_transmitter_ctl (cx_chan_t *c, int start); 483void cx_flush_transmit (cx_chan_t *c); 484void cx_xflow_ctl (cx_chan_t *c, int on); 485void cx_send_break (cx_chan_t *c, int msec); 486void cx_set_async_param (cx_chan_t *c, int baud, int bits, int parity, 487 int stop2, int ignpar, int rtscts, 488 int ixon, int ixany, int symstart, int symstop); 489