if_ath.c revision 154735
1/*- 2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 3. Neither the names of the above-listed copyright holders nor the names 16 * of any contributors may be used to endorse or promote products derived 17 * from this software without specific prior written permission. 18 * 19 * Alternatively, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") version 2 as published by the Free 21 * Software Foundation. 22 * 23 * NO WARRANTY 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGES. 35 */ 36 37#include <sys/cdefs.h> 38__FBSDID("$FreeBSD: head/sys/dev/ath/if_ath.c 154735 2006-01-23 20:58:05Z sam $"); 39 40/* 41 * Driver for the Atheros Wireless LAN controller. 42 * 43 * This software is derived from work of Atsushi Onoe; his contribution 44 * is greatly appreciated. 45 */ 46 47#include "opt_inet.h" 48 49#include <sys/param.h> 50#include <sys/systm.h> 51#include <sys/sysctl.h> 52#include <sys/mbuf.h> 53#include <sys/malloc.h> 54#include <sys/lock.h> 55#include <sys/mutex.h> 56#include <sys/kernel.h> 57#include <sys/socket.h> 58#include <sys/sockio.h> 59#include <sys/errno.h> 60#include <sys/callout.h> 61#include <sys/bus.h> 62#include <sys/endian.h> 63 64#include <machine/bus.h> 65 66#include <net/if.h> 67#include <net/if_dl.h> 68#include <net/if_media.h> 69#include <net/if_types.h> 70#include <net/if_arp.h> 71#include <net/ethernet.h> 72#include <net/if_llc.h> 73 74#include <net80211/ieee80211_var.h> 75 76#include <net/bpf.h> 77 78#ifdef INET 79#include <netinet/in.h> 80#include <netinet/if_ether.h> 81#endif 82 83#define AR_DEBUG 84#include <dev/ath/if_athvar.h> 85#include <contrib/dev/ath/ah_desc.h> 86#include <contrib/dev/ath/ah_devid.h> /* XXX for softled */ 87 88/* unaligned little endian access */ 89#define LE_READ_2(p) \ 90 ((u_int16_t) \ 91 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8))) 92#define LE_READ_4(p) \ 93 ((u_int32_t) \ 94 ((((u_int8_t *)(p))[0] ) | (((u_int8_t *)(p))[1] << 8) | \ 95 (((u_int8_t *)(p))[2] << 16) | (((u_int8_t *)(p))[3] << 24))) 96 97enum { 98 ATH_LED_TX, 99 ATH_LED_RX, 100 ATH_LED_POLL, 101}; 102 103static void ath_init(void *); 104static void ath_stop_locked(struct ifnet *); 105static void ath_stop(struct ifnet *); 106static void ath_start(struct ifnet *); 107static int ath_reset(struct ifnet *); 108static int ath_media_change(struct ifnet *); 109static void ath_watchdog(struct ifnet *); 110static int ath_ioctl(struct ifnet *, u_long, caddr_t); 111static void ath_fatal_proc(void *, int); 112static void ath_rxorn_proc(void *, int); 113static void ath_bmiss_proc(void *, int); 114static int ath_key_alloc(struct ieee80211com *, 115 const struct ieee80211_key *, 116 ieee80211_keyix *, ieee80211_keyix *); 117static int ath_key_delete(struct ieee80211com *, 118 const struct ieee80211_key *); 119static int ath_key_set(struct ieee80211com *, const struct ieee80211_key *, 120 const u_int8_t mac[IEEE80211_ADDR_LEN]); 121static void ath_key_update_begin(struct ieee80211com *); 122static void ath_key_update_end(struct ieee80211com *); 123static void ath_mode_init(struct ath_softc *); 124static void ath_setslottime(struct ath_softc *); 125static void ath_updateslot(struct ifnet *); 126static int ath_beaconq_setup(struct ath_hal *); 127static int ath_beacon_alloc(struct ath_softc *, struct ieee80211_node *); 128static void ath_beacon_setup(struct ath_softc *, struct ath_buf *); 129static void ath_beacon_proc(void *, int); 130static void ath_bstuck_proc(void *, int); 131static void ath_beacon_free(struct ath_softc *); 132static void ath_beacon_config(struct ath_softc *); 133static void ath_descdma_cleanup(struct ath_softc *sc, 134 struct ath_descdma *, ath_bufhead *); 135static int ath_desc_alloc(struct ath_softc *); 136static void ath_desc_free(struct ath_softc *); 137static struct ieee80211_node *ath_node_alloc(struct ieee80211_node_table *); 138static void ath_node_free(struct ieee80211_node *); 139static u_int8_t ath_node_getrssi(const struct ieee80211_node *); 140static int ath_rxbuf_init(struct ath_softc *, struct ath_buf *); 141static void ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 142 struct ieee80211_node *ni, 143 int subtype, int rssi, u_int32_t rstamp); 144static void ath_setdefantenna(struct ath_softc *, u_int); 145static void ath_rx_proc(void *, int); 146static struct ath_txq *ath_txq_setup(struct ath_softc*, int qtype, int subtype); 147static int ath_tx_setup(struct ath_softc *, int, int); 148static int ath_wme_update(struct ieee80211com *); 149static void ath_tx_cleanupq(struct ath_softc *, struct ath_txq *); 150static void ath_tx_cleanup(struct ath_softc *); 151static int ath_tx_start(struct ath_softc *, struct ieee80211_node *, 152 struct ath_buf *, struct mbuf *); 153static void ath_tx_proc_q0(void *, int); 154static void ath_tx_proc_q0123(void *, int); 155static void ath_tx_proc(void *, int); 156static int ath_chan_set(struct ath_softc *, struct ieee80211_channel *); 157static void ath_draintxq(struct ath_softc *); 158static void ath_stoprecv(struct ath_softc *); 159static int ath_startrecv(struct ath_softc *); 160static void ath_chan_change(struct ath_softc *, struct ieee80211_channel *); 161static void ath_next_scan(void *); 162static void ath_calibrate(void *); 163static int ath_newstate(struct ieee80211com *, enum ieee80211_state, int); 164static void ath_setup_stationkey(struct ieee80211_node *); 165static void ath_newassoc(struct ieee80211_node *, int); 166static int ath_getchannels(struct ath_softc *, u_int cc, 167 HAL_BOOL outdoor, HAL_BOOL xchanmode); 168static void ath_led_event(struct ath_softc *, int); 169static void ath_update_txpow(struct ath_softc *); 170 171static int ath_rate_setup(struct ath_softc *, u_int mode); 172static void ath_setcurmode(struct ath_softc *, enum ieee80211_phymode); 173 174static void ath_sysctlattach(struct ath_softc *); 175static void ath_bpfattach(struct ath_softc *); 176static void ath_announce(struct ath_softc *); 177 178SYSCTL_DECL(_hw_ath); 179 180/* XXX validate sysctl values */ 181static int ath_dwelltime = 200; /* 5 channels/second */ 182SYSCTL_INT(_hw_ath, OID_AUTO, dwell, CTLFLAG_RW, &ath_dwelltime, 183 0, "channel dwell time (ms) for AP/station scanning"); 184static int ath_calinterval = 30; /* calibrate every 30 secs */ 185SYSCTL_INT(_hw_ath, OID_AUTO, calibrate, CTLFLAG_RW, &ath_calinterval, 186 0, "chip calibration interval (secs)"); 187static int ath_outdoor = AH_TRUE; /* outdoor operation */ 188SYSCTL_INT(_hw_ath, OID_AUTO, outdoor, CTLFLAG_RD, &ath_outdoor, 189 0, "outdoor operation"); 190TUNABLE_INT("hw.ath.outdoor", &ath_outdoor); 191static int ath_xchanmode = AH_TRUE; /* extended channel use */ 192SYSCTL_INT(_hw_ath, OID_AUTO, xchanmode, CTLFLAG_RD, &ath_xchanmode, 193 0, "extended channel mode"); 194TUNABLE_INT("hw.ath.xchanmode", &ath_xchanmode); 195static int ath_countrycode = CTRY_DEFAULT; /* country code */ 196SYSCTL_INT(_hw_ath, OID_AUTO, countrycode, CTLFLAG_RD, &ath_countrycode, 197 0, "country code"); 198TUNABLE_INT("hw.ath.countrycode", &ath_countrycode); 199static int ath_regdomain = 0; /* regulatory domain */ 200SYSCTL_INT(_hw_ath, OID_AUTO, regdomain, CTLFLAG_RD, &ath_regdomain, 201 0, "regulatory domain"); 202 203#ifdef AR_DEBUG 204static int ath_debug = 0; 205SYSCTL_INT(_hw_ath, OID_AUTO, debug, CTLFLAG_RW, &ath_debug, 206 0, "control debugging printfs"); 207TUNABLE_INT("hw.ath.debug", &ath_debug); 208enum { 209 ATH_DEBUG_XMIT = 0x00000001, /* basic xmit operation */ 210 ATH_DEBUG_XMIT_DESC = 0x00000002, /* xmit descriptors */ 211 ATH_DEBUG_RECV = 0x00000004, /* basic recv operation */ 212 ATH_DEBUG_RECV_DESC = 0x00000008, /* recv descriptors */ 213 ATH_DEBUG_RATE = 0x00000010, /* rate control */ 214 ATH_DEBUG_RESET = 0x00000020, /* reset processing */ 215 ATH_DEBUG_MODE = 0x00000040, /* mode init/setup */ 216 ATH_DEBUG_BEACON = 0x00000080, /* beacon handling */ 217 ATH_DEBUG_WATCHDOG = 0x00000100, /* watchdog timeout */ 218 ATH_DEBUG_INTR = 0x00001000, /* ISR */ 219 ATH_DEBUG_TX_PROC = 0x00002000, /* tx ISR proc */ 220 ATH_DEBUG_RX_PROC = 0x00004000, /* rx ISR proc */ 221 ATH_DEBUG_BEACON_PROC = 0x00008000, /* beacon ISR proc */ 222 ATH_DEBUG_CALIBRATE = 0x00010000, /* periodic calibration */ 223 ATH_DEBUG_KEYCACHE = 0x00020000, /* key cache management */ 224 ATH_DEBUG_STATE = 0x00040000, /* 802.11 state transitions */ 225 ATH_DEBUG_NODE = 0x00080000, /* node management */ 226 ATH_DEBUG_LED = 0x00100000, /* led management */ 227 ATH_DEBUG_FATAL = 0x80000000, /* fatal errors */ 228 ATH_DEBUG_ANY = 0xffffffff 229}; 230#define IFF_DUMPPKTS(sc, m) \ 231 ((sc->sc_debug & (m)) || \ 232 (sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 233#define DPRINTF(sc, m, fmt, ...) do { \ 234 if (sc->sc_debug & (m)) \ 235 printf(fmt, __VA_ARGS__); \ 236} while (0) 237#define KEYPRINTF(sc, ix, hk, mac) do { \ 238 if (sc->sc_debug & ATH_DEBUG_KEYCACHE) \ 239 ath_keyprint(__func__, ix, hk, mac); \ 240} while (0) 241static void ath_printrxbuf(struct ath_buf *bf, int); 242static void ath_printtxbuf(struct ath_buf *bf, int); 243#else 244#define IFF_DUMPPKTS(sc, m) \ 245 ((sc->sc_ifp->if_flags & (IFF_DEBUG|IFF_LINK2)) == (IFF_DEBUG|IFF_LINK2)) 246#define DPRINTF(m, fmt, ...) 247#define KEYPRINTF(sc, k, ix, mac) 248#endif 249 250MALLOC_DEFINE(M_ATHDEV, "athdev", "ath driver dma buffers"); 251 252int 253ath_attach(u_int16_t devid, struct ath_softc *sc) 254{ 255 struct ifnet *ifp; 256 struct ieee80211com *ic = &sc->sc_ic; 257 struct ath_hal *ah = NULL; 258 HAL_STATUS status; 259 int error = 0, i; 260 261 DPRINTF(sc, ATH_DEBUG_ANY, "%s: devid 0x%x\n", __func__, devid); 262 263 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 264 if (ifp == NULL) { 265 device_printf(sc->sc_dev, "can not if_alloc()\n"); 266 error = ENOSPC; 267 goto bad; 268 } 269 270 /* set these up early for if_printf use */ 271 if_initname(ifp, device_get_name(sc->sc_dev), 272 device_get_unit(sc->sc_dev)); 273 274 ah = ath_hal_attach(devid, sc, sc->sc_st, sc->sc_sh, &status); 275 if (ah == NULL) { 276 if_printf(ifp, "unable to attach hardware; HAL status %u\n", 277 status); 278 error = ENXIO; 279 goto bad; 280 } 281 if (ah->ah_abi != HAL_ABI_VERSION) { 282 if_printf(ifp, "HAL ABI mismatch detected " 283 "(HAL:0x%x != driver:0x%x)\n", 284 ah->ah_abi, HAL_ABI_VERSION); 285 error = ENXIO; 286 goto bad; 287 } 288 sc->sc_ah = ah; 289 sc->sc_invalid = 0; /* ready to go, enable interrupt handling */ 290 291 /* 292 * Check if the MAC has multi-rate retry support. 293 * We do this by trying to setup a fake extended 294 * descriptor. MAC's that don't have support will 295 * return false w/o doing anything. MAC's that do 296 * support it will return true w/o doing anything. 297 */ 298 sc->sc_mrretry = ath_hal_setupxtxdesc(ah, NULL, 0,0, 0,0, 0,0); 299 300 /* 301 * Check if the device has hardware counters for PHY 302 * errors. If so we need to enable the MIB interrupt 303 * so we can act on stat triggers. 304 */ 305 if (ath_hal_hwphycounters(ah)) 306 sc->sc_needmib = 1; 307 308 /* 309 * Get the hardware key cache size. 310 */ 311 sc->sc_keymax = ath_hal_keycachesize(ah); 312 if (sc->sc_keymax > ATH_KEYMAX) { 313 if_printf(ifp, "Warning, using only %u of %u key cache slots\n", 314 ATH_KEYMAX, sc->sc_keymax); 315 sc->sc_keymax = ATH_KEYMAX; 316 } 317 /* 318 * Reset the key cache since some parts do not 319 * reset the contents on initial power up. 320 */ 321 for (i = 0; i < sc->sc_keymax; i++) 322 ath_hal_keyreset(ah, i); 323 /* 324 * Mark key cache slots associated with global keys 325 * as in use. If we knew TKIP was not to be used we 326 * could leave the +32, +64, and +32+64 slots free. 327 * XXX only for splitmic. 328 */ 329 for (i = 0; i < IEEE80211_WEP_NKID; i++) { 330 setbit(sc->sc_keymap, i); 331 setbit(sc->sc_keymap, i+32); 332 setbit(sc->sc_keymap, i+64); 333 setbit(sc->sc_keymap, i+32+64); 334 } 335 336 /* 337 * Collect the channel list using the default country 338 * code and including outdoor channels. The 802.11 layer 339 * is resposible for filtering this list based on settings 340 * like the phy mode. 341 */ 342 error = ath_getchannels(sc, ath_countrycode, 343 ath_outdoor, ath_xchanmode); 344 if (error != 0) 345 goto bad; 346 347 /* 348 * Setup rate tables for all potential media types. 349 */ 350 ath_rate_setup(sc, IEEE80211_MODE_11A); 351 ath_rate_setup(sc, IEEE80211_MODE_11B); 352 ath_rate_setup(sc, IEEE80211_MODE_11G); 353 ath_rate_setup(sc, IEEE80211_MODE_TURBO_A); 354 ath_rate_setup(sc, IEEE80211_MODE_TURBO_G); 355 /* NB: setup here so ath_rate_update is happy */ 356 ath_setcurmode(sc, IEEE80211_MODE_11A); 357 358 /* 359 * Allocate tx+rx descriptors and populate the lists. 360 */ 361 error = ath_desc_alloc(sc); 362 if (error != 0) { 363 if_printf(ifp, "failed to allocate descriptors: %d\n", error); 364 goto bad; 365 } 366 callout_init(&sc->sc_scan_ch, debug_mpsafenet ? CALLOUT_MPSAFE : 0); 367 callout_init(&sc->sc_cal_ch, CALLOUT_MPSAFE); 368 369 ATH_TXBUF_LOCK_INIT(sc); 370 371 TASK_INIT(&sc->sc_rxtask, 0, ath_rx_proc, sc); 372 TASK_INIT(&sc->sc_rxorntask, 0, ath_rxorn_proc, sc); 373 TASK_INIT(&sc->sc_fataltask, 0, ath_fatal_proc, sc); 374 TASK_INIT(&sc->sc_bmisstask, 0, ath_bmiss_proc, sc); 375 TASK_INIT(&sc->sc_bstucktask, 0, ath_bstuck_proc, sc); 376 377 /* 378 * Allocate hardware transmit queues: one queue for 379 * beacon frames and one data queue for each QoS 380 * priority. Note that the hal handles reseting 381 * these queues at the needed time. 382 * 383 * XXX PS-Poll 384 */ 385 sc->sc_bhalq = ath_beaconq_setup(ah); 386 if (sc->sc_bhalq == (u_int) -1) { 387 if_printf(ifp, "unable to setup a beacon xmit queue!\n"); 388 error = EIO; 389 goto bad2; 390 } 391 sc->sc_cabq = ath_txq_setup(sc, HAL_TX_QUEUE_CAB, 0); 392 if (sc->sc_cabq == NULL) { 393 if_printf(ifp, "unable to setup CAB xmit queue!\n"); 394 error = EIO; 395 goto bad2; 396 } 397 /* NB: insure BK queue is the lowest priority h/w queue */ 398 if (!ath_tx_setup(sc, WME_AC_BK, HAL_WME_AC_BK)) { 399 if_printf(ifp, "unable to setup xmit queue for %s traffic!\n", 400 ieee80211_wme_acnames[WME_AC_BK]); 401 error = EIO; 402 goto bad2; 403 } 404 if (!ath_tx_setup(sc, WME_AC_BE, HAL_WME_AC_BE) || 405 !ath_tx_setup(sc, WME_AC_VI, HAL_WME_AC_VI) || 406 !ath_tx_setup(sc, WME_AC_VO, HAL_WME_AC_VO)) { 407 /* 408 * Not enough hardware tx queues to properly do WME; 409 * just punt and assign them all to the same h/w queue. 410 * We could do a better job of this if, for example, 411 * we allocate queues when we switch from station to 412 * AP mode. 413 */ 414 if (sc->sc_ac2q[WME_AC_VI] != NULL) 415 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_VI]); 416 if (sc->sc_ac2q[WME_AC_BE] != NULL) 417 ath_tx_cleanupq(sc, sc->sc_ac2q[WME_AC_BE]); 418 sc->sc_ac2q[WME_AC_BE] = sc->sc_ac2q[WME_AC_BK]; 419 sc->sc_ac2q[WME_AC_VI] = sc->sc_ac2q[WME_AC_BK]; 420 sc->sc_ac2q[WME_AC_VO] = sc->sc_ac2q[WME_AC_BK]; 421 } 422 423 /* 424 * Special case certain configurations. Note the 425 * CAB queue is handled by these specially so don't 426 * include them when checking the txq setup mask. 427 */ 428 switch (sc->sc_txqsetup &~ (1<<sc->sc_cabq->axq_qnum)) { 429 case 0x01: 430 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0, sc); 431 break; 432 case 0x0f: 433 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc_q0123, sc); 434 break; 435 default: 436 TASK_INIT(&sc->sc_txtask, 0, ath_tx_proc, sc); 437 break; 438 } 439 440 /* 441 * Setup rate control. Some rate control modules 442 * call back to change the anntena state so expose 443 * the necessary entry points. 444 * XXX maybe belongs in struct ath_ratectrl? 445 */ 446 sc->sc_setdefantenna = ath_setdefantenna; 447 sc->sc_rc = ath_rate_attach(sc); 448 if (sc->sc_rc == NULL) { 449 error = EIO; 450 goto bad2; 451 } 452 453 sc->sc_blinking = 0; 454 sc->sc_ledstate = 1; 455 sc->sc_ledon = 0; /* low true */ 456 sc->sc_ledidle = (2700*hz)/1000; /* 2.7sec */ 457 callout_init(&sc->sc_ledtimer, CALLOUT_MPSAFE); 458 /* 459 * Auto-enable soft led processing for IBM cards and for 460 * 5211 minipci cards. Users can also manually enable/disable 461 * support with a sysctl. 462 */ 463 sc->sc_softled = (devid == AR5212_DEVID_IBM || devid == AR5211_DEVID); 464 if (sc->sc_softled) { 465 ath_hal_gpioCfgOutput(ah, sc->sc_ledpin); 466 ath_hal_gpioset(ah, sc->sc_ledpin, !sc->sc_ledon); 467 } 468 469 ifp->if_softc = sc; 470 ifp->if_flags = IFF_SIMPLEX | IFF_BROADCAST | IFF_MULTICAST; 471 ifp->if_start = ath_start; 472 ifp->if_watchdog = ath_watchdog; 473 ifp->if_ioctl = ath_ioctl; 474 ifp->if_init = ath_init; 475 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 476 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 477 IFQ_SET_READY(&ifp->if_snd); 478 479 ic->ic_ifp = ifp; 480 ic->ic_reset = ath_reset; 481 ic->ic_newassoc = ath_newassoc; 482 ic->ic_updateslot = ath_updateslot; 483 ic->ic_wme.wme_update = ath_wme_update; 484 /* XXX not right but it's not used anywhere important */ 485 ic->ic_phytype = IEEE80211_T_OFDM; 486 ic->ic_opmode = IEEE80211_M_STA; 487 ic->ic_caps = 488 IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ 489 | IEEE80211_C_HOSTAP /* hostap mode */ 490 | IEEE80211_C_MONITOR /* monitor mode */ 491 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 492 | IEEE80211_C_SHSLOT /* short slot time supported */ 493 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 494 ; 495 /* 496 * Query the hal to figure out h/w crypto support. 497 */ 498 if (ath_hal_ciphersupported(ah, HAL_CIPHER_WEP)) 499 ic->ic_caps |= IEEE80211_C_WEP; 500 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_OCB)) 501 ic->ic_caps |= IEEE80211_C_AES; 502 if (ath_hal_ciphersupported(ah, HAL_CIPHER_AES_CCM)) 503 ic->ic_caps |= IEEE80211_C_AES_CCM; 504 if (ath_hal_ciphersupported(ah, HAL_CIPHER_CKIP)) 505 ic->ic_caps |= IEEE80211_C_CKIP; 506 if (ath_hal_ciphersupported(ah, HAL_CIPHER_TKIP)) { 507 ic->ic_caps |= IEEE80211_C_TKIP; 508 /* 509 * Check if h/w does the MIC and/or whether the 510 * separate key cache entries are required to 511 * handle both tx+rx MIC keys. 512 */ 513 if (ath_hal_ciphersupported(ah, HAL_CIPHER_MIC)) 514 ic->ic_caps |= IEEE80211_C_TKIPMIC; 515 if (ath_hal_tkipsplit(ah)) 516 sc->sc_splitmic = 1; 517 } 518 sc->sc_hasclrkey = ath_hal_ciphersupported(ah, HAL_CIPHER_CLR); 519 sc->sc_mcastkey = ath_hal_getmcastkeysearch(ah); 520 /* 521 * TPC support can be done either with a global cap or 522 * per-packet support. The latter is not available on 523 * all parts. We're a bit pedantic here as all parts 524 * support a global cap. 525 */ 526 if (ath_hal_hastpc(ah) || ath_hal_hastxpowlimit(ah)) 527 ic->ic_caps |= IEEE80211_C_TXPMGT; 528 529 /* 530 * Mark WME capability only if we have sufficient 531 * hardware queues to do proper priority scheduling. 532 */ 533 if (sc->sc_ac2q[WME_AC_BE] != sc->sc_ac2q[WME_AC_BK]) 534 ic->ic_caps |= IEEE80211_C_WME; 535 /* 536 * Check for misc other capabilities. 537 */ 538 if (ath_hal_hasbursting(ah)) 539 ic->ic_caps |= IEEE80211_C_BURST; 540 541 /* 542 * Indicate we need the 802.11 header padded to a 543 * 32-bit boundary for 4-address and QoS frames. 544 */ 545 ic->ic_flags |= IEEE80211_F_DATAPAD; 546 547 /* 548 * Query the hal about antenna support. 549 */ 550 sc->sc_defant = ath_hal_getdefantenna(ah); 551 552 /* 553 * Not all chips have the VEOL support we want to 554 * use with IBSS beacons; check here for it. 555 */ 556 sc->sc_hasveol = ath_hal_hasveol(ah); 557 558 /* get mac address from hardware */ 559 ath_hal_getmac(ah, ic->ic_myaddr); 560 561 /* call MI attach routine. */ 562 ieee80211_ifattach(ic); 563 /* override default methods */ 564 ic->ic_node_alloc = ath_node_alloc; 565 sc->sc_node_free = ic->ic_node_free; 566 ic->ic_node_free = ath_node_free; 567 ic->ic_node_getrssi = ath_node_getrssi; 568 sc->sc_recv_mgmt = ic->ic_recv_mgmt; 569 ic->ic_recv_mgmt = ath_recv_mgmt; 570 sc->sc_newstate = ic->ic_newstate; 571 ic->ic_newstate = ath_newstate; 572 ic->ic_crypto.cs_max_keyix = sc->sc_keymax; 573 ic->ic_crypto.cs_key_alloc = ath_key_alloc; 574 ic->ic_crypto.cs_key_delete = ath_key_delete; 575 ic->ic_crypto.cs_key_set = ath_key_set; 576 ic->ic_crypto.cs_key_update_begin = ath_key_update_begin; 577 ic->ic_crypto.cs_key_update_end = ath_key_update_end; 578 /* complete initialization */ 579 ieee80211_media_init(ic, ath_media_change, ieee80211_media_status); 580 581 ath_bpfattach(sc); 582 /* 583 * Setup dynamic sysctl's now that country code and 584 * regdomain are available from the hal. 585 */ 586 ath_sysctlattach(sc); 587 588 if (bootverbose) 589 ieee80211_announce(ic); 590 ath_announce(sc); 591 return 0; 592bad2: 593 ath_tx_cleanup(sc); 594 ath_desc_free(sc); 595bad: 596 if (ah) 597 ath_hal_detach(ah); 598 if (ifp != NULL) 599 if_free(ifp); 600 sc->sc_invalid = 1; 601 return error; 602} 603 604int 605ath_detach(struct ath_softc *sc) 606{ 607 struct ifnet *ifp = sc->sc_ifp; 608 609 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 610 __func__, ifp->if_flags); 611 612 ath_stop(ifp); 613 bpfdetach(ifp); 614 /* 615 * NB: the order of these is important: 616 * o call the 802.11 layer before detaching the hal to 617 * insure callbacks into the driver to delete global 618 * key cache entries can be handled 619 * o reclaim the tx queue data structures after calling 620 * the 802.11 layer as we'll get called back to reclaim 621 * node state and potentially want to use them 622 * o to cleanup the tx queues the hal is called, so detach 623 * it last 624 * Other than that, it's straightforward... 625 */ 626 ieee80211_ifdetach(&sc->sc_ic); 627 ath_rate_detach(sc->sc_rc); 628 ath_desc_free(sc); 629 ath_tx_cleanup(sc); 630 ath_hal_detach(sc->sc_ah); 631 if_free(ifp); 632 633 return 0; 634} 635 636void 637ath_suspend(struct ath_softc *sc) 638{ 639 struct ifnet *ifp = sc->sc_ifp; 640 641 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 642 __func__, ifp->if_flags); 643 644 ath_stop(ifp); 645} 646 647void 648ath_resume(struct ath_softc *sc) 649{ 650 struct ifnet *ifp = sc->sc_ifp; 651 652 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 653 __func__, ifp->if_flags); 654 655 if (ifp->if_flags & IFF_UP) { 656 ath_init(sc); 657 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 658 ath_start(ifp); 659 } 660 if (sc->sc_softled) { 661 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin); 662 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 663 } 664} 665 666void 667ath_shutdown(struct ath_softc *sc) 668{ 669 struct ifnet *ifp = sc->sc_ifp; 670 671 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags %x\n", 672 __func__, ifp->if_flags); 673 674 ath_stop(ifp); 675} 676 677/* 678 * Interrupt handler. Most of the actual processing is deferred. 679 */ 680void 681ath_intr(void *arg) 682{ 683 struct ath_softc *sc = arg; 684 struct ifnet *ifp = sc->sc_ifp; 685 struct ath_hal *ah = sc->sc_ah; 686 HAL_INT status; 687 688 if (sc->sc_invalid) { 689 /* 690 * The hardware is not ready/present, don't touch anything. 691 * Note this can happen early on if the IRQ is shared. 692 */ 693 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid; ignored\n", __func__); 694 return; 695 } 696 if (!ath_hal_intrpend(ah)) /* shared irq, not for us */ 697 return; 698 if (!((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & 699 IFF_DRV_RUNNING))) { 700 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 701 __func__, ifp->if_flags); 702 ath_hal_getisr(ah, &status); /* clear ISR */ 703 ath_hal_intrset(ah, 0); /* disable further intr's */ 704 return; 705 } 706 /* 707 * Figure out the reason(s) for the interrupt. Note 708 * that the hal returns a pseudo-ISR that may include 709 * bits we haven't explicitly enabled so we mask the 710 * value to insure we only process bits we requested. 711 */ 712 ath_hal_getisr(ah, &status); /* NB: clears ISR too */ 713 DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x\n", __func__, status); 714 status &= sc->sc_imask; /* discard unasked for bits */ 715 if (status & HAL_INT_FATAL) { 716 /* 717 * Fatal errors are unrecoverable. Typically 718 * these are caused by DMA errors. Unfortunately 719 * the exact reason is not (presently) returned 720 * by the hal. 721 */ 722 sc->sc_stats.ast_hardware++; 723 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 724 taskqueue_enqueue(taskqueue_swi, &sc->sc_fataltask); 725 } else if (status & HAL_INT_RXORN) { 726 sc->sc_stats.ast_rxorn++; 727 ath_hal_intrset(ah, 0); /* disable intr's until reset */ 728 taskqueue_enqueue(taskqueue_swi, &sc->sc_rxorntask); 729 } else { 730 if (status & HAL_INT_SWBA) { 731 /* 732 * Software beacon alert--time to send a beacon. 733 * Handle beacon transmission directly; deferring 734 * this is too slow to meet timing constraints 735 * under load. 736 */ 737 ath_beacon_proc(sc, 0); 738 } 739 if (status & HAL_INT_RXEOL) { 740 /* 741 * NB: the hardware should re-read the link when 742 * RXE bit is written, but it doesn't work at 743 * least on older hardware revs. 744 */ 745 sc->sc_stats.ast_rxeol++; 746 sc->sc_rxlink = NULL; 747 } 748 if (status & HAL_INT_TXURN) { 749 sc->sc_stats.ast_txurn++; 750 /* bump tx trigger level */ 751 ath_hal_updatetxtriglevel(ah, AH_TRUE); 752 } 753 if (status & HAL_INT_RX) 754 taskqueue_enqueue(taskqueue_swi, &sc->sc_rxtask); 755 if (status & HAL_INT_TX) 756 taskqueue_enqueue(taskqueue_swi, &sc->sc_txtask); 757 if (status & HAL_INT_BMISS) { 758 sc->sc_stats.ast_bmiss++; 759 taskqueue_enqueue(taskqueue_swi, &sc->sc_bmisstask); 760 } 761 if (status & HAL_INT_MIB) { 762 sc->sc_stats.ast_mib++; 763 /* 764 * Disable interrupts until we service the MIB 765 * interrupt; otherwise it will continue to fire. 766 */ 767 ath_hal_intrset(ah, 0); 768 /* 769 * Let the hal handle the event. We assume it will 770 * clear whatever condition caused the interrupt. 771 */ 772 ath_hal_mibevent(ah, 773 &ATH_NODE(sc->sc_ic.ic_bss)->an_halstats); 774 ath_hal_intrset(ah, sc->sc_imask); 775 } 776 } 777} 778 779static void 780ath_fatal_proc(void *arg, int pending) 781{ 782 struct ath_softc *sc = arg; 783 struct ifnet *ifp = sc->sc_ifp; 784 785 if_printf(ifp, "hardware error; resetting\n"); 786 ath_reset(ifp); 787} 788 789static void 790ath_rxorn_proc(void *arg, int pending) 791{ 792 struct ath_softc *sc = arg; 793 struct ifnet *ifp = sc->sc_ifp; 794 795 if_printf(ifp, "rx FIFO overrun; resetting\n"); 796 ath_reset(ifp); 797} 798 799static void 800ath_bmiss_proc(void *arg, int pending) 801{ 802 struct ath_softc *sc = arg; 803 struct ieee80211com *ic = &sc->sc_ic; 804 805 DPRINTF(sc, ATH_DEBUG_ANY, "%s: pending %u\n", __func__, pending); 806 KASSERT(ic->ic_opmode == IEEE80211_M_STA, 807 ("unexpect operating mode %u", ic->ic_opmode)); 808 if (ic->ic_state == IEEE80211_S_RUN) { 809 /* 810 * Rather than go directly to scan state, try to 811 * reassociate first. If that fails then the state 812 * machine will drop us into scanning after timing 813 * out waiting for a probe response. 814 */ 815 NET_LOCK_GIANT(); 816 ieee80211_new_state(ic, IEEE80211_S_ASSOC, -1); 817 NET_UNLOCK_GIANT(); 818 } 819} 820 821static u_int 822ath_chan2flags(struct ieee80211com *ic, struct ieee80211_channel *chan) 823{ 824#define N(a) (sizeof(a) / sizeof(a[0])) 825 static const u_int modeflags[] = { 826 0, /* IEEE80211_MODE_AUTO */ 827 CHANNEL_A, /* IEEE80211_MODE_11A */ 828 CHANNEL_B, /* IEEE80211_MODE_11B */ 829 CHANNEL_PUREG, /* IEEE80211_MODE_11G */ 830 0, /* IEEE80211_MODE_FH */ 831 CHANNEL_T, /* IEEE80211_MODE_TURBO_A */ 832 CHANNEL_108G /* IEEE80211_MODE_TURBO_G */ 833 }; 834 enum ieee80211_phymode mode = ieee80211_chan2mode(ic, chan); 835 836 KASSERT(mode < N(modeflags), ("unexpected phy mode %u", mode)); 837 KASSERT(modeflags[mode] != 0, ("mode %u undefined", mode)); 838 return modeflags[mode]; 839#undef N 840} 841 842static void 843ath_init(void *arg) 844{ 845 struct ath_softc *sc = (struct ath_softc *) arg; 846 struct ieee80211com *ic = &sc->sc_ic; 847 struct ifnet *ifp = sc->sc_ifp; 848 struct ath_hal *ah = sc->sc_ah; 849 HAL_STATUS status; 850 851 DPRINTF(sc, ATH_DEBUG_ANY, "%s: if_flags 0x%x\n", 852 __func__, ifp->if_flags); 853 854 ATH_LOCK(sc); 855 /* 856 * Stop anything previously setup. This is safe 857 * whether this is the first time through or not. 858 */ 859 ath_stop_locked(ifp); 860 861 /* 862 * The basic interface to setting the hardware in a good 863 * state is ``reset''. On return the hardware is known to 864 * be powered up and with interrupts disabled. This must 865 * be followed by initialization of the appropriate bits 866 * and then setup of the interrupt mask. 867 */ 868 sc->sc_curchan.channel = ic->ic_curchan->ic_freq; 869 sc->sc_curchan.channelFlags = ath_chan2flags(ic, ic->ic_curchan); 870 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_FALSE, &status)) { 871 if_printf(ifp, "unable to reset hardware; hal status %u\n", 872 status); 873 goto done; 874 } 875 876 /* 877 * This is needed only to setup initial state 878 * but it's best done after a reset. 879 */ 880 ath_update_txpow(sc); 881 /* 882 * Likewise this is set during reset so update 883 * state cached in the driver. 884 */ 885 sc->sc_diversity = ath_hal_getdiversity(ah); 886 887 /* 888 * Setup the hardware after reset: the key cache 889 * is filled as needed and the receive engine is 890 * set going. Frame transmit is handled entirely 891 * in the frame output path; there's nothing to do 892 * here except setup the interrupt mask. 893 */ 894 if (ath_startrecv(sc) != 0) { 895 if_printf(ifp, "unable to start recv logic\n"); 896 goto done; 897 } 898 899 /* 900 * Enable interrupts. 901 */ 902 sc->sc_imask = HAL_INT_RX | HAL_INT_TX 903 | HAL_INT_RXEOL | HAL_INT_RXORN 904 | HAL_INT_FATAL | HAL_INT_GLOBAL; 905 /* 906 * Enable MIB interrupts when there are hardware phy counters. 907 * Note we only do this (at the moment) for station mode. 908 */ 909 if (sc->sc_needmib && ic->ic_opmode == IEEE80211_M_STA) 910 sc->sc_imask |= HAL_INT_MIB; 911 ath_hal_intrset(ah, sc->sc_imask); 912 913 ifp->if_drv_flags |= IFF_DRV_RUNNING; 914 ic->ic_state = IEEE80211_S_INIT; 915 916 /* 917 * The hardware should be ready to go now so it's safe 918 * to kick the 802.11 state machine as it's likely to 919 * immediately call back to us to send mgmt frames. 920 */ 921 ath_chan_change(sc, ic->ic_curchan); 922 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 923 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 924 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1); 925 } else 926 ieee80211_new_state(ic, IEEE80211_S_RUN, -1); 927done: 928 ATH_UNLOCK(sc); 929} 930 931static void 932ath_stop_locked(struct ifnet *ifp) 933{ 934 struct ath_softc *sc = ifp->if_softc; 935 struct ieee80211com *ic = &sc->sc_ic; 936 struct ath_hal *ah = sc->sc_ah; 937 938 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid %u if_flags 0x%x\n", 939 __func__, sc->sc_invalid, ifp->if_flags); 940 941 ATH_LOCK_ASSERT(sc); 942 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 943 /* 944 * Shutdown the hardware and driver: 945 * reset 802.11 state machine 946 * turn off timers 947 * disable interrupts 948 * turn off the radio 949 * clear transmit machinery 950 * clear receive machinery 951 * drain and release tx queues 952 * reclaim beacon resources 953 * power down hardware 954 * 955 * Note that some of this work is not possible if the 956 * hardware is gone (invalid). 957 */ 958 ieee80211_new_state(ic, IEEE80211_S_INIT, -1); 959 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 960 ifp->if_timer = 0; 961 if (!sc->sc_invalid) { 962 if (sc->sc_softled) { 963 callout_stop(&sc->sc_ledtimer); 964 ath_hal_gpioset(ah, sc->sc_ledpin, 965 !sc->sc_ledon); 966 sc->sc_blinking = 0; 967 } 968 ath_hal_intrset(ah, 0); 969 } 970 ath_draintxq(sc); 971 if (!sc->sc_invalid) { 972 ath_stoprecv(sc); 973 ath_hal_phydisable(ah); 974 } else 975 sc->sc_rxlink = NULL; 976 IFQ_DRV_PURGE(&ifp->if_snd); 977 ath_beacon_free(sc); 978 } 979} 980 981static void 982ath_stop(struct ifnet *ifp) 983{ 984 struct ath_softc *sc = ifp->if_softc; 985 986 ATH_LOCK(sc); 987 ath_stop_locked(ifp); 988 if (!sc->sc_invalid) { 989 /* 990 * Set the chip in full sleep mode. Note that we are 991 * careful to do this only when bringing the interface 992 * completely to a stop. When the chip is in this state 993 * it must be carefully woken up or references to 994 * registers in the PCI clock domain may freeze the bus 995 * (and system). This varies by chip and is mostly an 996 * issue with newer parts that go to sleep more quickly. 997 */ 998 ath_hal_setpower(sc->sc_ah, HAL_PM_FULL_SLEEP, 0); 999 } 1000 ATH_UNLOCK(sc); 1001} 1002 1003/* 1004 * Reset the hardware w/o losing operational state. This is 1005 * basically a more efficient way of doing ath_stop, ath_init, 1006 * followed by state transitions to the current 802.11 1007 * operational state. Used to recover from various errors and 1008 * to reset or reload hardware state. 1009 */ 1010static int 1011ath_reset(struct ifnet *ifp) 1012{ 1013 struct ath_softc *sc = ifp->if_softc; 1014 struct ieee80211com *ic = &sc->sc_ic; 1015 struct ath_hal *ah = sc->sc_ah; 1016 struct ieee80211_channel *c; 1017 HAL_STATUS status; 1018 1019 /* 1020 * Convert to a HAL channel description with the flags 1021 * constrained to reflect the current operating mode. 1022 */ 1023 c = ic->ic_curchan; 1024 sc->sc_curchan.channel = c->ic_freq; 1025 sc->sc_curchan.channelFlags = ath_chan2flags(ic, c); 1026 1027 ath_hal_intrset(ah, 0); /* disable interrupts */ 1028 ath_draintxq(sc); /* stop xmit side */ 1029 ath_stoprecv(sc); /* stop recv side */ 1030 /* NB: indicate channel change so we do a full reset */ 1031 if (!ath_hal_reset(ah, ic->ic_opmode, &sc->sc_curchan, AH_TRUE, &status)) 1032 if_printf(ifp, "%s: unable to reset hardware; hal status %u\n", 1033 __func__, status); 1034 ath_update_txpow(sc); /* update tx power state */ 1035 sc->sc_diversity = ath_hal_getdiversity(ah); 1036 if (ath_startrecv(sc) != 0) /* restart recv */ 1037 if_printf(ifp, "%s: unable to start recv logic\n", __func__); 1038 /* 1039 * We may be doing a reset in response to an ioctl 1040 * that changes the channel so update any state that 1041 * might change as a result. 1042 */ 1043 ath_chan_change(sc, c); 1044 if (ic->ic_state == IEEE80211_S_RUN) 1045 ath_beacon_config(sc); /* restart beacons */ 1046 ath_hal_intrset(ah, sc->sc_imask); 1047 1048 ath_start(ifp); /* restart xmit */ 1049 return 0; 1050} 1051 1052static void 1053ath_start(struct ifnet *ifp) 1054{ 1055 struct ath_softc *sc = ifp->if_softc; 1056 struct ath_hal *ah = sc->sc_ah; 1057 struct ieee80211com *ic = &sc->sc_ic; 1058 struct ieee80211_node *ni; 1059 struct ath_buf *bf; 1060 struct mbuf *m; 1061 struct ieee80211_frame *wh; 1062 struct ether_header *eh; 1063 1064 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) 1065 return; 1066 for (;;) { 1067 /* 1068 * Grab a TX buffer and associated resources. 1069 */ 1070 ATH_TXBUF_LOCK(sc); 1071 bf = STAILQ_FIRST(&sc->sc_txbuf); 1072 if (bf != NULL) 1073 STAILQ_REMOVE_HEAD(&sc->sc_txbuf, bf_list); 1074 ATH_TXBUF_UNLOCK(sc); 1075 if (bf == NULL) { 1076 DPRINTF(sc, ATH_DEBUG_ANY, "%s: out of xmit buffers\n", 1077 __func__); 1078 sc->sc_stats.ast_tx_qstop++; 1079 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1080 break; 1081 } 1082 /* 1083 * Poll the management queue for frames; they 1084 * have priority over normal data frames. 1085 */ 1086 IF_DEQUEUE(&ic->ic_mgtq, m); 1087 if (m == NULL) { 1088 /* 1089 * No data frames go out unless we're associated. 1090 */ 1091 if (ic->ic_state != IEEE80211_S_RUN) { 1092 DPRINTF(sc, ATH_DEBUG_ANY, 1093 "%s: ignore data packet, state %u\n", 1094 __func__, ic->ic_state); 1095 sc->sc_stats.ast_tx_discard++; 1096 ATH_TXBUF_LOCK(sc); 1097 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1098 ATH_TXBUF_UNLOCK(sc); 1099 break; 1100 } 1101 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */ 1102 if (m == NULL) { 1103 ATH_TXBUF_LOCK(sc); 1104 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1105 ATH_TXBUF_UNLOCK(sc); 1106 break; 1107 } 1108 /* 1109 * Find the node for the destination so we can do 1110 * things like power save and fast frames aggregation. 1111 */ 1112 if (m->m_len < sizeof(struct ether_header) && 1113 (m = m_pullup(m, sizeof(struct ether_header))) == NULL) { 1114 ic->ic_stats.is_tx_nobuf++; /* XXX */ 1115 ni = NULL; 1116 goto bad; 1117 } 1118 eh = mtod(m, struct ether_header *); 1119 ni = ieee80211_find_txnode(ic, eh->ether_dhost); 1120 if (ni == NULL) { 1121 /* NB: ieee80211_find_txnode does stat+msg */ 1122 m_freem(m); 1123 goto bad; 1124 } 1125 if ((ni->ni_flags & IEEE80211_NODE_PWR_MGT) && 1126 (m->m_flags & M_PWR_SAV) == 0) { 1127 /* 1128 * Station in power save mode; pass the frame 1129 * to the 802.11 layer and continue. We'll get 1130 * the frame back when the time is right. 1131 */ 1132 ieee80211_pwrsave(ic, ni, m); 1133 goto reclaim; 1134 } 1135 /* calculate priority so we can find the tx queue */ 1136 if (ieee80211_classify(ic, m, ni)) { 1137 DPRINTF(sc, ATH_DEBUG_XMIT, 1138 "%s: discard, classification failure\n", 1139 __func__); 1140 m_freem(m); 1141 goto bad; 1142 } 1143 ifp->if_opackets++; 1144 BPF_MTAP(ifp, m); 1145 /* 1146 * Encapsulate the packet in prep for transmission. 1147 */ 1148 m = ieee80211_encap(ic, m, ni); 1149 if (m == NULL) { 1150 DPRINTF(sc, ATH_DEBUG_ANY, 1151 "%s: encapsulation failure\n", 1152 __func__); 1153 sc->sc_stats.ast_tx_encap++; 1154 goto bad; 1155 } 1156 } else { 1157 /* 1158 * Hack! The referenced node pointer is in the 1159 * rcvif field of the packet header. This is 1160 * placed there by ieee80211_mgmt_output because 1161 * we need to hold the reference with the frame 1162 * and there's no other way (other than packet 1163 * tags which we consider too expensive to use) 1164 * to pass it along. 1165 */ 1166 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1167 m->m_pkthdr.rcvif = NULL; 1168 1169 wh = mtod(m, struct ieee80211_frame *); 1170 if ((wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1171 IEEE80211_FC0_SUBTYPE_PROBE_RESP) { 1172 /* fill time stamp */ 1173 u_int64_t tsf; 1174 u_int32_t *tstamp; 1175 1176 tsf = ath_hal_gettsf64(ah); 1177 /* XXX: adjust 100us delay to xmit */ 1178 tsf += 100; 1179 tstamp = (u_int32_t *)&wh[1]; 1180 tstamp[0] = htole32(tsf & 0xffffffff); 1181 tstamp[1] = htole32(tsf >> 32); 1182 } 1183 sc->sc_stats.ast_tx_mgmt++; 1184 } 1185 1186 if (ath_tx_start(sc, ni, bf, m)) { 1187 bad: 1188 ifp->if_oerrors++; 1189 reclaim: 1190 ATH_TXBUF_LOCK(sc); 1191 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 1192 ATH_TXBUF_UNLOCK(sc); 1193 if (ni != NULL) 1194 ieee80211_free_node(ni); 1195 continue; 1196 } 1197 1198 sc->sc_tx_timer = 5; 1199 ifp->if_timer = 1; 1200 } 1201} 1202 1203static int 1204ath_media_change(struct ifnet *ifp) 1205{ 1206#define IS_UP(ifp) \ 1207 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 1208 int error; 1209 1210 error = ieee80211_media_change(ifp); 1211 if (error == ENETRESET) { 1212 if (IS_UP(ifp)) 1213 ath_init(ifp->if_softc); /* XXX lose error */ 1214 error = 0; 1215 } 1216 return error; 1217#undef IS_UP 1218} 1219 1220#ifdef AR_DEBUG 1221static void 1222ath_keyprint(const char *tag, u_int ix, 1223 const HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1224{ 1225 static const char *ciphers[] = { 1226 "WEP", 1227 "AES-OCB", 1228 "AES-CCM", 1229 "CKIP", 1230 "TKIP", 1231 "CLR", 1232 }; 1233 int i, n; 1234 1235 printf("%s: [%02u] %-7s ", tag, ix, ciphers[hk->kv_type]); 1236 for (i = 0, n = hk->kv_len; i < n; i++) 1237 printf("%02x", hk->kv_val[i]); 1238 printf(" mac %s", ether_sprintf(mac)); 1239 if (hk->kv_type == HAL_CIPHER_TKIP) { 1240 printf(" mic "); 1241 for (i = 0; i < sizeof(hk->kv_mic); i++) 1242 printf("%02x", hk->kv_mic[i]); 1243 } 1244 printf("\n"); 1245} 1246#endif 1247 1248/* 1249 * Set a TKIP key into the hardware. This handles the 1250 * potential distribution of key state to multiple key 1251 * cache slots for TKIP. 1252 */ 1253static int 1254ath_keyset_tkip(struct ath_softc *sc, const struct ieee80211_key *k, 1255 HAL_KEYVAL *hk, const u_int8_t mac[IEEE80211_ADDR_LEN]) 1256{ 1257#define IEEE80211_KEY_XR (IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV) 1258 static const u_int8_t zerobssid[IEEE80211_ADDR_LEN]; 1259 struct ath_hal *ah = sc->sc_ah; 1260 1261 KASSERT(k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP, 1262 ("got a non-TKIP key, cipher %u", k->wk_cipher->ic_cipher)); 1263 KASSERT(sc->sc_splitmic, ("key cache !split")); 1264 if ((k->wk_flags & IEEE80211_KEY_XR) == IEEE80211_KEY_XR) { 1265 /* 1266 * TX key goes at first index, RX key at the rx index. 1267 * The hal handles the MIC keys at index+64. 1268 */ 1269 memcpy(hk->kv_mic, k->wk_txmic, sizeof(hk->kv_mic)); 1270 KEYPRINTF(sc, k->wk_keyix, hk, zerobssid); 1271 if (!ath_hal_keyset(ah, k->wk_keyix, hk, zerobssid)) 1272 return 0; 1273 1274 memcpy(hk->kv_mic, k->wk_rxmic, sizeof(hk->kv_mic)); 1275 KEYPRINTF(sc, k->wk_keyix+32, hk, mac); 1276 /* XXX delete tx key on failure? */ 1277 return ath_hal_keyset(ah, k->wk_keyix+32, hk, mac); 1278 } else if (k->wk_flags & IEEE80211_KEY_XR) { 1279 /* 1280 * TX/RX key goes at first index. 1281 * The hal handles the MIC keys are index+64. 1282 */ 1283 memcpy(hk->kv_mic, k->wk_flags & IEEE80211_KEY_XMIT ? 1284 k->wk_txmic : k->wk_rxmic, sizeof(hk->kv_mic)); 1285 KEYPRINTF(sc, k->wk_keyix, hk, mac); 1286 return ath_hal_keyset(ah, k->wk_keyix, hk, mac); 1287 } 1288 return 0; 1289#undef IEEE80211_KEY_XR 1290} 1291 1292/* 1293 * Set a net80211 key into the hardware. This handles the 1294 * potential distribution of key state to multiple key 1295 * cache slots for TKIP with hardware MIC support. 1296 */ 1297static int 1298ath_keyset(struct ath_softc *sc, const struct ieee80211_key *k, 1299 const u_int8_t mac0[IEEE80211_ADDR_LEN], 1300 struct ieee80211_node *bss) 1301{ 1302#define N(a) (sizeof(a)/sizeof(a[0])) 1303 static const u_int8_t ciphermap[] = { 1304 HAL_CIPHER_WEP, /* IEEE80211_CIPHER_WEP */ 1305 HAL_CIPHER_TKIP, /* IEEE80211_CIPHER_TKIP */ 1306 HAL_CIPHER_AES_OCB, /* IEEE80211_CIPHER_AES_OCB */ 1307 HAL_CIPHER_AES_CCM, /* IEEE80211_CIPHER_AES_CCM */ 1308 (u_int8_t) -1, /* 4 is not allocated */ 1309 HAL_CIPHER_CKIP, /* IEEE80211_CIPHER_CKIP */ 1310 HAL_CIPHER_CLR, /* IEEE80211_CIPHER_NONE */ 1311 }; 1312 struct ath_hal *ah = sc->sc_ah; 1313 const struct ieee80211_cipher *cip = k->wk_cipher; 1314 u_int8_t gmac[IEEE80211_ADDR_LEN]; 1315 const u_int8_t *mac; 1316 HAL_KEYVAL hk; 1317 1318 memset(&hk, 0, sizeof(hk)); 1319 /* 1320 * Software crypto uses a "clear key" so non-crypto 1321 * state kept in the key cache are maintained and 1322 * so that rx frames have an entry to match. 1323 */ 1324 if ((k->wk_flags & IEEE80211_KEY_SWCRYPT) == 0) { 1325 KASSERT(cip->ic_cipher < N(ciphermap), 1326 ("invalid cipher type %u", cip->ic_cipher)); 1327 hk.kv_type = ciphermap[cip->ic_cipher]; 1328 hk.kv_len = k->wk_keylen; 1329 memcpy(hk.kv_val, k->wk_key, k->wk_keylen); 1330 } else 1331 hk.kv_type = HAL_CIPHER_CLR; 1332 1333 if ((k->wk_flags & IEEE80211_KEY_GROUP) && sc->sc_mcastkey) { 1334 /* 1335 * Group keys on hardware that supports multicast frame 1336 * key search use a mac that is the sender's address with 1337 * the high bit set instead of the app-specified address. 1338 */ 1339 IEEE80211_ADDR_COPY(gmac, bss->ni_macaddr); 1340 gmac[0] |= 0x80; 1341 mac = gmac; 1342 } else 1343 mac = mac0; 1344 1345 if (hk.kv_type == HAL_CIPHER_TKIP && 1346 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && 1347 sc->sc_splitmic) { 1348 return ath_keyset_tkip(sc, k, &hk, mac); 1349 } else { 1350 KEYPRINTF(sc, k->wk_keyix, &hk, mac); 1351 return ath_hal_keyset(ah, k->wk_keyix, &hk, mac); 1352 } 1353#undef N 1354} 1355 1356/* 1357 * Allocate tx/rx key slots for TKIP. We allocate two slots for 1358 * each key, one for decrypt/encrypt and the other for the MIC. 1359 */ 1360static u_int16_t 1361key_alloc_2pair(struct ath_softc *sc, 1362 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1363{ 1364#define N(a) (sizeof(a)/sizeof(a[0])) 1365 u_int i, keyix; 1366 1367 KASSERT(sc->sc_splitmic, ("key cache !split")); 1368 /* XXX could optimize */ 1369 for (i = 0; i < N(sc->sc_keymap)/4; i++) { 1370 u_int8_t b = sc->sc_keymap[i]; 1371 if (b != 0xff) { 1372 /* 1373 * One or more slots in this byte are free. 1374 */ 1375 keyix = i*NBBY; 1376 while (b & 1) { 1377 again: 1378 keyix++; 1379 b >>= 1; 1380 } 1381 /* XXX IEEE80211_KEY_XMIT | IEEE80211_KEY_RECV */ 1382 if (isset(sc->sc_keymap, keyix+32) || 1383 isset(sc->sc_keymap, keyix+64) || 1384 isset(sc->sc_keymap, keyix+32+64)) { 1385 /* full pair unavailable */ 1386 /* XXX statistic */ 1387 if (keyix == (i+1)*NBBY) { 1388 /* no slots were appropriate, advance */ 1389 continue; 1390 } 1391 goto again; 1392 } 1393 setbit(sc->sc_keymap, keyix); 1394 setbit(sc->sc_keymap, keyix+64); 1395 setbit(sc->sc_keymap, keyix+32); 1396 setbit(sc->sc_keymap, keyix+32+64); 1397 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1398 "%s: key pair %u,%u %u,%u\n", 1399 __func__, keyix, keyix+64, 1400 keyix+32, keyix+32+64); 1401 *txkeyix = keyix; 1402 *rxkeyix = keyix+32; 1403 return 1; 1404 } 1405 } 1406 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of pair space\n", __func__); 1407 return 0; 1408#undef N 1409} 1410 1411/* 1412 * Allocate a single key cache slot. 1413 */ 1414static int 1415key_alloc_single(struct ath_softc *sc, 1416 ieee80211_keyix *txkeyix, ieee80211_keyix *rxkeyix) 1417{ 1418#define N(a) (sizeof(a)/sizeof(a[0])) 1419 u_int i, keyix; 1420 1421 /* XXX try i,i+32,i+64,i+32+64 to minimize key pair conflicts */ 1422 for (i = 0; i < N(sc->sc_keymap); i++) { 1423 u_int8_t b = sc->sc_keymap[i]; 1424 if (b != 0xff) { 1425 /* 1426 * One or more slots are free. 1427 */ 1428 keyix = i*NBBY; 1429 while (b & 1) 1430 keyix++, b >>= 1; 1431 setbit(sc->sc_keymap, keyix); 1432 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: key %u\n", 1433 __func__, keyix); 1434 *txkeyix = *rxkeyix = keyix; 1435 return 1; 1436 } 1437 } 1438 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: out of space\n", __func__); 1439 return 0; 1440#undef N 1441} 1442 1443/* 1444 * Allocate one or more key cache slots for a uniacst key. The 1445 * key itself is needed only to identify the cipher. For hardware 1446 * TKIP with split cipher+MIC keys we allocate two key cache slot 1447 * pairs so that we can setup separate TX and RX MIC keys. Note 1448 * that the MIC key for a TKIP key at slot i is assumed by the 1449 * hardware to be at slot i+64. This limits TKIP keys to the first 1450 * 64 entries. 1451 */ 1452static int 1453ath_key_alloc(struct ieee80211com *ic, const struct ieee80211_key *k, 1454 ieee80211_keyix *keyix, ieee80211_keyix *rxkeyix) 1455{ 1456 struct ath_softc *sc = ic->ic_ifp->if_softc; 1457 1458 /* 1459 * Group key allocation must be handled specially for 1460 * parts that do not support multicast key cache search 1461 * functionality. For those parts the key id must match 1462 * the h/w key index so lookups find the right key. On 1463 * parts w/ the key search facility we install the sender's 1464 * mac address (with the high bit set) and let the hardware 1465 * find the key w/o using the key id. This is preferred as 1466 * it permits us to support multiple users for adhoc and/or 1467 * multi-station operation. 1468 */ 1469 if ((k->wk_flags & IEEE80211_KEY_GROUP) && !sc->sc_mcastkey) { 1470 if (!(&ic->ic_nw_keys[0] <= k && 1471 k < &ic->ic_nw_keys[IEEE80211_WEP_NKID])) { 1472 /* should not happen */ 1473 DPRINTF(sc, ATH_DEBUG_KEYCACHE, 1474 "%s: bogus group key\n", __func__); 1475 return 0; 1476 } 1477 /* 1478 * XXX we pre-allocate the global keys so 1479 * have no way to check if they've already been allocated. 1480 */ 1481 *keyix = *rxkeyix = k - ic->ic_nw_keys; 1482 return 1; 1483 } 1484 1485 /* 1486 * We allocate two pair for TKIP when using the h/w to do 1487 * the MIC. For everything else, including software crypto, 1488 * we allocate a single entry. Note that s/w crypto requires 1489 * a pass-through slot on the 5211 and 5212. The 5210 does 1490 * not support pass-through cache entries and we map all 1491 * those requests to slot 0. 1492 */ 1493 if (k->wk_flags & IEEE80211_KEY_SWCRYPT) { 1494 return key_alloc_single(sc, keyix, rxkeyix); 1495 } else if (k->wk_cipher->ic_cipher == IEEE80211_CIPHER_TKIP && 1496 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) { 1497 return key_alloc_2pair(sc, keyix, rxkeyix); 1498 } else { 1499 return key_alloc_single(sc, keyix, rxkeyix); 1500 } 1501} 1502 1503/* 1504 * Delete an entry in the key cache allocated by ath_key_alloc. 1505 */ 1506static int 1507ath_key_delete(struct ieee80211com *ic, const struct ieee80211_key *k) 1508{ 1509 struct ath_softc *sc = ic->ic_ifp->if_softc; 1510 struct ath_hal *ah = sc->sc_ah; 1511 const struct ieee80211_cipher *cip = k->wk_cipher; 1512 u_int keyix = k->wk_keyix; 1513 1514 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s: delete key %u\n", __func__, keyix); 1515 1516 ath_hal_keyreset(ah, keyix); 1517 /* 1518 * Handle split tx/rx keying required for TKIP with h/w MIC. 1519 */ 1520 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1521 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && sc->sc_splitmic) 1522 ath_hal_keyreset(ah, keyix+32); /* RX key */ 1523 if (keyix >= IEEE80211_WEP_NKID) { 1524 /* 1525 * Don't touch keymap entries for global keys so 1526 * they are never considered for dynamic allocation. 1527 */ 1528 clrbit(sc->sc_keymap, keyix); 1529 if (cip->ic_cipher == IEEE80211_CIPHER_TKIP && 1530 (k->wk_flags & IEEE80211_KEY_SWMIC) == 0 && 1531 sc->sc_splitmic) { 1532 clrbit(sc->sc_keymap, keyix+64); /* TX key MIC */ 1533 clrbit(sc->sc_keymap, keyix+32); /* RX key */ 1534 clrbit(sc->sc_keymap, keyix+32+64); /* RX key MIC */ 1535 } 1536 } 1537 return 1; 1538} 1539 1540/* 1541 * Set the key cache contents for the specified key. Key cache 1542 * slot(s) must already have been allocated by ath_key_alloc. 1543 */ 1544static int 1545ath_key_set(struct ieee80211com *ic, const struct ieee80211_key *k, 1546 const u_int8_t mac[IEEE80211_ADDR_LEN]) 1547{ 1548 struct ath_softc *sc = ic->ic_ifp->if_softc; 1549 1550 return ath_keyset(sc, k, mac, ic->ic_bss); 1551} 1552 1553/* 1554 * Block/unblock tx+rx processing while a key change is done. 1555 * We assume the caller serializes key management operations 1556 * so we only need to worry about synchronization with other 1557 * uses that originate in the driver. 1558 */ 1559static void 1560ath_key_update_begin(struct ieee80211com *ic) 1561{ 1562 struct ifnet *ifp = ic->ic_ifp; 1563 struct ath_softc *sc = ifp->if_softc; 1564 1565 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1566#if 0 1567 tasklet_disable(&sc->sc_rxtq); 1568#endif 1569 IF_LOCK(&ifp->if_snd); /* NB: doesn't block mgmt frames */ 1570} 1571 1572static void 1573ath_key_update_end(struct ieee80211com *ic) 1574{ 1575 struct ifnet *ifp = ic->ic_ifp; 1576 struct ath_softc *sc = ifp->if_softc; 1577 1578 DPRINTF(sc, ATH_DEBUG_KEYCACHE, "%s:\n", __func__); 1579 IF_UNLOCK(&ifp->if_snd); 1580#if 0 1581 tasklet_enable(&sc->sc_rxtq); 1582#endif 1583} 1584 1585/* 1586 * Calculate the receive filter according to the 1587 * operating mode and state: 1588 * 1589 * o always accept unicast, broadcast, and multicast traffic 1590 * o maintain current state of phy error reception (the hal 1591 * may enable phy error frames for noise immunity work) 1592 * o probe request frames are accepted only when operating in 1593 * hostap, adhoc, or monitor modes 1594 * o enable promiscuous mode according to the interface state 1595 * o accept beacons: 1596 * - when operating in adhoc mode so the 802.11 layer creates 1597 * node table entries for peers, 1598 * - when operating in station mode for collecting rssi data when 1599 * the station is otherwise quiet, or 1600 * - when scanning 1601 */ 1602static u_int32_t 1603ath_calcrxfilter(struct ath_softc *sc, enum ieee80211_state state) 1604{ 1605 struct ieee80211com *ic = &sc->sc_ic; 1606 struct ath_hal *ah = sc->sc_ah; 1607 struct ifnet *ifp = sc->sc_ifp; 1608 u_int32_t rfilt; 1609 1610 rfilt = (ath_hal_getrxfilter(ah) & HAL_RX_FILTER_PHYERR) 1611 | HAL_RX_FILTER_UCAST | HAL_RX_FILTER_BCAST | HAL_RX_FILTER_MCAST; 1612 if (ic->ic_opmode != IEEE80211_M_STA) 1613 rfilt |= HAL_RX_FILTER_PROBEREQ; 1614 if (ic->ic_opmode != IEEE80211_M_HOSTAP && 1615 (ifp->if_flags & IFF_PROMISC)) 1616 rfilt |= HAL_RX_FILTER_PROM; 1617 if (ic->ic_opmode == IEEE80211_M_STA || 1618 ic->ic_opmode == IEEE80211_M_IBSS || 1619 state == IEEE80211_S_SCAN) 1620 rfilt |= HAL_RX_FILTER_BEACON; 1621 return rfilt; 1622} 1623 1624static void 1625ath_mode_init(struct ath_softc *sc) 1626{ 1627 struct ieee80211com *ic = &sc->sc_ic; 1628 struct ath_hal *ah = sc->sc_ah; 1629 struct ifnet *ifp = sc->sc_ifp; 1630 u_int32_t rfilt, mfilt[2], val; 1631 u_int8_t pos; 1632 struct ifmultiaddr *ifma; 1633 1634 /* configure rx filter */ 1635 rfilt = ath_calcrxfilter(sc, ic->ic_state); 1636 ath_hal_setrxfilter(ah, rfilt); 1637 1638 /* configure operational mode */ 1639 ath_hal_setopmode(ah); 1640 1641 /* 1642 * Handle any link-level address change. Note that we only 1643 * need to force ic_myaddr; any other addresses are handled 1644 * as a byproduct of the ifnet code marking the interface 1645 * down then up. 1646 * 1647 * XXX should get from lladdr instead of arpcom but that's more work 1648 */ 1649 IEEE80211_ADDR_COPY(ic->ic_myaddr, IF_LLADDR(ifp)); 1650 ath_hal_setmac(ah, ic->ic_myaddr); 1651 1652 /* calculate and install multicast filter */ 1653 if ((ifp->if_flags & IFF_ALLMULTI) == 0) { 1654 mfilt[0] = mfilt[1] = 0; 1655 IF_ADDR_LOCK(ifp); 1656 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1657 caddr_t dl; 1658 1659 /* calculate XOR of eight 6bit values */ 1660 dl = LLADDR((struct sockaddr_dl *) ifma->ifma_addr); 1661 val = LE_READ_4(dl + 0); 1662 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1663 val = LE_READ_4(dl + 3); 1664 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val; 1665 pos &= 0x3f; 1666 mfilt[pos / 32] |= (1 << (pos % 32)); 1667 } 1668 IF_ADDR_UNLOCK(ifp); 1669 } else { 1670 mfilt[0] = mfilt[1] = ~0; 1671 } 1672 ath_hal_setmcastfilter(ah, mfilt[0], mfilt[1]); 1673 DPRINTF(sc, ATH_DEBUG_MODE, "%s: RX filter 0x%x, MC filter %08x:%08x\n", 1674 __func__, rfilt, mfilt[0], mfilt[1]); 1675} 1676 1677/* 1678 * Set the slot time based on the current setting. 1679 */ 1680static void 1681ath_setslottime(struct ath_softc *sc) 1682{ 1683 struct ieee80211com *ic = &sc->sc_ic; 1684 struct ath_hal *ah = sc->sc_ah; 1685 1686 if (ic->ic_flags & IEEE80211_F_SHSLOT) 1687 ath_hal_setslottime(ah, HAL_SLOT_TIME_9); 1688 else 1689 ath_hal_setslottime(ah, HAL_SLOT_TIME_20); 1690 sc->sc_updateslot = OK; 1691} 1692 1693/* 1694 * Callback from the 802.11 layer to update the 1695 * slot time based on the current setting. 1696 */ 1697static void 1698ath_updateslot(struct ifnet *ifp) 1699{ 1700 struct ath_softc *sc = ifp->if_softc; 1701 struct ieee80211com *ic = &sc->sc_ic; 1702 1703 /* 1704 * When not coordinating the BSS, change the hardware 1705 * immediately. For other operation we defer the change 1706 * until beacon updates have propagated to the stations. 1707 */ 1708 if (ic->ic_opmode == IEEE80211_M_HOSTAP) 1709 sc->sc_updateslot = UPDATE; 1710 else 1711 ath_setslottime(sc); 1712} 1713 1714/* 1715 * Setup a h/w transmit queue for beacons. 1716 */ 1717static int 1718ath_beaconq_setup(struct ath_hal *ah) 1719{ 1720 HAL_TXQ_INFO qi; 1721 1722 memset(&qi, 0, sizeof(qi)); 1723 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 1724 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 1725 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 1726 /* NB: for dynamic turbo, don't enable any other interrupts */ 1727 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE; 1728 return ath_hal_setuptxqueue(ah, HAL_TX_QUEUE_BEACON, &qi); 1729} 1730 1731/* 1732 * Setup the transmit queue parameters for the beacon queue. 1733 */ 1734static int 1735ath_beaconq_config(struct ath_softc *sc) 1736{ 1737#define ATH_EXPONENT_TO_VALUE(v) ((1<<(v))-1) 1738 struct ieee80211com *ic = &sc->sc_ic; 1739 struct ath_hal *ah = sc->sc_ah; 1740 HAL_TXQ_INFO qi; 1741 1742 ath_hal_gettxqueueprops(ah, sc->sc_bhalq, &qi); 1743 if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 1744 /* 1745 * Always burst out beacon and CAB traffic. 1746 */ 1747 qi.tqi_aifs = ATH_BEACON_AIFS_DEFAULT; 1748 qi.tqi_cwmin = ATH_BEACON_CWMIN_DEFAULT; 1749 qi.tqi_cwmax = ATH_BEACON_CWMAX_DEFAULT; 1750 } else { 1751 struct wmeParams *wmep = 1752 &ic->ic_wme.wme_chanParams.cap_wmeParams[WME_AC_BE]; 1753 /* 1754 * Adhoc mode; important thing is to use 2x cwmin. 1755 */ 1756 qi.tqi_aifs = wmep->wmep_aifsn; 1757 qi.tqi_cwmin = 2*ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 1758 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 1759 } 1760 1761 if (!ath_hal_settxqueueprops(ah, sc->sc_bhalq, &qi)) { 1762 device_printf(sc->sc_dev, "unable to update parameters for " 1763 "beacon hardware queue!\n"); 1764 return 0; 1765 } else { 1766 ath_hal_resettxqueue(ah, sc->sc_bhalq); /* push to h/w */ 1767 return 1; 1768 } 1769#undef ATH_EXPONENT_TO_VALUE 1770} 1771 1772/* 1773 * Allocate and setup an initial beacon frame. 1774 */ 1775static int 1776ath_beacon_alloc(struct ath_softc *sc, struct ieee80211_node *ni) 1777{ 1778 struct ieee80211com *ic = ni->ni_ic; 1779 struct ath_buf *bf; 1780 struct mbuf *m; 1781 int error; 1782 1783 bf = STAILQ_FIRST(&sc->sc_bbuf); 1784 if (bf == NULL) { 1785 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: no dma buffers\n", __func__); 1786 sc->sc_stats.ast_be_nombuf++; /* XXX */ 1787 return ENOMEM; /* XXX */ 1788 } 1789 /* 1790 * NB: the beacon data buffer must be 32-bit aligned; 1791 * we assume the mbuf routines will return us something 1792 * with this alignment (perhaps should assert). 1793 */ 1794 m = ieee80211_beacon_alloc(ic, ni, &sc->sc_boff); 1795 if (m == NULL) { 1796 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: cannot get mbuf\n", 1797 __func__); 1798 sc->sc_stats.ast_be_nombuf++; 1799 return ENOMEM; 1800 } 1801 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 1802 bf->bf_segs, &bf->bf_nseg, 1803 BUS_DMA_NOWAIT); 1804 if (error == 0) { 1805 bf->bf_m = m; 1806 bf->bf_node = ieee80211_ref_node(ni); 1807 } else { 1808 m_freem(m); 1809 } 1810 return error; 1811} 1812 1813/* 1814 * Setup the beacon frame for transmit. 1815 */ 1816static void 1817ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf) 1818{ 1819#define USE_SHPREAMBLE(_ic) \ 1820 (((_ic)->ic_flags & (IEEE80211_F_SHPREAMBLE | IEEE80211_F_USEBARKER))\ 1821 == IEEE80211_F_SHPREAMBLE) 1822 struct ieee80211_node *ni = bf->bf_node; 1823 struct ieee80211com *ic = ni->ni_ic; 1824 struct mbuf *m = bf->bf_m; 1825 struct ath_hal *ah = sc->sc_ah; 1826 struct ath_node *an = ATH_NODE(ni); 1827 struct ath_desc *ds; 1828 int flags, antenna; 1829 u_int8_t rate; 1830 1831 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: m %p len %u\n", 1832 __func__, m, m->m_len); 1833 1834 /* setup descriptors */ 1835 ds = bf->bf_desc; 1836 1837 flags = HAL_TXDESC_NOACK; 1838 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) { 1839 ds->ds_link = bf->bf_daddr; /* self-linked */ 1840 flags |= HAL_TXDESC_VEOL; 1841 /* 1842 * Let hardware handle antenna switching. 1843 */ 1844 antenna = sc->sc_txantenna; 1845 } else { 1846 ds->ds_link = 0; 1847 /* 1848 * Switch antenna every 4 beacons. 1849 * XXX assumes two antenna 1850 */ 1851 antenna = (sc->sc_stats.ast_be_xmit & 4 ? 2 : 1); 1852 } 1853 1854 KASSERT(bf->bf_nseg == 1, 1855 ("multi-segment beacon frame; nseg %u", bf->bf_nseg)); 1856 ds->ds_data = bf->bf_segs[0].ds_addr; 1857 /* 1858 * Calculate rate code. 1859 * XXX everything at min xmit rate 1860 */ 1861 if (USE_SHPREAMBLE(ic)) 1862 rate = an->an_tx_mgtratesp; 1863 else 1864 rate = an->an_tx_mgtrate; 1865 ath_hal_setuptxdesc(ah, ds 1866 , m->m_len + IEEE80211_CRC_LEN /* frame length */ 1867 , sizeof(struct ieee80211_frame)/* header length */ 1868 , HAL_PKT_TYPE_BEACON /* Atheros packet type */ 1869 , ni->ni_txpower /* txpower XXX */ 1870 , rate, 1 /* series 0 rate/tries */ 1871 , HAL_TXKEYIX_INVALID /* no encryption */ 1872 , antenna /* antenna mode */ 1873 , flags /* no ack, veol for beacons */ 1874 , 0 /* rts/cts rate */ 1875 , 0 /* rts/cts duration */ 1876 ); 1877 /* NB: beacon's BufLen must be a multiple of 4 bytes */ 1878 ath_hal_filltxdesc(ah, ds 1879 , roundup(m->m_len, 4) /* buffer length */ 1880 , AH_TRUE /* first segment */ 1881 , AH_TRUE /* last segment */ 1882 , ds /* first descriptor */ 1883 ); 1884#undef USE_SHPREAMBLE 1885} 1886 1887/* 1888 * Transmit a beacon frame at SWBA. Dynamic updates to the 1889 * frame contents are done as needed and the slot time is 1890 * also adjusted based on current state. 1891 */ 1892static void 1893ath_beacon_proc(void *arg, int pending) 1894{ 1895 struct ath_softc *sc = arg; 1896 struct ath_buf *bf = STAILQ_FIRST(&sc->sc_bbuf); 1897 struct ieee80211_node *ni = bf->bf_node; 1898 struct ieee80211com *ic = ni->ni_ic; 1899 struct ath_hal *ah = sc->sc_ah; 1900 struct mbuf *m; 1901 int ncabq, error, otherant; 1902 1903 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s: pending %u\n", 1904 __func__, pending); 1905 1906 if (ic->ic_opmode == IEEE80211_M_STA || 1907 ic->ic_opmode == IEEE80211_M_MONITOR || 1908 bf == NULL || bf->bf_m == NULL) { 1909 DPRINTF(sc, ATH_DEBUG_ANY, "%s: ic_flags=%x bf=%p bf_m=%p\n", 1910 __func__, ic->ic_flags, bf, bf ? bf->bf_m : NULL); 1911 return; 1912 } 1913 /* 1914 * Check if the previous beacon has gone out. If 1915 * not don't don't try to post another, skip this 1916 * period and wait for the next. Missed beacons 1917 * indicate a problem and should not occur. If we 1918 * miss too many consecutive beacons reset the device. 1919 */ 1920 if (ath_hal_numtxpending(ah, sc->sc_bhalq) != 0) { 1921 sc->sc_bmisscount++; 1922 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 1923 "%s: missed %u consecutive beacons\n", 1924 __func__, sc->sc_bmisscount); 1925 if (sc->sc_bmisscount > 3) /* NB: 3 is a guess */ 1926 taskqueue_enqueue(taskqueue_swi, &sc->sc_bstucktask); 1927 return; 1928 } 1929 if (sc->sc_bmisscount != 0) { 1930 DPRINTF(sc, ATH_DEBUG_BEACON, 1931 "%s: resume beacon xmit after %u misses\n", 1932 __func__, sc->sc_bmisscount); 1933 sc->sc_bmisscount = 0; 1934 } 1935 1936 /* 1937 * Update dynamic beacon contents. If this returns 1938 * non-zero then we need to remap the memory because 1939 * the beacon frame changed size (probably because 1940 * of the TIM bitmap). 1941 */ 1942 m = bf->bf_m; 1943 ncabq = ath_hal_numtxpending(ah, sc->sc_cabq->axq_qnum); 1944 if (ieee80211_beacon_update(ic, bf->bf_node, &sc->sc_boff, m, ncabq)) { 1945 /* XXX too conservative? */ 1946 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 1947 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m, 1948 bf->bf_segs, &bf->bf_nseg, 1949 BUS_DMA_NOWAIT); 1950 if (error != 0) { 1951 if_printf(ic->ic_ifp, 1952 "%s: bus_dmamap_load_mbuf_sg failed, error %u\n", 1953 __func__, error); 1954 return; 1955 } 1956 } 1957 1958 /* 1959 * Handle slot time change when a non-ERP station joins/leaves 1960 * an 11g network. The 802.11 layer notifies us via callback, 1961 * we mark updateslot, then wait one beacon before effecting 1962 * the change. This gives associated stations at least one 1963 * beacon interval to note the state change. 1964 */ 1965 /* XXX locking */ 1966 if (sc->sc_updateslot == UPDATE) 1967 sc->sc_updateslot = COMMIT; /* commit next beacon */ 1968 else if (sc->sc_updateslot == COMMIT) 1969 ath_setslottime(sc); /* commit change to h/w */ 1970 1971 /* 1972 * Check recent per-antenna transmit statistics and flip 1973 * the default antenna if noticeably more frames went out 1974 * on the non-default antenna. 1975 * XXX assumes 2 anntenae 1976 */ 1977 otherant = sc->sc_defant & 1 ? 2 : 1; 1978 if (sc->sc_ant_tx[otherant] > sc->sc_ant_tx[sc->sc_defant] + 2) 1979 ath_setdefantenna(sc, otherant); 1980 sc->sc_ant_tx[1] = sc->sc_ant_tx[2] = 0; 1981 1982 /* 1983 * Construct tx descriptor. 1984 */ 1985 ath_beacon_setup(sc, bf); 1986 1987 /* 1988 * Stop any current dma and put the new frame on the queue. 1989 * This should never fail since we check above that no frames 1990 * are still pending on the queue. 1991 */ 1992 if (!ath_hal_stoptxdma(ah, sc->sc_bhalq)) { 1993 DPRINTF(sc, ATH_DEBUG_ANY, 1994 "%s: beacon queue %u did not stop?\n", 1995 __func__, sc->sc_bhalq); 1996 } 1997 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 1998 1999 /* 2000 * Enable the CAB queue before the beacon queue to 2001 * insure cab frames are triggered by this beacon. 2002 */ 2003 if (sc->sc_boff.bo_tim[4] & 1) /* NB: only at DTIM */ 2004 ath_hal_txstart(ah, sc->sc_cabq->axq_qnum); 2005 ath_hal_puttxbuf(ah, sc->sc_bhalq, bf->bf_daddr); 2006 ath_hal_txstart(ah, sc->sc_bhalq); 2007 DPRINTF(sc, ATH_DEBUG_BEACON_PROC, 2008 "%s: TXDP[%u] = %p (%p)\n", __func__, 2009 sc->sc_bhalq, (caddr_t)bf->bf_daddr, bf->bf_desc); 2010 2011 sc->sc_stats.ast_be_xmit++; 2012} 2013 2014/* 2015 * Reset the hardware after detecting beacons have stopped. 2016 */ 2017static void 2018ath_bstuck_proc(void *arg, int pending) 2019{ 2020 struct ath_softc *sc = arg; 2021 struct ifnet *ifp = sc->sc_ifp; 2022 2023 if_printf(ifp, "stuck beacon; resetting (bmiss count %u)\n", 2024 sc->sc_bmisscount); 2025 ath_reset(ifp); 2026} 2027 2028/* 2029 * Reclaim beacon resources. 2030 */ 2031static void 2032ath_beacon_free(struct ath_softc *sc) 2033{ 2034 struct ath_buf *bf; 2035 2036 STAILQ_FOREACH(bf, &sc->sc_bbuf, bf_list) { 2037 if (bf->bf_m != NULL) { 2038 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2039 m_freem(bf->bf_m); 2040 bf->bf_m = NULL; 2041 } 2042 if (bf->bf_node != NULL) { 2043 ieee80211_free_node(bf->bf_node); 2044 bf->bf_node = NULL; 2045 } 2046 } 2047} 2048 2049/* 2050 * Configure the beacon and sleep timers. 2051 * 2052 * When operating as an AP this resets the TSF and sets 2053 * up the hardware to notify us when we need to issue beacons. 2054 * 2055 * When operating in station mode this sets up the beacon 2056 * timers according to the timestamp of the last received 2057 * beacon and the current TSF, configures PCF and DTIM 2058 * handling, programs the sleep registers so the hardware 2059 * will wakeup in time to receive beacons, and configures 2060 * the beacon miss handling so we'll receive a BMISS 2061 * interrupt when we stop seeing beacons from the AP 2062 * we've associated with. 2063 */ 2064static void 2065ath_beacon_config(struct ath_softc *sc) 2066{ 2067#define TSF_TO_TU(_h,_l) (((_h) << 22) | ((_l) >> 10)) 2068 struct ath_hal *ah = sc->sc_ah; 2069 struct ieee80211com *ic = &sc->sc_ic; 2070 struct ieee80211_node *ni = ic->ic_bss; 2071 u_int32_t nexttbtt, intval; 2072 2073 /* extract tstamp from last beacon and convert to TU */ 2074 nexttbtt = TSF_TO_TU(LE_READ_4(ni->ni_tstamp.data + 4), 2075 LE_READ_4(ni->ni_tstamp.data)); 2076 /* NB: the beacon interval is kept internally in TU's */ 2077 intval = ni->ni_intval & HAL_BEACON_PERIOD; 2078 if (nexttbtt == 0) /* e.g. for ap mode */ 2079 nexttbtt = intval; 2080 else if (intval) /* NB: can be 0 for monitor mode */ 2081 nexttbtt = roundup(nexttbtt, intval); 2082 DPRINTF(sc, ATH_DEBUG_BEACON, "%s: nexttbtt %u intval %u (%u)\n", 2083 __func__, nexttbtt, intval, ni->ni_intval); 2084 if (ic->ic_opmode == IEEE80211_M_STA) { 2085 HAL_BEACON_STATE bs; 2086 u_int64_t tsf; 2087 u_int32_t tsftu; 2088 int dtimperiod, dtimcount; 2089 int cfpperiod, cfpcount; 2090 2091 /* 2092 * Setup dtim and cfp parameters according to 2093 * last beacon we received (which may be none). 2094 */ 2095 dtimperiod = ni->ni_dtim_period; 2096 if (dtimperiod <= 0) /* NB: 0 if not known */ 2097 dtimperiod = 1; 2098 dtimcount = ni->ni_dtim_count; 2099 if (dtimcount >= dtimperiod) /* NB: sanity check */ 2100 dtimcount = 0; /* XXX? */ 2101 cfpperiod = 1; /* NB: no PCF support yet */ 2102 cfpcount = 0; 2103#define FUDGE 2 2104 /* 2105 * Pull nexttbtt forward to reflect the current 2106 * TSF and calculate dtim+cfp state for the result. 2107 */ 2108 tsf = ath_hal_gettsf64(ah); 2109 tsftu = TSF_TO_TU((u_int32_t)(tsf>>32), (u_int32_t)tsf) + FUDGE; 2110 do { 2111 nexttbtt += intval; 2112 if (--dtimcount < 0) { 2113 dtimcount = dtimperiod - 1; 2114 if (--cfpcount < 0) 2115 cfpcount = cfpperiod - 1; 2116 } 2117 } while (nexttbtt < tsftu); 2118#undef FUDGE 2119 memset(&bs, 0, sizeof(bs)); 2120 bs.bs_intval = intval; 2121 bs.bs_nexttbtt = nexttbtt; 2122 bs.bs_dtimperiod = dtimperiod*intval; 2123 bs.bs_nextdtim = bs.bs_nexttbtt + dtimcount*intval; 2124 bs.bs_cfpperiod = cfpperiod*bs.bs_dtimperiod; 2125 bs.bs_cfpnext = bs.bs_nextdtim + cfpcount*bs.bs_dtimperiod; 2126 bs.bs_cfpmaxduration = 0; 2127#if 0 2128 /* 2129 * The 802.11 layer records the offset to the DTIM 2130 * bitmap while receiving beacons; use it here to 2131 * enable h/w detection of our AID being marked in 2132 * the bitmap vector (to indicate frames for us are 2133 * pending at the AP). 2134 * XXX do DTIM handling in s/w to WAR old h/w bugs 2135 * XXX enable based on h/w rev for newer chips 2136 */ 2137 bs.bs_timoffset = ni->ni_timoff; 2138#endif 2139 /* 2140 * Calculate the number of consecutive beacons to miss 2141 * before taking a BMISS interrupt. The configuration 2142 * is specified in ms, so we need to convert that to 2143 * TU's and then calculate based on the beacon interval. 2144 * Note that we clamp the result to at most 10 beacons. 2145 */ 2146 bs.bs_bmissthreshold = ic->ic_bmissthreshold; 2147 if (bs.bs_bmissthreshold > 10) 2148 bs.bs_bmissthreshold = 10; 2149 else if (bs.bs_bmissthreshold <= 0) 2150 bs.bs_bmissthreshold = 1; 2151 2152 /* 2153 * Calculate sleep duration. The configuration is 2154 * given in ms. We insure a multiple of the beacon 2155 * period is used. Also, if the sleep duration is 2156 * greater than the DTIM period then it makes senses 2157 * to make it a multiple of that. 2158 * 2159 * XXX fixed at 100ms 2160 */ 2161 bs.bs_sleepduration = 2162 roundup(IEEE80211_MS_TO_TU(100), bs.bs_intval); 2163 if (bs.bs_sleepduration > bs.bs_dtimperiod) 2164 bs.bs_sleepduration = roundup(bs.bs_sleepduration, bs.bs_dtimperiod); 2165 2166 DPRINTF(sc, ATH_DEBUG_BEACON, 2167 "%s: tsf %ju tsf:tu %u intval %u nexttbtt %u dtim %u nextdtim %u bmiss %u sleep %u cfp:period %u maxdur %u next %u timoffset %u\n" 2168 , __func__ 2169 , tsf, tsftu 2170 , bs.bs_intval 2171 , bs.bs_nexttbtt 2172 , bs.bs_dtimperiod 2173 , bs.bs_nextdtim 2174 , bs.bs_bmissthreshold 2175 , bs.bs_sleepduration 2176 , bs.bs_cfpperiod 2177 , bs.bs_cfpmaxduration 2178 , bs.bs_cfpnext 2179 , bs.bs_timoffset 2180 ); 2181 ath_hal_intrset(ah, 0); 2182 ath_hal_beacontimers(ah, &bs); 2183 sc->sc_imask |= HAL_INT_BMISS; 2184 ath_hal_intrset(ah, sc->sc_imask); 2185 } else { 2186 ath_hal_intrset(ah, 0); 2187 if (nexttbtt == intval) 2188 intval |= HAL_BEACON_RESET_TSF; 2189 if (ic->ic_opmode == IEEE80211_M_IBSS) { 2190 /* 2191 * In IBSS mode enable the beacon timers but only 2192 * enable SWBA interrupts if we need to manually 2193 * prepare beacon frames. Otherwise we use a 2194 * self-linked tx descriptor and let the hardware 2195 * deal with things. 2196 */ 2197 intval |= HAL_BEACON_ENA; 2198 if (!sc->sc_hasveol) 2199 sc->sc_imask |= HAL_INT_SWBA; 2200 ath_beaconq_config(sc); 2201 } else if (ic->ic_opmode == IEEE80211_M_HOSTAP) { 2202 /* 2203 * In AP mode we enable the beacon timers and 2204 * SWBA interrupts to prepare beacon frames. 2205 */ 2206 intval |= HAL_BEACON_ENA; 2207 sc->sc_imask |= HAL_INT_SWBA; /* beacon prepare */ 2208 ath_beaconq_config(sc); 2209 } 2210 ath_hal_beaconinit(ah, nexttbtt, intval); 2211 sc->sc_bmisscount = 0; 2212 ath_hal_intrset(ah, sc->sc_imask); 2213 /* 2214 * When using a self-linked beacon descriptor in 2215 * ibss mode load it once here. 2216 */ 2217 if (ic->ic_opmode == IEEE80211_M_IBSS && sc->sc_hasveol) 2218 ath_beacon_proc(sc, 0); 2219 } 2220#undef TSF_TO_TU 2221} 2222 2223static void 2224ath_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 2225{ 2226 bus_addr_t *paddr = (bus_addr_t*) arg; 2227 KASSERT(error == 0, ("error %u on bus_dma callback", error)); 2228 *paddr = segs->ds_addr; 2229} 2230 2231static int 2232ath_descdma_setup(struct ath_softc *sc, 2233 struct ath_descdma *dd, ath_bufhead *head, 2234 const char *name, int nbuf, int ndesc) 2235{ 2236#define DS2PHYS(_dd, _ds) \ 2237 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc)) 2238 struct ifnet *ifp = sc->sc_ifp; 2239 struct ath_desc *ds; 2240 struct ath_buf *bf; 2241 int i, bsize, error; 2242 2243 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA: %u buffers %u desc/buf\n", 2244 __func__, name, nbuf, ndesc); 2245 2246 dd->dd_name = name; 2247 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc; 2248 2249 /* 2250 * Setup DMA descriptor area. 2251 */ 2252 error = bus_dma_tag_create(NULL, /* parent */ 2253 PAGE_SIZE, 0, /* alignment, bounds */ 2254 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2255 BUS_SPACE_MAXADDR, /* highaddr */ 2256 NULL, NULL, /* filter, filterarg */ 2257 dd->dd_desc_len, /* maxsize */ 2258 1, /* nsegments */ 2259 BUS_SPACE_MAXADDR, /* maxsegsize */ 2260 BUS_DMA_ALLOCNOW, /* flags */ 2261 NULL, /* lockfunc */ 2262 NULL, /* lockarg */ 2263 &dd->dd_dmat); 2264 if (error != 0) { 2265 if_printf(ifp, "cannot allocate %s DMA tag\n", dd->dd_name); 2266 return error; 2267 } 2268 2269 /* allocate descriptors */ 2270 error = bus_dmamap_create(dd->dd_dmat, BUS_DMA_NOWAIT, &dd->dd_dmamap); 2271 if (error != 0) { 2272 if_printf(ifp, "unable to create dmamap for %s descriptors, " 2273 "error %u\n", dd->dd_name, error); 2274 goto fail0; 2275 } 2276 2277 error = bus_dmamem_alloc(dd->dd_dmat, (void**) &dd->dd_desc, 2278 BUS_DMA_NOWAIT, &dd->dd_dmamap); 2279 if (error != 0) { 2280 if_printf(ifp, "unable to alloc memory for %u %s descriptors, " 2281 "error %u\n", nbuf * ndesc, dd->dd_name, error); 2282 goto fail1; 2283 } 2284 2285 error = bus_dmamap_load(dd->dd_dmat, dd->dd_dmamap, 2286 dd->dd_desc, dd->dd_desc_len, 2287 ath_load_cb, &dd->dd_desc_paddr, 2288 BUS_DMA_NOWAIT); 2289 if (error != 0) { 2290 if_printf(ifp, "unable to map %s descriptors, error %u\n", 2291 dd->dd_name, error); 2292 goto fail2; 2293 } 2294 2295 ds = dd->dd_desc; 2296 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %s DMA map: %p (%lu) -> %p (%lu)\n", 2297 __func__, dd->dd_name, ds, (u_long) dd->dd_desc_len, 2298 (caddr_t) dd->dd_desc_paddr, /*XXX*/ (u_long) dd->dd_desc_len); 2299 2300 /* allocate rx buffers */ 2301 bsize = sizeof(struct ath_buf) * nbuf; 2302 bf = malloc(bsize, M_ATHDEV, M_NOWAIT | M_ZERO); 2303 if (bf == NULL) { 2304 if_printf(ifp, "malloc of %s buffers failed, size %u\n", 2305 dd->dd_name, bsize); 2306 goto fail3; 2307 } 2308 dd->dd_bufptr = bf; 2309 2310 STAILQ_INIT(head); 2311 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) { 2312 bf->bf_desc = ds; 2313 bf->bf_daddr = DS2PHYS(dd, ds); 2314 error = bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 2315 &bf->bf_dmamap); 2316 if (error != 0) { 2317 if_printf(ifp, "unable to create dmamap for %s " 2318 "buffer %u, error %u\n", dd->dd_name, i, error); 2319 ath_descdma_cleanup(sc, dd, head); 2320 return error; 2321 } 2322 STAILQ_INSERT_TAIL(head, bf, bf_list); 2323 } 2324 return 0; 2325fail3: 2326 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2327fail2: 2328 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 2329fail1: 2330 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2331fail0: 2332 bus_dma_tag_destroy(dd->dd_dmat); 2333 memset(dd, 0, sizeof(*dd)); 2334 return error; 2335#undef DS2PHYS 2336} 2337 2338static void 2339ath_descdma_cleanup(struct ath_softc *sc, 2340 struct ath_descdma *dd, ath_bufhead *head) 2341{ 2342 struct ath_buf *bf; 2343 struct ieee80211_node *ni; 2344 2345 bus_dmamap_unload(dd->dd_dmat, dd->dd_dmamap); 2346 bus_dmamem_free(dd->dd_dmat, dd->dd_desc, dd->dd_dmamap); 2347 bus_dmamap_destroy(dd->dd_dmat, dd->dd_dmamap); 2348 bus_dma_tag_destroy(dd->dd_dmat); 2349 2350 STAILQ_FOREACH(bf, head, bf_list) { 2351 if (bf->bf_m) { 2352 m_freem(bf->bf_m); 2353 bf->bf_m = NULL; 2354 } 2355 if (bf->bf_dmamap != NULL) { 2356 bus_dmamap_destroy(sc->sc_dmat, bf->bf_dmamap); 2357 bf->bf_dmamap = NULL; 2358 } 2359 ni = bf->bf_node; 2360 bf->bf_node = NULL; 2361 if (ni != NULL) { 2362 /* 2363 * Reclaim node reference. 2364 */ 2365 ieee80211_free_node(ni); 2366 } 2367 } 2368 2369 STAILQ_INIT(head); 2370 free(dd->dd_bufptr, M_ATHDEV); 2371 memset(dd, 0, sizeof(*dd)); 2372} 2373 2374static int 2375ath_desc_alloc(struct ath_softc *sc) 2376{ 2377 int error; 2378 2379 error = ath_descdma_setup(sc, &sc->sc_rxdma, &sc->sc_rxbuf, 2380 "rx", ATH_RXBUF, 1); 2381 if (error != 0) 2382 return error; 2383 2384 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf, 2385 "tx", ATH_TXBUF, ATH_TXDESC); 2386 if (error != 0) { 2387 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2388 return error; 2389 } 2390 2391 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf, 2392 "beacon", 1, 1); 2393 if (error != 0) { 2394 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2395 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2396 return error; 2397 } 2398 return 0; 2399} 2400 2401static void 2402ath_desc_free(struct ath_softc *sc) 2403{ 2404 2405 if (sc->sc_bdma.dd_desc_len != 0) 2406 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf); 2407 if (sc->sc_txdma.dd_desc_len != 0) 2408 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf); 2409 if (sc->sc_rxdma.dd_desc_len != 0) 2410 ath_descdma_cleanup(sc, &sc->sc_rxdma, &sc->sc_rxbuf); 2411} 2412 2413static struct ieee80211_node * 2414ath_node_alloc(struct ieee80211_node_table *nt) 2415{ 2416 struct ieee80211com *ic = nt->nt_ic; 2417 struct ath_softc *sc = ic->ic_ifp->if_softc; 2418 const size_t space = sizeof(struct ath_node) + sc->sc_rc->arc_space; 2419 struct ath_node *an; 2420 2421 an = malloc(space, M_80211_NODE, M_NOWAIT|M_ZERO); 2422 if (an == NULL) { 2423 /* XXX stat+msg */ 2424 return NULL; 2425 } 2426 an->an_avgrssi = ATH_RSSI_DUMMY_MARKER; 2427 an->an_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER; 2428 an->an_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER; 2429 an->an_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER; 2430 ath_rate_node_init(sc, an); 2431 2432 DPRINTF(sc, ATH_DEBUG_NODE, "%s: an %p\n", __func__, an); 2433 return &an->an_node; 2434} 2435 2436static void 2437ath_node_free(struct ieee80211_node *ni) 2438{ 2439 struct ieee80211com *ic = ni->ni_ic; 2440 struct ath_softc *sc = ic->ic_ifp->if_softc; 2441 2442 DPRINTF(sc, ATH_DEBUG_NODE, "%s: ni %p\n", __func__, ni); 2443 2444 ath_rate_node_cleanup(sc, ATH_NODE(ni)); 2445 sc->sc_node_free(ni); 2446} 2447 2448static u_int8_t 2449ath_node_getrssi(const struct ieee80211_node *ni) 2450{ 2451#define HAL_EP_RND(x, mul) \ 2452 ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) 2453 u_int32_t avgrssi = ATH_NODE_CONST(ni)->an_avgrssi; 2454 int32_t rssi; 2455 2456 /* 2457 * When only one frame is received there will be no state in 2458 * avgrssi so fallback on the value recorded by the 802.11 layer. 2459 */ 2460 if (avgrssi != ATH_RSSI_DUMMY_MARKER) 2461 rssi = HAL_EP_RND(avgrssi, HAL_RSSI_EP_MULTIPLIER); 2462 else 2463 rssi = ni->ni_rssi; 2464 /* NB: theoretically we shouldn't need this, but be paranoid */ 2465 return rssi < 0 ? 0 : rssi > 127 ? 127 : rssi; 2466#undef HAL_EP_RND 2467} 2468 2469static int 2470ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf) 2471{ 2472 struct ath_hal *ah = sc->sc_ah; 2473 int error; 2474 struct mbuf *m; 2475 struct ath_desc *ds; 2476 2477 m = bf->bf_m; 2478 if (m == NULL) { 2479 /* 2480 * NB: by assigning a page to the rx dma buffer we 2481 * implicitly satisfy the Atheros requirement that 2482 * this buffer be cache-line-aligned and sized to be 2483 * multiple of the cache line size. Not doing this 2484 * causes weird stuff to happen (for the 5210 at least). 2485 */ 2486 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2487 if (m == NULL) { 2488 DPRINTF(sc, ATH_DEBUG_ANY, 2489 "%s: no mbuf/cluster\n", __func__); 2490 sc->sc_stats.ast_rx_nombuf++; 2491 return ENOMEM; 2492 } 2493 bf->bf_m = m; 2494 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; 2495 2496 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, 2497 bf->bf_dmamap, m, 2498 bf->bf_segs, &bf->bf_nseg, 2499 BUS_DMA_NOWAIT); 2500 if (error != 0) { 2501 DPRINTF(sc, ATH_DEBUG_ANY, 2502 "%s: bus_dmamap_load_mbuf_sg failed; error %d\n", 2503 __func__, error); 2504 sc->sc_stats.ast_rx_busdma++; 2505 return error; 2506 } 2507 KASSERT(bf->bf_nseg == 1, 2508 ("multi-segment packet; nseg %u", bf->bf_nseg)); 2509 } 2510 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREREAD); 2511 2512 /* 2513 * Setup descriptors. For receive we always terminate 2514 * the descriptor list with a self-linked entry so we'll 2515 * not get overrun under high load (as can happen with a 2516 * 5212 when ANI processing enables PHY error frames). 2517 * 2518 * To insure the last descriptor is self-linked we create 2519 * each descriptor as self-linked and add it to the end. As 2520 * each additional descriptor is added the previous self-linked 2521 * entry is ``fixed'' naturally. This should be safe even 2522 * if DMA is happening. When processing RX interrupts we 2523 * never remove/process the last, self-linked, entry on the 2524 * descriptor list. This insures the hardware always has 2525 * someplace to write a new frame. 2526 */ 2527 ds = bf->bf_desc; 2528 ds->ds_link = bf->bf_daddr; /* link to self */ 2529 ds->ds_data = bf->bf_segs[0].ds_addr; 2530 ath_hal_setuprxdesc(ah, ds 2531 , m->m_len /* buffer size */ 2532 , 0 2533 ); 2534 2535 if (sc->sc_rxlink != NULL) 2536 *sc->sc_rxlink = bf->bf_daddr; 2537 sc->sc_rxlink = &ds->ds_link; 2538 return 0; 2539} 2540 2541/* 2542 * Extend 15-bit time stamp from rx descriptor to 2543 * a full 64-bit TSF using the specified TSF. 2544 */ 2545static __inline u_int64_t 2546ath_extend_tsf(u_int32_t rstamp, u_int64_t tsf) 2547{ 2548 if ((tsf & 0x7fff) < rstamp) 2549 tsf -= 0x8000; 2550 return ((tsf &~ 0x7fff) | rstamp); 2551} 2552 2553/* 2554 * Intercept management frames to collect beacon rssi data 2555 * and to do ibss merges. 2556 */ 2557static void 2558ath_recv_mgmt(struct ieee80211com *ic, struct mbuf *m, 2559 struct ieee80211_node *ni, 2560 int subtype, int rssi, u_int32_t rstamp) 2561{ 2562 struct ath_softc *sc = ic->ic_ifp->if_softc; 2563 2564 /* 2565 * Call up first so subsequent work can use information 2566 * potentially stored in the node (e.g. for ibss merge). 2567 */ 2568 sc->sc_recv_mgmt(ic, m, ni, subtype, rssi, rstamp); 2569 switch (subtype) { 2570 case IEEE80211_FC0_SUBTYPE_BEACON: 2571 /* update rssi statistics for use by the hal */ 2572 ATH_RSSI_LPF(ATH_NODE(ni)->an_halstats.ns_avgbrssi, rssi); 2573 /* fall thru... */ 2574 case IEEE80211_FC0_SUBTYPE_PROBE_RESP: 2575 if (ic->ic_opmode == IEEE80211_M_IBSS && 2576 ic->ic_state == IEEE80211_S_RUN) { 2577 u_int64_t tsf = ath_extend_tsf(rstamp, 2578 ath_hal_gettsf64(sc->sc_ah)); 2579 /* 2580 * Handle ibss merge as needed; check the tsf on the 2581 * frame before attempting the merge. The 802.11 spec 2582 * says the station should change it's bssid to match 2583 * the oldest station with the same ssid, where oldest 2584 * is determined by the tsf. Note that hardware 2585 * reconfiguration happens through callback to 2586 * ath_newstate as the state machine will go from 2587 * RUN -> RUN when this happens. 2588 */ 2589 if (le64toh(ni->ni_tstamp.tsf) >= tsf) { 2590 DPRINTF(sc, ATH_DEBUG_STATE, 2591 "ibss merge, rstamp %u tsf %ju " 2592 "tstamp %ju\n", rstamp, (uintmax_t)tsf, 2593 (uintmax_t)ni->ni_tstamp.tsf); 2594 (void) ieee80211_ibss_merge(ni); 2595 } 2596 } 2597 break; 2598 } 2599} 2600 2601/* 2602 * Set the default antenna. 2603 */ 2604static void 2605ath_setdefantenna(struct ath_softc *sc, u_int antenna) 2606{ 2607 struct ath_hal *ah = sc->sc_ah; 2608 2609 /* XXX block beacon interrupts */ 2610 ath_hal_setdefantenna(ah, antenna); 2611 if (sc->sc_defant != antenna) 2612 sc->sc_stats.ast_ant_defswitch++; 2613 sc->sc_defant = antenna; 2614 sc->sc_rxotherant = 0; 2615} 2616 2617static int 2618ath_rx_tap(struct ath_softc *sc, struct mbuf *m, 2619 const struct ath_desc *ds, u_int64_t tsf, int16_t nf) 2620{ 2621 u_int8_t rix; 2622 2623 KASSERT(sc->sc_drvbpf != NULL, ("no tap")); 2624 2625 /* 2626 * Discard anything shorter than an ack or cts. 2627 */ 2628 if (m->m_pkthdr.len < IEEE80211_ACK_LEN) { 2629 DPRINTF(sc, ATH_DEBUG_RECV, "%s: runt packet %d\n", 2630 __func__, m->m_pkthdr.len); 2631 sc->sc_stats.ast_rx_tooshort++; 2632 return 0; 2633 } 2634 sc->sc_rx_th.wr_tsf = htole64( 2635 ath_extend_tsf(ds->ds_rxstat.rs_tstamp, tsf)); 2636 rix = ds->ds_rxstat.rs_rate; 2637 sc->sc_rx_th.wr_flags = sc->sc_hwmap[rix].rxflags; 2638 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC) 2639 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_BADFCS; 2640 /* XXX propagate other error flags from descriptor */ 2641 sc->sc_rx_th.wr_rate = sc->sc_hwmap[rix].ieeerate; 2642 sc->sc_rx_th.wr_antsignal = ds->ds_rxstat.rs_rssi + nf; 2643 sc->sc_rx_th.wr_antnoise = nf; 2644 sc->sc_rx_th.wr_antenna = ds->ds_rxstat.rs_antenna; 2645 2646 bpf_mtap2(sc->sc_drvbpf, &sc->sc_rx_th, sc->sc_rx_th_len, m); 2647 2648 return 1; 2649} 2650 2651static void 2652ath_rx_proc(void *arg, int npending) 2653{ 2654#define PA2DESC(_sc, _pa) \ 2655 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 2656 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 2657 struct ath_softc *sc = arg; 2658 struct ath_buf *bf; 2659 struct ieee80211com *ic = &sc->sc_ic; 2660 struct ifnet *ifp = sc->sc_ifp; 2661 struct ath_hal *ah = sc->sc_ah; 2662 struct ath_desc *ds; 2663 struct mbuf *m; 2664 struct ieee80211_node *ni; 2665 struct ath_node *an; 2666 int len, type; 2667 u_int phyerr; 2668 HAL_STATUS status; 2669 int16_t nf; 2670 u_int64_t tsf; 2671 2672 NET_LOCK_GIANT(); /* XXX */ 2673 2674 DPRINTF(sc, ATH_DEBUG_RX_PROC, "%s: pending %u\n", __func__, npending); 2675 nf = ath_hal_getchannoise(ah, &sc->sc_curchan); 2676 tsf = ath_hal_gettsf64(ah); 2677 do { 2678 bf = STAILQ_FIRST(&sc->sc_rxbuf); 2679 if (bf == NULL) { /* NB: shouldn't happen */ 2680 if_printf(ifp, "%s: no buffer!\n", __func__); 2681 break; 2682 } 2683 ds = bf->bf_desc; 2684 if (ds->ds_link == bf->bf_daddr) { 2685 /* NB: never process the self-linked entry at the end */ 2686 break; 2687 } 2688 m = bf->bf_m; 2689 if (m == NULL) { /* NB: shouldn't happen */ 2690 if_printf(ifp, "%s: no mbuf!\n", __func__); 2691 continue; 2692 } 2693 /* XXX sync descriptor memory */ 2694 /* 2695 * Must provide the virtual address of the current 2696 * descriptor, the physical address, and the virtual 2697 * address of the next descriptor in the h/w chain. 2698 * This allows the HAL to look ahead to see if the 2699 * hardware is done with a descriptor by checking the 2700 * done bit in the following descriptor and the address 2701 * of the current descriptor the DMA engine is working 2702 * on. All this is necessary because of our use of 2703 * a self-linked list to avoid rx overruns. 2704 */ 2705 status = ath_hal_rxprocdesc(ah, ds, 2706 bf->bf_daddr, PA2DESC(sc, ds->ds_link)); 2707#ifdef AR_DEBUG 2708 if (sc->sc_debug & ATH_DEBUG_RECV_DESC) 2709 ath_printrxbuf(bf, status == HAL_OK); 2710#endif 2711 if (status == HAL_EINPROGRESS) 2712 break; 2713 STAILQ_REMOVE_HEAD(&sc->sc_rxbuf, bf_list); 2714 if (ds->ds_rxstat.rs_more) { 2715 /* 2716 * Frame spans multiple descriptors; this 2717 * cannot happen yet as we don't support 2718 * jumbograms. If not in monitor mode, 2719 * discard the frame. 2720 */ 2721 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2722 sc->sc_stats.ast_rx_toobig++; 2723 goto rx_next; 2724 } 2725 /* fall thru for monitor mode handling... */ 2726 } else if (ds->ds_rxstat.rs_status != 0) { 2727 if (ds->ds_rxstat.rs_status & HAL_RXERR_CRC) 2728 sc->sc_stats.ast_rx_crcerr++; 2729 if (ds->ds_rxstat.rs_status & HAL_RXERR_FIFO) 2730 sc->sc_stats.ast_rx_fifoerr++; 2731 if (ds->ds_rxstat.rs_status & HAL_RXERR_PHY) { 2732 sc->sc_stats.ast_rx_phyerr++; 2733 phyerr = ds->ds_rxstat.rs_phyerr & 0x1f; 2734 sc->sc_stats.ast_rx_phy[phyerr]++; 2735 goto rx_next; 2736 } 2737 if (ds->ds_rxstat.rs_status & HAL_RXERR_DECRYPT) { 2738 /* 2739 * Decrypt error. If the error occurred 2740 * because there was no hardware key, then 2741 * let the frame through so the upper layers 2742 * can process it. This is necessary for 5210 2743 * parts which have no way to setup a ``clear'' 2744 * key cache entry. 2745 * 2746 * XXX do key cache faulting 2747 */ 2748 if (ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID) 2749 goto rx_accept; 2750 sc->sc_stats.ast_rx_badcrypt++; 2751 } 2752 if (ds->ds_rxstat.rs_status & HAL_RXERR_MIC) { 2753 sc->sc_stats.ast_rx_badmic++; 2754 /* 2755 * Do minimal work required to hand off 2756 * the 802.11 header for notifcation. 2757 */ 2758 /* XXX frag's and qos frames */ 2759 len = ds->ds_rxstat.rs_datalen; 2760 if (len >= sizeof (struct ieee80211_frame)) { 2761 bus_dmamap_sync(sc->sc_dmat, 2762 bf->bf_dmamap, 2763 BUS_DMASYNC_POSTREAD); 2764 ieee80211_notify_michael_failure(ic, 2765 mtod(m, struct ieee80211_frame *), 2766 sc->sc_splitmic ? 2767 ds->ds_rxstat.rs_keyix-32 : 2768 ds->ds_rxstat.rs_keyix 2769 ); 2770 } 2771 } 2772 ifp->if_ierrors++; 2773 /* 2774 * When a tap is present pass error frames 2775 * that have been requested. By default we 2776 * pass decrypt+mic errors but others may be 2777 * interesting (e.g. crc). 2778 */ 2779 if (sc->sc_drvbpf != NULL && 2780 (ds->ds_rxstat.rs_status & sc->sc_monpass)) { 2781 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 2782 BUS_DMASYNC_POSTREAD); 2783 /* NB: bpf needs the mbuf length setup */ 2784 len = ds->ds_rxstat.rs_datalen; 2785 m->m_pkthdr.len = m->m_len = len; 2786 (void) ath_rx_tap(sc, m, ds, tsf, nf); 2787 } 2788 /* XXX pass MIC errors up for s/w reclaculation */ 2789 goto rx_next; 2790 } 2791rx_accept: 2792 /* 2793 * Sync and unmap the frame. At this point we're 2794 * committed to passing the mbuf somewhere so clear 2795 * bf_m; this means a new sk_buff must be allocated 2796 * when the rx descriptor is setup again to receive 2797 * another frame. 2798 */ 2799 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 2800 BUS_DMASYNC_POSTREAD); 2801 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 2802 bf->bf_m = NULL; 2803 2804 m->m_pkthdr.rcvif = ifp; 2805 len = ds->ds_rxstat.rs_datalen; 2806 m->m_pkthdr.len = m->m_len = len; 2807 2808 sc->sc_stats.ast_ant_rx[ds->ds_rxstat.rs_antenna]++; 2809 2810 if (sc->sc_drvbpf != NULL && !ath_rx_tap(sc, m, ds, tsf, nf)) { 2811 m_freem(m); /* XXX reclaim */ 2812 goto rx_next; 2813 } 2814 2815 /* 2816 * From this point on we assume the frame is at least 2817 * as large as ieee80211_frame_min; verify that. 2818 */ 2819 if (len < IEEE80211_MIN_LEN) { 2820 DPRINTF(sc, ATH_DEBUG_RECV, "%s: short packet %d\n", 2821 __func__, len); 2822 sc->sc_stats.ast_rx_tooshort++; 2823 m_freem(m); 2824 goto rx_next; 2825 } 2826 2827 if (IFF_DUMPPKTS(sc, ATH_DEBUG_RECV)) { 2828 ieee80211_dump_pkt(mtod(m, caddr_t), len, 2829 sc->sc_hwmap[ds->ds_rxstat.rs_rate].ieeerate, 2830 ds->ds_rxstat.rs_rssi); 2831 } 2832 2833 m_adj(m, -IEEE80211_CRC_LEN); 2834 2835 /* 2836 * Locate the node for sender, track state, and then 2837 * pass the (referenced) node up to the 802.11 layer 2838 * for its use. 2839 */ 2840 ni = ieee80211_find_rxnode_withkey(ic, 2841 mtod(m, const struct ieee80211_frame_min *), 2842 ds->ds_rxstat.rs_keyix == HAL_RXKEYIX_INVALID ? 2843 IEEE80211_KEYIX_NONE : ds->ds_rxstat.rs_keyix); 2844 /* 2845 * Track rx rssi and do any rx antenna management. 2846 */ 2847 an = ATH_NODE(ni); 2848 ATH_RSSI_LPF(an->an_avgrssi, ds->ds_rxstat.rs_rssi); 2849 /* 2850 * Send frame up for processing. 2851 */ 2852 type = ieee80211_input(ic, m, ni, 2853 ds->ds_rxstat.rs_rssi, ds->ds_rxstat.rs_tstamp); 2854 ieee80211_free_node(ni); 2855 if (sc->sc_diversity) { 2856 /* 2857 * When using fast diversity, change the default rx 2858 * antenna if diversity chooses the other antenna 3 2859 * times in a row. 2860 */ 2861 if (sc->sc_defant != ds->ds_rxstat.rs_antenna) { 2862 if (++sc->sc_rxotherant >= 3) 2863 ath_setdefantenna(sc, 2864 ds->ds_rxstat.rs_antenna); 2865 } else 2866 sc->sc_rxotherant = 0; 2867 } 2868 if (sc->sc_softled) { 2869 /* 2870 * Blink for any data frame. Otherwise do a 2871 * heartbeat-style blink when idle. The latter 2872 * is mainly for station mode where we depend on 2873 * periodic beacon frames to trigger the poll event. 2874 */ 2875 if (type == IEEE80211_FC0_TYPE_DATA) { 2876 sc->sc_rxrate = ds->ds_rxstat.rs_rate; 2877 ath_led_event(sc, ATH_LED_RX); 2878 } else if (ticks - sc->sc_ledevent >= sc->sc_ledidle) 2879 ath_led_event(sc, ATH_LED_POLL); 2880 } 2881rx_next: 2882 STAILQ_INSERT_TAIL(&sc->sc_rxbuf, bf, bf_list); 2883 } while (ath_rxbuf_init(sc, bf) == 0); 2884 2885 /* rx signal state monitoring */ 2886 ath_hal_rxmonitor(ah, &ATH_NODE(ic->ic_bss)->an_halstats); 2887 2888 NET_UNLOCK_GIANT(); /* XXX */ 2889#undef PA2DESC 2890} 2891 2892/* 2893 * Setup a h/w transmit queue. 2894 */ 2895static struct ath_txq * 2896ath_txq_setup(struct ath_softc *sc, int qtype, int subtype) 2897{ 2898#define N(a) (sizeof(a)/sizeof(a[0])) 2899 struct ath_hal *ah = sc->sc_ah; 2900 HAL_TXQ_INFO qi; 2901 int qnum; 2902 2903 memset(&qi, 0, sizeof(qi)); 2904 qi.tqi_subtype = subtype; 2905 qi.tqi_aifs = HAL_TXQ_USEDEFAULT; 2906 qi.tqi_cwmin = HAL_TXQ_USEDEFAULT; 2907 qi.tqi_cwmax = HAL_TXQ_USEDEFAULT; 2908 /* 2909 * Enable interrupts only for EOL and DESC conditions. 2910 * We mark tx descriptors to receive a DESC interrupt 2911 * when a tx queue gets deep; otherwise waiting for the 2912 * EOL to reap descriptors. Note that this is done to 2913 * reduce interrupt load and this only defers reaping 2914 * descriptors, never transmitting frames. Aside from 2915 * reducing interrupts this also permits more concurrency. 2916 * The only potential downside is if the tx queue backs 2917 * up in which case the top half of the kernel may backup 2918 * due to a lack of tx descriptors. 2919 */ 2920 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE | TXQ_FLAG_TXDESCINT_ENABLE; 2921 qnum = ath_hal_setuptxqueue(ah, qtype, &qi); 2922 if (qnum == -1) { 2923 /* 2924 * NB: don't print a message, this happens 2925 * normally on parts with too few tx queues 2926 */ 2927 return NULL; 2928 } 2929 if (qnum >= N(sc->sc_txq)) { 2930 device_printf(sc->sc_dev, 2931 "hal qnum %u out of range, max %zu!\n", 2932 qnum, N(sc->sc_txq)); 2933 ath_hal_releasetxqueue(ah, qnum); 2934 return NULL; 2935 } 2936 if (!ATH_TXQ_SETUP(sc, qnum)) { 2937 struct ath_txq *txq = &sc->sc_txq[qnum]; 2938 2939 txq->axq_qnum = qnum; 2940 txq->axq_depth = 0; 2941 txq->axq_intrcnt = 0; 2942 txq->axq_link = NULL; 2943 STAILQ_INIT(&txq->axq_q); 2944 ATH_TXQ_LOCK_INIT(sc, txq); 2945 sc->sc_txqsetup |= 1<<qnum; 2946 } 2947 return &sc->sc_txq[qnum]; 2948#undef N 2949} 2950 2951/* 2952 * Setup a hardware data transmit queue for the specified 2953 * access control. The hal may not support all requested 2954 * queues in which case it will return a reference to a 2955 * previously setup queue. We record the mapping from ac's 2956 * to h/w queues for use by ath_tx_start and also track 2957 * the set of h/w queues being used to optimize work in the 2958 * transmit interrupt handler and related routines. 2959 */ 2960static int 2961ath_tx_setup(struct ath_softc *sc, int ac, int haltype) 2962{ 2963#define N(a) (sizeof(a)/sizeof(a[0])) 2964 struct ath_txq *txq; 2965 2966 if (ac >= N(sc->sc_ac2q)) { 2967 device_printf(sc->sc_dev, "AC %u out of range, max %zu!\n", 2968 ac, N(sc->sc_ac2q)); 2969 return 0; 2970 } 2971 txq = ath_txq_setup(sc, HAL_TX_QUEUE_DATA, haltype); 2972 if (txq != NULL) { 2973 sc->sc_ac2q[ac] = txq; 2974 return 1; 2975 } else 2976 return 0; 2977#undef N 2978} 2979 2980/* 2981 * Update WME parameters for a transmit queue. 2982 */ 2983static int 2984ath_txq_update(struct ath_softc *sc, int ac) 2985{ 2986#define ATH_EXPONENT_TO_VALUE(v) ((1<<v)-1) 2987#define ATH_TXOP_TO_US(v) (v<<5) 2988 struct ieee80211com *ic = &sc->sc_ic; 2989 struct ath_txq *txq = sc->sc_ac2q[ac]; 2990 struct wmeParams *wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[ac]; 2991 struct ath_hal *ah = sc->sc_ah; 2992 HAL_TXQ_INFO qi; 2993 2994 ath_hal_gettxqueueprops(ah, txq->axq_qnum, &qi); 2995 qi.tqi_aifs = wmep->wmep_aifsn; 2996 qi.tqi_cwmin = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmin); 2997 qi.tqi_cwmax = ATH_EXPONENT_TO_VALUE(wmep->wmep_logcwmax); 2998 qi.tqi_burstTime = ATH_TXOP_TO_US(wmep->wmep_txopLimit); 2999 3000 if (!ath_hal_settxqueueprops(ah, txq->axq_qnum, &qi)) { 3001 device_printf(sc->sc_dev, "unable to update hardware queue " 3002 "parameters for %s traffic!\n", 3003 ieee80211_wme_acnames[ac]); 3004 return 0; 3005 } else { 3006 ath_hal_resettxqueue(ah, txq->axq_qnum); /* push to h/w */ 3007 return 1; 3008 } 3009#undef ATH_TXOP_TO_US 3010#undef ATH_EXPONENT_TO_VALUE 3011} 3012 3013/* 3014 * Callback from the 802.11 layer to update WME parameters. 3015 */ 3016static int 3017ath_wme_update(struct ieee80211com *ic) 3018{ 3019 struct ath_softc *sc = ic->ic_ifp->if_softc; 3020 3021 return !ath_txq_update(sc, WME_AC_BE) || 3022 !ath_txq_update(sc, WME_AC_BK) || 3023 !ath_txq_update(sc, WME_AC_VI) || 3024 !ath_txq_update(sc, WME_AC_VO) ? EIO : 0; 3025} 3026 3027/* 3028 * Reclaim resources for a setup queue. 3029 */ 3030static void 3031ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq) 3032{ 3033 3034 ath_hal_releasetxqueue(sc->sc_ah, txq->axq_qnum); 3035 ATH_TXQ_LOCK_DESTROY(txq); 3036 sc->sc_txqsetup &= ~(1<<txq->axq_qnum); 3037} 3038 3039/* 3040 * Reclaim all tx queue resources. 3041 */ 3042static void 3043ath_tx_cleanup(struct ath_softc *sc) 3044{ 3045 int i; 3046 3047 ATH_TXBUF_LOCK_DESTROY(sc); 3048 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3049 if (ATH_TXQ_SETUP(sc, i)) 3050 ath_tx_cleanupq(sc, &sc->sc_txq[i]); 3051} 3052 3053/* 3054 * Defragment an mbuf chain, returning at most maxfrags separate 3055 * mbufs+clusters. If this is not possible NULL is returned and 3056 * the original mbuf chain is left in it's present (potentially 3057 * modified) state. We use two techniques: collapsing consecutive 3058 * mbufs and replacing consecutive mbufs by a cluster. 3059 */ 3060static struct mbuf * 3061ath_defrag(struct mbuf *m0, int how, int maxfrags) 3062{ 3063 struct mbuf *m, *n, *n2, **prev; 3064 u_int curfrags; 3065 3066 /* 3067 * Calculate the current number of frags. 3068 */ 3069 curfrags = 0; 3070 for (m = m0; m != NULL; m = m->m_next) 3071 curfrags++; 3072 /* 3073 * First, try to collapse mbufs. Note that we always collapse 3074 * towards the front so we don't need to deal with moving the 3075 * pkthdr. This may be suboptimal if the first mbuf has much 3076 * less data than the following. 3077 */ 3078 m = m0; 3079again: 3080 for (;;) { 3081 n = m->m_next; 3082 if (n == NULL) 3083 break; 3084 if ((m->m_flags & M_RDONLY) == 0 && 3085 n->m_len < M_TRAILINGSPACE(m)) { 3086 bcopy(mtod(n, void *), mtod(m, char *) + m->m_len, 3087 n->m_len); 3088 m->m_len += n->m_len; 3089 m->m_next = n->m_next; 3090 m_free(n); 3091 if (--curfrags <= maxfrags) 3092 return m0; 3093 } else 3094 m = n; 3095 } 3096 KASSERT(maxfrags > 1, 3097 ("maxfrags %u, but normal collapse failed", maxfrags)); 3098 /* 3099 * Collapse consecutive mbufs to a cluster. 3100 */ 3101 prev = &m0->m_next; /* NB: not the first mbuf */ 3102 while ((n = *prev) != NULL) { 3103 if ((n2 = n->m_next) != NULL && 3104 n->m_len + n2->m_len < MCLBYTES) { 3105 m = m_getcl(how, MT_DATA, 0); 3106 if (m == NULL) 3107 goto bad; 3108 bcopy(mtod(n, void *), mtod(m, void *), n->m_len); 3109 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len, 3110 n2->m_len); 3111 m->m_len = n->m_len + n2->m_len; 3112 m->m_next = n2->m_next; 3113 *prev = m; 3114 m_free(n); 3115 m_free(n2); 3116 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */ 3117 return m0; 3118 /* 3119 * Still not there, try the normal collapse 3120 * again before we allocate another cluster. 3121 */ 3122 goto again; 3123 } 3124 prev = &n->m_next; 3125 } 3126 /* 3127 * No place where we can collapse to a cluster; punt. 3128 * This can occur if, for example, you request 2 frags 3129 * but the packet requires that both be clusters (we 3130 * never reallocate the first mbuf to avoid moving the 3131 * packet header). 3132 */ 3133bad: 3134 return NULL; 3135} 3136 3137static int 3138ath_tx_start(struct ath_softc *sc, struct ieee80211_node *ni, struct ath_buf *bf, 3139 struct mbuf *m0) 3140{ 3141 struct ieee80211com *ic = &sc->sc_ic; 3142 struct ath_hal *ah = sc->sc_ah; 3143 struct ifnet *ifp = sc->sc_ifp; 3144 const struct chanAccParams *cap = &ic->ic_wme.wme_chanParams; 3145 int i, error, iswep, ismcast, keyix, hdrlen, pktlen, try0; 3146 u_int8_t rix, txrate, ctsrate; 3147 u_int8_t cix = 0xff; /* NB: silence compiler */ 3148 struct ath_desc *ds, *ds0; 3149 struct ath_txq *txq; 3150 struct ieee80211_frame *wh; 3151 u_int subtype, flags, ctsduration; 3152 HAL_PKT_TYPE atype; 3153 const HAL_RATE_TABLE *rt; 3154 HAL_BOOL shortPreamble; 3155 struct ath_node *an; 3156 struct mbuf *m; 3157 u_int pri; 3158 3159 wh = mtod(m0, struct ieee80211_frame *); 3160 iswep = wh->i_fc[1] & IEEE80211_FC1_WEP; 3161 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3162 hdrlen = ieee80211_anyhdrsize(wh); 3163 /* 3164 * Packet length must not include any 3165 * pad bytes; deduct them here. 3166 */ 3167 pktlen = m0->m_pkthdr.len - (hdrlen & 3); 3168 3169 if (iswep) { 3170 const struct ieee80211_cipher *cip; 3171 struct ieee80211_key *k; 3172 3173 /* 3174 * Construct the 802.11 header+trailer for an encrypted 3175 * frame. The only reason this can fail is because of an 3176 * unknown or unsupported cipher/key type. 3177 */ 3178 k = ieee80211_crypto_encap(ic, ni, m0); 3179 if (k == NULL) { 3180 /* 3181 * This can happen when the key is yanked after the 3182 * frame was queued. Just discard the frame; the 3183 * 802.11 layer counts failures and provides 3184 * debugging/diagnostics. 3185 */ 3186 m_freem(m0); 3187 return EIO; 3188 } 3189 /* 3190 * Adjust the packet + header lengths for the crypto 3191 * additions and calculate the h/w key index. When 3192 * a s/w mic is done the frame will have had any mic 3193 * added to it prior to entry so skb->len above will 3194 * account for it. Otherwise we need to add it to the 3195 * packet length. 3196 */ 3197 cip = k->wk_cipher; 3198 hdrlen += cip->ic_header; 3199 pktlen += cip->ic_header + cip->ic_trailer; 3200 if ((k->wk_flags & IEEE80211_KEY_SWMIC) == 0) 3201 pktlen += cip->ic_miclen; 3202 keyix = k->wk_keyix; 3203 3204 /* packet header may have moved, reset our local pointer */ 3205 wh = mtod(m0, struct ieee80211_frame *); 3206 } else if (ni->ni_ucastkey.wk_cipher == &ieee80211_cipher_none) { 3207 /* 3208 * Use station key cache slot, if assigned. 3209 */ 3210 keyix = ni->ni_ucastkey.wk_keyix; 3211 if (keyix == IEEE80211_KEYIX_NONE) 3212 keyix = HAL_TXKEYIX_INVALID; 3213 } else 3214 keyix = HAL_TXKEYIX_INVALID; 3215 3216 pktlen += IEEE80211_CRC_LEN; 3217 3218 /* 3219 * Load the DMA map so any coalescing is done. This 3220 * also calculates the number of descriptors we need. 3221 */ 3222 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 3223 bf->bf_segs, &bf->bf_nseg, 3224 BUS_DMA_NOWAIT); 3225 if (error == EFBIG) { 3226 /* XXX packet requires too many descriptors */ 3227 bf->bf_nseg = ATH_TXDESC+1; 3228 } else if (error != 0) { 3229 sc->sc_stats.ast_tx_busdma++; 3230 m_freem(m0); 3231 return error; 3232 } 3233 /* 3234 * Discard null packets and check for packets that 3235 * require too many TX descriptors. We try to convert 3236 * the latter to a cluster. 3237 */ 3238 if (bf->bf_nseg > ATH_TXDESC) { /* too many desc's, linearize */ 3239 sc->sc_stats.ast_tx_linear++; 3240 m = ath_defrag(m0, M_DONTWAIT, ATH_TXDESC); 3241 if (m == NULL) { 3242 m_freem(m0); 3243 sc->sc_stats.ast_tx_nombuf++; 3244 return ENOMEM; 3245 } 3246 m0 = m; 3247 error = bus_dmamap_load_mbuf_sg(sc->sc_dmat, bf->bf_dmamap, m0, 3248 bf->bf_segs, &bf->bf_nseg, 3249 BUS_DMA_NOWAIT); 3250 if (error != 0) { 3251 sc->sc_stats.ast_tx_busdma++; 3252 m_freem(m0); 3253 return error; 3254 } 3255 KASSERT(bf->bf_nseg <= ATH_TXDESC, 3256 ("too many segments after defrag; nseg %u", bf->bf_nseg)); 3257 } else if (bf->bf_nseg == 0) { /* null packet, discard */ 3258 sc->sc_stats.ast_tx_nodata++; 3259 m_freem(m0); 3260 return EIO; 3261 } 3262 DPRINTF(sc, ATH_DEBUG_XMIT, "%s: m %p len %u\n", __func__, m0, pktlen); 3263 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, BUS_DMASYNC_PREWRITE); 3264 bf->bf_m = m0; 3265 bf->bf_node = ni; /* NB: held reference */ 3266 3267 /* setup descriptors */ 3268 ds = bf->bf_desc; 3269 rt = sc->sc_currates; 3270 KASSERT(rt != NULL, ("no rate table, mode %u", sc->sc_curmode)); 3271 3272 /* 3273 * NB: the 802.11 layer marks whether or not we should 3274 * use short preamble based on the current mode and 3275 * negotiated parameters. 3276 */ 3277 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 3278 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE)) { 3279 shortPreamble = AH_TRUE; 3280 sc->sc_stats.ast_tx_shortpre++; 3281 } else { 3282 shortPreamble = AH_FALSE; 3283 } 3284 3285 an = ATH_NODE(ni); 3286 flags = HAL_TXDESC_CLRDMASK; /* XXX needed for crypto errs */ 3287 /* 3288 * Calculate Atheros packet type from IEEE80211 packet header, 3289 * setup for rate calculations, and select h/w transmit queue. 3290 */ 3291 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) { 3292 case IEEE80211_FC0_TYPE_MGT: 3293 subtype = wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; 3294 if (subtype == IEEE80211_FC0_SUBTYPE_BEACON) 3295 atype = HAL_PKT_TYPE_BEACON; 3296 else if (subtype == IEEE80211_FC0_SUBTYPE_PROBE_RESP) 3297 atype = HAL_PKT_TYPE_PROBE_RESP; 3298 else if (subtype == IEEE80211_FC0_SUBTYPE_ATIM) 3299 atype = HAL_PKT_TYPE_ATIM; 3300 else 3301 atype = HAL_PKT_TYPE_NORMAL; /* XXX */ 3302 rix = 0; /* XXX lowest rate */ 3303 try0 = ATH_TXMAXTRY; 3304 if (shortPreamble) 3305 txrate = an->an_tx_mgtratesp; 3306 else 3307 txrate = an->an_tx_mgtrate; 3308 /* NB: force all management frames to highest queue */ 3309 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3310 /* NB: force all management frames to highest queue */ 3311 pri = WME_AC_VO; 3312 } else 3313 pri = WME_AC_BE; 3314 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3315 break; 3316 case IEEE80211_FC0_TYPE_CTL: 3317 atype = HAL_PKT_TYPE_PSPOLL; /* stop setting of duration */ 3318 rix = 0; /* XXX lowest rate */ 3319 try0 = ATH_TXMAXTRY; 3320 if (shortPreamble) 3321 txrate = an->an_tx_mgtratesp; 3322 else 3323 txrate = an->an_tx_mgtrate; 3324 /* NB: force all ctl frames to highest queue */ 3325 if (ni->ni_flags & IEEE80211_NODE_QOS) { 3326 /* NB: force all ctl frames to highest queue */ 3327 pri = WME_AC_VO; 3328 } else 3329 pri = WME_AC_BE; 3330 flags |= HAL_TXDESC_INTREQ; /* force interrupt */ 3331 break; 3332 case IEEE80211_FC0_TYPE_DATA: 3333 atype = HAL_PKT_TYPE_NORMAL; /* default */ 3334 /* 3335 * Data frames; consult the rate control module. 3336 */ 3337 ath_rate_findrate(sc, an, shortPreamble, pktlen, 3338 &rix, &try0, &txrate); 3339 sc->sc_txrate = txrate; /* for LED blinking */ 3340 /* 3341 * Default all non-QoS traffic to the background queue. 3342 */ 3343 if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) { 3344 pri = M_WME_GETAC(m0); 3345 if (cap->cap_wmeParams[pri].wmep_noackPolicy) { 3346 flags |= HAL_TXDESC_NOACK; 3347 sc->sc_stats.ast_tx_noack++; 3348 } 3349 } else 3350 pri = WME_AC_BE; 3351 break; 3352 default: 3353 if_printf(ifp, "bogus frame type 0x%x (%s)\n", 3354 wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK, __func__); 3355 /* XXX statistic */ 3356 m_freem(m0); 3357 return EIO; 3358 } 3359 txq = sc->sc_ac2q[pri]; 3360 3361 /* 3362 * When servicing one or more stations in power-save mode 3363 * multicast frames must be buffered until after the beacon. 3364 * We use the CAB queue for that. 3365 */ 3366 if (ismcast && ic->ic_ps_sta) { 3367 txq = sc->sc_cabq; 3368 /* XXX? more bit in 802.11 frame header */ 3369 } 3370 3371 /* 3372 * Calculate miscellaneous flags. 3373 */ 3374 if (ismcast) { 3375 flags |= HAL_TXDESC_NOACK; /* no ack on broad/multicast */ 3376 sc->sc_stats.ast_tx_noack++; 3377 } else if (pktlen > ic->ic_rtsthreshold) { 3378 flags |= HAL_TXDESC_RTSENA; /* RTS based on frame length */ 3379 cix = rt->info[rix].controlRate; 3380 sc->sc_stats.ast_tx_rts++; 3381 } 3382 3383 /* 3384 * If 802.11g protection is enabled, determine whether 3385 * to use RTS/CTS or just CTS. Note that this is only 3386 * done for OFDM unicast frames. 3387 */ 3388 if ((ic->ic_flags & IEEE80211_F_USEPROT) && 3389 rt->info[rix].phy == IEEE80211_T_OFDM && 3390 (flags & HAL_TXDESC_NOACK) == 0) { 3391 /* XXX fragments must use CCK rates w/ protection */ 3392 if (ic->ic_protmode == IEEE80211_PROT_RTSCTS) 3393 flags |= HAL_TXDESC_RTSENA; 3394 else if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) 3395 flags |= HAL_TXDESC_CTSENA; 3396 cix = rt->info[sc->sc_protrix].controlRate; 3397 sc->sc_stats.ast_tx_protect++; 3398 } 3399 3400 /* 3401 * Calculate duration. This logically belongs in the 802.11 3402 * layer but it lacks sufficient information to calculate it. 3403 */ 3404 if ((flags & HAL_TXDESC_NOACK) == 0 && 3405 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) != IEEE80211_FC0_TYPE_CTL) { 3406 u_int16_t dur; 3407 /* 3408 * XXX not right with fragmentation. 3409 */ 3410 if (shortPreamble) 3411 dur = rt->info[rix].spAckDuration; 3412 else 3413 dur = rt->info[rix].lpAckDuration; 3414 *(u_int16_t *)wh->i_dur = htole16(dur); 3415 } 3416 3417 /* 3418 * Calculate RTS/CTS rate and duration if needed. 3419 */ 3420 ctsduration = 0; 3421 if (flags & (HAL_TXDESC_RTSENA|HAL_TXDESC_CTSENA)) { 3422 /* 3423 * CTS transmit rate is derived from the transmit rate 3424 * by looking in the h/w rate table. We must also factor 3425 * in whether or not a short preamble is to be used. 3426 */ 3427 /* NB: cix is set above where RTS/CTS is enabled */ 3428 KASSERT(cix != 0xff, ("cix not setup")); 3429 ctsrate = rt->info[cix].rateCode; 3430 /* 3431 * Compute the transmit duration based on the frame 3432 * size and the size of an ACK frame. We call into the 3433 * HAL to do the computation since it depends on the 3434 * characteristics of the actual PHY being used. 3435 * 3436 * NB: CTS is assumed the same size as an ACK so we can 3437 * use the precalculated ACK durations. 3438 */ 3439 if (shortPreamble) { 3440 ctsrate |= rt->info[cix].shortPreamble; 3441 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3442 ctsduration += rt->info[cix].spAckDuration; 3443 ctsduration += ath_hal_computetxtime(ah, 3444 rt, pktlen, rix, AH_TRUE); 3445 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3446 ctsduration += rt->info[rix].spAckDuration; 3447 } else { 3448 if (flags & HAL_TXDESC_RTSENA) /* SIFS + CTS */ 3449 ctsduration += rt->info[cix].lpAckDuration; 3450 ctsduration += ath_hal_computetxtime(ah, 3451 rt, pktlen, rix, AH_FALSE); 3452 if ((flags & HAL_TXDESC_NOACK) == 0) /* SIFS + ACK */ 3453 ctsduration += rt->info[rix].lpAckDuration; 3454 } 3455 /* 3456 * Must disable multi-rate retry when using RTS/CTS. 3457 */ 3458 try0 = ATH_TXMAXTRY; 3459 } else 3460 ctsrate = 0; 3461 3462 if (IFF_DUMPPKTS(sc, ATH_DEBUG_XMIT)) 3463 ieee80211_dump_pkt(mtod(m0, caddr_t), m0->m_len, 3464 sc->sc_hwmap[txrate].ieeerate, -1); 3465 3466 if (ic->ic_rawbpf) 3467 bpf_mtap(ic->ic_rawbpf, m0); 3468 if (sc->sc_drvbpf) { 3469 u_int64_t tsf = ath_hal_gettsf64(ah); 3470 3471 sc->sc_tx_th.wt_tsf = htole64(tsf); 3472 sc->sc_tx_th.wt_flags = sc->sc_hwmap[txrate].txflags; 3473 if (iswep) 3474 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3475 sc->sc_tx_th.wt_rate = sc->sc_hwmap[txrate].ieeerate; 3476 sc->sc_tx_th.wt_txpower = ni->ni_txpower; 3477 sc->sc_tx_th.wt_antenna = sc->sc_txantenna; 3478 3479 bpf_mtap2(sc->sc_drvbpf, 3480 &sc->sc_tx_th, sc->sc_tx_th_len, m0); 3481 } 3482 3483 /* 3484 * Determine if a tx interrupt should be generated for 3485 * this descriptor. We take a tx interrupt to reap 3486 * descriptors when the h/w hits an EOL condition or 3487 * when the descriptor is specifically marked to generate 3488 * an interrupt. We periodically mark descriptors in this 3489 * way to insure timely replenishing of the supply needed 3490 * for sending frames. Defering interrupts reduces system 3491 * load and potentially allows more concurrent work to be 3492 * done but if done to aggressively can cause senders to 3493 * backup. 3494 * 3495 * NB: use >= to deal with sc_txintrperiod changing 3496 * dynamically through sysctl. 3497 */ 3498 if (flags & HAL_TXDESC_INTREQ) { 3499 txq->axq_intrcnt = 0; 3500 } else if (++txq->axq_intrcnt >= sc->sc_txintrperiod) { 3501 flags |= HAL_TXDESC_INTREQ; 3502 txq->axq_intrcnt = 0; 3503 } 3504 3505 /* 3506 * Formulate first tx descriptor with tx controls. 3507 */ 3508 /* XXX check return value? */ 3509 ath_hal_setuptxdesc(ah, ds 3510 , pktlen /* packet length */ 3511 , hdrlen /* header length */ 3512 , atype /* Atheros packet type */ 3513 , ni->ni_txpower /* txpower */ 3514 , txrate, try0 /* series 0 rate/tries */ 3515 , keyix /* key cache index */ 3516 , sc->sc_txantenna /* antenna mode */ 3517 , flags /* flags */ 3518 , ctsrate /* rts/cts rate */ 3519 , ctsduration /* rts/cts duration */ 3520 ); 3521 bf->bf_flags = flags; 3522 /* 3523 * Setup the multi-rate retry state only when we're 3524 * going to use it. This assumes ath_hal_setuptxdesc 3525 * initializes the descriptors (so we don't have to) 3526 * when the hardware supports multi-rate retry and 3527 * we don't use it. 3528 */ 3529 if (try0 != ATH_TXMAXTRY) 3530 ath_rate_setupxtxdesc(sc, an, ds, shortPreamble, rix); 3531 3532 /* 3533 * Fillin the remainder of the descriptor info. 3534 */ 3535 ds0 = ds; 3536 for (i = 0; i < bf->bf_nseg; i++, ds++) { 3537 ds->ds_data = bf->bf_segs[i].ds_addr; 3538 if (i == bf->bf_nseg - 1) 3539 ds->ds_link = 0; 3540 else 3541 ds->ds_link = bf->bf_daddr + sizeof(*ds) * (i + 1); 3542 ath_hal_filltxdesc(ah, ds 3543 , bf->bf_segs[i].ds_len /* segment length */ 3544 , i == 0 /* first segment */ 3545 , i == bf->bf_nseg - 1 /* last segment */ 3546 , ds0 /* first descriptor */ 3547 ); 3548 DPRINTF(sc, ATH_DEBUG_XMIT, 3549 "%s: %d: %08x %08x %08x %08x %08x %08x\n", 3550 __func__, i, ds->ds_link, ds->ds_data, 3551 ds->ds_ctl0, ds->ds_ctl1, ds->ds_hw[0], ds->ds_hw[1]); 3552 } 3553 /* 3554 * Insert the frame on the outbound list and 3555 * pass it on to the hardware. 3556 */ 3557 ATH_TXQ_LOCK(txq); 3558 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 3559 if (txq->axq_link == NULL) { 3560 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 3561 DPRINTF(sc, ATH_DEBUG_XMIT, 3562 "%s: TXDP[%u] = %p (%p) depth %d\n", __func__, 3563 txq->axq_qnum, (caddr_t)bf->bf_daddr, bf->bf_desc, 3564 txq->axq_depth); 3565 } else { 3566 *txq->axq_link = bf->bf_daddr; 3567 DPRINTF(sc, ATH_DEBUG_XMIT, 3568 "%s: link[%u](%p)=%p (%p) depth %d\n", __func__, 3569 txq->axq_qnum, txq->axq_link, 3570 (caddr_t)bf->bf_daddr, bf->bf_desc, txq->axq_depth); 3571 } 3572 txq->axq_link = &bf->bf_desc[bf->bf_nseg - 1].ds_link; 3573 /* 3574 * The CAB queue is started from the SWBA handler since 3575 * frames only go out on DTIM and to avoid possible races. 3576 */ 3577 if (txq != sc->sc_cabq) 3578 ath_hal_txstart(ah, txq->axq_qnum); 3579 ATH_TXQ_UNLOCK(txq); 3580 3581 return 0; 3582} 3583 3584/* 3585 * Process completed xmit descriptors from the specified queue. 3586 */ 3587static void 3588ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq) 3589{ 3590 struct ath_hal *ah = sc->sc_ah; 3591 struct ieee80211com *ic = &sc->sc_ic; 3592 struct ath_buf *bf; 3593 struct ath_desc *ds, *ds0; 3594 struct ieee80211_node *ni; 3595 struct ath_node *an; 3596 int sr, lr, pri; 3597 HAL_STATUS status; 3598 3599 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: tx queue %u head %p link %p\n", 3600 __func__, txq->axq_qnum, 3601 (caddr_t)(uintptr_t) ath_hal_gettxbuf(sc->sc_ah, txq->axq_qnum), 3602 txq->axq_link); 3603 for (;;) { 3604 ATH_TXQ_LOCK(txq); 3605 txq->axq_intrcnt = 0; /* reset periodic desc intr count */ 3606 bf = STAILQ_FIRST(&txq->axq_q); 3607 if (bf == NULL) { 3608 txq->axq_link = NULL; 3609 ATH_TXQ_UNLOCK(txq); 3610 break; 3611 } 3612 ds0 = &bf->bf_desc[0]; 3613 ds = &bf->bf_desc[bf->bf_nseg - 1]; 3614 status = ath_hal_txprocdesc(ah, ds); 3615#ifdef AR_DEBUG 3616 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 3617 ath_printtxbuf(bf, status == HAL_OK); 3618#endif 3619 if (status == HAL_EINPROGRESS) { 3620 ATH_TXQ_UNLOCK(txq); 3621 break; 3622 } 3623 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 3624 ATH_TXQ_UNLOCK(txq); 3625 3626 ni = bf->bf_node; 3627 if (ni != NULL) { 3628 an = ATH_NODE(ni); 3629 if (ds->ds_txstat.ts_status == 0) { 3630 u_int8_t txant = ds->ds_txstat.ts_antenna; 3631 sc->sc_stats.ast_ant_tx[txant]++; 3632 sc->sc_ant_tx[txant]++; 3633 if (ds->ds_txstat.ts_rate & HAL_TXSTAT_ALTRATE) 3634 sc->sc_stats.ast_tx_altrate++; 3635 sc->sc_stats.ast_tx_rssi = 3636 ds->ds_txstat.ts_rssi; 3637 ATH_RSSI_LPF(an->an_halstats.ns_avgtxrssi, 3638 ds->ds_txstat.ts_rssi); 3639 pri = M_WME_GETAC(bf->bf_m); 3640 if (pri >= WME_AC_VO) 3641 ic->ic_wme.wme_hipri_traffic++; 3642 ni->ni_inact = ni->ni_inact_reload; 3643 } else { 3644 if (ds->ds_txstat.ts_status & HAL_TXERR_XRETRY) 3645 sc->sc_stats.ast_tx_xretries++; 3646 if (ds->ds_txstat.ts_status & HAL_TXERR_FIFO) 3647 sc->sc_stats.ast_tx_fifoerr++; 3648 if (ds->ds_txstat.ts_status & HAL_TXERR_FILT) 3649 sc->sc_stats.ast_tx_filtered++; 3650 } 3651 sr = ds->ds_txstat.ts_shortretry; 3652 lr = ds->ds_txstat.ts_longretry; 3653 sc->sc_stats.ast_tx_shortretry += sr; 3654 sc->sc_stats.ast_tx_longretry += lr; 3655 /* 3656 * Hand the descriptor to the rate control algorithm. 3657 */ 3658 if ((ds->ds_txstat.ts_status & HAL_TXERR_FILT) == 0 && 3659 (bf->bf_flags & HAL_TXDESC_NOACK) == 0) 3660 ath_rate_tx_complete(sc, an, ds, ds0); 3661 /* 3662 * Reclaim reference to node. 3663 * 3664 * NB: the node may be reclaimed here if, for example 3665 * this is a DEAUTH message that was sent and the 3666 * node was timed out due to inactivity. 3667 */ 3668 ieee80211_free_node(ni); 3669 } 3670 bus_dmamap_sync(sc->sc_dmat, bf->bf_dmamap, 3671 BUS_DMASYNC_POSTWRITE); 3672 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3673 m_freem(bf->bf_m); 3674 bf->bf_m = NULL; 3675 bf->bf_node = NULL; 3676 3677 ATH_TXBUF_LOCK(sc); 3678 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 3679 ATH_TXBUF_UNLOCK(sc); 3680 } 3681} 3682 3683/* 3684 * Deferred processing of transmit interrupt; special-cased 3685 * for a single hardware transmit queue (e.g. 5210 and 5211). 3686 */ 3687static void 3688ath_tx_proc_q0(void *arg, int npending) 3689{ 3690 struct ath_softc *sc = arg; 3691 struct ifnet *ifp = sc->sc_ifp; 3692 3693 ath_tx_processq(sc, &sc->sc_txq[0]); 3694 ath_tx_processq(sc, sc->sc_cabq); 3695 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3696 sc->sc_tx_timer = 0; 3697 3698 if (sc->sc_softled) 3699 ath_led_event(sc, ATH_LED_TX); 3700 3701 ath_start(ifp); 3702} 3703 3704/* 3705 * Deferred processing of transmit interrupt; special-cased 3706 * for four hardware queues, 0-3 (e.g. 5212 w/ WME support). 3707 */ 3708static void 3709ath_tx_proc_q0123(void *arg, int npending) 3710{ 3711 struct ath_softc *sc = arg; 3712 struct ifnet *ifp = sc->sc_ifp; 3713 3714 /* 3715 * Process each active queue. 3716 */ 3717 ath_tx_processq(sc, &sc->sc_txq[0]); 3718 ath_tx_processq(sc, &sc->sc_txq[1]); 3719 ath_tx_processq(sc, &sc->sc_txq[2]); 3720 ath_tx_processq(sc, &sc->sc_txq[3]); 3721 ath_tx_processq(sc, sc->sc_cabq); 3722 3723 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3724 sc->sc_tx_timer = 0; 3725 3726 if (sc->sc_softled) 3727 ath_led_event(sc, ATH_LED_TX); 3728 3729 ath_start(ifp); 3730} 3731 3732/* 3733 * Deferred processing of transmit interrupt. 3734 */ 3735static void 3736ath_tx_proc(void *arg, int npending) 3737{ 3738 struct ath_softc *sc = arg; 3739 struct ifnet *ifp = sc->sc_ifp; 3740 int i; 3741 3742 /* 3743 * Process each active queue. 3744 */ 3745 /* XXX faster to read ISR_S0_S and ISR_S1_S to determine q's? */ 3746 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3747 if (ATH_TXQ_SETUP(sc, i)) 3748 ath_tx_processq(sc, &sc->sc_txq[i]); 3749 3750 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3751 sc->sc_tx_timer = 0; 3752 3753 if (sc->sc_softled) 3754 ath_led_event(sc, ATH_LED_TX); 3755 3756 ath_start(ifp); 3757} 3758 3759static void 3760ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq) 3761{ 3762 struct ath_hal *ah = sc->sc_ah; 3763 struct ieee80211_node *ni; 3764 struct ath_buf *bf; 3765 3766 /* 3767 * NB: this assumes output has been stopped and 3768 * we do not need to block ath_tx_tasklet 3769 */ 3770 for (;;) { 3771 ATH_TXQ_LOCK(txq); 3772 bf = STAILQ_FIRST(&txq->axq_q); 3773 if (bf == NULL) { 3774 txq->axq_link = NULL; 3775 ATH_TXQ_UNLOCK(txq); 3776 break; 3777 } 3778 ATH_TXQ_REMOVE_HEAD(txq, bf_list); 3779 ATH_TXQ_UNLOCK(txq); 3780#ifdef AR_DEBUG 3781 if (sc->sc_debug & ATH_DEBUG_RESET) 3782 ath_printtxbuf(bf, 3783 ath_hal_txprocdesc(ah, bf->bf_desc) == HAL_OK); 3784#endif /* AR_DEBUG */ 3785 bus_dmamap_unload(sc->sc_dmat, bf->bf_dmamap); 3786 m_freem(bf->bf_m); 3787 bf->bf_m = NULL; 3788 ni = bf->bf_node; 3789 bf->bf_node = NULL; 3790 if (ni != NULL) { 3791 /* 3792 * Reclaim node reference. 3793 */ 3794 ieee80211_free_node(ni); 3795 } 3796 ATH_TXBUF_LOCK(sc); 3797 STAILQ_INSERT_TAIL(&sc->sc_txbuf, bf, bf_list); 3798 ATH_TXBUF_UNLOCK(sc); 3799 } 3800} 3801 3802static void 3803ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq) 3804{ 3805 struct ath_hal *ah = sc->sc_ah; 3806 3807 (void) ath_hal_stoptxdma(ah, txq->axq_qnum); 3808 DPRINTF(sc, ATH_DEBUG_RESET, "%s: tx queue [%u] %p, link %p\n", 3809 __func__, txq->axq_qnum, 3810 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, txq->axq_qnum), 3811 txq->axq_link); 3812} 3813 3814/* 3815 * Drain the transmit queues and reclaim resources. 3816 */ 3817static void 3818ath_draintxq(struct ath_softc *sc) 3819{ 3820 struct ath_hal *ah = sc->sc_ah; 3821 struct ifnet *ifp = sc->sc_ifp; 3822 int i; 3823 3824 /* XXX return value */ 3825 if (!sc->sc_invalid) { 3826 /* don't touch the hardware if marked invalid */ 3827 (void) ath_hal_stoptxdma(ah, sc->sc_bhalq); 3828 DPRINTF(sc, ATH_DEBUG_RESET, 3829 "%s: beacon queue %p\n", __func__, 3830 (caddr_t)(uintptr_t) ath_hal_gettxbuf(ah, sc->sc_bhalq)); 3831 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3832 if (ATH_TXQ_SETUP(sc, i)) 3833 ath_tx_stopdma(sc, &sc->sc_txq[i]); 3834 } 3835 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) 3836 if (ATH_TXQ_SETUP(sc, i)) 3837 ath_tx_draintxq(sc, &sc->sc_txq[i]); 3838 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3839 sc->sc_tx_timer = 0; 3840} 3841 3842/* 3843 * Disable the receive h/w in preparation for a reset. 3844 */ 3845static void 3846ath_stoprecv(struct ath_softc *sc) 3847{ 3848#define PA2DESC(_sc, _pa) \ 3849 ((struct ath_desc *)((caddr_t)(_sc)->sc_rxdma.dd_desc + \ 3850 ((_pa) - (_sc)->sc_rxdma.dd_desc_paddr))) 3851 struct ath_hal *ah = sc->sc_ah; 3852 3853 ath_hal_stoppcurecv(ah); /* disable PCU */ 3854 ath_hal_setrxfilter(ah, 0); /* clear recv filter */ 3855 ath_hal_stopdmarecv(ah); /* disable DMA engine */ 3856 DELAY(3000); /* 3ms is long enough for 1 frame */ 3857#ifdef AR_DEBUG 3858 if (sc->sc_debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL)) { 3859 struct ath_buf *bf; 3860 3861 printf("%s: rx queue %p, link %p\n", __func__, 3862 (caddr_t)(uintptr_t) ath_hal_getrxbuf(ah), sc->sc_rxlink); 3863 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 3864 struct ath_desc *ds = bf->bf_desc; 3865 HAL_STATUS status = ath_hal_rxprocdesc(ah, ds, 3866 bf->bf_daddr, PA2DESC(sc, ds->ds_link)); 3867 if (status == HAL_OK || (sc->sc_debug & ATH_DEBUG_FATAL)) 3868 ath_printrxbuf(bf, status == HAL_OK); 3869 } 3870 } 3871#endif 3872 sc->sc_rxlink = NULL; /* just in case */ 3873#undef PA2DESC 3874} 3875 3876/* 3877 * Enable the receive h/w following a reset. 3878 */ 3879static int 3880ath_startrecv(struct ath_softc *sc) 3881{ 3882 struct ath_hal *ah = sc->sc_ah; 3883 struct ath_buf *bf; 3884 3885 sc->sc_rxlink = NULL; 3886 STAILQ_FOREACH(bf, &sc->sc_rxbuf, bf_list) { 3887 int error = ath_rxbuf_init(sc, bf); 3888 if (error != 0) { 3889 DPRINTF(sc, ATH_DEBUG_RECV, 3890 "%s: ath_rxbuf_init failed %d\n", 3891 __func__, error); 3892 return error; 3893 } 3894 } 3895 3896 bf = STAILQ_FIRST(&sc->sc_rxbuf); 3897 ath_hal_putrxbuf(ah, bf->bf_daddr); 3898 ath_hal_rxena(ah); /* enable recv descriptors */ 3899 ath_mode_init(sc); /* set filters, etc. */ 3900 ath_hal_startpcurecv(ah); /* re-enable PCU/DMA engine */ 3901 return 0; 3902} 3903 3904/* 3905 * Update internal state after a channel change. 3906 */ 3907static void 3908ath_chan_change(struct ath_softc *sc, struct ieee80211_channel *chan) 3909{ 3910 struct ieee80211com *ic = &sc->sc_ic; 3911 enum ieee80211_phymode mode; 3912 u_int16_t flags; 3913 3914 /* 3915 * Change channels and update the h/w rate map 3916 * if we're switching; e.g. 11a to 11b/g. 3917 */ 3918 mode = ieee80211_chan2mode(ic, chan); 3919 if (mode != sc->sc_curmode) 3920 ath_setcurmode(sc, mode); 3921 /* 3922 * Update BPF state. NB: ethereal et. al. don't handle 3923 * merged flags well so pick a unique mode for their use. 3924 */ 3925 if (IEEE80211_IS_CHAN_A(chan)) 3926 flags = IEEE80211_CHAN_A; 3927 /* XXX 11g schizophrenia */ 3928 else if (IEEE80211_IS_CHAN_G(chan) || 3929 IEEE80211_IS_CHAN_PUREG(chan)) 3930 flags = IEEE80211_CHAN_G; 3931 else 3932 flags = IEEE80211_CHAN_B; 3933 if (IEEE80211_IS_CHAN_T(chan)) 3934 flags |= IEEE80211_CHAN_TURBO; 3935 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 3936 htole16(chan->ic_freq); 3937 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 3938 htole16(flags); 3939} 3940 3941/* 3942 * Set/change channels. If the channel is really being changed, 3943 * it's done by reseting the chip. To accomplish this we must 3944 * first cleanup any pending DMA, then restart stuff after a la 3945 * ath_init. 3946 */ 3947static int 3948ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan) 3949{ 3950 struct ath_hal *ah = sc->sc_ah; 3951 struct ieee80211com *ic = &sc->sc_ic; 3952 HAL_CHANNEL hchan; 3953 3954 /* 3955 * Convert to a HAL channel description with 3956 * the flags constrained to reflect the current 3957 * operating mode. 3958 */ 3959 hchan.channel = chan->ic_freq; 3960 hchan.channelFlags = ath_chan2flags(ic, chan); 3961 3962 DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz) -> %u (%u MHz)\n", 3963 __func__, 3964 ath_hal_mhz2ieee(sc->sc_curchan.channel, 3965 sc->sc_curchan.channelFlags), 3966 sc->sc_curchan.channel, 3967 ath_hal_mhz2ieee(hchan.channel, hchan.channelFlags), hchan.channel); 3968 if (hchan.channel != sc->sc_curchan.channel || 3969 hchan.channelFlags != sc->sc_curchan.channelFlags) { 3970 HAL_STATUS status; 3971 3972 /* 3973 * To switch channels clear any pending DMA operations; 3974 * wait long enough for the RX fifo to drain, reset the 3975 * hardware at the new frequency, and then re-enable 3976 * the relevant bits of the h/w. 3977 */ 3978 ath_hal_intrset(ah, 0); /* disable interrupts */ 3979 ath_draintxq(sc); /* clear pending tx frames */ 3980 ath_stoprecv(sc); /* turn off frame recv */ 3981 if (!ath_hal_reset(ah, ic->ic_opmode, &hchan, AH_TRUE, &status)) { 3982 if_printf(ic->ic_ifp, "ath_chan_set: unable to reset " 3983 "channel %u (%u Mhz)\n", 3984 ieee80211_chan2ieee(ic, chan), chan->ic_freq); 3985 return EIO; 3986 } 3987 sc->sc_curchan = hchan; 3988 ath_update_txpow(sc); /* update tx power state */ 3989 sc->sc_diversity = ath_hal_getdiversity(ah); 3990 3991 /* 3992 * Re-enable rx framework. 3993 */ 3994 if (ath_startrecv(sc) != 0) { 3995 if_printf(ic->ic_ifp, 3996 "ath_chan_set: unable to restart recv logic\n"); 3997 return EIO; 3998 } 3999 4000 /* 4001 * Change channels and update the h/w rate map 4002 * if we're switching; e.g. 11a to 11b/g. 4003 */ 4004 ic->ic_ibss_chan = chan; 4005 ath_chan_change(sc, chan); 4006 4007 /* 4008 * Re-enable interrupts. 4009 */ 4010 ath_hal_intrset(ah, sc->sc_imask); 4011 } 4012 return 0; 4013} 4014 4015static void 4016ath_next_scan(void *arg) 4017{ 4018 struct ath_softc *sc = arg; 4019 struct ieee80211com *ic = &sc->sc_ic; 4020 4021 if (ic->ic_state == IEEE80211_S_SCAN) 4022 ieee80211_next_scan(ic); 4023} 4024 4025/* 4026 * Periodically recalibrate the PHY to account 4027 * for temperature/environment changes. 4028 */ 4029static void 4030ath_calibrate(void *arg) 4031{ 4032 struct ath_softc *sc = arg; 4033 struct ath_hal *ah = sc->sc_ah; 4034 4035 sc->sc_stats.ast_per_cal++; 4036 4037 DPRINTF(sc, ATH_DEBUG_CALIBRATE, "%s: channel %u/%x\n", 4038 __func__, sc->sc_curchan.channel, sc->sc_curchan.channelFlags); 4039 4040 if (ath_hal_getrfgain(ah) == HAL_RFGAIN_NEED_CHANGE) { 4041 /* 4042 * Rfgain is out of bounds, reset the chip 4043 * to load new gain values. 4044 */ 4045 sc->sc_stats.ast_per_rfgain++; 4046 ath_reset(sc->sc_ifp); 4047 } 4048 if (!ath_hal_calibrate(ah, &sc->sc_curchan)) { 4049 DPRINTF(sc, ATH_DEBUG_ANY, 4050 "%s: calibration of channel %u failed\n", 4051 __func__, sc->sc_curchan.channel); 4052 sc->sc_stats.ast_per_calfail++; 4053 } 4054 /* 4055 * Calibrate noise floor data again in case of change. 4056 */ 4057 ath_hal_process_noisefloor(ah); 4058 callout_reset(&sc->sc_cal_ch, ath_calinterval * hz, ath_calibrate, sc); 4059} 4060 4061static int 4062ath_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg) 4063{ 4064 struct ifnet *ifp = ic->ic_ifp; 4065 struct ath_softc *sc = ifp->if_softc; 4066 struct ath_hal *ah = sc->sc_ah; 4067 struct ieee80211_node *ni; 4068 int i, error; 4069 const u_int8_t *bssid; 4070 u_int32_t rfilt; 4071 static const HAL_LED_STATE leds[] = { 4072 HAL_LED_INIT, /* IEEE80211_S_INIT */ 4073 HAL_LED_SCAN, /* IEEE80211_S_SCAN */ 4074 HAL_LED_AUTH, /* IEEE80211_S_AUTH */ 4075 HAL_LED_ASSOC, /* IEEE80211_S_ASSOC */ 4076 HAL_LED_RUN, /* IEEE80211_S_RUN */ 4077 }; 4078 4079 DPRINTF(sc, ATH_DEBUG_STATE, "%s: %s -> %s\n", __func__, 4080 ieee80211_state_name[ic->ic_state], 4081 ieee80211_state_name[nstate]); 4082 4083 callout_stop(&sc->sc_scan_ch); 4084 callout_stop(&sc->sc_cal_ch); 4085 ath_hal_setledstate(ah, leds[nstate]); /* set LED */ 4086 4087 if (nstate == IEEE80211_S_INIT) { 4088 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4089 /* 4090 * NB: disable interrupts so we don't rx frames. 4091 */ 4092 ath_hal_intrset(ah, sc->sc_imask &~ HAL_INT_GLOBAL); 4093 /* 4094 * Notify the rate control algorithm. 4095 */ 4096 ath_rate_newstate(sc, nstate); 4097 goto done; 4098 } 4099 ni = ic->ic_bss; 4100 error = ath_chan_set(sc, ic->ic_curchan); 4101 if (error != 0) 4102 goto bad; 4103 rfilt = ath_calcrxfilter(sc, nstate); 4104 if (nstate == IEEE80211_S_SCAN) 4105 bssid = ifp->if_broadcastaddr; 4106 else 4107 bssid = ni->ni_bssid; 4108 ath_hal_setrxfilter(ah, rfilt); 4109 DPRINTF(sc, ATH_DEBUG_STATE, "%s: RX filter 0x%x bssid %s\n", 4110 __func__, rfilt, ether_sprintf(bssid)); 4111 4112 if (nstate == IEEE80211_S_RUN && ic->ic_opmode == IEEE80211_M_STA) 4113 ath_hal_setassocid(ah, bssid, ni->ni_associd); 4114 else 4115 ath_hal_setassocid(ah, bssid, 0); 4116 if (ic->ic_flags & IEEE80211_F_PRIVACY) { 4117 for (i = 0; i < IEEE80211_WEP_NKID; i++) 4118 if (ath_hal_keyisvalid(ah, i)) 4119 ath_hal_keysetmac(ah, i, bssid); 4120 } 4121 4122 /* 4123 * Notify the rate control algorithm so rates 4124 * are setup should ath_beacon_alloc be called. 4125 */ 4126 ath_rate_newstate(sc, nstate); 4127 4128 if (ic->ic_opmode == IEEE80211_M_MONITOR) { 4129 /* nothing to do */; 4130 } else if (nstate == IEEE80211_S_RUN) { 4131 DPRINTF(sc, ATH_DEBUG_STATE, 4132 "%s(RUN): ic_flags=0x%08x iv=%d bssid=%s " 4133 "capinfo=0x%04x chan=%d\n" 4134 , __func__ 4135 , ic->ic_flags 4136 , ni->ni_intval 4137 , ether_sprintf(ni->ni_bssid) 4138 , ni->ni_capinfo 4139 , ieee80211_chan2ieee(ic, ic->ic_curchan)); 4140 4141 switch (ic->ic_opmode) { 4142 case IEEE80211_M_HOSTAP: 4143 case IEEE80211_M_IBSS: 4144 /* 4145 * Allocate and setup the beacon frame. 4146 * 4147 * Stop any previous beacon DMA. This may be 4148 * necessary, for example, when an ibss merge 4149 * causes reconfiguration; there will be a state 4150 * transition from RUN->RUN that means we may 4151 * be called with beacon transmission active. 4152 */ 4153 ath_hal_stoptxdma(ah, sc->sc_bhalq); 4154 ath_beacon_free(sc); 4155 error = ath_beacon_alloc(sc, ni); 4156 if (error != 0) 4157 goto bad; 4158 break; 4159 case IEEE80211_M_STA: 4160 /* 4161 * Allocate a key cache slot to the station. 4162 */ 4163 if ((ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && 4164 sc->sc_hasclrkey && 4165 ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE) 4166 ath_setup_stationkey(ni); 4167 break; 4168 default: 4169 break; 4170 } 4171 4172 /* 4173 * Let the hal process statistics collected during a 4174 * scan so it can provide calibrated noise floor data. 4175 */ 4176 ath_hal_process_noisefloor(ah); 4177 /* 4178 * Configure the beacon and sleep timers. 4179 */ 4180 ath_beacon_config(sc); 4181 } else { 4182 ath_hal_intrset(ah, 4183 sc->sc_imask &~ (HAL_INT_SWBA | HAL_INT_BMISS)); 4184 sc->sc_imask &= ~(HAL_INT_SWBA | HAL_INT_BMISS); 4185 } 4186done: 4187 /* 4188 * Invoke the parent method to complete the work. 4189 */ 4190 error = sc->sc_newstate(ic, nstate, arg); 4191 /* 4192 * Finally, start any timers. 4193 */ 4194 if (nstate == IEEE80211_S_RUN) { 4195 /* start periodic recalibration timer */ 4196 callout_reset(&sc->sc_cal_ch, ath_calinterval * hz, 4197 ath_calibrate, sc); 4198 } else if (nstate == IEEE80211_S_SCAN) { 4199 /* start ap/neighbor scan timer */ 4200 callout_reset(&sc->sc_scan_ch, (ath_dwelltime * hz) / 1000, 4201 ath_next_scan, sc); 4202 } 4203bad: 4204 return error; 4205} 4206 4207/* 4208 * Allocate a key cache slot to the station so we can 4209 * setup a mapping from key index to node. The key cache 4210 * slot is needed for managing antenna state and for 4211 * compression when stations do not use crypto. We do 4212 * it uniliaterally here; if crypto is employed this slot 4213 * will be reassigned. 4214 */ 4215static void 4216ath_setup_stationkey(struct ieee80211_node *ni) 4217{ 4218 struct ieee80211com *ic = ni->ni_ic; 4219 struct ath_softc *sc = ic->ic_ifp->if_softc; 4220 ieee80211_keyix keyix, rxkeyix; 4221 4222 if (!ath_key_alloc(ic, &ni->ni_ucastkey, &keyix, &rxkeyix)) { 4223 /* 4224 * Key cache is full; we'll fall back to doing 4225 * the more expensive lookup in software. Note 4226 * this also means no h/w compression. 4227 */ 4228 /* XXX msg+statistic */ 4229 } else { 4230 /* XXX locking? */ 4231 ni->ni_ucastkey.wk_keyix = keyix; 4232 ni->ni_ucastkey.wk_rxkeyix = rxkeyix; 4233 /* NB: this will create a pass-thru key entry */ 4234 ath_keyset(sc, &ni->ni_ucastkey, ni->ni_macaddr, ic->ic_bss); 4235 } 4236} 4237 4238/* 4239 * Setup driver-specific state for a newly associated node. 4240 * Note that we're called also on a re-associate, the isnew 4241 * param tells us if this is the first time or not. 4242 */ 4243static void 4244ath_newassoc(struct ieee80211_node *ni, int isnew) 4245{ 4246 struct ieee80211com *ic = ni->ni_ic; 4247 struct ath_softc *sc = ic->ic_ifp->if_softc; 4248 4249 ath_rate_newassoc(sc, ATH_NODE(ni), isnew); 4250 if (isnew && 4251 (ic->ic_flags & IEEE80211_F_PRIVACY) == 0 && sc->sc_hasclrkey) { 4252 KASSERT(ni->ni_ucastkey.wk_keyix == IEEE80211_KEYIX_NONE, 4253 ("new assoc with a unicast key already setup (keyix %u)", 4254 ni->ni_ucastkey.wk_keyix)); 4255 ath_setup_stationkey(ni); 4256 } 4257} 4258 4259static int 4260ath_getchannels(struct ath_softc *sc, u_int cc, 4261 HAL_BOOL outdoor, HAL_BOOL xchanmode) 4262{ 4263 struct ieee80211com *ic = &sc->sc_ic; 4264 struct ifnet *ifp = sc->sc_ifp; 4265 struct ath_hal *ah = sc->sc_ah; 4266 HAL_CHANNEL *chans; 4267 int i, ix, nchan; 4268 4269 chans = malloc(IEEE80211_CHAN_MAX * sizeof(HAL_CHANNEL), 4270 M_TEMP, M_NOWAIT); 4271 if (chans == NULL) { 4272 if_printf(ifp, "unable to allocate channel table\n"); 4273 return ENOMEM; 4274 } 4275 if (!ath_hal_init_channels(ah, chans, IEEE80211_CHAN_MAX, &nchan, 4276 cc, HAL_MODE_ALL, outdoor, xchanmode)) { 4277 u_int32_t rd; 4278 4279 ath_hal_getregdomain(ah, &rd); 4280 if_printf(ifp, "unable to collect channel list from hal; " 4281 "regdomain likely %u country code %u\n", rd, cc); 4282 free(chans, M_TEMP); 4283 return EINVAL; 4284 } 4285 4286 /* 4287 * Convert HAL channels to ieee80211 ones and insert 4288 * them in the table according to their channel number. 4289 */ 4290 for (i = 0; i < nchan; i++) { 4291 HAL_CHANNEL *c = &chans[i]; 4292 ix = ath_hal_mhz2ieee(c->channel, c->channelFlags); 4293 if (ix > IEEE80211_CHAN_MAX) { 4294 if_printf(ifp, "bad hal channel %u (%u/%x) ignored\n", 4295 ix, c->channel, c->channelFlags); 4296 continue; 4297 } 4298 /* NB: flags are known to be compatible */ 4299 if (ic->ic_channels[ix].ic_freq == 0) { 4300 ic->ic_channels[ix].ic_freq = c->channel; 4301 ic->ic_channels[ix].ic_flags = c->channelFlags; 4302 } else { 4303 /* channels overlap; e.g. 11g and 11b */ 4304 ic->ic_channels[ix].ic_flags |= c->channelFlags; 4305 } 4306 } 4307 free(chans, M_TEMP); 4308 return 0; 4309} 4310 4311static void 4312ath_led_done(void *arg) 4313{ 4314 struct ath_softc *sc = arg; 4315 4316 sc->sc_blinking = 0; 4317} 4318 4319/* 4320 * Turn the LED off: flip the pin and then set a timer so no 4321 * update will happen for the specified duration. 4322 */ 4323static void 4324ath_led_off(void *arg) 4325{ 4326 struct ath_softc *sc = arg; 4327 4328 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, !sc->sc_ledon); 4329 callout_reset(&sc->sc_ledtimer, sc->sc_ledoff, ath_led_done, sc); 4330} 4331 4332/* 4333 * Blink the LED according to the specified on/off times. 4334 */ 4335static void 4336ath_led_blink(struct ath_softc *sc, int on, int off) 4337{ 4338 DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off); 4339 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, sc->sc_ledon); 4340 sc->sc_blinking = 1; 4341 sc->sc_ledoff = off; 4342 callout_reset(&sc->sc_ledtimer, on, ath_led_off, sc); 4343} 4344 4345static void 4346ath_led_event(struct ath_softc *sc, int event) 4347{ 4348 4349 sc->sc_ledevent = ticks; /* time of last event */ 4350 if (sc->sc_blinking) /* don't interrupt active blink */ 4351 return; 4352 switch (event) { 4353 case ATH_LED_POLL: 4354 ath_led_blink(sc, sc->sc_hwmap[0].ledon, 4355 sc->sc_hwmap[0].ledoff); 4356 break; 4357 case ATH_LED_TX: 4358 ath_led_blink(sc, sc->sc_hwmap[sc->sc_txrate].ledon, 4359 sc->sc_hwmap[sc->sc_txrate].ledoff); 4360 break; 4361 case ATH_LED_RX: 4362 ath_led_blink(sc, sc->sc_hwmap[sc->sc_rxrate].ledon, 4363 sc->sc_hwmap[sc->sc_rxrate].ledoff); 4364 break; 4365 } 4366} 4367 4368static void 4369ath_update_txpow(struct ath_softc *sc) 4370{ 4371 struct ieee80211com *ic = &sc->sc_ic; 4372 struct ath_hal *ah = sc->sc_ah; 4373 u_int32_t txpow; 4374 4375 if (sc->sc_curtxpow != ic->ic_txpowlimit) { 4376 ath_hal_settxpowlimit(ah, ic->ic_txpowlimit); 4377 /* read back in case value is clamped */ 4378 ath_hal_gettxpowlimit(ah, &txpow); 4379 ic->ic_txpowlimit = sc->sc_curtxpow = txpow; 4380 } 4381 /* 4382 * Fetch max tx power level for status requests. 4383 */ 4384 ath_hal_getmaxtxpow(sc->sc_ah, &txpow); 4385 ic->ic_bss->ni_txpower = txpow; 4386} 4387 4388static int 4389ath_rate_setup(struct ath_softc *sc, u_int mode) 4390{ 4391 struct ath_hal *ah = sc->sc_ah; 4392 struct ieee80211com *ic = &sc->sc_ic; 4393 const HAL_RATE_TABLE *rt; 4394 struct ieee80211_rateset *rs; 4395 int i, maxrates; 4396 4397 switch (mode) { 4398 case IEEE80211_MODE_11A: 4399 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11A); 4400 break; 4401 case IEEE80211_MODE_11B: 4402 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11B); 4403 break; 4404 case IEEE80211_MODE_11G: 4405 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_11G); 4406 break; 4407 case IEEE80211_MODE_TURBO_A: 4408 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_TURBO); 4409 break; 4410 case IEEE80211_MODE_TURBO_G: 4411 sc->sc_rates[mode] = ath_hal_getratetable(ah, HAL_MODE_108G); 4412 break; 4413 default: 4414 DPRINTF(sc, ATH_DEBUG_ANY, "%s: invalid mode %u\n", 4415 __func__, mode); 4416 return 0; 4417 } 4418 rt = sc->sc_rates[mode]; 4419 if (rt == NULL) 4420 return 0; 4421 if (rt->rateCount > IEEE80211_RATE_MAXSIZE) { 4422 DPRINTF(sc, ATH_DEBUG_ANY, 4423 "%s: rate table too small (%u > %u)\n", 4424 __func__, rt->rateCount, IEEE80211_RATE_MAXSIZE); 4425 maxrates = IEEE80211_RATE_MAXSIZE; 4426 } else 4427 maxrates = rt->rateCount; 4428 rs = &ic->ic_sup_rates[mode]; 4429 for (i = 0; i < maxrates; i++) 4430 rs->rs_rates[i] = rt->info[i].dot11Rate; 4431 rs->rs_nrates = maxrates; 4432 return 1; 4433} 4434 4435static void 4436ath_setcurmode(struct ath_softc *sc, enum ieee80211_phymode mode) 4437{ 4438#define N(a) (sizeof(a)/sizeof(a[0])) 4439 /* NB: on/off times from the Atheros NDIS driver, w/ permission */ 4440 static const struct { 4441 u_int rate; /* tx/rx 802.11 rate */ 4442 u_int16_t timeOn; /* LED on time (ms) */ 4443 u_int16_t timeOff; /* LED off time (ms) */ 4444 } blinkrates[] = { 4445 { 108, 40, 10 }, 4446 { 96, 44, 11 }, 4447 { 72, 50, 13 }, 4448 { 48, 57, 14 }, 4449 { 36, 67, 16 }, 4450 { 24, 80, 20 }, 4451 { 22, 100, 25 }, 4452 { 18, 133, 34 }, 4453 { 12, 160, 40 }, 4454 { 10, 200, 50 }, 4455 { 6, 240, 58 }, 4456 { 4, 267, 66 }, 4457 { 2, 400, 100 }, 4458 { 0, 500, 130 }, 4459 }; 4460 const HAL_RATE_TABLE *rt; 4461 int i, j; 4462 4463 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap)); 4464 rt = sc->sc_rates[mode]; 4465 KASSERT(rt != NULL, ("no h/w rate set for phy mode %u", mode)); 4466 for (i = 0; i < rt->rateCount; i++) 4467 sc->sc_rixmap[rt->info[i].dot11Rate & IEEE80211_RATE_VAL] = i; 4468 memset(sc->sc_hwmap, 0, sizeof(sc->sc_hwmap)); 4469 for (i = 0; i < 32; i++) { 4470 u_int8_t ix = rt->rateCodeToIndex[i]; 4471 if (ix == 0xff) { 4472 sc->sc_hwmap[i].ledon = (500 * hz) / 1000; 4473 sc->sc_hwmap[i].ledoff = (130 * hz) / 1000; 4474 continue; 4475 } 4476 sc->sc_hwmap[i].ieeerate = 4477 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL; 4478 sc->sc_hwmap[i].txflags = IEEE80211_RADIOTAP_F_DATAPAD; 4479 if (rt->info[ix].shortPreamble || 4480 rt->info[ix].phy == IEEE80211_T_OFDM) 4481 sc->sc_hwmap[i].txflags |= IEEE80211_RADIOTAP_F_SHORTPRE; 4482 /* NB: receive frames include FCS */ 4483 sc->sc_hwmap[i].rxflags = sc->sc_hwmap[i].txflags | 4484 IEEE80211_RADIOTAP_F_FCS; 4485 /* setup blink rate table to avoid per-packet lookup */ 4486 for (j = 0; j < N(blinkrates)-1; j++) 4487 if (blinkrates[j].rate == sc->sc_hwmap[i].ieeerate) 4488 break; 4489 /* NB: this uses the last entry if the rate isn't found */ 4490 /* XXX beware of overlow */ 4491 sc->sc_hwmap[i].ledon = (blinkrates[j].timeOn * hz) / 1000; 4492 sc->sc_hwmap[i].ledoff = (blinkrates[j].timeOff * hz) / 1000; 4493 } 4494 sc->sc_currates = rt; 4495 sc->sc_curmode = mode; 4496 /* 4497 * All protection frames are transmited at 2Mb/s for 4498 * 11g, otherwise at 1Mb/s. 4499 * XXX select protection rate index from rate table. 4500 */ 4501 sc->sc_protrix = (mode == IEEE80211_MODE_11G ? 1 : 0); 4502 /* NB: caller is responsible for reseting rate control state */ 4503#undef N 4504} 4505 4506#ifdef AR_DEBUG 4507static void 4508ath_printrxbuf(struct ath_buf *bf, int done) 4509{ 4510 struct ath_desc *ds; 4511 int i; 4512 4513 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 4514 printf("R%d (%p %p) %08x %08x %08x %08x %08x %08x %c\n", 4515 i, ds, (struct ath_desc *)bf->bf_daddr + i, 4516 ds->ds_link, ds->ds_data, 4517 ds->ds_ctl0, ds->ds_ctl1, 4518 ds->ds_hw[0], ds->ds_hw[1], 4519 !done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!'); 4520 } 4521} 4522 4523static void 4524ath_printtxbuf(struct ath_buf *bf, int done) 4525{ 4526 struct ath_desc *ds; 4527 int i; 4528 4529 for (i = 0, ds = bf->bf_desc; i < bf->bf_nseg; i++, ds++) { 4530 printf("T%d (%p %p) %08x %08x %08x %08x %08x %08x %08x %08x %c\n", 4531 i, ds, (struct ath_desc *)bf->bf_daddr + i, 4532 ds->ds_link, ds->ds_data, 4533 ds->ds_ctl0, ds->ds_ctl1, 4534 ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3], 4535 !done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!'); 4536 } 4537} 4538#endif /* AR_DEBUG */ 4539 4540static void 4541ath_watchdog(struct ifnet *ifp) 4542{ 4543 struct ath_softc *sc = ifp->if_softc; 4544 struct ieee80211com *ic = &sc->sc_ic; 4545 4546 ifp->if_timer = 0; 4547 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || sc->sc_invalid) 4548 return; 4549 if (sc->sc_tx_timer) { 4550 if (--sc->sc_tx_timer == 0) { 4551 if_printf(ifp, "device timeout\n"); 4552 ath_reset(ifp); 4553 ifp->if_oerrors++; 4554 sc->sc_stats.ast_watchdog++; 4555 } else 4556 ifp->if_timer = 1; 4557 } 4558 ieee80211_watchdog(ic); 4559} 4560 4561/* 4562 * Diagnostic interface to the HAL. This is used by various 4563 * tools to do things like retrieve register contents for 4564 * debugging. The mechanism is intentionally opaque so that 4565 * it can change frequently w/o concern for compatiblity. 4566 */ 4567static int 4568ath_ioctl_diag(struct ath_softc *sc, struct ath_diag *ad) 4569{ 4570 struct ath_hal *ah = sc->sc_ah; 4571 u_int id = ad->ad_id & ATH_DIAG_ID; 4572 void *indata = NULL; 4573 void *outdata = NULL; 4574 u_int32_t insize = ad->ad_in_size; 4575 u_int32_t outsize = ad->ad_out_size; 4576 int error = 0; 4577 4578 if (ad->ad_id & ATH_DIAG_IN) { 4579 /* 4580 * Copy in data. 4581 */ 4582 indata = malloc(insize, M_TEMP, M_NOWAIT); 4583 if (indata == NULL) { 4584 error = ENOMEM; 4585 goto bad; 4586 } 4587 error = copyin(ad->ad_in_data, indata, insize); 4588 if (error) 4589 goto bad; 4590 } 4591 if (ad->ad_id & ATH_DIAG_DYN) { 4592 /* 4593 * Allocate a buffer for the results (otherwise the HAL 4594 * returns a pointer to a buffer where we can read the 4595 * results). Note that we depend on the HAL leaving this 4596 * pointer for us to use below in reclaiming the buffer; 4597 * may want to be more defensive. 4598 */ 4599 outdata = malloc(outsize, M_TEMP, M_NOWAIT); 4600 if (outdata == NULL) { 4601 error = ENOMEM; 4602 goto bad; 4603 } 4604 } 4605 if (ath_hal_getdiagstate(ah, id, indata, insize, &outdata, &outsize)) { 4606 if (outsize < ad->ad_out_size) 4607 ad->ad_out_size = outsize; 4608 if (outdata != NULL) 4609 error = copyout(outdata, ad->ad_out_data, 4610 ad->ad_out_size); 4611 } else { 4612 error = EINVAL; 4613 } 4614bad: 4615 if ((ad->ad_id & ATH_DIAG_IN) && indata != NULL) 4616 free(indata, M_TEMP); 4617 if ((ad->ad_id & ATH_DIAG_DYN) && outdata != NULL) 4618 free(outdata, M_TEMP); 4619 return error; 4620} 4621 4622static int 4623ath_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 4624{ 4625#define IS_RUNNING(ifp) \ 4626 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 4627 struct ath_softc *sc = ifp->if_softc; 4628 struct ieee80211com *ic = &sc->sc_ic; 4629 struct ifreq *ifr = (struct ifreq *)data; 4630 int error = 0; 4631 4632 ATH_LOCK(sc); 4633 switch (cmd) { 4634 case SIOCSIFFLAGS: 4635 if (IS_RUNNING(ifp)) { 4636 /* 4637 * To avoid rescanning another access point, 4638 * do not call ath_init() here. Instead, 4639 * only reflect promisc mode settings. 4640 */ 4641 ath_mode_init(sc); 4642 } else if (ifp->if_flags & IFF_UP) { 4643 /* 4644 * Beware of being called during attach/detach 4645 * to reset promiscuous mode. In that case we 4646 * will still be marked UP but not RUNNING. 4647 * However trying to re-init the interface 4648 * is the wrong thing to do as we've already 4649 * torn down much of our state. There's 4650 * probably a better way to deal with this. 4651 */ 4652 if (!sc->sc_invalid && ic->ic_bss != NULL) 4653 ath_init(sc); /* XXX lose error */ 4654 } else 4655 ath_stop_locked(ifp); 4656 break; 4657 case SIOCADDMULTI: 4658 case SIOCDELMULTI: 4659 /* 4660 * The upper layer has already installed/removed 4661 * the multicast address(es), just recalculate the 4662 * multicast filter for the card. 4663 */ 4664 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4665 ath_mode_init(sc); 4666 break; 4667 case SIOCGATHSTATS: 4668 /* NB: embed these numbers to get a consistent view */ 4669 sc->sc_stats.ast_tx_packets = ifp->if_opackets; 4670 sc->sc_stats.ast_rx_packets = ifp->if_ipackets; 4671 sc->sc_stats.ast_rx_rssi = ieee80211_getrssi(ic); 4672 ATH_UNLOCK(sc); 4673 /* 4674 * NB: Drop the softc lock in case of a page fault; 4675 * we'll accept any potential inconsisentcy in the 4676 * statistics. The alternative is to copy the data 4677 * to a local structure. 4678 */ 4679 return copyout(&sc->sc_stats, 4680 ifr->ifr_data, sizeof (sc->sc_stats)); 4681 case SIOCGATHDIAG: 4682 error = ath_ioctl_diag(sc, (struct ath_diag *) ifr); 4683 break; 4684 default: 4685 error = ieee80211_ioctl(ic, cmd, data); 4686 if (error == ENETRESET) { 4687 if (IS_RUNNING(ifp) && 4688 ic->ic_roaming != IEEE80211_ROAMING_MANUAL) 4689 ath_init(sc); /* XXX lose error */ 4690 error = 0; 4691 } 4692 if (error == ERESTART) 4693 error = IS_RUNNING(ifp) ? ath_reset(ifp) : 0; 4694 break; 4695 } 4696 ATH_UNLOCK(sc); 4697 return error; 4698#undef IS_RUNNING 4699} 4700 4701static int 4702ath_sysctl_slottime(SYSCTL_HANDLER_ARGS) 4703{ 4704 struct ath_softc *sc = arg1; 4705 u_int slottime = ath_hal_getslottime(sc->sc_ah); 4706 int error; 4707 4708 error = sysctl_handle_int(oidp, &slottime, 0, req); 4709 if (error || !req->newptr) 4710 return error; 4711 return !ath_hal_setslottime(sc->sc_ah, slottime) ? EINVAL : 0; 4712} 4713 4714static int 4715ath_sysctl_acktimeout(SYSCTL_HANDLER_ARGS) 4716{ 4717 struct ath_softc *sc = arg1; 4718 u_int acktimeout = ath_hal_getacktimeout(sc->sc_ah); 4719 int error; 4720 4721 error = sysctl_handle_int(oidp, &acktimeout, 0, req); 4722 if (error || !req->newptr) 4723 return error; 4724 return !ath_hal_setacktimeout(sc->sc_ah, acktimeout) ? EINVAL : 0; 4725} 4726 4727static int 4728ath_sysctl_ctstimeout(SYSCTL_HANDLER_ARGS) 4729{ 4730 struct ath_softc *sc = arg1; 4731 u_int ctstimeout = ath_hal_getctstimeout(sc->sc_ah); 4732 int error; 4733 4734 error = sysctl_handle_int(oidp, &ctstimeout, 0, req); 4735 if (error || !req->newptr) 4736 return error; 4737 return !ath_hal_setctstimeout(sc->sc_ah, ctstimeout) ? EINVAL : 0; 4738} 4739 4740static int 4741ath_sysctl_softled(SYSCTL_HANDLER_ARGS) 4742{ 4743 struct ath_softc *sc = arg1; 4744 int softled = sc->sc_softled; 4745 int error; 4746 4747 error = sysctl_handle_int(oidp, &softled, 0, req); 4748 if (error || !req->newptr) 4749 return error; 4750 softled = (softled != 0); 4751 if (softled != sc->sc_softled) { 4752 if (softled) { 4753 /* NB: handle any sc_ledpin change */ 4754 ath_hal_gpioCfgOutput(sc->sc_ah, sc->sc_ledpin); 4755 ath_hal_gpioset(sc->sc_ah, sc->sc_ledpin, 4756 !sc->sc_ledon); 4757 } 4758 sc->sc_softled = softled; 4759 } 4760 return 0; 4761} 4762 4763static int 4764ath_sysctl_rxantenna(SYSCTL_HANDLER_ARGS) 4765{ 4766 struct ath_softc *sc = arg1; 4767 u_int defantenna = ath_hal_getdefantenna(sc->sc_ah); 4768 int error; 4769 4770 error = sysctl_handle_int(oidp, &defantenna, 0, req); 4771 if (!error && req->newptr) 4772 ath_hal_setdefantenna(sc->sc_ah, defantenna); 4773 return error; 4774} 4775 4776static int 4777ath_sysctl_diversity(SYSCTL_HANDLER_ARGS) 4778{ 4779 struct ath_softc *sc = arg1; 4780 u_int diversity = ath_hal_getdiversity(sc->sc_ah); 4781 int error; 4782 4783 error = sysctl_handle_int(oidp, &diversity, 0, req); 4784 if (error || !req->newptr) 4785 return error; 4786 if (!ath_hal_setdiversity(sc->sc_ah, diversity)) 4787 return EINVAL; 4788 sc->sc_diversity = diversity; 4789 return 0; 4790} 4791 4792static int 4793ath_sysctl_diag(SYSCTL_HANDLER_ARGS) 4794{ 4795 struct ath_softc *sc = arg1; 4796 u_int32_t diag; 4797 int error; 4798 4799 if (!ath_hal_getdiag(sc->sc_ah, &diag)) 4800 return EINVAL; 4801 error = sysctl_handle_int(oidp, &diag, 0, req); 4802 if (error || !req->newptr) 4803 return error; 4804 return !ath_hal_setdiag(sc->sc_ah, diag) ? EINVAL : 0; 4805} 4806 4807static int 4808ath_sysctl_tpscale(SYSCTL_HANDLER_ARGS) 4809{ 4810 struct ath_softc *sc = arg1; 4811 struct ifnet *ifp = sc->sc_ifp; 4812 u_int32_t scale; 4813 int error; 4814 4815 ath_hal_gettpscale(sc->sc_ah, &scale); 4816 error = sysctl_handle_int(oidp, &scale, 0, req); 4817 if (error || !req->newptr) 4818 return error; 4819 return !ath_hal_settpscale(sc->sc_ah, scale) ? EINVAL : ath_reset(ifp); 4820} 4821 4822static int 4823ath_sysctl_tpc(SYSCTL_HANDLER_ARGS) 4824{ 4825 struct ath_softc *sc = arg1; 4826 u_int tpc = ath_hal_gettpc(sc->sc_ah); 4827 int error; 4828 4829 error = sysctl_handle_int(oidp, &tpc, 0, req); 4830 if (error || !req->newptr) 4831 return error; 4832 return !ath_hal_settpc(sc->sc_ah, tpc) ? EINVAL : 0; 4833} 4834 4835static void 4836ath_sysctlattach(struct ath_softc *sc) 4837{ 4838 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); 4839 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); 4840 struct ath_hal *ah = sc->sc_ah; 4841 4842 ath_hal_getcountrycode(sc->sc_ah, &sc->sc_countrycode); 4843 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4844 "countrycode", CTLFLAG_RD, &sc->sc_countrycode, 0, 4845 "EEPROM country code"); 4846 ath_hal_getregdomain(sc->sc_ah, &sc->sc_regdomain); 4847 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4848 "regdomain", CTLFLAG_RD, &sc->sc_regdomain, 0, 4849 "EEPROM regdomain code"); 4850 sc->sc_debug = ath_debug; 4851 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4852 "debug", CTLFLAG_RW, &sc->sc_debug, 0, 4853 "control debugging printfs"); 4854 4855 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4856 "slottime", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 4857 ath_sysctl_slottime, "I", "802.11 slot time (us)"); 4858 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4859 "acktimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 4860 ath_sysctl_acktimeout, "I", "802.11 ACK timeout (us)"); 4861 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4862 "ctstimeout", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 4863 ath_sysctl_ctstimeout, "I", "802.11 CTS timeout (us)"); 4864 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4865 "softled", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 4866 ath_sysctl_softled, "I", "enable/disable software LED support"); 4867 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4868 "ledpin", CTLFLAG_RW, &sc->sc_ledpin, 0, 4869 "GPIO pin connected to LED"); 4870 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4871 "ledon", CTLFLAG_RW, &sc->sc_ledon, 0, 4872 "setting to turn LED on"); 4873 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4874 "ledidle", CTLFLAG_RW, &sc->sc_ledidle, 0, 4875 "idle time for inactivity LED (ticks)"); 4876 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4877 "txantenna", CTLFLAG_RW, &sc->sc_txantenna, 0, 4878 "tx antenna (0=auto)"); 4879 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4880 "rxantenna", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 4881 ath_sysctl_rxantenna, "I", "default/rx antenna"); 4882 if (ath_hal_hasdiversity(ah)) 4883 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4884 "diversity", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 4885 ath_sysctl_diversity, "I", "antenna diversity"); 4886 sc->sc_txintrperiod = ATH_TXINTR_PERIOD; 4887 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4888 "txintrperiod", CTLFLAG_RW, &sc->sc_txintrperiod, 0, 4889 "tx descriptor batching"); 4890 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4891 "diag", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 4892 ath_sysctl_diag, "I", "h/w diagnostic control"); 4893 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4894 "tpscale", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 4895 ath_sysctl_tpscale, "I", "tx power scaling"); 4896 if (ath_hal_hastpc(ah)) 4897 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4898 "tpc", CTLTYPE_INT | CTLFLAG_RW, sc, 0, 4899 ath_sysctl_tpc, "I", "enable/disable per-packet TPC"); 4900 sc->sc_monpass = HAL_RXERR_DECRYPT | HAL_RXERR_MIC; 4901 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 4902 "monpass", CTLFLAG_RW, &sc->sc_monpass, 0, 4903 "mask of error frames to pass when monitoring"); 4904} 4905 4906static void 4907ath_bpfattach(struct ath_softc *sc) 4908{ 4909 struct ifnet *ifp = sc->sc_ifp; 4910 4911 bpfattach2(ifp, DLT_IEEE802_11_RADIO, 4912 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th), 4913 &sc->sc_drvbpf); 4914 /* 4915 * Initialize constant fields. 4916 * XXX make header lengths a multiple of 32-bits so subsequent 4917 * headers are properly aligned; this is a kludge to keep 4918 * certain applications happy. 4919 * 4920 * NB: the channel is setup each time we transition to the 4921 * RUN state to avoid filling it in for each frame. 4922 */ 4923 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(u_int32_t)); 4924 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len); 4925 sc->sc_tx_th.wt_ihdr.it_present = htole32(ATH_TX_RADIOTAP_PRESENT); 4926 4927 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(u_int32_t)); 4928 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len); 4929 sc->sc_rx_th.wr_ihdr.it_present = htole32(ATH_RX_RADIOTAP_PRESENT); 4930} 4931 4932/* 4933 * Announce various information on device/driver attach. 4934 */ 4935static void 4936ath_announce(struct ath_softc *sc) 4937{ 4938#define HAL_MODE_DUALBAND (HAL_MODE_11A|HAL_MODE_11B) 4939 struct ifnet *ifp = sc->sc_ifp; 4940 struct ath_hal *ah = sc->sc_ah; 4941 u_int modes, cc; 4942 4943 if_printf(ifp, "mac %d.%d phy %d.%d", 4944 ah->ah_macVersion, ah->ah_macRev, 4945 ah->ah_phyRev >> 4, ah->ah_phyRev & 0xf); 4946 /* 4947 * Print radio revision(s). We check the wireless modes 4948 * to avoid falsely printing revs for inoperable parts. 4949 * Dual-band radio revs are returned in the 5Ghz rev number. 4950 */ 4951 ath_hal_getcountrycode(ah, &cc); 4952 modes = ath_hal_getwirelessmodes(ah, cc); 4953 if ((modes & HAL_MODE_DUALBAND) == HAL_MODE_DUALBAND) { 4954 if (ah->ah_analog5GhzRev && ah->ah_analog2GhzRev) 4955 printf(" 5ghz radio %d.%d 2ghz radio %d.%d", 4956 ah->ah_analog5GhzRev >> 4, 4957 ah->ah_analog5GhzRev & 0xf, 4958 ah->ah_analog2GhzRev >> 4, 4959 ah->ah_analog2GhzRev & 0xf); 4960 else 4961 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 4962 ah->ah_analog5GhzRev & 0xf); 4963 } else 4964 printf(" radio %d.%d", ah->ah_analog5GhzRev >> 4, 4965 ah->ah_analog5GhzRev & 0xf); 4966 printf("\n"); 4967 if (bootverbose) { 4968 int i; 4969 for (i = 0; i <= WME_AC_VO; i++) { 4970 struct ath_txq *txq = sc->sc_ac2q[i]; 4971 if_printf(ifp, "Use hw queue %u for %s traffic\n", 4972 txq->axq_qnum, ieee80211_wme_acnames[i]); 4973 } 4974 if_printf(ifp, "Use hw queue %u for CAB traffic\n", 4975 sc->sc_cabq->axq_qnum); 4976 if_printf(ifp, "Use hw queue %u for beacons\n", sc->sc_bhalq); 4977 } 4978#undef HAL_MODE_DUALBAND 4979} 4980