ar9280_attach.c revision 235972
11553Srgrimes/* 21553Srgrimes * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting 31553Srgrimes * Copyright (c) 2008 Atheros Communications, Inc. 41553Srgrimes * 51553Srgrimes * Permission to use, copy, modify, and/or distribute this software for any 61553Srgrimes * purpose with or without fee is hereby granted, provided that the above 71553Srgrimes * copyright notice and this permission notice appear in all copies. 81553Srgrimes * 91553Srgrimes * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 101553Srgrimes * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 111553Srgrimes * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 121553Srgrimes * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 131553Srgrimes * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 141553Srgrimes * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 151553Srgrimes * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 161553Srgrimes * 171553Srgrimes * $FreeBSD: head/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c 235972 2012-05-25 05:01:27Z adrian $ 181553Srgrimes */ 191553Srgrimes#include "opt_ah.h" 201553Srgrimes 211553Srgrimes#include "ah.h" 221553Srgrimes#include "ah_internal.h" 231553Srgrimes#include "ah_devid.h" 241553Srgrimes 251553Srgrimes#include "ah_eeprom_v14.h" /* XXX for tx/rx gain */ 261553Srgrimes 271553Srgrimes#include "ar9002/ar9280.h" 281553Srgrimes#include "ar5416/ar5416reg.h" 291553Srgrimes#include "ar5416/ar5416phy.h" 301553Srgrimes 311553Srgrimes#include "ar9002/ar9280v1.ini" 321553Srgrimes#include "ar9002/ar9280v2.ini" 331553Srgrimes#include "ar9002/ar9280_olc.h" 34114601Sobrien 351553Srgrimesstatic const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */ 361553Srgrimes .calName = "IQ", .calType = IQ_MISMATCH_CAL, 37114601Sobrien .calNumSamples = MIN_CAL_SAMPLES, 3830027Scharnier .calCountMax = PER_MAX_LOG_COUNT, 39114601Sobrien .calCollect = ar5416IQCalCollect, 40114601Sobrien .calPostProc = ar5416IQCalibration 411553Srgrimes}; 421553Srgrimesstatic const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */ 431553Srgrimes .calName = "ADC Gain", .calType = ADC_GAIN_CAL, 441553Srgrimes .calNumSamples = MIN_CAL_SAMPLES, 4530027Scharnier .calCountMax = PER_MAX_LOG_COUNT, 4630027Scharnier .calCollect = ar5416AdcGainCalCollect, 471553Srgrimes .calPostProc = ar5416AdcGainCalibration 481553Srgrimes}; 4930027Scharnierstatic const HAL_PERCAL_DATA ar9280_adc_dc_cal = { /* single sample */ 501553Srgrimes .calName = "ADC DC", .calType = ADC_DC_CAL, 511553Srgrimes .calNumSamples = MIN_CAL_SAMPLES, 521553Srgrimes .calCountMax = PER_MAX_LOG_COUNT, 531553Srgrimes .calCollect = ar5416AdcDcCalCollect, 542860Srgrimes .calPostProc = ar5416AdcDcCalibration 5563853Simp}; 561553Srgrimesstatic const HAL_PERCAL_DATA ar9280_adc_init_dc_cal = { 5730027Scharnier .calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL, 581553Srgrimes .calNumSamples = MIN_CAL_SAMPLES, 591553Srgrimes .calCountMax = INIT_LOG_COUNT, 601553Srgrimes .calCollect = ar5416AdcDcCalCollect, 611553Srgrimes .calPostProc = ar5416AdcDcCalibration 6299800Salfred}; 6399800Salfred 641553Srgrimesstatic void ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, 651553Srgrimes HAL_BOOL power_off); 661553Srgrimesstatic void ar9280DisablePCIE(struct ath_hal *ah); 671553Srgrimesstatic HAL_BOOL ar9280FillCapabilityInfo(struct ath_hal *ah); 681553Srgrimesstatic void ar9280WriteIni(struct ath_hal *ah, 691553Srgrimes const struct ieee80211_channel *chan); 701553Srgrimes 711553Srgrimesstatic void 721553Srgrimesar9280AniSetup(struct ath_hal *ah) 731553Srgrimes{ 741553Srgrimes /* 751553Srgrimes * These are the parameters from the AR5416 ANI code; 761553Srgrimes * they likely need quite a bit of adjustment for the 771553Srgrimes * AR9280. 781553Srgrimes */ 791553Srgrimes static const struct ar5212AniParams aniparams = { 801553Srgrimes .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 811553Srgrimes .totalSizeDesired = { -55, -55, -55, -55, -62 }, 829675Sbde .coarseHigh = { -14, -14, -14, -14, -12 }, 831553Srgrimes .coarseLow = { -64, -64, -64, -64, -70 }, 8499802Salfred .firpwr = { -78, -78, -78, -78, -80 }, 851553Srgrimes .maxSpurImmunityLevel = 2, 8699802Salfred .cycPwrThr1 = { 2, 4, 6 }, 871553Srgrimes .maxFirstepLevel = 2, /* levels 0..2 */ 881553Srgrimes .firstep = { 0, 4, 8 }, 8930027Scharnier .ofdmTrigHigh = 500, 901553Srgrimes .ofdmTrigLow = 200, 919675Sbde .cckTrigHigh = 200, 922860Srgrimes .cckTrigLow = 100, 9360418Swollman .rssiThrHigh = 40, 9460418Swollman .rssiThrLow = 7, 9560418Swollman .period = 100, 9660418Swollman }; 971553Srgrimes /* NB: disable ANI noise immmunity for reliable RIFS rx */ 981553Srgrimes AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL); 9963086Sjoe 1001553Srgrimes /* NB: ANI is not enabled yet */ 1011553Srgrimes ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 1029675Sbde} 1031553Srgrimes 1048857Srgrimesvoid 1051553Srgrimesar9280InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan) 1061553Srgrimes{ 1071553Srgrimes uint32_t pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); 1081553Srgrimes 1091553Srgrimes if (AR_SREV_MERLIN_20(ah) && 1101553Srgrimes chan != AH_NULL && IEEE80211_IS_CHAN_5GHZ(chan)) { 11130027Scharnier /* 1121553Srgrimes * PLL WAR for Merlin 2.0/2.1 1131553Srgrimes * When doing fast clock, set PLL to 0x142c 1141553Srgrimes * Else, set PLL to 0x2850 to prevent reset-to-reset variation 1151553Srgrimes */ 1161553Srgrimes pll = IS_5GHZ_FAST_CLOCK_EN(ah, chan) ? 0x142c : 0x2850; 1171553Srgrimes } else if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 1189675Sbde pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); 1199675Sbde if (chan != AH_NULL) { 1201553Srgrimes if (IEEE80211_IS_CHAN_HALF(chan)) 1212860Srgrimes pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL); 1222860Srgrimes else if (IEEE80211_IS_CHAN_QUARTER(chan)) 1231553Srgrimes pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL); 1241553Srgrimes if (IEEE80211_IS_CHAN_5GHZ(chan)) 12536670Speter pll |= SM(0x28, AR_RTC_SOWL_PLL_DIV); 12636670Speter else 1271553Srgrimes pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV); 12836841Speter } else 1291553Srgrimes pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV); 1301553Srgrimes } 1311553Srgrimes 1321553Srgrimes OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 1331553Srgrimes OS_DELAY(RTC_PLL_SETTLE_DELAY); 1341553Srgrimes OS_REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_SLEEP_DERIVED_CLK); 1351553Srgrimes} 1361553Srgrimes 1371553Srgrimes/* XXX shouldn't be here! */ 1381553Srgrimes#define EEP_MINOR(_ah) \ 1391553Srgrimes (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK) 1409675Sbde 1411553Srgrimes/* 14266584Sphk * Attach for an AR9280 part. 1431553Srgrimes */ 1449675Sbdestatic struct ath_hal * 1459675Sbdear9280Attach(uint16_t devid, HAL_SOFTC sc, 1461553Srgrimes HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 1471553Srgrimes HAL_STATUS *status) 1481553Srgrimes{ 1491553Srgrimes struct ath_hal_9280 *ahp9280; 1501553Srgrimes struct ath_hal_5212 *ahp; 1511553Srgrimes struct ath_hal *ah; 1521553Srgrimes uint32_t val; 1531553Srgrimes HAL_STATUS ecode; 1541553Srgrimes HAL_BOOL rfStatus; 1551553Srgrimes int8_t pwr_table_offset; 1561553Srgrimes uint8_t pwr; 157112214Srobert 1581553Srgrimes HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 1591553Srgrimes __func__, sc, (void*) st, (void*) sh); 1601553Srgrimes 1611553Srgrimes /* NB: memory is returned zero'd */ 1621553Srgrimes ahp9280 = ath_hal_malloc(sizeof (struct ath_hal_9280)); 1631553Srgrimes if (ahp9280 == AH_NULL) { 1641553Srgrimes HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 1651553Srgrimes "%s: cannot allocate memory for state block\n", __func__); 1661553Srgrimes *status = HAL_ENOMEM; 1671553Srgrimes return AH_NULL; 16863087Sjoe } 1691553Srgrimes ahp = AH5212(ahp9280); 1701553Srgrimes ah = &ahp->ah_priv.h; 1711553Srgrimes 1721553Srgrimes ar5416InitState(AH5416(ah), devid, sc, st, sh, status); 1731553Srgrimes 17463853Simp /* 17563853Simp * Use the "local" EEPROM data given to us by the higher layers. 17663853Simp * This is a private copy out of system flash. The Linux ath9k 17763853Simp * commit for the initial AR9130 support mentions MMIO flash 17863853Simp * access is "unreliable." -adrian 17963853Simp */ 18063853Simp if (eepromdata != AH_NULL) { 18163853Simp AH_PRIVATE((ah))->ah_eepromRead = ath_hal_EepromDataRead; 18266584Sphk AH_PRIVATE((ah))->ah_eepromWrite = NULL; 18363853Simp ah->ah_eepromdata = eepromdata; 18463087Sjoe } 1851553Srgrimes 1861553Srgrimes /* XXX override with 9280 specific state */ 1871553Srgrimes /* override 5416 methods for our needs */ 1881553Srgrimes AH5416(ah)->ah_initPLL = ar9280InitPLL; 1891553Srgrimes 19063087Sjoe ah->ah_setAntennaSwitch = ar9280SetAntennaSwitch; 19163087Sjoe ah->ah_configPCIE = ar9280ConfigPCIE; 19263087Sjoe ah->ah_disablePCIE = ar9280DisablePCIE; 19363087Sjoe 19451705Sbillf AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal; 1951553Srgrimes AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal; 19663087Sjoe AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal; 1971553Srgrimes AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal; 19863087Sjoe AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; 19963087Sjoe 20063087Sjoe AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate; 20163087Sjoe AH5416(ah)->ah_writeIni = ar9280WriteIni; 20263087Sjoe AH5416(ah)->ah_olcInit = ar9280olcInit; 20363087Sjoe AH5416(ah)->ah_olcTempCompensation = ar9280olcTemperatureCompensation; 20463087Sjoe AH5416(ah)->ah_setPowerCalTable = ar9280SetPowerCalTable; 20563087Sjoe 20663087Sjoe AH5416(ah)->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK; 20763087Sjoe AH5416(ah)->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK; 20863087Sjoe 20963087Sjoe if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 21036670Speter /* reset chip */ 2111553Srgrimes HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", 21236670Speter __func__); 2131553Srgrimes ecode = HAL_EIO; 2141553Srgrimes goto bad; 2151553Srgrimes } 2161553Srgrimes 2171553Srgrimes if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 21851705Sbillf HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 2191553Srgrimes __func__); 2201553Srgrimes ecode = HAL_EIO; 2211553Srgrimes goto bad; 2221553Srgrimes } 2231553Srgrimes /* Read Revisions from Chips before taking out of reset */ 2241553Srgrimes val = OS_REG_READ(ah, AR_SREV); 2251553Srgrimes HALDEBUG(ah, HAL_DEBUG_ATTACH, 2261553Srgrimes "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n", 2271553Srgrimes __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION), 2281553Srgrimes MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION)); 2291553Srgrimes /* NB: include chip type to differentiate from pre-Sowl versions */ 2301553Srgrimes AH_PRIVATE(ah)->ah_macVersion = 2311553Srgrimes (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S; 23254375Sjoe AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION); 23354375Sjoe AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0; 2341553Srgrimes 2351553Srgrimes /* setup common ini data; rf backends handle remainder */ 2361553Srgrimes if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 2371553Srgrimes HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v2, 6); 2381553Srgrimes HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v2, 2); 23954375Sjoe HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 24054375Sjoe ar9280PciePhy_clkreq_always_on_L1_v2, 2); 24154375Sjoe HAL_INI_INIT(&ahp9280->ah_ini_xmodes, 24254375Sjoe ar9280Modes_fast_clock_v2, 3); 2431553Srgrimes } else { 2441553Srgrimes HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v1, 6); 245 HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v1, 2); 246 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 247 ar9280PciePhy_v1, 2); 248 } 249 ar5416AttachPCIE(ah); 250 251 ecode = ath_hal_v14EepromAttach(ah); 252 if (ecode != HAL_OK) 253 goto bad; 254 255 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 256 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 257 ecode = HAL_EIO; 258 goto bad; 259 } 260 261 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 262 263 if (!ar5212ChipTest(ah)) { 264 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 265 __func__); 266 ecode = HAL_ESELFTEST; 267 goto bad; 268 } 269 270 /* 271 * Set correct Baseband to analog shift 272 * setting to access analog chips. 273 */ 274 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 275 276 /* Read Radio Chip Rev Extract */ 277 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah); 278 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 279 case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */ 280 case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */ 281 break; 282 default: 283 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 284 AH_PRIVATE(ah)->ah_analog5GhzRev = 285 AR_RAD5133_SREV_MAJOR; 286 break; 287 } 288#ifdef AH_DEBUG 289 HALDEBUG(ah, HAL_DEBUG_ANY, 290 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 291 "this driver\n", __func__, 292 AH_PRIVATE(ah)->ah_analog5GhzRev); 293 ecode = HAL_ENOTSUPP; 294 goto bad; 295#endif 296 } 297 rfStatus = ar9280RfAttach(ah, &ecode); 298 if (!rfStatus) { 299 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 300 __func__, ecode); 301 goto bad; 302 } 303 304 /* Enable fixup for AR_AN_TOP2 if necessary */ 305 /* 306 * The v14 EEPROM layer returns HAL_EIO if PWDCLKIND isn't supported 307 * by the EEPROM version. 308 * 309 * ath9k checks the EEPROM minor version is >= 0x0a here, instead of 310 * the abstracted EEPROM access layer. 311 */ 312 ecode = ath_hal_eepromGet(ah, AR_EEP_PWDCLKIND, &pwr); 313 if (AR_SREV_MERLIN_20_OR_LATER(ah) && ecode == HAL_OK && pwr == 0) { 314 printf("[ath] enabling AN_TOP2_FIXUP\n"); 315 AH5416(ah)->ah_need_an_top2_fixup = 1; 316 } 317 318 /* 319 * Check whether the power table offset isn't the default. 320 * This can occur with eeprom minor V21 or greater on Merlin. 321 */ 322 (void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET, &pwr_table_offset); 323 if (pwr_table_offset != AR5416_PWR_TABLE_OFFSET_DB) 324 ath_hal_printf(ah, "[ath]: default pwr offset: %d dBm != EEPROM pwr offset: %d dBm; curves will be adjusted.\n", 325 AR5416_PWR_TABLE_OFFSET_DB, (int) pwr_table_offset); 326 327 /* XXX check for >= minor ver 17 */ 328 if (AR_SREV_MERLIN_20(ah)) { 329 /* setup rxgain table */ 330 switch (ath_hal_eepromGet(ah, AR_EEP_RXGAIN_TYPE, AH_NULL)) { 331 case AR5416_EEP_RXGAIN_13dB_BACKOFF: 332 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 333 ar9280Modes_backoff_13db_rxgain_v2, 6); 334 break; 335 case AR5416_EEP_RXGAIN_23dB_BACKOFF: 336 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 337 ar9280Modes_backoff_23db_rxgain_v2, 6); 338 break; 339 case AR5416_EEP_RXGAIN_ORIG: 340 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 341 ar9280Modes_original_rxgain_v2, 6); 342 break; 343 default: 344 HALASSERT(AH_FALSE); 345 goto bad; /* XXX ? try to continue */ 346 } 347 } 348 349 /* XXX check for >= minor ver 19 */ 350 if (AR_SREV_MERLIN_20(ah)) { 351 /* setp txgain table */ 352 switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) { 353 case AR5416_EEP_TXGAIN_HIGH_POWER: 354 HAL_INI_INIT(&ahp9280->ah_ini_txgain, 355 ar9280Modes_high_power_tx_gain_v2, 6); 356 break; 357 case AR5416_EEP_TXGAIN_ORIG: 358 HAL_INI_INIT(&ahp9280->ah_ini_txgain, 359 ar9280Modes_original_tx_gain_v2, 6); 360 break; 361 default: 362 HALASSERT(AH_FALSE); 363 goto bad; /* XXX ? try to continue */ 364 } 365 } 366 367 /* 368 * Got everything we need now to setup the capabilities. 369 */ 370 if (!ar9280FillCapabilityInfo(ah)) { 371 ecode = HAL_EEREAD; 372 goto bad; 373 } 374 375 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 376 if (ecode != HAL_OK) { 377 HALDEBUG(ah, HAL_DEBUG_ANY, 378 "%s: error getting mac address from EEPROM\n", __func__); 379 goto bad; 380 } 381 /* XXX How about the serial number ? */ 382 /* Read Reg Domain */ 383 AH_PRIVATE(ah)->ah_currentRD = 384 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 385 AH_PRIVATE(ah)->ah_currentRDext = 386 ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL); 387 388 /* 389 * ah_miscMode is populated by ar5416FillCapabilityInfo() 390 * starting from griffin. Set here to make sure that 391 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 392 * placed into hardware. 393 */ 394 if (ahp->ah_miscMode != 0) 395 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 396 397 ar9280AniSetup(ah); /* Anti Noise Immunity */ 398 399 /* Setup noise floor min/max/nominal values */ 400 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ; 401 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ; 402 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9280_2GHZ; 403 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ; 404 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ; 405 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9280_5GHZ; 406 407 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 408 409 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 410 411 return ah; 412bad: 413 if (ah != AH_NULL) 414 ah->ah_detach(ah); 415 if (status) 416 *status = ecode; 417 return AH_NULL; 418} 419 420static void 421ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off) 422{ 423 if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 424 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 425 OS_DELAY(1000); 426 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 427 OS_REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT); 428 } 429} 430 431static void 432ar9280DisablePCIE(struct ath_hal *ah) 433{ 434 /* XXX TODO */ 435} 436 437static void 438ar9280WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 439{ 440 u_int modesIndex, freqIndex; 441 int regWrites = 0; 442 int i; 443 const HAL_INI_ARRAY *ia; 444 445 /* Setup the indices for the next set of register array writes */ 446 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 447 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 448 freqIndex = 2; 449 if (IEEE80211_IS_CHAN_HT40(chan)) 450 modesIndex = 3; 451 else if (IEEE80211_IS_CHAN_108G(chan)) 452 modesIndex = 5; 453 else 454 modesIndex = 4; 455 } else { 456 freqIndex = 1; 457 if (IEEE80211_IS_CHAN_HT40(chan) || 458 IEEE80211_IS_CHAN_TURBO(chan)) 459 modesIndex = 2; 460 else 461 modesIndex = 1; 462 } 463 464 /* Set correct Baseband to analog shift setting to access analog chips. */ 465 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 466 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 467 468 /* 469 * This is unwound because at the moment, there's a requirement 470 * for Merlin (and later, perhaps) to have a specific bit fixed 471 * in the AR_AN_TOP2 register before writing it. 472 */ 473 ia = &AH5212(ah)->ah_ini_modes; 474#if 0 475 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 476 modesIndex, regWrites); 477#endif 478 HALASSERT(modesIndex < ia->cols); 479 for (i = 0; i < ia->rows; i++) { 480 uint32_t reg = HAL_INI_VAL(ia, i, 0); 481 uint32_t val = HAL_INI_VAL(ia, i, modesIndex); 482 483 if (reg == AR_AN_TOP2 && AH5416(ah)->ah_need_an_top2_fixup) 484 val &= ~AR_AN_TOP2_PWDCLKIND; 485 486 OS_REG_WRITE(ah, reg, val); 487 488 /* Analog shift register delay seems needed for Merlin - PR kern/154220 */ 489 if (reg >= 0x7800 && reg < 0x7900) 490 OS_DELAY(100); 491 492 DMA_YIELD(regWrites); 493 } 494 495 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 496 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_rxgain, 497 modesIndex, regWrites); 498 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain, 499 modesIndex, regWrites); 500 } 501 /* XXX Merlin 100us delay for shift registers */ 502 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 503 1, regWrites); 504 505 if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { 506 /* 5GHz channels w/ Fast Clock use different modal values */ 507 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_xmodes, 508 modesIndex, regWrites); 509 } 510} 511 512#define AR_BASE_FREQ_2GHZ 2300 513#define AR_BASE_FREQ_5GHZ 4900 514#define AR_SPUR_FEEQ_BOUND_HT40 19 515#define AR_SPUR_FEEQ_BOUND_HT20 10 516 517void 518ar9280SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 519{ 520 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 521 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 522 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 523 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 524 static int inc[4] = { 0, 100, 0, 0 }; 525 526 int bb_spur = AR_NO_SPUR; 527 int freq; 528 int bin, cur_bin; 529 int bb_spur_off, spur_subchannel_sd; 530 int spur_freq_sd; 531 int spur_delta_phase; 532 int denominator; 533 int upper, lower, cur_vit_mask; 534 int tmp, newVal; 535 int i; 536 CHAN_CENTERS centers; 537 538 int8_t mask_m[123]; 539 int8_t mask_p[123]; 540 int8_t mask_amt; 541 int tmp_mask; 542 int cur_bb_spur; 543 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 544 545 OS_MEMZERO(&mask_m, sizeof(int8_t) * 123); 546 OS_MEMZERO(&mask_p, sizeof(int8_t) * 123); 547 548 ar5416GetChannelCenters(ah, chan, ¢ers); 549 freq = centers.synth_center; 550 551 /* 552 * Need to verify range +/- 9.38 for static ht20 and +/- 18.75 for ht40, 553 * otherwise spur is out-of-band and can be ignored. 554 */ 555 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 556 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 557 /* Get actual spur freq in MHz from EEPROM read value */ 558 if (is2GHz) { 559 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ; 560 } else { 561 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ; 562 } 563 564 if (AR_NO_SPUR == cur_bb_spur) 565 break; 566 cur_bb_spur = cur_bb_spur - freq; 567 568 if (IEEE80211_IS_CHAN_HT40(chan)) { 569 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) && 570 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) { 571 bb_spur = cur_bb_spur; 572 break; 573 } 574 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) && 575 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) { 576 bb_spur = cur_bb_spur; 577 break; 578 } 579 } 580 581 if (AR_NO_SPUR == bb_spur) { 582#if 1 583 /* 584 * MRC CCK can interfere with beacon detection and cause deaf/mute. 585 * Disable MRC CCK for now. 586 */ 587 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 588#else 589 /* Enable MRC CCK if no spur is found in this channel. */ 590 OS_REG_SET_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 591#endif 592 return; 593 } else { 594 /* 595 * For Merlin, spur can break CCK MRC algorithm. Disable CCK MRC if spur 596 * is found in this channel. 597 */ 598 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 599 } 600 601 bin = bb_spur * 320; 602 603 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 604 605 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 606 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 607 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 608 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 609 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), newVal); 610 611 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 612 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 613 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 614 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 615 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 616 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); 617 618 /* Pick control or extn channel to cancel the spur */ 619 if (IEEE80211_IS_CHAN_HT40(chan)) { 620 if (bb_spur < 0) { 621 spur_subchannel_sd = 1; 622 bb_spur_off = bb_spur + 10; 623 } else { 624 spur_subchannel_sd = 0; 625 bb_spur_off = bb_spur - 10; 626 } 627 } else { 628 spur_subchannel_sd = 0; 629 bb_spur_off = bb_spur; 630 } 631 632 /* 633 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 634 * /80 for dyn2040. 635 */ 636 if (IEEE80211_IS_CHAN_HT40(chan)) 637 spur_delta_phase = ((bb_spur * 262144) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 638 else 639 spur_delta_phase = ((bb_spur * 524288) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 640 641 /* 642 * in 11A mode the denominator of spur_freq_sd should be 40 and 643 * it should be 44 in 11G 644 */ 645 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 44 : 40; 646 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff; 647 648 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 649 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 650 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 651 OS_REG_WRITE(ah, AR_PHY_TIMING11, newVal); 652 653 /* Choose to cancel between control and extension channels */ 654 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S; 655 OS_REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); 656 657 /* 658 * ============================================ 659 * Set Pilot and Channel Masks 660 * 661 * pilot mask 1 [31:0] = +6..-26, no 0 bin 662 * pilot mask 2 [19:0] = +26..+7 663 * 664 * channel mask 1 [31:0] = +6..-26, no 0 bin 665 * channel mask 2 [19:0] = +26..+7 666 */ 667 cur_bin = -6000; 668 upper = bin + 100; 669 lower = bin - 100; 670 671 for (i = 0; i < 4; i++) { 672 int pilot_mask = 0; 673 int chan_mask = 0; 674 int bp = 0; 675 for (bp = 0; bp < 30; bp++) { 676 if ((cur_bin > lower) && (cur_bin < upper)) { 677 pilot_mask = pilot_mask | 0x1 << bp; 678 chan_mask = chan_mask | 0x1 << bp; 679 } 680 cur_bin += 100; 681 } 682 cur_bin += inc[i]; 683 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 684 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 685 } 686 687 /* ================================================= 688 * viterbi mask 1 based on channel magnitude 689 * four levels 0-3 690 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 691 * [1 2 2 1] for -9.6 or [1 2 1] for +16 692 * - enable_mask_ppm, all bins move with freq 693 * 694 * - mask_select, 8 bits for rates (reg 67,0x990c) 695 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 696 * choose which mask to use mask or mask2 697 */ 698 699 /* 700 * viterbi mask 2 2nd set for per data rate puncturing 701 * four levels 0-3 702 * - mask_select, 8 bits for rates (reg 67) 703 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 704 * [1 2 2 1] for -9.6 or [1 2 1] for +16 705 */ 706 cur_vit_mask = 6100; 707 upper = bin + 120; 708 lower = bin - 120; 709 710 for (i = 0; i < 123; i++) { 711 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 712 if ((abs(cur_vit_mask - bin)) < 75) { 713 mask_amt = 1; 714 } else { 715 mask_amt = 0; 716 } 717 if (cur_vit_mask < 0) { 718 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 719 } else { 720 mask_p[cur_vit_mask / 100] = mask_amt; 721 } 722 } 723 cur_vit_mask -= 100; 724 } 725 726 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 727 | (mask_m[48] << 26) | (mask_m[49] << 24) 728 | (mask_m[50] << 22) | (mask_m[51] << 20) 729 | (mask_m[52] << 18) | (mask_m[53] << 16) 730 | (mask_m[54] << 14) | (mask_m[55] << 12) 731 | (mask_m[56] << 10) | (mask_m[57] << 8) 732 | (mask_m[58] << 6) | (mask_m[59] << 4) 733 | (mask_m[60] << 2) | (mask_m[61] << 0); 734 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 735 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 736 737 tmp_mask = (mask_m[31] << 28) 738 | (mask_m[32] << 26) | (mask_m[33] << 24) 739 | (mask_m[34] << 22) | (mask_m[35] << 20) 740 | (mask_m[36] << 18) | (mask_m[37] << 16) 741 | (mask_m[48] << 14) | (mask_m[39] << 12) 742 | (mask_m[40] << 10) | (mask_m[41] << 8) 743 | (mask_m[42] << 6) | (mask_m[43] << 4) 744 | (mask_m[44] << 2) | (mask_m[45] << 0); 745 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 746 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 747 748 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 749 | (mask_m[18] << 26) | (mask_m[18] << 24) 750 | (mask_m[20] << 22) | (mask_m[20] << 20) 751 | (mask_m[22] << 18) | (mask_m[22] << 16) 752 | (mask_m[24] << 14) | (mask_m[24] << 12) 753 | (mask_m[25] << 10) | (mask_m[26] << 8) 754 | (mask_m[27] << 6) | (mask_m[28] << 4) 755 | (mask_m[29] << 2) | (mask_m[30] << 0); 756 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 757 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 758 759 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 760 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 761 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 762 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 763 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 764 | (mask_m[10] << 10) | (mask_m[11] << 8) 765 | (mask_m[12] << 6) | (mask_m[13] << 4) 766 | (mask_m[14] << 2) | (mask_m[15] << 0); 767 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 768 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 769 770 tmp_mask = (mask_p[15] << 28) 771 | (mask_p[14] << 26) | (mask_p[13] << 24) 772 | (mask_p[12] << 22) | (mask_p[11] << 20) 773 | (mask_p[10] << 18) | (mask_p[ 9] << 16) 774 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 775 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 776 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 777 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 778 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 779 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 780 781 tmp_mask = (mask_p[30] << 28) 782 | (mask_p[29] << 26) | (mask_p[28] << 24) 783 | (mask_p[27] << 22) | (mask_p[26] << 20) 784 | (mask_p[25] << 18) | (mask_p[24] << 16) 785 | (mask_p[23] << 14) | (mask_p[22] << 12) 786 | (mask_p[21] << 10) | (mask_p[20] << 8) 787 | (mask_p[19] << 6) | (mask_p[18] << 4) 788 | (mask_p[17] << 2) | (mask_p[16] << 0); 789 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 790 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 791 792 tmp_mask = (mask_p[45] << 28) 793 | (mask_p[44] << 26) | (mask_p[43] << 24) 794 | (mask_p[42] << 22) | (mask_p[41] << 20) 795 | (mask_p[40] << 18) | (mask_p[39] << 16) 796 | (mask_p[38] << 14) | (mask_p[37] << 12) 797 | (mask_p[36] << 10) | (mask_p[35] << 8) 798 | (mask_p[34] << 6) | (mask_p[33] << 4) 799 | (mask_p[32] << 2) | (mask_p[31] << 0); 800 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 801 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 802 803 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 804 | (mask_p[59] << 26) | (mask_p[58] << 24) 805 | (mask_p[57] << 22) | (mask_p[56] << 20) 806 | (mask_p[55] << 18) | (mask_p[54] << 16) 807 | (mask_p[53] << 14) | (mask_p[52] << 12) 808 | (mask_p[51] << 10) | (mask_p[50] << 8) 809 | (mask_p[49] << 6) | (mask_p[48] << 4) 810 | (mask_p[47] << 2) | (mask_p[46] << 0); 811 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 812 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 813} 814 815/* 816 * Fill all software cached or static hardware state information. 817 * Return failure if capabilities are to come from EEPROM and 818 * cannot be read. 819 */ 820static HAL_BOOL 821ar9280FillCapabilityInfo(struct ath_hal *ah) 822{ 823 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 824 825 if (!ar5416FillCapabilityInfo(ah)) 826 return AH_FALSE; 827 pCap->halNumGpioPins = 10; 828 pCap->halWowSupport = AH_TRUE; 829 pCap->halWowMatchPatternExact = AH_TRUE; 830#if 0 831 pCap->halWowMatchPatternDword = AH_TRUE; 832#endif 833 pCap->halCSTSupport = AH_TRUE; 834 pCap->halRifsRxSupport = AH_TRUE; 835 pCap->halRifsTxSupport = AH_TRUE; 836 pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */ 837 pCap->halExtChanDfsSupport = AH_TRUE; 838 pCap->halUseCombinedRadarRssi = AH_TRUE; 839#if 0 840 /* XXX bluetooth */ 841 pCap->halBtCoexSupport = AH_TRUE; 842#endif 843 pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */ 844 pCap->hal4kbSplitTransSupport = AH_FALSE; 845 /* Disable this so Block-ACK works correctly */ 846 pCap->halHasRxSelfLinkedTail = AH_FALSE; 847 pCap->halMbssidAggrSupport = AH_TRUE; 848 pCap->hal4AddrAggrSupport = AH_TRUE; 849 850 if (AR_SREV_MERLIN_20(ah)) { 851 pCap->halPSPollBroken = AH_FALSE; 852 /* 853 * This just enables the support; it doesn't 854 * state 5ghz fast clock will always be used. 855 */ 856 pCap->halSupportsFastClock5GHz = AH_TRUE; 857 } 858 pCap->halRxStbcSupport = 1; 859 pCap->halTxStbcSupport = 1; 860 pCap->halEnhancedDfsSupport = AH_TRUE; 861 862 return AH_TRUE; 863} 864 865/* 866 * This has been disabled - having the HAL flip chainmasks on/off 867 * when attempting to implement 11n disrupts things. For now, just 868 * leave this flipped off and worry about implementing TX diversity 869 * for legacy and MCS0-7 when 11n is fully functioning. 870 */ 871HAL_BOOL 872ar9280SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings) 873{ 874#define ANTENNA0_CHAINMASK 0x1 875#define ANTENNA1_CHAINMASK 0x2 876#if 0 877 struct ath_hal_5416 *ahp = AH5416(ah); 878 879 /* Antenna selection is done by setting the tx/rx chainmasks approp. */ 880 switch (settings) { 881 case HAL_ANT_FIXED_A: 882 /* Enable first antenna only */ 883 ahp->ah_tx_chainmask = ANTENNA0_CHAINMASK; 884 ahp->ah_rx_chainmask = ANTENNA0_CHAINMASK; 885 break; 886 case HAL_ANT_FIXED_B: 887 /* Enable second antenna only, after checking capability */ 888 if (AH_PRIVATE(ah)->ah_caps.halTxChainMask > ANTENNA1_CHAINMASK) 889 ahp->ah_tx_chainmask = ANTENNA1_CHAINMASK; 890 ahp->ah_rx_chainmask = ANTENNA1_CHAINMASK; 891 break; 892 case HAL_ANT_VARIABLE: 893 /* Restore original chainmask settings */ 894 /* XXX */ 895 ahp->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK; 896 ahp->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK; 897 break; 898 } 899 900 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: settings=%d, tx/rx chainmask=%d/%d\n", 901 __func__, settings, ahp->ah_tx_chainmask, ahp->ah_rx_chainmask); 902 903#endif 904 return AH_TRUE; 905#undef ANTENNA0_CHAINMASK 906#undef ANTENNA1_CHAINMASK 907} 908 909static const char* 910ar9280Probe(uint16_t vendorid, uint16_t devid) 911{ 912 if (vendorid == ATHEROS_VENDOR_ID) { 913 if (devid == AR9280_DEVID_PCI) 914 return "Atheros 9220"; 915 if (devid == AR9280_DEVID_PCIE) 916 return "Atheros 9280"; 917 } 918 return AH_NULL; 919} 920AH_CHIP(AR9280, ar9280Probe, ar9280Attach); 921