ar9280_attach.c revision 224634
1/* 2 * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c 224634 2011-08-03 13:39:11Z adrian $ 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23#include "ah_devid.h" 24 25#include "ah_eeprom_v14.h" /* XXX for tx/rx gain */ 26 27#include "ar9002/ar9280.h" 28#include "ar5416/ar5416reg.h" 29#include "ar5416/ar5416phy.h" 30 31#include "ar9001/ar9130_eeprom.h" 32 33#include "ar9002/ar9280v1.ini" 34#include "ar9002/ar9280v2.ini" 35#include "ar9002/ar9280_olc.h" 36 37static const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */ 38 .calName = "IQ", .calType = IQ_MISMATCH_CAL, 39 .calNumSamples = MIN_CAL_SAMPLES, 40 .calCountMax = PER_MAX_LOG_COUNT, 41 .calCollect = ar5416IQCalCollect, 42 .calPostProc = ar5416IQCalibration 43}; 44static const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */ 45 .calName = "ADC Gain", .calType = ADC_GAIN_CAL, 46 .calNumSamples = MIN_CAL_SAMPLES, 47 .calCountMax = PER_MAX_LOG_COUNT, 48 .calCollect = ar5416AdcGainCalCollect, 49 .calPostProc = ar5416AdcGainCalibration 50}; 51static const HAL_PERCAL_DATA ar9280_adc_dc_cal = { /* single sample */ 52 .calName = "ADC DC", .calType = ADC_DC_CAL, 53 .calNumSamples = MIN_CAL_SAMPLES, 54 .calCountMax = PER_MAX_LOG_COUNT, 55 .calCollect = ar5416AdcDcCalCollect, 56 .calPostProc = ar5416AdcDcCalibration 57}; 58static const HAL_PERCAL_DATA ar9280_adc_init_dc_cal = { 59 .calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL, 60 .calNumSamples = MIN_CAL_SAMPLES, 61 .calCountMax = INIT_LOG_COUNT, 62 .calCollect = ar5416AdcDcCalCollect, 63 .calPostProc = ar5416AdcDcCalibration 64}; 65 66static void ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 67static HAL_BOOL ar9280FillCapabilityInfo(struct ath_hal *ah); 68static void ar9280WriteIni(struct ath_hal *ah, 69 const struct ieee80211_channel *chan); 70 71static void 72ar9280AniSetup(struct ath_hal *ah) 73{ 74 /* 75 * These are the parameters from the AR5416 ANI code; 76 * they likely need quite a bit of adjustment for the 77 * AR9280. 78 */ 79 static const struct ar5212AniParams aniparams = { 80 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 81 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 82 .coarseHigh = { -14, -14, -14, -14, -12 }, 83 .coarseLow = { -64, -64, -64, -64, -70 }, 84 .firpwr = { -78, -78, -78, -78, -80 }, 85 .maxSpurImmunityLevel = 2, 86 .cycPwrThr1 = { 2, 4, 6 }, 87 .maxFirstepLevel = 2, /* levels 0..2 */ 88 .firstep = { 0, 4, 8 }, 89 .ofdmTrigHigh = 500, 90 .ofdmTrigLow = 200, 91 .cckTrigHigh = 200, 92 .cckTrigLow = 100, 93 .rssiThrHigh = 40, 94 .rssiThrLow = 7, 95 .period = 100, 96 }; 97 /* NB: disable ANI noise immmunity for reliable RIFS rx */ 98 AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL); 99 100 /* NB: ANI is not enabled yet */ 101 ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 102} 103 104void 105ar9280InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan) 106{ 107 uint32_t pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); 108 109 if (AR_SREV_MERLIN_20(ah) && 110 chan != AH_NULL && IEEE80211_IS_CHAN_5GHZ(chan)) { 111 /* 112 * PLL WAR for Merlin 2.0/2.1 113 * When doing fast clock, set PLL to 0x142c 114 * Else, set PLL to 0x2850 to prevent reset-to-reset variation 115 */ 116 pll = IS_5GHZ_FAST_CLOCK_EN(ah, chan) ? 0x142c : 0x2850; 117 } else if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 118 pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); 119 if (chan != AH_NULL) { 120 if (IEEE80211_IS_CHAN_HALF(chan)) 121 pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL); 122 else if (IEEE80211_IS_CHAN_QUARTER(chan)) 123 pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL); 124 if (IEEE80211_IS_CHAN_5GHZ(chan)) 125 pll |= SM(0x28, AR_RTC_SOWL_PLL_DIV); 126 else 127 pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV); 128 } else 129 pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV); 130 } 131 132 OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 133 OS_DELAY(RTC_PLL_SETTLE_DELAY); 134 OS_REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_SLEEP_DERIVED_CLK); 135} 136 137/* XXX shouldn't be here! */ 138#define EEP_MINOR(_ah) \ 139 (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK) 140 141/* 142 * Attach for an AR9280 part. 143 */ 144static struct ath_hal * 145ar9280Attach(uint16_t devid, HAL_SOFTC sc, 146 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 147 HAL_STATUS *status) 148{ 149 struct ath_hal_9280 *ahp9280; 150 struct ath_hal_5212 *ahp; 151 struct ath_hal *ah; 152 uint32_t val; 153 HAL_STATUS ecode; 154 HAL_BOOL rfStatus; 155 int8_t pwr_table_offset; 156 uint8_t pwr; 157 158 HALDEBUG_G(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 159 __func__, sc, (void*) st, (void*) sh); 160 161 /* NB: memory is returned zero'd */ 162 ahp9280 = ath_hal_malloc(sizeof (struct ath_hal_9280)); 163 if (ahp9280 == AH_NULL) { 164 HALDEBUG_G(AH_NULL, HAL_DEBUG_ANY, 165 "%s: cannot allocate memory for state block\n", __func__); 166 *status = HAL_ENOMEM; 167 return AH_NULL; 168 } 169 ahp = AH5212(ahp9280); 170 ah = &ahp->ah_priv.h; 171 172 ar5416InitState(AH5416(ah), devid, sc, st, sh, status); 173 174 /* XXX override with 9280 specific state */ 175 /* override 5416 methods for our needs */ 176 AH5416(ah)->ah_initPLL = ar9280InitPLL; 177 178 ah->ah_setAntennaSwitch = ar9280SetAntennaSwitch; 179 ah->ah_configPCIE = ar9280ConfigPCIE; 180 181 AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal; 182 AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal; 183 AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal; 184 AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal; 185 AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; 186 187 AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate; 188 AH5416(ah)->ah_writeIni = ar9280WriteIni; 189 AH5416(ah)->ah_olcInit = ar9280olcInit; 190 AH5416(ah)->ah_olcTempCompensation = ar9280olcTemperatureCompensation; 191 AH5416(ah)->ah_setPowerCalTable = ar9280SetPowerCalTable; 192 193 AH5416(ah)->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK; 194 AH5416(ah)->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK; 195 196 if (eepromdata) { 197 AH_PRIVATE((ah))->ah_eepromRead = ar9130EepromRead; 198 AH_PRIVATE((ah))->ah_eepromWrite = NULL; 199 ah->ah_eepromdata = eepromdata; 200 } 201 202 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 203 /* reset chip */ 204 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", 205 __func__); 206 ecode = HAL_EIO; 207 goto bad; 208 } 209 210 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 211 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 212 __func__); 213 ecode = HAL_EIO; 214 goto bad; 215 } 216 /* Read Revisions from Chips before taking out of reset */ 217 val = OS_REG_READ(ah, AR_SREV); 218 HALDEBUG(ah, HAL_DEBUG_ATTACH, 219 "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n", 220 __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION), 221 MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION)); 222 /* NB: include chip type to differentiate from pre-Sowl versions */ 223 AH_PRIVATE(ah)->ah_macVersion = 224 (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S; 225 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION); 226 AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0; 227 228 /* setup common ini data; rf backends handle remainder */ 229 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 230 HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v2, 6); 231 HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v2, 2); 232 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 233 ar9280PciePhy_clkreq_always_on_L1_v2, 2); 234 HAL_INI_INIT(&ahp9280->ah_ini_xmodes, 235 ar9280Modes_fast_clock_v2, 3); 236 } else { 237 HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v1, 6); 238 HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v1, 2); 239 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 240 ar9280PciePhy_v1, 2); 241 } 242 ar5416AttachPCIE(ah); 243 244 ecode = ath_hal_v14EepromAttach(ah); 245 if (ecode != HAL_OK) 246 goto bad; 247 248 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 249 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 250 ecode = HAL_EIO; 251 goto bad; 252 } 253 254 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 255 256 if (!ar5212ChipTest(ah)) { 257 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 258 __func__); 259 ecode = HAL_ESELFTEST; 260 goto bad; 261 } 262 263 /* 264 * Set correct Baseband to analog shift 265 * setting to access analog chips. 266 */ 267 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 268 269 /* Read Radio Chip Rev Extract */ 270 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah); 271 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 272 case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */ 273 case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */ 274 break; 275 default: 276 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 277 AH_PRIVATE(ah)->ah_analog5GhzRev = 278 AR_RAD5133_SREV_MAJOR; 279 break; 280 } 281#ifdef AH_DEBUG 282 HALDEBUG(ah, HAL_DEBUG_ANY, 283 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 284 "this driver\n", __func__, 285 AH_PRIVATE(ah)->ah_analog5GhzRev); 286 ecode = HAL_ENOTSUPP; 287 goto bad; 288#endif 289 } 290 rfStatus = ar9280RfAttach(ah, &ecode); 291 if (!rfStatus) { 292 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 293 __func__, ecode); 294 goto bad; 295 } 296 297 /* Enable fixup for AR_AN_TOP2 if necessary */ 298 /* 299 * The v14 EEPROM layer returns HAL_EIO if PWDCLKIND isn't supported 300 * by the EEPROM version. 301 * 302 * ath9k checks the EEPROM minor version is >= 0x0a here, instead of 303 * the abstracted EEPROM access layer. 304 */ 305 ecode = ath_hal_eepromGet(ah, AR_EEP_PWDCLKIND, &pwr); 306 if (AR_SREV_MERLIN_20_OR_LATER(ah) && ecode == HAL_OK && pwr == 0) { 307 printf("[ath] enabling AN_TOP2_FIXUP\n"); 308 AH5416(ah)->ah_need_an_top2_fixup = 1; 309 } 310 311 /* 312 * Check whether the power table offset isn't the default. 313 * This can occur with eeprom minor V21 or greater on Merlin. 314 */ 315 (void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET, &pwr_table_offset); 316 if (pwr_table_offset != AR5416_PWR_TABLE_OFFSET_DB) 317 ath_hal_printf(ah, "[ath]: default pwr offset: %d dBm != EEPROM pwr offset: %d dBm; curves will be adjusted.\n", 318 AR5416_PWR_TABLE_OFFSET_DB, (int) pwr_table_offset); 319 320 /* XXX check for >= minor ver 17 */ 321 if (AR_SREV_MERLIN_20(ah)) { 322 /* setup rxgain table */ 323 switch (ath_hal_eepromGet(ah, AR_EEP_RXGAIN_TYPE, AH_NULL)) { 324 case AR5416_EEP_RXGAIN_13dB_BACKOFF: 325 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 326 ar9280Modes_backoff_13db_rxgain_v2, 6); 327 break; 328 case AR5416_EEP_RXGAIN_23dB_BACKOFF: 329 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 330 ar9280Modes_backoff_23db_rxgain_v2, 6); 331 break; 332 case AR5416_EEP_RXGAIN_ORIG: 333 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 334 ar9280Modes_original_rxgain_v2, 6); 335 break; 336 default: 337 HALASSERT(AH_FALSE); 338 goto bad; /* XXX ? try to continue */ 339 } 340 } 341 342 /* XXX check for >= minor ver 19 */ 343 if (AR_SREV_MERLIN_20(ah)) { 344 /* setp txgain table */ 345 switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) { 346 case AR5416_EEP_TXGAIN_HIGH_POWER: 347 HAL_INI_INIT(&ahp9280->ah_ini_txgain, 348 ar9280Modes_high_power_tx_gain_v2, 6); 349 break; 350 case AR5416_EEP_TXGAIN_ORIG: 351 HAL_INI_INIT(&ahp9280->ah_ini_txgain, 352 ar9280Modes_original_tx_gain_v2, 6); 353 break; 354 default: 355 HALASSERT(AH_FALSE); 356 goto bad; /* XXX ? try to continue */ 357 } 358 } 359 360 /* 361 * Got everything we need now to setup the capabilities. 362 */ 363 if (!ar9280FillCapabilityInfo(ah)) { 364 ecode = HAL_EEREAD; 365 goto bad; 366 } 367 368 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 369 if (ecode != HAL_OK) { 370 HALDEBUG(ah, HAL_DEBUG_ANY, 371 "%s: error getting mac address from EEPROM\n", __func__); 372 goto bad; 373 } 374 /* XXX How about the serial number ? */ 375 /* Read Reg Domain */ 376 AH_PRIVATE(ah)->ah_currentRD = 377 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 378 AH_PRIVATE(ah)->ah_currentRDext = 379 ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL); 380 381 /* 382 * ah_miscMode is populated by ar5416FillCapabilityInfo() 383 * starting from griffin. Set here to make sure that 384 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 385 * placed into hardware. 386 */ 387 if (ahp->ah_miscMode != 0) 388 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 389 390 ar9280AniSetup(ah); /* Anti Noise Immunity */ 391 392 /* Setup noise floor min/max/nominal values */ 393 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ; 394 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ; 395 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9280_2GHZ; 396 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ; 397 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ; 398 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9280_5GHZ; 399 400 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 401 402 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 403 404 return ah; 405bad: 406 if (ah != AH_NULL) 407 ah->ah_detach(ah); 408 if (status) 409 *status = ecode; 410 return AH_NULL; 411} 412 413static void 414ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 415{ 416 if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 417 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 418 OS_DELAY(1000); 419 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 420 OS_REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT); 421 } 422} 423 424static void 425ar9280WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 426{ 427 u_int modesIndex, freqIndex; 428 int regWrites = 0; 429 int i; 430 const HAL_INI_ARRAY *ia; 431 432 /* Setup the indices for the next set of register array writes */ 433 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 434 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 435 freqIndex = 2; 436 if (IEEE80211_IS_CHAN_HT40(chan)) 437 modesIndex = 3; 438 else if (IEEE80211_IS_CHAN_108G(chan)) 439 modesIndex = 5; 440 else 441 modesIndex = 4; 442 } else { 443 freqIndex = 1; 444 if (IEEE80211_IS_CHAN_HT40(chan) || 445 IEEE80211_IS_CHAN_TURBO(chan)) 446 modesIndex = 2; 447 else 448 modesIndex = 1; 449 } 450 451 /* Set correct Baseband to analog shift setting to access analog chips. */ 452 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 453 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 454 455 /* 456 * This is unwound because at the moment, there's a requirement 457 * for Merlin (and later, perhaps) to have a specific bit fixed 458 * in the AR_AN_TOP2 register before writing it. 459 */ 460 ia = &AH5212(ah)->ah_ini_modes; 461#if 0 462 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 463 modesIndex, regWrites); 464#endif 465 HALASSERT(modesIndex < ia->cols); 466 for (i = 0; i < ia->rows; i++) { 467 uint32_t reg = HAL_INI_VAL(ia, i, 0); 468 uint32_t val = HAL_INI_VAL(ia, i, modesIndex); 469 470 if (reg == AR_AN_TOP2 && AH5416(ah)->ah_need_an_top2_fixup) 471 val &= ~AR_AN_TOP2_PWDCLKIND; 472 473 OS_REG_WRITE(ah, reg, val); 474 475 /* Analog shift register delay seems needed for Merlin - PR kern/154220 */ 476 if (reg >= 0x7800 && reg < 0x7900) 477 OS_DELAY(100); 478 479 DMA_YIELD(regWrites); 480 } 481 482 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 483 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_rxgain, 484 modesIndex, regWrites); 485 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain, 486 modesIndex, regWrites); 487 } 488 /* XXX Merlin 100us delay for shift registers */ 489 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 490 1, regWrites); 491 492 if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { 493 /* 5GHz channels w/ Fast Clock use different modal values */ 494 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_xmodes, 495 modesIndex, regWrites); 496 } 497} 498 499#define AR_BASE_FREQ_2GHZ 2300 500#define AR_BASE_FREQ_5GHZ 4900 501#define AR_SPUR_FEEQ_BOUND_HT40 19 502#define AR_SPUR_FEEQ_BOUND_HT20 10 503 504void 505ar9280SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 506{ 507 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 508 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 509 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 510 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 511 static int inc[4] = { 0, 100, 0, 0 }; 512 513 int bb_spur = AR_NO_SPUR; 514 int freq; 515 int bin, cur_bin; 516 int bb_spur_off, spur_subchannel_sd; 517 int spur_freq_sd; 518 int spur_delta_phase; 519 int denominator; 520 int upper, lower, cur_vit_mask; 521 int tmp, newVal; 522 int i; 523 CHAN_CENTERS centers; 524 525 int8_t mask_m[123]; 526 int8_t mask_p[123]; 527 int8_t mask_amt; 528 int tmp_mask; 529 int cur_bb_spur; 530 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 531 532 OS_MEMZERO(&mask_m, sizeof(int8_t) * 123); 533 OS_MEMZERO(&mask_p, sizeof(int8_t) * 123); 534 535 ar5416GetChannelCenters(ah, chan, ¢ers); 536 freq = centers.synth_center; 537 538 /* 539 * Need to verify range +/- 9.38 for static ht20 and +/- 18.75 for ht40, 540 * otherwise spur is out-of-band and can be ignored. 541 */ 542 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 543 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 544 /* Get actual spur freq in MHz from EEPROM read value */ 545 if (is2GHz) { 546 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ; 547 } else { 548 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ; 549 } 550 551 if (AR_NO_SPUR == cur_bb_spur) 552 break; 553 cur_bb_spur = cur_bb_spur - freq; 554 555 if (IEEE80211_IS_CHAN_HT40(chan)) { 556 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) && 557 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) { 558 bb_spur = cur_bb_spur; 559 break; 560 } 561 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) && 562 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) { 563 bb_spur = cur_bb_spur; 564 break; 565 } 566 } 567 568 if (AR_NO_SPUR == bb_spur) { 569#if 1 570 /* 571 * MRC CCK can interfere with beacon detection and cause deaf/mute. 572 * Disable MRC CCK for now. 573 */ 574 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 575#else 576 /* Enable MRC CCK if no spur is found in this channel. */ 577 OS_REG_SET_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 578#endif 579 return; 580 } else { 581 /* 582 * For Merlin, spur can break CCK MRC algorithm. Disable CCK MRC if spur 583 * is found in this channel. 584 */ 585 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 586 } 587 588 bin = bb_spur * 320; 589 590 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 591 592 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 593 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 594 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 595 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 596 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), newVal); 597 598 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 599 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 600 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 601 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 602 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 603 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); 604 605 /* Pick control or extn channel to cancel the spur */ 606 if (IEEE80211_IS_CHAN_HT40(chan)) { 607 if (bb_spur < 0) { 608 spur_subchannel_sd = 1; 609 bb_spur_off = bb_spur + 10; 610 } else { 611 spur_subchannel_sd = 0; 612 bb_spur_off = bb_spur - 10; 613 } 614 } else { 615 spur_subchannel_sd = 0; 616 bb_spur_off = bb_spur; 617 } 618 619 /* 620 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 621 * /80 for dyn2040. 622 */ 623 if (IEEE80211_IS_CHAN_HT40(chan)) 624 spur_delta_phase = ((bb_spur * 262144) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 625 else 626 spur_delta_phase = ((bb_spur * 524288) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 627 628 /* 629 * in 11A mode the denominator of spur_freq_sd should be 40 and 630 * it should be 44 in 11G 631 */ 632 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 44 : 40; 633 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff; 634 635 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 636 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 637 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 638 OS_REG_WRITE(ah, AR_PHY_TIMING11, newVal); 639 640 /* Choose to cancel between control and extension channels */ 641 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S; 642 OS_REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); 643 644 /* 645 * ============================================ 646 * Set Pilot and Channel Masks 647 * 648 * pilot mask 1 [31:0] = +6..-26, no 0 bin 649 * pilot mask 2 [19:0] = +26..+7 650 * 651 * channel mask 1 [31:0] = +6..-26, no 0 bin 652 * channel mask 2 [19:0] = +26..+7 653 */ 654 cur_bin = -6000; 655 upper = bin + 100; 656 lower = bin - 100; 657 658 for (i = 0; i < 4; i++) { 659 int pilot_mask = 0; 660 int chan_mask = 0; 661 int bp = 0; 662 for (bp = 0; bp < 30; bp++) { 663 if ((cur_bin > lower) && (cur_bin < upper)) { 664 pilot_mask = pilot_mask | 0x1 << bp; 665 chan_mask = chan_mask | 0x1 << bp; 666 } 667 cur_bin += 100; 668 } 669 cur_bin += inc[i]; 670 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 671 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 672 } 673 674 /* ================================================= 675 * viterbi mask 1 based on channel magnitude 676 * four levels 0-3 677 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 678 * [1 2 2 1] for -9.6 or [1 2 1] for +16 679 * - enable_mask_ppm, all bins move with freq 680 * 681 * - mask_select, 8 bits for rates (reg 67,0x990c) 682 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 683 * choose which mask to use mask or mask2 684 */ 685 686 /* 687 * viterbi mask 2 2nd set for per data rate puncturing 688 * four levels 0-3 689 * - mask_select, 8 bits for rates (reg 67) 690 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 691 * [1 2 2 1] for -9.6 or [1 2 1] for +16 692 */ 693 cur_vit_mask = 6100; 694 upper = bin + 120; 695 lower = bin - 120; 696 697 for (i = 0; i < 123; i++) { 698 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 699 if ((abs(cur_vit_mask - bin)) < 75) { 700 mask_amt = 1; 701 } else { 702 mask_amt = 0; 703 } 704 if (cur_vit_mask < 0) { 705 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 706 } else { 707 mask_p[cur_vit_mask / 100] = mask_amt; 708 } 709 } 710 cur_vit_mask -= 100; 711 } 712 713 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 714 | (mask_m[48] << 26) | (mask_m[49] << 24) 715 | (mask_m[50] << 22) | (mask_m[51] << 20) 716 | (mask_m[52] << 18) | (mask_m[53] << 16) 717 | (mask_m[54] << 14) | (mask_m[55] << 12) 718 | (mask_m[56] << 10) | (mask_m[57] << 8) 719 | (mask_m[58] << 6) | (mask_m[59] << 4) 720 | (mask_m[60] << 2) | (mask_m[61] << 0); 721 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 722 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 723 724 tmp_mask = (mask_m[31] << 28) 725 | (mask_m[32] << 26) | (mask_m[33] << 24) 726 | (mask_m[34] << 22) | (mask_m[35] << 20) 727 | (mask_m[36] << 18) | (mask_m[37] << 16) 728 | (mask_m[48] << 14) | (mask_m[39] << 12) 729 | (mask_m[40] << 10) | (mask_m[41] << 8) 730 | (mask_m[42] << 6) | (mask_m[43] << 4) 731 | (mask_m[44] << 2) | (mask_m[45] << 0); 732 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 733 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 734 735 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 736 | (mask_m[18] << 26) | (mask_m[18] << 24) 737 | (mask_m[20] << 22) | (mask_m[20] << 20) 738 | (mask_m[22] << 18) | (mask_m[22] << 16) 739 | (mask_m[24] << 14) | (mask_m[24] << 12) 740 | (mask_m[25] << 10) | (mask_m[26] << 8) 741 | (mask_m[27] << 6) | (mask_m[28] << 4) 742 | (mask_m[29] << 2) | (mask_m[30] << 0); 743 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 744 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 745 746 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 747 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 748 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 749 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 750 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 751 | (mask_m[10] << 10) | (mask_m[11] << 8) 752 | (mask_m[12] << 6) | (mask_m[13] << 4) 753 | (mask_m[14] << 2) | (mask_m[15] << 0); 754 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 755 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 756 757 tmp_mask = (mask_p[15] << 28) 758 | (mask_p[14] << 26) | (mask_p[13] << 24) 759 | (mask_p[12] << 22) | (mask_p[11] << 20) 760 | (mask_p[10] << 18) | (mask_p[ 9] << 16) 761 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 762 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 763 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 764 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 765 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 766 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 767 768 tmp_mask = (mask_p[30] << 28) 769 | (mask_p[29] << 26) | (mask_p[28] << 24) 770 | (mask_p[27] << 22) | (mask_p[26] << 20) 771 | (mask_p[25] << 18) | (mask_p[24] << 16) 772 | (mask_p[23] << 14) | (mask_p[22] << 12) 773 | (mask_p[21] << 10) | (mask_p[20] << 8) 774 | (mask_p[19] << 6) | (mask_p[18] << 4) 775 | (mask_p[17] << 2) | (mask_p[16] << 0); 776 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 777 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 778 779 tmp_mask = (mask_p[45] << 28) 780 | (mask_p[44] << 26) | (mask_p[43] << 24) 781 | (mask_p[42] << 22) | (mask_p[41] << 20) 782 | (mask_p[40] << 18) | (mask_p[39] << 16) 783 | (mask_p[38] << 14) | (mask_p[37] << 12) 784 | (mask_p[36] << 10) | (mask_p[35] << 8) 785 | (mask_p[34] << 6) | (mask_p[33] << 4) 786 | (mask_p[32] << 2) | (mask_p[31] << 0); 787 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 788 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 789 790 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 791 | (mask_p[59] << 26) | (mask_p[58] << 24) 792 | (mask_p[57] << 22) | (mask_p[56] << 20) 793 | (mask_p[55] << 18) | (mask_p[54] << 16) 794 | (mask_p[53] << 14) | (mask_p[52] << 12) 795 | (mask_p[51] << 10) | (mask_p[50] << 8) 796 | (mask_p[49] << 6) | (mask_p[48] << 4) 797 | (mask_p[47] << 2) | (mask_p[46] << 0); 798 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 799 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 800} 801 802/* 803 * Fill all software cached or static hardware state information. 804 * Return failure if capabilities are to come from EEPROM and 805 * cannot be read. 806 */ 807static HAL_BOOL 808ar9280FillCapabilityInfo(struct ath_hal *ah) 809{ 810 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 811 812 if (!ar5416FillCapabilityInfo(ah)) 813 return AH_FALSE; 814 pCap->halNumGpioPins = 10; 815 pCap->halWowSupport = AH_TRUE; 816 pCap->halWowMatchPatternExact = AH_TRUE; 817#if 0 818 pCap->halWowMatchPatternDword = AH_TRUE; 819#endif 820 /* AR9280 is a 2x2 stream device */ 821 pCap->halTxStreams = 2; 822 pCap->halRxStreams = 2; 823 824 pCap->halCSTSupport = AH_TRUE; 825 pCap->halRifsRxSupport = AH_TRUE; 826 pCap->halRifsTxSupport = AH_TRUE; 827 pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */ 828 pCap->halExtChanDfsSupport = AH_TRUE; 829 pCap->halUseCombinedRadarRssi = AH_TRUE; 830#if 0 831 /* XXX bluetooth */ 832 pCap->halBtCoexSupport = AH_TRUE; 833#endif 834 pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */ 835 pCap->hal4kbSplitTransSupport = AH_FALSE; 836 /* Disable this so Block-ACK works correctly */ 837 pCap->halHasRxSelfLinkedTail = AH_FALSE; 838 pCap->halMbssidAggrSupport = AH_TRUE; 839 pCap->hal4AddrAggrSupport = AH_TRUE; 840 841 if (AR_SREV_MERLIN_20(ah)) { 842 pCap->halPSPollBroken = AH_FALSE; 843 /* 844 * This just enables the support; it doesn't 845 * state 5ghz fast clock will always be used. 846 */ 847 pCap->halSupportsFastClock5GHz = AH_TRUE; 848 } 849 pCap->halRxStbcSupport = 1; 850 pCap->halTxStbcSupport = 1; 851 pCap->halEnhancedDfsSupport = AH_TRUE; 852 853 return AH_TRUE; 854} 855 856/* 857 * This has been disabled - having the HAL flip chainmasks on/off 858 * when attempting to implement 11n disrupts things. For now, just 859 * leave this flipped off and worry about implementing TX diversity 860 * for legacy and MCS0-7 when 11n is fully functioning. 861 */ 862HAL_BOOL 863ar9280SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings) 864{ 865#define ANTENNA0_CHAINMASK 0x1 866#define ANTENNA1_CHAINMASK 0x2 867#if 0 868 struct ath_hal_5416 *ahp = AH5416(ah); 869 870 /* Antenna selection is done by setting the tx/rx chainmasks approp. */ 871 switch (settings) { 872 case HAL_ANT_FIXED_A: 873 /* Enable first antenna only */ 874 ahp->ah_tx_chainmask = ANTENNA0_CHAINMASK; 875 ahp->ah_rx_chainmask = ANTENNA0_CHAINMASK; 876 break; 877 case HAL_ANT_FIXED_B: 878 /* Enable second antenna only, after checking capability */ 879 if (AH_PRIVATE(ah)->ah_caps.halTxChainMask > ANTENNA1_CHAINMASK) 880 ahp->ah_tx_chainmask = ANTENNA1_CHAINMASK; 881 ahp->ah_rx_chainmask = ANTENNA1_CHAINMASK; 882 break; 883 case HAL_ANT_VARIABLE: 884 /* Restore original chainmask settings */ 885 /* XXX */ 886 ahp->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK; 887 ahp->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK; 888 break; 889 } 890 891 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: settings=%d, tx/rx chainmask=%d/%d\n", 892 __func__, settings, ahp->ah_tx_chainmask, ahp->ah_rx_chainmask); 893 894#endif 895 return AH_TRUE; 896#undef ANTENNA0_CHAINMASK 897#undef ANTENNA1_CHAINMASK 898} 899 900static const char* 901ar9280Probe(uint16_t vendorid, uint16_t devid) 902{ 903 if (vendorid == ATHEROS_VENDOR_ID && 904 (devid == AR9280_DEVID_PCI || devid == AR9280_DEVID_PCIE)) 905 return "Atheros 9280"; 906 return AH_NULL; 907} 908AH_CHIP(AR9280, ar9280Probe, ar9280Attach); 909