ar9280_attach.c revision 222276
1/* 2 * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c 222276 2011-05-25 07:19:19Z adrian $ 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23#include "ah_devid.h" 24 25#include "ah_eeprom_v14.h" /* XXX for tx/rx gain */ 26 27#include "ar9002/ar9280.h" 28#include "ar5416/ar5416reg.h" 29#include "ar5416/ar5416phy.h" 30 31#include "ar9002/ar9280v1.ini" 32#include "ar9002/ar9280v2.ini" 33#include "ar9002/ar9280_olc.h" 34 35static const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */ 36 .calName = "IQ", .calType = IQ_MISMATCH_CAL, 37 .calNumSamples = MIN_CAL_SAMPLES, 38 .calCountMax = PER_MAX_LOG_COUNT, 39 .calCollect = ar5416IQCalCollect, 40 .calPostProc = ar5416IQCalibration 41}; 42static const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */ 43 .calName = "ADC Gain", .calType = ADC_GAIN_CAL, 44 .calNumSamples = MIN_CAL_SAMPLES, 45 .calCountMax = PER_MIN_LOG_COUNT, 46 .calCollect = ar5416AdcGainCalCollect, 47 .calPostProc = ar5416AdcGainCalibration 48}; 49static const HAL_PERCAL_DATA ar9280_adc_dc_cal = { /* single sample */ 50 .calName = "ADC DC", .calType = ADC_DC_CAL, 51 .calNumSamples = MIN_CAL_SAMPLES, 52 .calCountMax = PER_MIN_LOG_COUNT, 53 .calCollect = ar5416AdcDcCalCollect, 54 .calPostProc = ar5416AdcDcCalibration 55}; 56static const HAL_PERCAL_DATA ar9280_adc_init_dc_cal = { 57 .calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL, 58 .calNumSamples = MIN_CAL_SAMPLES, 59 .calCountMax = INIT_LOG_COUNT, 60 .calCollect = ar5416AdcDcCalCollect, 61 .calPostProc = ar5416AdcDcCalibration 62}; 63 64static void ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 65static HAL_BOOL ar9280FillCapabilityInfo(struct ath_hal *ah); 66static void ar9280WriteIni(struct ath_hal *ah, 67 const struct ieee80211_channel *chan); 68 69static void 70ar9280AniSetup(struct ath_hal *ah) 71{ 72 /* 73 * These are the parameters from the AR5416 ANI code; 74 * they likely need quite a bit of adjustment for the 75 * AR9280. 76 */ 77 static const struct ar5212AniParams aniparams = { 78 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 79 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 80 .coarseHigh = { -14, -14, -14, -14, -12 }, 81 .coarseLow = { -64, -64, -64, -64, -70 }, 82 .firpwr = { -78, -78, -78, -78, -80 }, 83 .maxSpurImmunityLevel = 2, 84 .cycPwrThr1 = { 2, 4, 6 }, 85 .maxFirstepLevel = 2, /* levels 0..2 */ 86 .firstep = { 0, 4, 8 }, 87 .ofdmTrigHigh = 500, 88 .ofdmTrigLow = 200, 89 .cckTrigHigh = 200, 90 .cckTrigLow = 100, 91 .rssiThrHigh = 40, 92 .rssiThrLow = 7, 93 .period = 100, 94 }; 95 /* NB: disable ANI noise immmunity for reliable RIFS rx */ 96 AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL); 97 98 /* NB: ANI is not enabled yet */ 99 ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 100} 101 102/* XXX shouldn't be here! */ 103#define EEP_MINOR(_ah) \ 104 (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK) 105 106/* 107 * Attach for an AR9280 part. 108 */ 109static struct ath_hal * 110ar9280Attach(uint16_t devid, HAL_SOFTC sc, 111 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 112 HAL_STATUS *status) 113{ 114 struct ath_hal_9280 *ahp9280; 115 struct ath_hal_5212 *ahp; 116 struct ath_hal *ah; 117 uint32_t val; 118 HAL_STATUS ecode; 119 HAL_BOOL rfStatus; 120 int8_t pwr_table_offset; 121 uint8_t pwr; 122 123 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 124 __func__, sc, (void*) st, (void*) sh); 125 126 /* NB: memory is returned zero'd */ 127 ahp9280 = ath_hal_malloc(sizeof (struct ath_hal_9280)); 128 if (ahp9280 == AH_NULL) { 129 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 130 "%s: cannot allocate memory for state block\n", __func__); 131 *status = HAL_ENOMEM; 132 return AH_NULL; 133 } 134 ahp = AH5212(ahp9280); 135 ah = &ahp->ah_priv.h; 136 137 ar5416InitState(AH5416(ah), devid, sc, st, sh, status); 138 139 /* XXX override with 9280 specific state */ 140 /* override 5416 methods for our needs */ 141 ah->ah_setAntennaSwitch = ar9280SetAntennaSwitch; 142 ah->ah_configPCIE = ar9280ConfigPCIE; 143 144 AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal; 145 AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal; 146 AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal; 147 AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal; 148 AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; 149 150 AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate; 151 AH5416(ah)->ah_writeIni = ar9280WriteIni; 152 AH5416(ah)->ah_olcInit = ar9280olcInit; 153 AH5416(ah)->ah_olcTempCompensation = ar9280olcTemperatureCompensation; 154 AH5416(ah)->ah_setPowerCalTable = ar9280SetPowerCalTable; 155 156 AH5416(ah)->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK; 157 AH5416(ah)->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK; 158 159 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 160 /* reset chip */ 161 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", 162 __func__); 163 ecode = HAL_EIO; 164 goto bad; 165 } 166 167 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 168 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 169 __func__); 170 ecode = HAL_EIO; 171 goto bad; 172 } 173 /* Read Revisions from Chips before taking out of reset */ 174 val = OS_REG_READ(ah, AR_SREV); 175 HALDEBUG(ah, HAL_DEBUG_ATTACH, 176 "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n", 177 __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION), 178 MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION)); 179 /* NB: include chip type to differentiate from pre-Sowl versions */ 180 AH_PRIVATE(ah)->ah_macVersion = 181 (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S; 182 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION); 183 AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0; 184 185 /* setup common ini data; rf backends handle remainder */ 186 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 187 HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v2, 6); 188 HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v2, 2); 189 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 190 ar9280PciePhy_clkreq_always_on_L1_v2, 2); 191 HAL_INI_INIT(&ahp9280->ah_ini_xmodes, 192 ar9280Modes_fast_clock_v2, 3); 193 } else { 194 HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v1, 6); 195 HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v1, 2); 196 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 197 ar9280PciePhy_v1, 2); 198 } 199 ar5416AttachPCIE(ah); 200 201 ecode = ath_hal_v14EepromAttach(ah); 202 if (ecode != HAL_OK) 203 goto bad; 204 205 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 206 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 207 ecode = HAL_EIO; 208 goto bad; 209 } 210 211 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 212 213 if (!ar5212ChipTest(ah)) { 214 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 215 __func__); 216 ecode = HAL_ESELFTEST; 217 goto bad; 218 } 219 220 /* 221 * Set correct Baseband to analog shift 222 * setting to access analog chips. 223 */ 224 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 225 226 /* Read Radio Chip Rev Extract */ 227 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah); 228 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 229 case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */ 230 case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */ 231 break; 232 default: 233 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 234 AH_PRIVATE(ah)->ah_analog5GhzRev = 235 AR_RAD5133_SREV_MAJOR; 236 break; 237 } 238#ifdef AH_DEBUG 239 HALDEBUG(ah, HAL_DEBUG_ANY, 240 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 241 "this driver\n", __func__, 242 AH_PRIVATE(ah)->ah_analog5GhzRev); 243 ecode = HAL_ENOTSUPP; 244 goto bad; 245#endif 246 } 247 rfStatus = ar9280RfAttach(ah, &ecode); 248 if (!rfStatus) { 249 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 250 __func__, ecode); 251 goto bad; 252 } 253 254 /* Enable fixup for AR_AN_TOP2 if necessary */ 255 /* 256 * The v14 EEPROM layer returns HAL_EIO if PWDCLKIND isn't supported 257 * by the EEPROM version. 258 * 259 * ath9k checks the EEPROM minor version is >= 0x0a here, instead of 260 * the abstracted EEPROM access layer. 261 */ 262 ecode = ath_hal_eepromGet(ah, AR_EEP_PWDCLKIND, &pwr); 263 if (AR_SREV_MERLIN_20_OR_LATER(ah) && ecode == HAL_OK && pwr == 0) { 264 printf("[ath] enabling AN_TOP2_FIXUP\n"); 265 AH5416(ah)->ah_need_an_top2_fixup = 1; 266 } 267 268 /* 269 * Check whether the power table offset isn't the default. 270 * This can occur with eeprom minor V21 or greater on Merlin. 271 */ 272 (void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET, &pwr_table_offset); 273 if (pwr_table_offset != AR5416_PWR_TABLE_OFFSET_DB) 274 ath_hal_printf(ah, "[ath]: default pwr offset: %d dBm != EEPROM pwr offset: %d dBm; curves will be adjusted.\n", 275 AR5416_PWR_TABLE_OFFSET_DB, (int) pwr_table_offset); 276 277 /* XXX check for >= minor ver 17 */ 278 if (AR_SREV_MERLIN_20(ah)) { 279 /* setup rxgain table */ 280 switch (ath_hal_eepromGet(ah, AR_EEP_RXGAIN_TYPE, AH_NULL)) { 281 case AR5416_EEP_RXGAIN_13dB_BACKOFF: 282 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 283 ar9280Modes_backoff_13db_rxgain_v2, 6); 284 break; 285 case AR5416_EEP_RXGAIN_23dB_BACKOFF: 286 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 287 ar9280Modes_backoff_23db_rxgain_v2, 6); 288 break; 289 case AR5416_EEP_RXGAIN_ORIG: 290 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 291 ar9280Modes_original_rxgain_v2, 6); 292 break; 293 default: 294 HALASSERT(AH_FALSE); 295 goto bad; /* XXX ? try to continue */ 296 } 297 } 298 299 /* XXX check for >= minor ver 19 */ 300 if (AR_SREV_MERLIN_20(ah)) { 301 /* setp txgain table */ 302 switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) { 303 case AR5416_EEP_TXGAIN_HIGH_POWER: 304 HAL_INI_INIT(&ahp9280->ah_ini_txgain, 305 ar9280Modes_high_power_tx_gain_v2, 6); 306 break; 307 case AR5416_EEP_TXGAIN_ORIG: 308 HAL_INI_INIT(&ahp9280->ah_ini_txgain, 309 ar9280Modes_original_tx_gain_v2, 6); 310 break; 311 default: 312 HALASSERT(AH_FALSE); 313 goto bad; /* XXX ? try to continue */ 314 } 315 } 316 317 /* 318 * Got everything we need now to setup the capabilities. 319 */ 320 if (!ar9280FillCapabilityInfo(ah)) { 321 ecode = HAL_EEREAD; 322 goto bad; 323 } 324 325 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 326 if (ecode != HAL_OK) { 327 HALDEBUG(ah, HAL_DEBUG_ANY, 328 "%s: error getting mac address from EEPROM\n", __func__); 329 goto bad; 330 } 331 /* XXX How about the serial number ? */ 332 /* Read Reg Domain */ 333 AH_PRIVATE(ah)->ah_currentRD = 334 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 335 AH_PRIVATE(ah)->ah_currentRDext = 336 ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL); 337 338 /* 339 * ah_miscMode is populated by ar5416FillCapabilityInfo() 340 * starting from griffin. Set here to make sure that 341 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 342 * placed into hardware. 343 */ 344 if (ahp->ah_miscMode != 0) 345 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 346 347 ar9280AniSetup(ah); /* Anti Noise Immunity */ 348 349 /* Setup noise floor min/max/nominal values */ 350 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ; 351 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ; 352 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9280_2GHZ; 353 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ; 354 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ; 355 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9280_5GHZ; 356 357 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 358 359 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 360 361 return ah; 362bad: 363 if (ah != AH_NULL) 364 ah->ah_detach(ah); 365 if (status) 366 *status = ecode; 367 return AH_NULL; 368} 369 370static void 371ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 372{ 373 if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 374 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 375 OS_DELAY(1000); 376 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 377 OS_REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT); 378 } 379} 380 381static void 382ar9280WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 383{ 384 u_int modesIndex, freqIndex; 385 int regWrites = 0; 386 int i; 387 const HAL_INI_ARRAY *ia; 388 389 /* Setup the indices for the next set of register array writes */ 390 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 391 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 392 freqIndex = 2; 393 if (IEEE80211_IS_CHAN_HT40(chan)) 394 modesIndex = 3; 395 else if (IEEE80211_IS_CHAN_108G(chan)) 396 modesIndex = 5; 397 else 398 modesIndex = 4; 399 } else { 400 freqIndex = 1; 401 if (IEEE80211_IS_CHAN_HT40(chan) || 402 IEEE80211_IS_CHAN_TURBO(chan)) 403 modesIndex = 2; 404 else 405 modesIndex = 1; 406 } 407 408 /* Set correct Baseband to analog shift setting to access analog chips. */ 409 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 410 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 411 412 /* 413 * This is unwound because at the moment, there's a requirement 414 * for Merlin (and later, perhaps) to have a specific bit fixed 415 * in the AR_AN_TOP2 register before writing it. 416 */ 417 ia = &AH5212(ah)->ah_ini_modes; 418#if 0 419 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 420 modesIndex, regWrites); 421#endif 422 HALASSERT(modesIndex < ia->cols); 423 for (i = 0; i < ia->rows; i++) { 424 uint32_t reg = HAL_INI_VAL(ia, i, 0); 425 uint32_t val = HAL_INI_VAL(ia, i, modesIndex); 426 427 if (reg == AR_AN_TOP2 && AH5416(ah)->ah_need_an_top2_fixup) 428 val &= ~AR_AN_TOP2_PWDCLKIND; 429 430 OS_REG_WRITE(ah, reg, val); 431 432 /* Analog shift register delay seems needed for Merlin - PR kern/154220 */ 433 if (reg >= 0x7800 && reg < 0x7900) 434 OS_DELAY(100); 435 436 DMA_YIELD(regWrites); 437 } 438 439 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 440 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_rxgain, 441 modesIndex, regWrites); 442 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain, 443 modesIndex, regWrites); 444 } 445 /* XXX Merlin 100us delay for shift registers */ 446 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 447 1, regWrites); 448 449 if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { 450 /* 5GHz channels w/ Fast Clock use different modal values */ 451 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_xmodes, 452 modesIndex, regWrites); 453 } 454} 455 456#define AR_BASE_FREQ_2GHZ 2300 457#define AR_BASE_FREQ_5GHZ 4900 458#define AR_SPUR_FEEQ_BOUND_HT40 19 459#define AR_SPUR_FEEQ_BOUND_HT20 10 460 461void 462ar9280SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 463{ 464 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 465 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 466 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 467 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 468 static int inc[4] = { 0, 100, 0, 0 }; 469 470 int bb_spur = AR_NO_SPUR; 471 int freq; 472 int bin, cur_bin; 473 int bb_spur_off, spur_subchannel_sd; 474 int spur_freq_sd; 475 int spur_delta_phase; 476 int denominator; 477 int upper, lower, cur_vit_mask; 478 int tmp, newVal; 479 int i; 480 CHAN_CENTERS centers; 481 482 int8_t mask_m[123]; 483 int8_t mask_p[123]; 484 int8_t mask_amt; 485 int tmp_mask; 486 int cur_bb_spur; 487 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 488 489 OS_MEMZERO(&mask_m, sizeof(int8_t) * 123); 490 OS_MEMZERO(&mask_p, sizeof(int8_t) * 123); 491 492 ar5416GetChannelCenters(ah, chan, ¢ers); 493 freq = centers.synth_center; 494 495 /* 496 * Need to verify range +/- 9.38 for static ht20 and +/- 18.75 for ht40, 497 * otherwise spur is out-of-band and can be ignored. 498 */ 499 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 500 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 501 /* Get actual spur freq in MHz from EEPROM read value */ 502 if (is2GHz) { 503 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ; 504 } else { 505 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ; 506 } 507 508 if (AR_NO_SPUR == cur_bb_spur) 509 break; 510 cur_bb_spur = cur_bb_spur - freq; 511 512 if (IEEE80211_IS_CHAN_HT40(chan)) { 513 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) && 514 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) { 515 bb_spur = cur_bb_spur; 516 break; 517 } 518 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) && 519 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) { 520 bb_spur = cur_bb_spur; 521 break; 522 } 523 } 524 525 if (AR_NO_SPUR == bb_spur) { 526#if 1 527 /* 528 * MRC CCK can interfere with beacon detection and cause deaf/mute. 529 * Disable MRC CCK for now. 530 */ 531 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 532#else 533 /* Enable MRC CCK if no spur is found in this channel. */ 534 OS_REG_SET_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 535#endif 536 return; 537 } else { 538 /* 539 * For Merlin, spur can break CCK MRC algorithm. Disable CCK MRC if spur 540 * is found in this channel. 541 */ 542 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 543 } 544 545 bin = bb_spur * 320; 546 547 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 548 549 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 550 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 551 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 552 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 553 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), newVal); 554 555 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 556 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 557 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 558 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 559 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 560 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); 561 562 /* Pick control or extn channel to cancel the spur */ 563 if (IEEE80211_IS_CHAN_HT40(chan)) { 564 if (bb_spur < 0) { 565 spur_subchannel_sd = 1; 566 bb_spur_off = bb_spur + 10; 567 } else { 568 spur_subchannel_sd = 0; 569 bb_spur_off = bb_spur - 10; 570 } 571 } else { 572 spur_subchannel_sd = 0; 573 bb_spur_off = bb_spur; 574 } 575 576 /* 577 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 578 * /80 for dyn2040. 579 */ 580 if (IEEE80211_IS_CHAN_HT40(chan)) 581 spur_delta_phase = ((bb_spur * 262144) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 582 else 583 spur_delta_phase = ((bb_spur * 524288) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 584 585 /* 586 * in 11A mode the denominator of spur_freq_sd should be 40 and 587 * it should be 44 in 11G 588 */ 589 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 44 : 40; 590 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff; 591 592 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 593 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 594 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 595 OS_REG_WRITE(ah, AR_PHY_TIMING11, newVal); 596 597 /* Choose to cancel between control and extension channels */ 598 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S; 599 OS_REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); 600 601 /* 602 * ============================================ 603 * Set Pilot and Channel Masks 604 * 605 * pilot mask 1 [31:0] = +6..-26, no 0 bin 606 * pilot mask 2 [19:0] = +26..+7 607 * 608 * channel mask 1 [31:0] = +6..-26, no 0 bin 609 * channel mask 2 [19:0] = +26..+7 610 */ 611 cur_bin = -6000; 612 upper = bin + 100; 613 lower = bin - 100; 614 615 for (i = 0; i < 4; i++) { 616 int pilot_mask = 0; 617 int chan_mask = 0; 618 int bp = 0; 619 for (bp = 0; bp < 30; bp++) { 620 if ((cur_bin > lower) && (cur_bin < upper)) { 621 pilot_mask = pilot_mask | 0x1 << bp; 622 chan_mask = chan_mask | 0x1 << bp; 623 } 624 cur_bin += 100; 625 } 626 cur_bin += inc[i]; 627 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 628 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 629 } 630 631 /* ================================================= 632 * viterbi mask 1 based on channel magnitude 633 * four levels 0-3 634 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 635 * [1 2 2 1] for -9.6 or [1 2 1] for +16 636 * - enable_mask_ppm, all bins move with freq 637 * 638 * - mask_select, 8 bits for rates (reg 67,0x990c) 639 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 640 * choose which mask to use mask or mask2 641 */ 642 643 /* 644 * viterbi mask 2 2nd set for per data rate puncturing 645 * four levels 0-3 646 * - mask_select, 8 bits for rates (reg 67) 647 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 648 * [1 2 2 1] for -9.6 or [1 2 1] for +16 649 */ 650 cur_vit_mask = 6100; 651 upper = bin + 120; 652 lower = bin - 120; 653 654 for (i = 0; i < 123; i++) { 655 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 656 if ((abs(cur_vit_mask - bin)) < 75) { 657 mask_amt = 1; 658 } else { 659 mask_amt = 0; 660 } 661 if (cur_vit_mask < 0) { 662 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 663 } else { 664 mask_p[cur_vit_mask / 100] = mask_amt; 665 } 666 } 667 cur_vit_mask -= 100; 668 } 669 670 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 671 | (mask_m[48] << 26) | (mask_m[49] << 24) 672 | (mask_m[50] << 22) | (mask_m[51] << 20) 673 | (mask_m[52] << 18) | (mask_m[53] << 16) 674 | (mask_m[54] << 14) | (mask_m[55] << 12) 675 | (mask_m[56] << 10) | (mask_m[57] << 8) 676 | (mask_m[58] << 6) | (mask_m[59] << 4) 677 | (mask_m[60] << 2) | (mask_m[61] << 0); 678 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 679 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 680 681 tmp_mask = (mask_m[31] << 28) 682 | (mask_m[32] << 26) | (mask_m[33] << 24) 683 | (mask_m[34] << 22) | (mask_m[35] << 20) 684 | (mask_m[36] << 18) | (mask_m[37] << 16) 685 | (mask_m[48] << 14) | (mask_m[39] << 12) 686 | (mask_m[40] << 10) | (mask_m[41] << 8) 687 | (mask_m[42] << 6) | (mask_m[43] << 4) 688 | (mask_m[44] << 2) | (mask_m[45] << 0); 689 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 690 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 691 692 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 693 | (mask_m[18] << 26) | (mask_m[18] << 24) 694 | (mask_m[20] << 22) | (mask_m[20] << 20) 695 | (mask_m[22] << 18) | (mask_m[22] << 16) 696 | (mask_m[24] << 14) | (mask_m[24] << 12) 697 | (mask_m[25] << 10) | (mask_m[26] << 8) 698 | (mask_m[27] << 6) | (mask_m[28] << 4) 699 | (mask_m[29] << 2) | (mask_m[30] << 0); 700 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 701 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 702 703 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 704 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 705 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 706 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 707 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 708 | (mask_m[10] << 10) | (mask_m[11] << 8) 709 | (mask_m[12] << 6) | (mask_m[13] << 4) 710 | (mask_m[14] << 2) | (mask_m[15] << 0); 711 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 712 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 713 714 tmp_mask = (mask_p[15] << 28) 715 | (mask_p[14] << 26) | (mask_p[13] << 24) 716 | (mask_p[12] << 22) | (mask_p[11] << 20) 717 | (mask_p[10] << 18) | (mask_p[ 9] << 16) 718 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 719 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 720 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 721 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 722 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 723 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 724 725 tmp_mask = (mask_p[30] << 28) 726 | (mask_p[29] << 26) | (mask_p[28] << 24) 727 | (mask_p[27] << 22) | (mask_p[26] << 20) 728 | (mask_p[25] << 18) | (mask_p[24] << 16) 729 | (mask_p[23] << 14) | (mask_p[22] << 12) 730 | (mask_p[21] << 10) | (mask_p[20] << 8) 731 | (mask_p[19] << 6) | (mask_p[18] << 4) 732 | (mask_p[17] << 2) | (mask_p[16] << 0); 733 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 734 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 735 736 tmp_mask = (mask_p[45] << 28) 737 | (mask_p[44] << 26) | (mask_p[43] << 24) 738 | (mask_p[42] << 22) | (mask_p[41] << 20) 739 | (mask_p[40] << 18) | (mask_p[39] << 16) 740 | (mask_p[38] << 14) | (mask_p[37] << 12) 741 | (mask_p[36] << 10) | (mask_p[35] << 8) 742 | (mask_p[34] << 6) | (mask_p[33] << 4) 743 | (mask_p[32] << 2) | (mask_p[31] << 0); 744 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 745 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 746 747 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 748 | (mask_p[59] << 26) | (mask_p[58] << 24) 749 | (mask_p[57] << 22) | (mask_p[56] << 20) 750 | (mask_p[55] << 18) | (mask_p[54] << 16) 751 | (mask_p[53] << 14) | (mask_p[52] << 12) 752 | (mask_p[51] << 10) | (mask_p[50] << 8) 753 | (mask_p[49] << 6) | (mask_p[48] << 4) 754 | (mask_p[47] << 2) | (mask_p[46] << 0); 755 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 756 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 757} 758 759/* 760 * Fill all software cached or static hardware state information. 761 * Return failure if capabilities are to come from EEPROM and 762 * cannot be read. 763 */ 764static HAL_BOOL 765ar9280FillCapabilityInfo(struct ath_hal *ah) 766{ 767 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 768 769 if (!ar5416FillCapabilityInfo(ah)) 770 return AH_FALSE; 771 pCap->halNumGpioPins = 10; 772 pCap->halWowSupport = AH_TRUE; 773 pCap->halWowMatchPatternExact = AH_TRUE; 774#if 0 775 pCap->halWowMatchPatternDword = AH_TRUE; 776#endif 777 /* AR9280 is a 2x2 stream device */ 778 pCap->halTxStreams = 2; 779 pCap->halRxStreams = 2; 780 781 pCap->halCSTSupport = AH_TRUE; 782 pCap->halRifsRxSupport = AH_TRUE; 783 pCap->halRifsTxSupport = AH_TRUE; 784 pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */ 785 pCap->halExtChanDfsSupport = AH_TRUE; 786#if 0 787 /* XXX bluetooth */ 788 pCap->halBtCoexSupport = AH_TRUE; 789#endif 790 pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */ 791 pCap->hal4kbSplitTransSupport = AH_FALSE; 792 /* Disable this so Block-ACK works correctly */ 793 pCap->halHasRxSelfLinkedTail = AH_FALSE; 794 pCap->halMbssidAggrSupport = AH_TRUE; 795 pCap->hal4AddrAggrSupport = AH_TRUE; 796 797 if (AR_SREV_MERLIN_20(ah)) { 798 pCap->halPSPollBroken = AH_FALSE; 799 /* 800 * This just enables the support; it doesn't 801 * state 5ghz fast clock will always be used. 802 */ 803 pCap->halSupportsFastClock5GHz = AH_TRUE; 804 } 805 pCap->halRxStbcSupport = 1; 806 pCap->halTxStbcSupport = 1; 807 808 return AH_TRUE; 809} 810 811/* 812 * This has been disabled - having the HAL flip chainmasks on/off 813 * when attempting to implement 11n disrupts things. For now, just 814 * leave this flipped off and worry about implementing TX diversity 815 * for legacy and MCS0-7 when 11n is fully functioning. 816 */ 817HAL_BOOL 818ar9280SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings) 819{ 820#define ANTENNA0_CHAINMASK 0x1 821#define ANTENNA1_CHAINMASK 0x2 822#if 0 823 struct ath_hal_5416 *ahp = AH5416(ah); 824 825 /* Antenna selection is done by setting the tx/rx chainmasks approp. */ 826 switch (settings) { 827 case HAL_ANT_FIXED_A: 828 /* Enable first antenna only */ 829 ahp->ah_tx_chainmask = ANTENNA0_CHAINMASK; 830 ahp->ah_rx_chainmask = ANTENNA0_CHAINMASK; 831 break; 832 case HAL_ANT_FIXED_B: 833 /* Enable second antenna only, after checking capability */ 834 if (AH_PRIVATE(ah)->ah_caps.halTxChainMask > ANTENNA1_CHAINMASK) 835 ahp->ah_tx_chainmask = ANTENNA1_CHAINMASK; 836 ahp->ah_rx_chainmask = ANTENNA1_CHAINMASK; 837 break; 838 case HAL_ANT_VARIABLE: 839 /* Restore original chainmask settings */ 840 /* XXX */ 841 ahp->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK; 842 ahp->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK; 843 break; 844 } 845 846 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: settings=%d, tx/rx chainmask=%d/%d\n", 847 __func__, settings, ahp->ah_tx_chainmask, ahp->ah_rx_chainmask); 848 849#endif 850 return AH_TRUE; 851#undef ANTENNA0_CHAINMASK 852#undef ANTENNA1_CHAINMASK 853} 854 855static const char* 856ar9280Probe(uint16_t vendorid, uint16_t devid) 857{ 858 if (vendorid == ATHEROS_VENDOR_ID && 859 (devid == AR9280_DEVID_PCI || devid == AR9280_DEVID_PCIE)) 860 return "Atheros 9280"; 861 return AH_NULL; 862} 863AH_CHIP(AR9280, ar9280Probe, ar9280Attach); 864