ar9280_attach.c revision 219852
1/* 2 * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c 219852 2011-03-22 00:12:26Z adrian $ 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23#include "ah_devid.h" 24 25#include "ah_eeprom_v14.h" /* XXX for tx/rx gain */ 26 27#include "ar9002/ar9280.h" 28#include "ar5416/ar5416reg.h" 29#include "ar5416/ar5416phy.h" 30 31#include "ar9002/ar9280v1.ini" 32#include "ar9002/ar9280v2.ini" 33#include "ar9002/ar9280_olc.h" 34 35static const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */ 36 .calName = "IQ", .calType = IQ_MISMATCH_CAL, 37 .calNumSamples = MIN_CAL_SAMPLES, 38 .calCountMax = PER_MAX_LOG_COUNT, 39 .calCollect = ar5416IQCalCollect, 40 .calPostProc = ar5416IQCalibration 41}; 42static const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */ 43 .calName = "ADC Gain", .calType = ADC_GAIN_CAL, 44 .calNumSamples = MIN_CAL_SAMPLES, 45 .calCountMax = PER_MIN_LOG_COUNT, 46 .calCollect = ar5416AdcGainCalCollect, 47 .calPostProc = ar5416AdcGainCalibration 48}; 49static const HAL_PERCAL_DATA ar9280_adc_dc_cal = { /* single sample */ 50 .calName = "ADC DC", .calType = ADC_DC_CAL, 51 .calNumSamples = MIN_CAL_SAMPLES, 52 .calCountMax = PER_MIN_LOG_COUNT, 53 .calCollect = ar5416AdcDcCalCollect, 54 .calPostProc = ar5416AdcDcCalibration 55}; 56static const HAL_PERCAL_DATA ar9280_adc_init_dc_cal = { 57 .calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL, 58 .calNumSamples = MIN_CAL_SAMPLES, 59 .calCountMax = INIT_LOG_COUNT, 60 .calCollect = ar5416AdcDcCalCollect, 61 .calPostProc = ar5416AdcDcCalibration 62}; 63 64static void ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 65static HAL_BOOL ar9280FillCapabilityInfo(struct ath_hal *ah); 66static void ar9280WriteIni(struct ath_hal *ah, 67 const struct ieee80211_channel *chan); 68 69static void 70ar9280AniSetup(struct ath_hal *ah) 71{ 72 /* 73 * These are the parameters from the AR5416 ANI code; 74 * they likely need quite a bit of adjustment for the 75 * AR9280. 76 */ 77 static const struct ar5212AniParams aniparams = { 78 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 79 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 80 .coarseHigh = { -14, -14, -14, -14, -12 }, 81 .coarseLow = { -64, -64, -64, -64, -70 }, 82 .firpwr = { -78, -78, -78, -78, -80 }, 83 .maxSpurImmunityLevel = 2, 84 .cycPwrThr1 = { 2, 4, 6 }, 85 .maxFirstepLevel = 2, /* levels 0..2 */ 86 .firstep = { 0, 4, 8 }, 87 .ofdmTrigHigh = 500, 88 .ofdmTrigLow = 200, 89 .cckTrigHigh = 200, 90 .cckTrigLow = 100, 91 .rssiThrHigh = 40, 92 .rssiThrLow = 7, 93 .period = 100, 94 }; 95 /* NB: disable ANI noise immmunity for reliable RIFS rx */ 96 AH5416(ah)->ah_ani_function &= ~ HAL_ANI_NOISE_IMMUNITY_LEVEL; 97 98 /* NB: ANI is not enabled yet */ 99 ar5416AniAttach(ah, &aniparams, &aniparams, AH_FALSE); 100} 101 102/* 103 * Attach for an AR9280 part. 104 */ 105static struct ath_hal * 106ar9280Attach(uint16_t devid, HAL_SOFTC sc, 107 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 108 HAL_STATUS *status) 109{ 110 struct ath_hal_9280 *ahp9280; 111 struct ath_hal_5212 *ahp; 112 struct ath_hal *ah; 113 uint32_t val; 114 HAL_STATUS ecode; 115 HAL_BOOL rfStatus; 116 int8_t pwr_table_offset; 117 uint8_t pwr; 118 119 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 120 __func__, sc, (void*) st, (void*) sh); 121 122 /* NB: memory is returned zero'd */ 123 ahp9280 = ath_hal_malloc(sizeof (struct ath_hal_9280)); 124 if (ahp9280 == AH_NULL) { 125 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 126 "%s: cannot allocate memory for state block\n", __func__); 127 *status = HAL_ENOMEM; 128 return AH_NULL; 129 } 130 ahp = AH5212(ahp9280); 131 ah = &ahp->ah_priv.h; 132 133 ar5416InitState(AH5416(ah), devid, sc, st, sh, status); 134 135 /* XXX override with 9280 specific state */ 136 /* override 5416 methods for our needs */ 137 ah->ah_setAntennaSwitch = ar9280SetAntennaSwitch; 138 ah->ah_configPCIE = ar9280ConfigPCIE; 139 140 AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal; 141 AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal; 142 AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal; 143 AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal; 144 AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; 145 146 AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate; 147 AH5416(ah)->ah_writeIni = ar9280WriteIni; 148 AH5416(ah)->ah_olcInit = ar9280olcInit; 149 AH5416(ah)->ah_olcTempCompensation = ar9280olcTemperatureCompensation; 150 AH5416(ah)->ah_setPowerCalTable = ar9280SetPowerCalTable; 151 152 AH5416(ah)->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK; 153 AH5416(ah)->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK; 154 155 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 156 /* reset chip */ 157 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", 158 __func__); 159 ecode = HAL_EIO; 160 goto bad; 161 } 162 163 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 164 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 165 __func__); 166 ecode = HAL_EIO; 167 goto bad; 168 } 169 /* Read Revisions from Chips before taking out of reset */ 170 val = OS_REG_READ(ah, AR_SREV); 171 HALDEBUG(ah, HAL_DEBUG_ATTACH, 172 "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n", 173 __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION), 174 MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION)); 175 /* NB: include chip type to differentiate from pre-Sowl versions */ 176 AH_PRIVATE(ah)->ah_macVersion = 177 (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S; 178 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION); 179 AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0; 180 181 /* setup common ini data; rf backends handle remainder */ 182 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 183 HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v2, 6); 184 HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v2, 2); 185 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 186 ar9280PciePhy_clkreq_always_on_L1_v2, 2); 187 HAL_INI_INIT(&ahp9280->ah_ini_xmodes, 188 ar9280Modes_fast_clock_v2, 3); 189 } else { 190 HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v1, 6); 191 HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v1, 2); 192 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 193 ar9280PciePhy_v1, 2); 194 } 195 ar5416AttachPCIE(ah); 196 197 ecode = ath_hal_v14EepromAttach(ah); 198 if (ecode != HAL_OK) 199 goto bad; 200 201 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 202 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 203 ecode = HAL_EIO; 204 goto bad; 205 } 206 207 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 208 209 if (!ar5212ChipTest(ah)) { 210 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 211 __func__); 212 ecode = HAL_ESELFTEST; 213 goto bad; 214 } 215 216 /* 217 * Set correct Baseband to analog shift 218 * setting to access analog chips. 219 */ 220 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 221 222 /* Read Radio Chip Rev Extract */ 223 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah); 224 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 225 case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */ 226 case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */ 227 break; 228 default: 229 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 230 AH_PRIVATE(ah)->ah_analog5GhzRev = 231 AR_RAD5133_SREV_MAJOR; 232 break; 233 } 234#ifdef AH_DEBUG 235 HALDEBUG(ah, HAL_DEBUG_ANY, 236 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 237 "this driver\n", __func__, 238 AH_PRIVATE(ah)->ah_analog5GhzRev); 239 ecode = HAL_ENOTSUPP; 240 goto bad; 241#endif 242 } 243 rfStatus = ar9280RfAttach(ah, &ecode); 244 if (!rfStatus) { 245 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 246 __func__, ecode); 247 goto bad; 248 } 249 250 /* Enable fixup for AR_AN_TOP2 if necessary */ 251 /* 252 * The v14 EEPROM layer returns HAL_EIO if PWDCLKIND isn't supported 253 * by the EEPROM version. 254 * 255 * ath9k checks the EEPROM minor version is >= 0x0a here, instead of 256 * the abstracted EEPROM access layer. 257 */ 258 ecode = ath_hal_eepromGet(ah, AR_EEP_PWDCLKIND, &pwr); 259 if (AR_SREV_MERLIN_20_OR_LATER(ah) && ecode == HAL_OK && pwr == 0) { 260 printf("[ath] enabling AN_TOP2_FIXUP\n"); 261 AH5416(ah)->ah_need_an_top2_fixup = 1; 262 } 263 264 /* 265 * Check whether the power table offset isn't the default. 266 * This can occur with eeprom minor V21 or greater on Merlin. 267 */ 268 (void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET, &pwr_table_offset); 269 if (pwr_table_offset != AR5416_PWR_TABLE_OFFSET_DB) 270 ath_hal_printf(ah, "[ath]: default pwr offset: %d dBm != EEPROM pwr offset: %d dBm; curves will be adjusted.\n", 271 AR5416_PWR_TABLE_OFFSET_DB, (int) pwr_table_offset); 272 273 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 274 /* setup rxgain table */ 275 switch (ath_hal_eepromGet(ah, AR_EEP_RXGAIN_TYPE, AH_NULL)) { 276 case AR5416_EEP_RXGAIN_13dB_BACKOFF: 277 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 278 ar9280Modes_backoff_13db_rxgain_v2, 6); 279 break; 280 case AR5416_EEP_RXGAIN_23dB_BACKOFF: 281 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 282 ar9280Modes_backoff_23db_rxgain_v2, 6); 283 break; 284 case AR5416_EEP_RXGAIN_ORIG: 285 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 286 ar9280Modes_original_rxgain_v2, 6); 287 break; 288 default: 289 HALASSERT(AH_FALSE); 290 goto bad; /* XXX ? try to continue */ 291 } 292 } 293 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 294 /* setp txgain table */ 295 switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) { 296 case AR5416_EEP_TXGAIN_HIGH_POWER: 297 HAL_INI_INIT(&ahp9280->ah_ini_txgain, 298 ar9280Modes_high_power_tx_gain_v2, 6); 299 break; 300 case AR5416_EEP_TXGAIN_ORIG: 301 HAL_INI_INIT(&ahp9280->ah_ini_txgain, 302 ar9280Modes_original_tx_gain_v2, 6); 303 break; 304 default: 305 HALASSERT(AH_FALSE); 306 goto bad; /* XXX ? try to continue */ 307 } 308 } 309 310 /* 311 * Got everything we need now to setup the capabilities. 312 */ 313 if (!ar9280FillCapabilityInfo(ah)) { 314 ecode = HAL_EEREAD; 315 goto bad; 316 } 317 318 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 319 if (ecode != HAL_OK) { 320 HALDEBUG(ah, HAL_DEBUG_ANY, 321 "%s: error getting mac address from EEPROM\n", __func__); 322 goto bad; 323 } 324 /* XXX How about the serial number ? */ 325 /* Read Reg Domain */ 326 AH_PRIVATE(ah)->ah_currentRD = 327 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 328 329 /* 330 * ah_miscMode is populated by ar5416FillCapabilityInfo() 331 * starting from griffin. Set here to make sure that 332 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 333 * placed into hardware. 334 */ 335 if (ahp->ah_miscMode != 0) 336 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 337 338 ar9280AniSetup(ah); /* Anti Noise Immunity */ 339 340 /* Setup noise floor min/max/nominal values */ 341 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ; 342 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ; 343 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9280_2GHZ; 344 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ; 345 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ; 346 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9280_5GHZ; 347 348 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 349 350 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 351 352 return ah; 353bad: 354 if (ah != AH_NULL) 355 ah->ah_detach(ah); 356 if (status) 357 *status = ecode; 358 return AH_NULL; 359} 360 361static void 362ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 363{ 364 if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 365 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 366 OS_DELAY(1000); 367 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 368 OS_REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT); 369 } 370} 371 372static void 373ar9280WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 374{ 375 u_int modesIndex, freqIndex; 376 int regWrites = 0; 377 int i; 378 const HAL_INI_ARRAY *ia; 379 380 /* Setup the indices for the next set of register array writes */ 381 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 382 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 383 freqIndex = 2; 384 if (IEEE80211_IS_CHAN_HT40(chan)) 385 modesIndex = 3; 386 else if (IEEE80211_IS_CHAN_108G(chan)) 387 modesIndex = 5; 388 else 389 modesIndex = 4; 390 } else { 391 freqIndex = 1; 392 if (IEEE80211_IS_CHAN_HT40(chan) || 393 IEEE80211_IS_CHAN_TURBO(chan)) 394 modesIndex = 2; 395 else 396 modesIndex = 1; 397 } 398 399 /* Set correct Baseband to analog shift setting to access analog chips. */ 400 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 401 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 402 403 /* 404 * This is unwound because at the moment, there's a requirement 405 * for Merlin (and later, perhaps) to have a specific bit fixed 406 * in the AR_AN_TOP2 register before writing it. 407 */ 408 ia = &AH5212(ah)->ah_ini_modes; 409#if 0 410 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 411 modesIndex, regWrites); 412#endif 413 HALASSERT(modesIndex < ia->cols); 414 for (i = 0; i < ia->rows; i++) { 415 uint32_t reg = HAL_INI_VAL(ia, i, 0); 416 uint32_t val = HAL_INI_VAL(ia, i, modesIndex); 417 418 if (reg == AR_AN_TOP2 && AH5416(ah)->ah_need_an_top2_fixup) 419 val &= ~AR_AN_TOP2_PWDCLKIND; 420 421 OS_REG_WRITE(ah, reg, val); 422 423 /* Analog shift register delay seems needed for Merlin - PR kern/154220 */ 424 if (reg >= 0x7800 && reg < 0x78a0) 425 OS_DELAY(100); 426 427 DMA_YIELD(regWrites); 428 } 429 430 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 431 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_rxgain, 432 modesIndex, regWrites); 433 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain, 434 modesIndex, regWrites); 435 } 436 /* XXX Merlin 100us delay for shift registers */ 437 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 438 1, regWrites); 439 440 if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { 441 /* 5GHz channels w/ Fast Clock use different modal values */ 442 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_xmodes, 443 modesIndex, regWrites); 444 } 445} 446 447#define AR_BASE_FREQ_2GHZ 2300 448#define AR_BASE_FREQ_5GHZ 4900 449#define AR_SPUR_FEEQ_BOUND_HT40 19 450#define AR_SPUR_FEEQ_BOUND_HT20 10 451 452void 453ar9280SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 454{ 455 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 456 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 457 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 458 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 459 static int inc[4] = { 0, 100, 0, 0 }; 460 461 int bb_spur = AR_NO_SPUR; 462 int freq; 463 int bin, cur_bin; 464 int bb_spur_off, spur_subchannel_sd; 465 int spur_freq_sd; 466 int spur_delta_phase; 467 int denominator; 468 int upper, lower, cur_vit_mask; 469 int tmp, newVal; 470 int i; 471 CHAN_CENTERS centers; 472 473 int8_t mask_m[123]; 474 int8_t mask_p[123]; 475 int8_t mask_amt; 476 int tmp_mask; 477 int cur_bb_spur; 478 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 479 480 OS_MEMZERO(&mask_m, sizeof(int8_t) * 123); 481 OS_MEMZERO(&mask_p, sizeof(int8_t) * 123); 482 483 ar5416GetChannelCenters(ah, chan, ¢ers); 484 freq = centers.synth_center; 485 486 /* 487 * Need to verify range +/- 9.38 for static ht20 and +/- 18.75 for ht40, 488 * otherwise spur is out-of-band and can be ignored. 489 */ 490 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 491 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 492 /* Get actual spur freq in MHz from EEPROM read value */ 493 if (is2GHz) { 494 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ; 495 } else { 496 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ; 497 } 498 499 if (AR_NO_SPUR == cur_bb_spur) 500 break; 501 cur_bb_spur = cur_bb_spur - freq; 502 503 if (IEEE80211_IS_CHAN_HT40(chan)) { 504 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) && 505 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) { 506 bb_spur = cur_bb_spur; 507 break; 508 } 509 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) && 510 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) { 511 bb_spur = cur_bb_spur; 512 break; 513 } 514 } 515 516 if (AR_NO_SPUR == bb_spur) { 517#if 1 518 /* 519 * MRC CCK can interfere with beacon detection and cause deaf/mute. 520 * Disable MRC CCK for now. 521 */ 522 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 523#else 524 /* Enable MRC CCK if no spur is found in this channel. */ 525 OS_REG_SET_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 526#endif 527 return; 528 } else { 529 /* 530 * For Merlin, spur can break CCK MRC algorithm. Disable CCK MRC if spur 531 * is found in this channel. 532 */ 533 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 534 } 535 536 bin = bb_spur * 320; 537 538 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 539 540 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 541 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 542 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 543 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 544 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), newVal); 545 546 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 547 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 548 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 549 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 550 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 551 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); 552 553 /* Pick control or extn channel to cancel the spur */ 554 if (IEEE80211_IS_CHAN_HT40(chan)) { 555 if (bb_spur < 0) { 556 spur_subchannel_sd = 1; 557 bb_spur_off = bb_spur + 10; 558 } else { 559 spur_subchannel_sd = 0; 560 bb_spur_off = bb_spur - 10; 561 } 562 } else { 563 spur_subchannel_sd = 0; 564 bb_spur_off = bb_spur; 565 } 566 567 /* 568 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 569 * /80 for dyn2040. 570 */ 571 if (IEEE80211_IS_CHAN_HT40(chan)) 572 spur_delta_phase = ((bb_spur * 262144) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 573 else 574 spur_delta_phase = ((bb_spur * 524288) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 575 576 /* 577 * in 11A mode the denominator of spur_freq_sd should be 40 and 578 * it should be 44 in 11G 579 */ 580 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 44 : 40; 581 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff; 582 583 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 584 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 585 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 586 OS_REG_WRITE(ah, AR_PHY_TIMING11, newVal); 587 588 /* Choose to cancel between control and extension channels */ 589 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S; 590 OS_REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); 591 592 /* 593 * ============================================ 594 * Set Pilot and Channel Masks 595 * 596 * pilot mask 1 [31:0] = +6..-26, no 0 bin 597 * pilot mask 2 [19:0] = +26..+7 598 * 599 * channel mask 1 [31:0] = +6..-26, no 0 bin 600 * channel mask 2 [19:0] = +26..+7 601 */ 602 cur_bin = -6000; 603 upper = bin + 100; 604 lower = bin - 100; 605 606 for (i = 0; i < 4; i++) { 607 int pilot_mask = 0; 608 int chan_mask = 0; 609 int bp = 0; 610 for (bp = 0; bp < 30; bp++) { 611 if ((cur_bin > lower) && (cur_bin < upper)) { 612 pilot_mask = pilot_mask | 0x1 << bp; 613 chan_mask = chan_mask | 0x1 << bp; 614 } 615 cur_bin += 100; 616 } 617 cur_bin += inc[i]; 618 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 619 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 620 } 621 622 /* ================================================= 623 * viterbi mask 1 based on channel magnitude 624 * four levels 0-3 625 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 626 * [1 2 2 1] for -9.6 or [1 2 1] for +16 627 * - enable_mask_ppm, all bins move with freq 628 * 629 * - mask_select, 8 bits for rates (reg 67,0x990c) 630 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 631 * choose which mask to use mask or mask2 632 */ 633 634 /* 635 * viterbi mask 2 2nd set for per data rate puncturing 636 * four levels 0-3 637 * - mask_select, 8 bits for rates (reg 67) 638 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 639 * [1 2 2 1] for -9.6 or [1 2 1] for +16 640 */ 641 cur_vit_mask = 6100; 642 upper = bin + 120; 643 lower = bin - 120; 644 645 for (i = 0; i < 123; i++) { 646 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 647 if ((abs(cur_vit_mask - bin)) < 75) { 648 mask_amt = 1; 649 } else { 650 mask_amt = 0; 651 } 652 if (cur_vit_mask < 0) { 653 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 654 } else { 655 mask_p[cur_vit_mask / 100] = mask_amt; 656 } 657 } 658 cur_vit_mask -= 100; 659 } 660 661 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 662 | (mask_m[48] << 26) | (mask_m[49] << 24) 663 | (mask_m[50] << 22) | (mask_m[51] << 20) 664 | (mask_m[52] << 18) | (mask_m[53] << 16) 665 | (mask_m[54] << 14) | (mask_m[55] << 12) 666 | (mask_m[56] << 10) | (mask_m[57] << 8) 667 | (mask_m[58] << 6) | (mask_m[59] << 4) 668 | (mask_m[60] << 2) | (mask_m[61] << 0); 669 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 670 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 671 672 tmp_mask = (mask_m[31] << 28) 673 | (mask_m[32] << 26) | (mask_m[33] << 24) 674 | (mask_m[34] << 22) | (mask_m[35] << 20) 675 | (mask_m[36] << 18) | (mask_m[37] << 16) 676 | (mask_m[48] << 14) | (mask_m[39] << 12) 677 | (mask_m[40] << 10) | (mask_m[41] << 8) 678 | (mask_m[42] << 6) | (mask_m[43] << 4) 679 | (mask_m[44] << 2) | (mask_m[45] << 0); 680 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 681 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 682 683 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 684 | (mask_m[18] << 26) | (mask_m[18] << 24) 685 | (mask_m[20] << 22) | (mask_m[20] << 20) 686 | (mask_m[22] << 18) | (mask_m[22] << 16) 687 | (mask_m[24] << 14) | (mask_m[24] << 12) 688 | (mask_m[25] << 10) | (mask_m[26] << 8) 689 | (mask_m[27] << 6) | (mask_m[28] << 4) 690 | (mask_m[29] << 2) | (mask_m[30] << 0); 691 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 692 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 693 694 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 695 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 696 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 697 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 698 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 699 | (mask_m[10] << 10) | (mask_m[11] << 8) 700 | (mask_m[12] << 6) | (mask_m[13] << 4) 701 | (mask_m[14] << 2) | (mask_m[15] << 0); 702 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 703 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 704 705 tmp_mask = (mask_p[15] << 28) 706 | (mask_p[14] << 26) | (mask_p[13] << 24) 707 | (mask_p[12] << 22) | (mask_p[11] << 20) 708 | (mask_p[10] << 18) | (mask_p[ 9] << 16) 709 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 710 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 711 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 712 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 713 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 714 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 715 716 tmp_mask = (mask_p[30] << 28) 717 | (mask_p[29] << 26) | (mask_p[28] << 24) 718 | (mask_p[27] << 22) | (mask_p[26] << 20) 719 | (mask_p[25] << 18) | (mask_p[24] << 16) 720 | (mask_p[23] << 14) | (mask_p[22] << 12) 721 | (mask_p[21] << 10) | (mask_p[20] << 8) 722 | (mask_p[19] << 6) | (mask_p[18] << 4) 723 | (mask_p[17] << 2) | (mask_p[16] << 0); 724 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 725 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 726 727 tmp_mask = (mask_p[45] << 28) 728 | (mask_p[44] << 26) | (mask_p[43] << 24) 729 | (mask_p[42] << 22) | (mask_p[41] << 20) 730 | (mask_p[40] << 18) | (mask_p[39] << 16) 731 | (mask_p[38] << 14) | (mask_p[37] << 12) 732 | (mask_p[36] << 10) | (mask_p[35] << 8) 733 | (mask_p[34] << 6) | (mask_p[33] << 4) 734 | (mask_p[32] << 2) | (mask_p[31] << 0); 735 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 736 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 737 738 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 739 | (mask_p[59] << 26) | (mask_p[58] << 24) 740 | (mask_p[57] << 22) | (mask_p[56] << 20) 741 | (mask_p[55] << 18) | (mask_p[54] << 16) 742 | (mask_p[53] << 14) | (mask_p[52] << 12) 743 | (mask_p[51] << 10) | (mask_p[50] << 8) 744 | (mask_p[49] << 6) | (mask_p[48] << 4) 745 | (mask_p[47] << 2) | (mask_p[46] << 0); 746 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 747 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 748} 749 750/* 751 * Fill all software cached or static hardware state information. 752 * Return failure if capabilities are to come from EEPROM and 753 * cannot be read. 754 */ 755static HAL_BOOL 756ar9280FillCapabilityInfo(struct ath_hal *ah) 757{ 758 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 759 760 if (!ar5416FillCapabilityInfo(ah)) 761 return AH_FALSE; 762 pCap->halNumGpioPins = 10; 763 pCap->halWowSupport = AH_TRUE; 764 pCap->halWowMatchPatternExact = AH_TRUE; 765#if 0 766 pCap->halWowMatchPatternDword = AH_TRUE; 767#endif 768 /* AR9280 is a 2x2 stream device */ 769 pCap->halTxStreams = 2; 770 pCap->halRxStreams = 2; 771 772 pCap->halCSTSupport = AH_TRUE; 773 pCap->halRifsRxSupport = AH_TRUE; 774 pCap->halRifsTxSupport = AH_TRUE; 775 pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */ 776 pCap->halExtChanDfsSupport = AH_TRUE; 777#if 0 778 /* XXX bluetooth */ 779 pCap->halBtCoexSupport = AH_TRUE; 780#endif 781 pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */ 782 pCap->hal4kbSplitTransSupport = AH_FALSE; 783 pCap->halRxStbcSupport = 1; 784 pCap->halTxStbcSupport = 1; 785 786 return AH_TRUE; 787} 788 789/* 790 * This has been disabled - having the HAL flip chainmasks on/off 791 * when attempting to implement 11n disrupts things. For now, just 792 * leave this flipped off and worry about implementing TX diversity 793 * for legacy and MCS0-7 when 11n is fully functioning. 794 */ 795HAL_BOOL 796ar9280SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings) 797{ 798#define ANTENNA0_CHAINMASK 0x1 799#define ANTENNA1_CHAINMASK 0x2 800#if 0 801 struct ath_hal_5416 *ahp = AH5416(ah); 802 803 /* Antenna selection is done by setting the tx/rx chainmasks approp. */ 804 switch (settings) { 805 case HAL_ANT_FIXED_A: 806 /* Enable first antenna only */ 807 ahp->ah_tx_chainmask = ANTENNA0_CHAINMASK; 808 ahp->ah_rx_chainmask = ANTENNA0_CHAINMASK; 809 break; 810 case HAL_ANT_FIXED_B: 811 /* Enable second antenna only, after checking capability */ 812 if (AH_PRIVATE(ah)->ah_caps.halTxChainMask > ANTENNA1_CHAINMASK) 813 ahp->ah_tx_chainmask = ANTENNA1_CHAINMASK; 814 ahp->ah_rx_chainmask = ANTENNA1_CHAINMASK; 815 break; 816 case HAL_ANT_VARIABLE: 817 /* Restore original chainmask settings */ 818 /* XXX */ 819 ahp->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK; 820 ahp->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK; 821 break; 822 } 823 824 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: settings=%d, tx/rx chainmask=%d/%d\n", 825 __func__, settings, ahp->ah_tx_chainmask, ahp->ah_rx_chainmask); 826 827#endif 828 return AH_TRUE; 829#undef ANTENNA0_CHAINMASK 830#undef ANTENNA1_CHAINMASK 831} 832 833static const char* 834ar9280Probe(uint16_t vendorid, uint16_t devid) 835{ 836 if (vendorid == ATHEROS_VENDOR_ID && 837 (devid == AR9280_DEVID_PCI || devid == AR9280_DEVID_PCIE)) 838 return "Atheros 9280"; 839 return AH_NULL; 840} 841AH_CHIP(AR9280, ar9280Probe, ar9280Attach); 842