ar9280_attach.c revision 203882
1/* 2 * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar9280_attach.c 203882 2010-02-14 16:26:32Z rpaulo $ 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23#include "ah_devid.h" 24 25#include "ah_eeprom_v14.h" /* XXX for tx/rx gain */ 26 27#include "ar5416/ar9280.h" 28#include "ar5416/ar5416reg.h" 29#include "ar5416/ar5416phy.h" 30 31#include "ar5416/ar9280v1.ini" 32#include "ar5416/ar9280v2.ini" 33 34static const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */ 35 .calName = "IQ", .calType = IQ_MISMATCH_CAL, 36 .calNumSamples = MIN_CAL_SAMPLES, 37 .calCountMax = PER_MAX_LOG_COUNT, 38 .calCollect = ar5416IQCalCollect, 39 .calPostProc = ar5416IQCalibration 40}; 41static const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */ 42 .calName = "ADC Gain", .calType = ADC_GAIN_CAL, 43 .calNumSamples = MIN_CAL_SAMPLES, 44 .calCountMax = PER_MIN_LOG_COUNT, 45 .calCollect = ar5416AdcGainCalCollect, 46 .calPostProc = ar5416AdcGainCalibration 47}; 48static const HAL_PERCAL_DATA ar9280_adc_dc_cal = { /* single sample */ 49 .calName = "ADC DC", .calType = ADC_DC_CAL, 50 .calNumSamples = MIN_CAL_SAMPLES, 51 .calCountMax = PER_MIN_LOG_COUNT, 52 .calCollect = ar5416AdcDcCalCollect, 53 .calPostProc = ar5416AdcDcCalibration 54}; 55static const HAL_PERCAL_DATA ar9280_adc_init_dc_cal = { 56 .calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL, 57 .calNumSamples = MIN_CAL_SAMPLES, 58 .calCountMax = INIT_LOG_COUNT, 59 .calCollect = ar5416AdcDcCalCollect, 60 .calPostProc = ar5416AdcDcCalibration 61}; 62 63static void ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 64static HAL_BOOL ar9280FillCapabilityInfo(struct ath_hal *ah); 65static void ar9280WriteIni(struct ath_hal *ah, 66 const struct ieee80211_channel *chan); 67static void ar9280SpurMitigate(struct ath_hal *ah, 68 const struct ieee80211_channel *chan); 69 70static void 71ar9280AniSetup(struct ath_hal *ah) 72{ 73 /* NB: disable ANI for reliable RIFS rx */ 74 ar5212AniAttach(ah, AH_NULL, AH_NULL, AH_FALSE); 75} 76 77/* 78 * Attach for an AR9280 part. 79 */ 80static struct ath_hal * 81ar9280Attach(uint16_t devid, HAL_SOFTC sc, 82 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 83{ 84 struct ath_hal_9280 *ahp9280; 85 struct ath_hal_5212 *ahp; 86 struct ath_hal *ah; 87 uint32_t val; 88 HAL_STATUS ecode; 89 HAL_BOOL rfStatus; 90 91 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 92 __func__, sc, (void*) st, (void*) sh); 93 94 /* NB: memory is returned zero'd */ 95 ahp9280 = ath_hal_malloc(sizeof (struct ath_hal_9280)); 96 if (ahp9280 == AH_NULL) { 97 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 98 "%s: cannot allocate memory for state block\n", __func__); 99 *status = HAL_ENOMEM; 100 return AH_NULL; 101 } 102 ahp = AH5212(ahp9280); 103 ah = &ahp->ah_priv.h; 104 105 ar5416InitState(AH5416(ah), devid, sc, st, sh, status); 106 107 /* XXX override with 9280 specific state */ 108 /* override 5416 methods for our needs */ 109 ah->ah_setAntennaSwitch = ar9280SetAntennaSwitch; 110 ah->ah_configPCIE = ar9280ConfigPCIE; 111 112 AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal; 113 AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal; 114 AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal; 115 AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal; 116 AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; 117 118 AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate; 119 AH5416(ah)->ah_writeIni = ar9280WriteIni; 120 AH5416(ah)->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK; 121 AH5416(ah)->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK; 122 123 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 124 /* reset chip */ 125 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", 126 __func__); 127 ecode = HAL_EIO; 128 goto bad; 129 } 130 131 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 132 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 133 __func__); 134 ecode = HAL_EIO; 135 goto bad; 136 } 137 /* Read Revisions from Chips before taking out of reset */ 138 val = OS_REG_READ(ah, AR_SREV); 139 HALDEBUG(ah, HAL_DEBUG_ATTACH, 140 "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n", 141 __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION), 142 MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION)); 143 /* NB: include chip type to differentiate from pre-Sowl versions */ 144 AH_PRIVATE(ah)->ah_macVersion = 145 (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S; 146 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION); 147 AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0; 148 149 /* setup common ini data; rf backends handle remainder */ 150 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 151 HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v2, 6); 152 HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v2, 2); 153 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 154 ar9280PciePhy_clkreq_always_on_L1_v2, 2); 155 HAL_INI_INIT(&ahp9280->ah_ini_xmodes, 156 ar9280Modes_fast_clock_v2, 3); 157 } else { 158 HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v1, 6); 159 HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v1, 2); 160 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 161 ar9280PciePhy_v1, 2); 162 } 163 ar5416AttachPCIE(ah); 164 165 ecode = ath_hal_v14EepromAttach(ah); 166 if (ecode != HAL_OK) 167 goto bad; 168 169 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 170 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 171 ecode = HAL_EIO; 172 goto bad; 173 } 174 175 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 176 177 if (!ar5212ChipTest(ah)) { 178 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 179 __func__); 180 ecode = HAL_ESELFTEST; 181 goto bad; 182 } 183 184 /* 185 * Set correct Baseband to analog shift 186 * setting to access analog chips. 187 */ 188 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 189 190 /* Read Radio Chip Rev Extract */ 191 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah); 192 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 193 case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */ 194 case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */ 195 break; 196 default: 197 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 198 AH_PRIVATE(ah)->ah_analog5GhzRev = 199 AR_RAD5133_SREV_MAJOR; 200 break; 201 } 202#ifdef AH_DEBUG 203 HALDEBUG(ah, HAL_DEBUG_ANY, 204 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 205 "this driver\n", __func__, 206 AH_PRIVATE(ah)->ah_analog5GhzRev); 207 ecode = HAL_ENOTSUPP; 208 goto bad; 209#endif 210 } 211 rfStatus = ar9280RfAttach(ah, &ecode); 212 if (!rfStatus) { 213 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 214 __func__, ecode); 215 goto bad; 216 } 217 218 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 219 /* setup rxgain table */ 220 switch (ath_hal_eepromGet(ah, AR_EEP_RXGAIN_TYPE, AH_NULL)) { 221 case AR5416_EEP_RXGAIN_13dB_BACKOFF: 222 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 223 ar9280Modes_backoff_13db_rxgain_v2, 6); 224 break; 225 case AR5416_EEP_RXGAIN_23dB_BACKOFF: 226 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 227 ar9280Modes_backoff_23db_rxgain_v2, 6); 228 break; 229 case AR5416_EEP_RXGAIN_ORIG: 230 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 231 ar9280Modes_original_rxgain_v2, 6); 232 break; 233 default: 234 HALASSERT(AH_FALSE); 235 goto bad; /* XXX ? try to continue */ 236 } 237 } 238 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 239 /* setp txgain table */ 240 switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) { 241 case AR5416_EEP_TXGAIN_HIGH_POWER: 242 HAL_INI_INIT(&ahp9280->ah_ini_txgain, 243 ar9280Modes_high_power_tx_gain_v2, 6); 244 break; 245 case AR5416_EEP_TXGAIN_ORIG: 246 HAL_INI_INIT(&ahp9280->ah_ini_txgain, 247 ar9280Modes_original_tx_gain_v2, 6); 248 break; 249 default: 250 HALASSERT(AH_FALSE); 251 goto bad; /* XXX ? try to continue */ 252 } 253 } 254 255 /* 256 * Got everything we need now to setup the capabilities. 257 */ 258 if (!ar9280FillCapabilityInfo(ah)) { 259 ecode = HAL_EEREAD; 260 goto bad; 261 } 262 263 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 264 if (ecode != HAL_OK) { 265 HALDEBUG(ah, HAL_DEBUG_ANY, 266 "%s: error getting mac address from EEPROM\n", __func__); 267 goto bad; 268 } 269 /* XXX How about the serial number ? */ 270 /* Read Reg Domain */ 271 AH_PRIVATE(ah)->ah_currentRD = 272 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 273 274 /* 275 * ah_miscMode is populated by ar5416FillCapabilityInfo() 276 * starting from griffin. Set here to make sure that 277 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 278 * placed into hardware. 279 */ 280 if (ahp->ah_miscMode != 0) 281 OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode); 282 283 ar9280AniSetup(ah); /* Anti Noise Immunity */ 284 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 285 286 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 287 288 return ah; 289bad: 290 if (ah != AH_NULL) 291 ah->ah_detach(ah); 292 if (status) 293 *status = ecode; 294 return AH_NULL; 295} 296 297static void 298ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 299{ 300 if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 301 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 302 OS_DELAY(1000); 303 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 304 OS_REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT); 305 } 306} 307 308static void 309ar9280WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 310{ 311 u_int modesIndex, freqIndex; 312 int regWrites = 0; 313 314 /* Setup the indices for the next set of register array writes */ 315 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 316 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 317 freqIndex = 2; 318 if (IEEE80211_IS_CHAN_HT40(chan)) 319 modesIndex = 3; 320 else if (IEEE80211_IS_CHAN_108G(chan)) 321 modesIndex = 5; 322 else 323 modesIndex = 4; 324 } else { 325 freqIndex = 1; 326 if (IEEE80211_IS_CHAN_HT40(chan) || 327 IEEE80211_IS_CHAN_TURBO(chan)) 328 modesIndex = 2; 329 else 330 modesIndex = 1; 331 } 332 333 /* Set correct Baseband to analog shift setting to access analog chips. */ 334 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 335 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 336 337 /* XXX Merlin ini fixups */ 338 /* XXX Merlin 100us delay for shift registers */ 339 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 340 modesIndex, regWrites); 341 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 342 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_rxgain, 343 modesIndex, regWrites); 344 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain, 345 modesIndex, regWrites); 346 } 347 /* XXX Merlin 100us delay for shift registers */ 348 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 349 1, regWrites); 350 351 if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { 352 /* 5GHz channels w/ Fast Clock use different modal values */ 353 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_xmodes, 354 modesIndex, regWrites); 355 } 356} 357 358#define AR_BASE_FREQ_2GHZ 2300 359#define AR_BASE_FREQ_5GHZ 4900 360#define AR_SPUR_FEEQ_BOUND_HT40 19 361#define AR_SPUR_FEEQ_BOUND_HT20 10 362 363static void 364ar9280SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 365{ 366 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 367 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 368 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 369 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 370 static int inc[4] = { 0, 100, 0, 0 }; 371 372 int bb_spur = AR_NO_SPUR; 373 int freq; 374 int bin, cur_bin; 375 int bb_spur_off, spur_subchannel_sd; 376 int spur_freq_sd; 377 int spur_delta_phase; 378 int denominator; 379 int upper, lower, cur_vit_mask; 380 int tmp, newVal; 381 int i; 382 CHAN_CENTERS centers; 383 384 int8_t mask_m[123]; 385 int8_t mask_p[123]; 386 int8_t mask_amt; 387 int tmp_mask; 388 int cur_bb_spur; 389 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 390 391 OS_MEMZERO(&mask_m, sizeof(int8_t) * 123); 392 OS_MEMZERO(&mask_p, sizeof(int8_t) * 123); 393 394 ar5416GetChannelCenters(ah, chan, ¢ers); 395 freq = centers.synth_center; 396 397 /* 398 * Need to verify range +/- 9.38 for static ht20 and +/- 18.75 for ht40, 399 * otherwise spur is out-of-band and can be ignored. 400 */ 401 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 402 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 403 /* Get actual spur freq in MHz from EEPROM read value */ 404 if (is2GHz) { 405 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ; 406 } else { 407 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ; 408 } 409 410 if (AR_NO_SPUR == cur_bb_spur) 411 break; 412 cur_bb_spur = cur_bb_spur - freq; 413 414 if (IEEE80211_IS_CHAN_HT40(chan)) { 415 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) && 416 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) { 417 bb_spur = cur_bb_spur; 418 break; 419 } 420 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) && 421 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) { 422 bb_spur = cur_bb_spur; 423 break; 424 } 425 } 426 427 if (AR_NO_SPUR == bb_spur) { 428#if 1 429 /* 430 * MRC CCK can interfere with beacon detection and cause deaf/mute. 431 * Disable MRC CCK for now. 432 */ 433 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 434#else 435 /* Enable MRC CCK if no spur is found in this channel. */ 436 OS_REG_SET_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 437#endif 438 return; 439 } else { 440 /* 441 * For Merlin, spur can break CCK MRC algorithm. Disable CCK MRC if spur 442 * is found in this channel. 443 */ 444 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 445 } 446 447 bin = bb_spur * 320; 448 449 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 450 451 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 452 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 453 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 454 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 455 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), newVal); 456 457 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 458 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 459 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 460 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 461 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 462 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); 463 464 /* Pick control or extn channel to cancel the spur */ 465 if (IEEE80211_IS_CHAN_HT40(chan)) { 466 if (bb_spur < 0) { 467 spur_subchannel_sd = 1; 468 bb_spur_off = bb_spur + 10; 469 } else { 470 spur_subchannel_sd = 0; 471 bb_spur_off = bb_spur - 10; 472 } 473 } else { 474 spur_subchannel_sd = 0; 475 bb_spur_off = bb_spur; 476 } 477 478 /* 479 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 480 * /80 for dyn2040. 481 */ 482 if (IEEE80211_IS_CHAN_HT40(chan)) 483 spur_delta_phase = ((bb_spur * 262144) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 484 else 485 spur_delta_phase = ((bb_spur * 524288) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 486 487 /* 488 * in 11A mode the denominator of spur_freq_sd should be 40 and 489 * it should be 44 in 11G 490 */ 491 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 44 : 40; 492 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff; 493 494 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 495 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 496 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 497 OS_REG_WRITE(ah, AR_PHY_TIMING11, newVal); 498 499 /* Choose to cancel between control and extension channels */ 500 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S; 501 OS_REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); 502 503 /* 504 * ============================================ 505 * Set Pilot and Channel Masks 506 * 507 * pilot mask 1 [31:0] = +6..-26, no 0 bin 508 * pilot mask 2 [19:0] = +26..+7 509 * 510 * channel mask 1 [31:0] = +6..-26, no 0 bin 511 * channel mask 2 [19:0] = +26..+7 512 */ 513 cur_bin = -6000; 514 upper = bin + 100; 515 lower = bin - 100; 516 517 for (i = 0; i < 4; i++) { 518 int pilot_mask = 0; 519 int chan_mask = 0; 520 int bp = 0; 521 for (bp = 0; bp < 30; bp++) { 522 if ((cur_bin > lower) && (cur_bin < upper)) { 523 pilot_mask = pilot_mask | 0x1 << bp; 524 chan_mask = chan_mask | 0x1 << bp; 525 } 526 cur_bin += 100; 527 } 528 cur_bin += inc[i]; 529 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 530 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 531 } 532 533 /* ================================================= 534 * viterbi mask 1 based on channel magnitude 535 * four levels 0-3 536 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 537 * [1 2 2 1] for -9.6 or [1 2 1] for +16 538 * - enable_mask_ppm, all bins move with freq 539 * 540 * - mask_select, 8 bits for rates (reg 67,0x990c) 541 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 542 * choose which mask to use mask or mask2 543 */ 544 545 /* 546 * viterbi mask 2 2nd set for per data rate puncturing 547 * four levels 0-3 548 * - mask_select, 8 bits for rates (reg 67) 549 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 550 * [1 2 2 1] for -9.6 or [1 2 1] for +16 551 */ 552 cur_vit_mask = 6100; 553 upper = bin + 120; 554 lower = bin - 120; 555 556 for (i = 0; i < 123; i++) { 557 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 558 if ((abs(cur_vit_mask - bin)) < 75) { 559 mask_amt = 1; 560 } else { 561 mask_amt = 0; 562 } 563 if (cur_vit_mask < 0) { 564 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 565 } else { 566 mask_p[cur_vit_mask / 100] = mask_amt; 567 } 568 } 569 cur_vit_mask -= 100; 570 } 571 572 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 573 | (mask_m[48] << 26) | (mask_m[49] << 24) 574 | (mask_m[50] << 22) | (mask_m[51] << 20) 575 | (mask_m[52] << 18) | (mask_m[53] << 16) 576 | (mask_m[54] << 14) | (mask_m[55] << 12) 577 | (mask_m[56] << 10) | (mask_m[57] << 8) 578 | (mask_m[58] << 6) | (mask_m[59] << 4) 579 | (mask_m[60] << 2) | (mask_m[61] << 0); 580 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 581 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 582 583 tmp_mask = (mask_m[31] << 28) 584 | (mask_m[32] << 26) | (mask_m[33] << 24) 585 | (mask_m[34] << 22) | (mask_m[35] << 20) 586 | (mask_m[36] << 18) | (mask_m[37] << 16) 587 | (mask_m[48] << 14) | (mask_m[39] << 12) 588 | (mask_m[40] << 10) | (mask_m[41] << 8) 589 | (mask_m[42] << 6) | (mask_m[43] << 4) 590 | (mask_m[44] << 2) | (mask_m[45] << 0); 591 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 592 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 593 594 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 595 | (mask_m[18] << 26) | (mask_m[18] << 24) 596 | (mask_m[20] << 22) | (mask_m[20] << 20) 597 | (mask_m[22] << 18) | (mask_m[22] << 16) 598 | (mask_m[24] << 14) | (mask_m[24] << 12) 599 | (mask_m[25] << 10) | (mask_m[26] << 8) 600 | (mask_m[27] << 6) | (mask_m[28] << 4) 601 | (mask_m[29] << 2) | (mask_m[30] << 0); 602 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 603 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 604 605 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 606 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 607 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 608 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 609 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 610 | (mask_m[10] << 10) | (mask_m[11] << 8) 611 | (mask_m[12] << 6) | (mask_m[13] << 4) 612 | (mask_m[14] << 2) | (mask_m[15] << 0); 613 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 614 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 615 616 tmp_mask = (mask_p[15] << 28) 617 | (mask_p[14] << 26) | (mask_p[13] << 24) 618 | (mask_p[12] << 22) | (mask_p[11] << 20) 619 | (mask_p[10] << 18) | (mask_p[ 9] << 16) 620 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 621 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 622 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 623 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 624 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 625 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 626 627 tmp_mask = (mask_p[30] << 28) 628 | (mask_p[29] << 26) | (mask_p[28] << 24) 629 | (mask_p[27] << 22) | (mask_p[26] << 20) 630 | (mask_p[25] << 18) | (mask_p[24] << 16) 631 | (mask_p[23] << 14) | (mask_p[22] << 12) 632 | (mask_p[21] << 10) | (mask_p[20] << 8) 633 | (mask_p[19] << 6) | (mask_p[18] << 4) 634 | (mask_p[17] << 2) | (mask_p[16] << 0); 635 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 636 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 637 638 tmp_mask = (mask_p[45] << 28) 639 | (mask_p[44] << 26) | (mask_p[43] << 24) 640 | (mask_p[42] << 22) | (mask_p[41] << 20) 641 | (mask_p[40] << 18) | (mask_p[39] << 16) 642 | (mask_p[38] << 14) | (mask_p[37] << 12) 643 | (mask_p[36] << 10) | (mask_p[35] << 8) 644 | (mask_p[34] << 6) | (mask_p[33] << 4) 645 | (mask_p[32] << 2) | (mask_p[31] << 0); 646 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 647 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 648 649 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 650 | (mask_p[59] << 26) | (mask_p[58] << 24) 651 | (mask_p[57] << 22) | (mask_p[56] << 20) 652 | (mask_p[55] << 18) | (mask_p[54] << 16) 653 | (mask_p[53] << 14) | (mask_p[52] << 12) 654 | (mask_p[51] << 10) | (mask_p[50] << 8) 655 | (mask_p[49] << 6) | (mask_p[48] << 4) 656 | (mask_p[47] << 2) | (mask_p[46] << 0); 657 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 658 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 659} 660 661/* 662 * Fill all software cached or static hardware state information. 663 * Return failure if capabilities are to come from EEPROM and 664 * cannot be read. 665 */ 666static HAL_BOOL 667ar9280FillCapabilityInfo(struct ath_hal *ah) 668{ 669 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 670 671 if (!ar5416FillCapabilityInfo(ah)) 672 return AH_FALSE; 673 pCap->halNumGpioPins = 10; 674 pCap->halWowSupport = AH_TRUE; 675 pCap->halWowMatchPatternExact = AH_TRUE; 676#if 0 677 pCap->halWowMatchPatternDword = AH_TRUE; 678#endif 679 pCap->halCSTSupport = AH_TRUE; 680 pCap->halRifsRxSupport = AH_TRUE; 681 pCap->halRifsTxSupport = AH_TRUE; 682 pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */ 683 pCap->halExtChanDfsSupport = AH_TRUE; 684#if 0 685 /* XXX bluetooth */ 686 pCap->halBtCoexSupport = AH_TRUE; 687#endif 688 pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */ 689#if 0 690 pCap->hal4kbSplitTransSupport = AH_FALSE; 691#endif 692 pCap->halRxStbcSupport = 1; 693 pCap->halTxStbcSupport = 1; 694 695 return AH_TRUE; 696} 697 698HAL_BOOL 699ar9280SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings) 700{ 701#define ANTENNA0_CHAINMASK 0x1 702#define ANTENNA1_CHAINMASK 0x2 703 struct ath_hal_5416 *ahp = AH5416(ah); 704 705 /* Antenna selection is done by setting the tx/rx chainmasks approp. */ 706 switch (settings) { 707 case HAL_ANT_FIXED_A: 708 /* Enable first antenna only */ 709 ahp->ah_tx_chainmask = ANTENNA0_CHAINMASK; 710 ahp->ah_rx_chainmask = ANTENNA0_CHAINMASK; 711 break; 712 case HAL_ANT_FIXED_B: 713 /* Enable second antenna only, after checking capability */ 714 if (AH_PRIVATE(ah)->ah_caps.halTxChainMask > ANTENNA1_CHAINMASK) 715 ahp->ah_tx_chainmask = ANTENNA1_CHAINMASK; 716 ahp->ah_rx_chainmask = ANTENNA1_CHAINMASK; 717 break; 718 case HAL_ANT_VARIABLE: 719 /* Restore original chainmask settings */ 720 /* XXX */ 721 ahp->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK; 722 ahp->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK; 723 break; 724 } 725 return AH_TRUE; 726#undef ANTENNA0_CHAINMASK 727#undef ANTENNA1_CHAINMASK 728} 729 730static const char* 731ar9280Probe(uint16_t vendorid, uint16_t devid) 732{ 733 if (vendorid == ATHEROS_VENDOR_ID && 734 (devid == AR9280_DEVID_PCI || devid == AR9280_DEVID_PCIE)) 735 return "Atheros 9280"; 736 return AH_NULL; 737} 738AH_CHIP(AR9280, ar9280Probe, ar9280Attach); 739