ar9280_attach.c revision 203682
1/* 2 * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting 3 * Copyright (c) 2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar9280_attach.c 203682 2010-02-08 20:12:01Z rpaulo $ 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23#include "ah_devid.h" 24 25#include "ah_eeprom_v14.h" /* XXX for tx/rx gain */ 26#include "ah_eeprom_v4k.h" 27 28#include "ar5416/ar9280.h" 29#include "ar5416/ar5416reg.h" 30#include "ar5416/ar5416phy.h" 31 32#include "ar5416/ar9280v1.ini" 33#include "ar5416/ar9280v2.ini" 34#include "ar5416/ar9285.ini" 35#include "ar5416/ar9285v2.ini" 36 37 38static const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */ 39 .calName = "IQ", .calType = IQ_MISMATCH_CAL, 40 .calNumSamples = MIN_CAL_SAMPLES, 41 .calCountMax = PER_MAX_LOG_COUNT, 42 .calCollect = ar5416IQCalCollect, 43 .calPostProc = ar5416IQCalibration 44}; 45static const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */ 46 .calName = "ADC Gain", .calType = ADC_GAIN_CAL, 47 .calNumSamples = MIN_CAL_SAMPLES, 48 .calCountMax = PER_MIN_LOG_COUNT, 49 .calCollect = ar5416AdcGainCalCollect, 50 .calPostProc = ar5416AdcGainCalibration 51}; 52static const HAL_PERCAL_DATA ar9280_adc_dc_cal = { /* single sample */ 53 .calName = "ADC DC", .calType = ADC_DC_CAL, 54 .calNumSamples = MIN_CAL_SAMPLES, 55 .calCountMax = PER_MIN_LOG_COUNT, 56 .calCollect = ar5416AdcDcCalCollect, 57 .calPostProc = ar5416AdcDcCalibration 58}; 59static const HAL_PERCAL_DATA ar9280_adc_init_dc_cal = { 60 .calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL, 61 .calNumSamples = MIN_CAL_SAMPLES, 62 .calCountMax = INIT_LOG_COUNT, 63 .calCollect = ar5416AdcDcCalCollect, 64 .calPostProc = ar5416AdcDcCalibration 65}; 66 67static void ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 68static HAL_BOOL ar9280FillCapabilityInfo(struct ath_hal *ah); 69static void ar9280WriteIni(struct ath_hal *ah, 70 const struct ieee80211_channel *chan); 71static void ar9280SpurMitigate(struct ath_hal *ah, 72 const struct ieee80211_channel *chan); 73 74static void 75ar9280AniSetup(struct ath_hal *ah) 76{ 77 /* NB: disable ANI for reliable RIFS rx */ 78 ar5212AniAttach(ah, AH_NULL, AH_NULL, AH_FALSE); 79} 80 81/* 82 * Attach for an AR9280 part. 83 */ 84static struct ath_hal * 85ar9280Attach(uint16_t devid, HAL_SOFTC sc, 86 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 87{ 88 struct ath_hal_9280 *ahp9280; 89 struct ath_hal_5212 *ahp; 90 struct ath_hal *ah; 91 uint32_t val; 92 HAL_STATUS ecode; 93 HAL_BOOL rfStatus; 94 95 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 96 __func__, sc, (void*) st, (void*) sh); 97 98 /* NB: memory is returned zero'd */ 99 ahp9280 = ath_hal_malloc(sizeof (struct ath_hal_9280)); 100 if (ahp9280 == AH_NULL) { 101 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 102 "%s: cannot allocate memory for state block\n", __func__); 103 *status = HAL_ENOMEM; 104 return AH_NULL; 105 } 106 ahp = AH5212(ahp9280); 107 ah = &ahp->ah_priv.h; 108 109 ar5416InitState(AH5416(ah), devid, sc, st, sh, status); 110 111 /* XXX override with 9280 specific state */ 112 /* override 5416 methods for our needs */ 113 ah->ah_setAntennaSwitch = ar9280SetAntennaSwitch; 114 ah->ah_configPCIE = ar9280ConfigPCIE; 115 116 AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal; 117 AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal; 118 AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal; 119 AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal; 120 AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; 121 122 AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate; 123 AH5416(ah)->ah_writeIni = ar9280WriteIni; 124 AH5416(ah)->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK; 125 AH5416(ah)->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK; 126 if (AR_SREV_KITE(ah)) { 127 AH5416(ah)->ah_rx_chainmask = AR9285_DEFAULT_RXCHAINMASK; 128 AH5416(ah)->ah_tx_chainmask = AR9285_DEFAULT_TXCHAINMASK; 129 } 130 131 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 132 /* reset chip */ 133 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", 134 __func__); 135 ecode = HAL_EIO; 136 goto bad; 137 } 138 139 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 140 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 141 __func__); 142 ecode = HAL_EIO; 143 goto bad; 144 } 145 /* Read Revisions from Chips before taking out of reset */ 146 val = OS_REG_READ(ah, AR_SREV); 147 HALDEBUG(ah, HAL_DEBUG_ATTACH, 148 "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n", 149 __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION), 150 MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION)); 151 /* NB: include chip type to differentiate from pre-Sowl versions */ 152 AH_PRIVATE(ah)->ah_macVersion = 153 (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S; 154 AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION); 155 AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0; 156 157 /* setup common ini data; rf backends handle remainder */ 158 /* XXX power consumption higer if clkreq is on */ 159 if (AR_SREV_KITE_12_OR_LATER(ah)) { 160 HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes_v2, 6); 161 HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common_v2, 2); 162 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 163 ar9285PciePhy_clkreq_always_on_L1_v2, 2); 164 } else if (AR_SREV_KITE_10_OR_LATER(ah)) { 165 HAL_INI_INIT(&ahp->ah_ini_modes, ar9285Modes, 6); 166 HAL_INI_INIT(&ahp->ah_ini_common, ar9285Common, 2); 167 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 168 ar9285PciePhy_clkreq_always_on_L1, 2); 169 } else if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 170 HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v2, 6); 171 HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v2, 2); 172 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 173 ar9280PciePhy_clkreq_always_on_L1_v2, 2); 174 HAL_INI_INIT(&ahp9280->ah_ini_xmodes, 175 ar9280Modes_fast_clock_v2, 3); 176 } else { 177 HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v1, 6); 178 HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v1, 2); 179 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 180 ar9280PciePhy_v1, 2); 181 } 182 ar5416AttachPCIE(ah); 183 184 if (devid == AR9285_DEVID_PCIE) 185 ecode = ath_hal_v4kEepromAttach(ah); 186 else 187 ecode = ath_hal_v14EepromAttach(ah); 188 if (ecode != HAL_OK) 189 goto bad; 190 191 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 192 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 193 ecode = HAL_EIO; 194 goto bad; 195 } 196 197 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 198 199 if (!ar5212ChipTest(ah)) { 200 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 201 __func__); 202 ecode = HAL_ESELFTEST; 203 goto bad; 204 } 205 206 /* 207 * Set correct Baseband to analog shift 208 * setting to access analog chips. 209 */ 210 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 211 212 /* Read Radio Chip Rev Extract */ 213 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah); 214 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 215 case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */ 216 case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */ 217 break; 218 default: 219 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 220 AH_PRIVATE(ah)->ah_analog5GhzRev = 221 AR_RAD5133_SREV_MAJOR; 222 break; 223 } 224#ifdef AH_DEBUG 225 HALDEBUG(ah, HAL_DEBUG_ANY, 226 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 227 "this driver\n", __func__, 228 AH_PRIVATE(ah)->ah_analog5GhzRev); 229 ecode = HAL_ENOTSUPP; 230 goto bad; 231#endif 232 } 233 rfStatus = ar9280RfAttach(ah, &ecode); 234 if (!rfStatus) { 235 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 236 __func__, ecode); 237 goto bad; 238 } 239 240 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 241 /* setup rxgain table */ 242 switch (ath_hal_eepromGet(ah, AR_EEP_RXGAIN_TYPE, AH_NULL)) { 243 case AR5416_EEP_RXGAIN_13dB_BACKOFF: 244 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 245 ar9280Modes_backoff_13db_rxgain_v2, 6); 246 break; 247 case AR5416_EEP_RXGAIN_23dB_BACKOFF: 248 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 249 ar9280Modes_backoff_23db_rxgain_v2, 6); 250 break; 251 case AR5416_EEP_RXGAIN_ORIG: 252 HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 253 ar9280Modes_original_rxgain_v2, 6); 254 break; 255 default: 256 HALASSERT(AH_FALSE); 257 goto bad; /* XXX ? try to continue */ 258 } 259 } 260 261 if (AR_SREV_KITE_12_OR_LATER(ah)) { 262 switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) { 263 case AR5416_EEP_TXGAIN_HIGH_POWER: 264 HAL_INI_INIT(&ahp9280->ah_ini_txgain, 265 ar9285Modes_high_power_tx_gain_v2, 6); 266 break; 267 default: 268 HAL_INI_INIT(&ahp9280->ah_ini_txgain, 269 ar9285Modes_original_tx_gain_v2, 6); 270 break; 271 } 272 } else if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 273 /* setp txgain table */ 274 switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) { 275 case AR5416_EEP_TXGAIN_HIGH_POWER: 276 HAL_INI_INIT(&ahp9280->ah_ini_txgain, 277 ar9280Modes_high_power_tx_gain_v2, 6); 278 break; 279 case AR5416_EEP_TXGAIN_ORIG: 280 HAL_INI_INIT(&ahp9280->ah_ini_txgain, 281 ar9280Modes_original_tx_gain_v2, 6); 282 break; 283 default: 284 HALASSERT(AH_FALSE); 285 goto bad; /* XXX ? try to continue */ 286 } 287 } 288 289 /* 290 * Got everything we need now to setup the capabilities. 291 */ 292 if (!ar9280FillCapabilityInfo(ah)) { 293 ecode = HAL_EEREAD; 294 goto bad; 295 } 296 297 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 298 if (ecode != HAL_OK) { 299 HALDEBUG(ah, HAL_DEBUG_ANY, 300 "%s: error getting mac address from EEPROM\n", __func__); 301 goto bad; 302 } 303 /* XXX How about the serial number ? */ 304 /* Read Reg Domain */ 305 AH_PRIVATE(ah)->ah_currentRD = 306 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 307 308 /* 309 * ah_miscMode is populated by ar5416FillCapabilityInfo() 310 * starting from griffin. Set here to make sure that 311 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 312 * placed into hardware. 313 */ 314 if (ahp->ah_miscMode != 0) 315 OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode); 316 317 ar9280AniSetup(ah); /* Anti Noise Immunity */ 318 ar5416InitNfHistBuff(ah, AH5416(ah)->ah_cal.nfCalHist); 319 320 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 321 322 return ah; 323bad: 324 if (ah != AH_NULL) 325 ah->ah_detach(ah); 326 if (status) 327 *status = ecode; 328 return AH_NULL; 329} 330 331static void 332ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 333{ 334 if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 335 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 336 OS_DELAY(1000); 337 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 338 if (AR_SREV_KITE(ah)) 339 OS_REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT); 340 else 341 OS_REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT); 342 } 343} 344 345static void 346ar9280WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 347{ 348 u_int modesIndex, freqIndex; 349 int regWrites = 0; 350 351 /* Setup the indices for the next set of register array writes */ 352 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 353 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 354 freqIndex = 2; 355 if (IEEE80211_IS_CHAN_HT40(chan)) 356 modesIndex = 3; 357 else if (IEEE80211_IS_CHAN_108G(chan)) 358 modesIndex = 5; 359 else 360 modesIndex = 4; 361 } else { 362 freqIndex = 1; 363 if (IEEE80211_IS_CHAN_HT40(chan) || 364 IEEE80211_IS_CHAN_TURBO(chan)) 365 modesIndex = 2; 366 else 367 modesIndex = 1; 368 } 369 370 /* Set correct Baseband to analog shift setting to access analog chips. */ 371 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 372 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 373 374 /* XXX Merlin ini fixups */ 375 /* XXX Merlin 100us delay for shift registers */ 376 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 377 modesIndex, regWrites); 378 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 379 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_rxgain, 380 modesIndex, regWrites); 381 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain, 382 modesIndex, regWrites); 383 } 384 if (AR_SREV_KITE_12_OR_LATER(ah)) 385 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain, 386 modesIndex, regWrites); 387 388 /* XXX Merlin 100us delay for shift registers */ 389 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 390 1, regWrites); 391 392 if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { 393 /* 5GHz channels w/ Fast Clock use different modal values */ 394 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_xmodes, 395 modesIndex, regWrites); 396 } 397} 398 399#define AR_BASE_FREQ_2GHZ 2300 400#define AR_BASE_FREQ_5GHZ 4900 401#define AR_SPUR_FEEQ_BOUND_HT40 19 402#define AR_SPUR_FEEQ_BOUND_HT20 10 403 404static void 405ar9280SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 406{ 407 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 408 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 409 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 410 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 411 static int inc[4] = { 0, 100, 0, 0 }; 412 413 int bb_spur = AR_NO_SPUR; 414 int freq; 415 int bin, cur_bin; 416 int bb_spur_off, spur_subchannel_sd; 417 int spur_freq_sd; 418 int spur_delta_phase; 419 int denominator; 420 int upper, lower, cur_vit_mask; 421 int tmp, newVal; 422 int i; 423 CHAN_CENTERS centers; 424 425 int8_t mask_m[123]; 426 int8_t mask_p[123]; 427 int8_t mask_amt; 428 int tmp_mask; 429 int cur_bb_spur; 430 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 431 432 OS_MEMZERO(&mask_m, sizeof(int8_t) * 123); 433 OS_MEMZERO(&mask_p, sizeof(int8_t) * 123); 434 435 ar5416GetChannelCenters(ah, chan, ¢ers); 436 freq = centers.synth_center; 437 438 /* 439 * Need to verify range +/- 9.38 for static ht20 and +/- 18.75 for ht40, 440 * otherwise spur is out-of-band and can be ignored. 441 */ 442 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 443 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 444 /* Get actual spur freq in MHz from EEPROM read value */ 445 if (is2GHz) { 446 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ; 447 } else { 448 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ; 449 } 450 451 if (AR_NO_SPUR == cur_bb_spur) 452 break; 453 cur_bb_spur = cur_bb_spur - freq; 454 455 if (IEEE80211_IS_CHAN_HT40(chan)) { 456 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) && 457 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) { 458 bb_spur = cur_bb_spur; 459 break; 460 } 461 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) && 462 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) { 463 bb_spur = cur_bb_spur; 464 break; 465 } 466 } 467 468 if (AR_NO_SPUR == bb_spur) { 469#if 1 470 /* 471 * MRC CCK can interfere with beacon detection and cause deaf/mute. 472 * Disable MRC CCK for now. 473 */ 474 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 475#else 476 /* Enable MRC CCK if no spur is found in this channel. */ 477 OS_REG_SET_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 478#endif 479 return; 480 } else { 481 /* 482 * For Merlin, spur can break CCK MRC algorithm. Disable CCK MRC if spur 483 * is found in this channel. 484 */ 485 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 486 } 487 488 bin = bb_spur * 320; 489 490 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 491 492 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 493 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 494 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 495 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 496 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), newVal); 497 498 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 499 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 500 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 501 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 502 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 503 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); 504 505 /* Pick control or extn channel to cancel the spur */ 506 if (IEEE80211_IS_CHAN_HT40(chan)) { 507 if (bb_spur < 0) { 508 spur_subchannel_sd = 1; 509 bb_spur_off = bb_spur + 10; 510 } else { 511 spur_subchannel_sd = 0; 512 bb_spur_off = bb_spur - 10; 513 } 514 } else { 515 spur_subchannel_sd = 0; 516 bb_spur_off = bb_spur; 517 } 518 519 /* 520 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 521 * /80 for dyn2040. 522 */ 523 if (IEEE80211_IS_CHAN_HT40(chan)) 524 spur_delta_phase = ((bb_spur * 262144) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 525 else 526 spur_delta_phase = ((bb_spur * 524288) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 527 528 /* 529 * in 11A mode the denominator of spur_freq_sd should be 40 and 530 * it should be 44 in 11G 531 */ 532 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 44 : 40; 533 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff; 534 535 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 536 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 537 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 538 OS_REG_WRITE(ah, AR_PHY_TIMING11, newVal); 539 540 /* Choose to cancel between control and extension channels */ 541 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S; 542 OS_REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); 543 544 /* 545 * ============================================ 546 * Set Pilot and Channel Masks 547 * 548 * pilot mask 1 [31:0] = +6..-26, no 0 bin 549 * pilot mask 2 [19:0] = +26..+7 550 * 551 * channel mask 1 [31:0] = +6..-26, no 0 bin 552 * channel mask 2 [19:0] = +26..+7 553 */ 554 cur_bin = -6000; 555 upper = bin + 100; 556 lower = bin - 100; 557 558 for (i = 0; i < 4; i++) { 559 int pilot_mask = 0; 560 int chan_mask = 0; 561 int bp = 0; 562 for (bp = 0; bp < 30; bp++) { 563 if ((cur_bin > lower) && (cur_bin < upper)) { 564 pilot_mask = pilot_mask | 0x1 << bp; 565 chan_mask = chan_mask | 0x1 << bp; 566 } 567 cur_bin += 100; 568 } 569 cur_bin += inc[i]; 570 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 571 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 572 } 573 574 /* ================================================= 575 * viterbi mask 1 based on channel magnitude 576 * four levels 0-3 577 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 578 * [1 2 2 1] for -9.6 or [1 2 1] for +16 579 * - enable_mask_ppm, all bins move with freq 580 * 581 * - mask_select, 8 bits for rates (reg 67,0x990c) 582 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 583 * choose which mask to use mask or mask2 584 */ 585 586 /* 587 * viterbi mask 2 2nd set for per data rate puncturing 588 * four levels 0-3 589 * - mask_select, 8 bits for rates (reg 67) 590 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 591 * [1 2 2 1] for -9.6 or [1 2 1] for +16 592 */ 593 cur_vit_mask = 6100; 594 upper = bin + 120; 595 lower = bin - 120; 596 597 for (i = 0; i < 123; i++) { 598 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 599 if ((abs(cur_vit_mask - bin)) < 75) { 600 mask_amt = 1; 601 } else { 602 mask_amt = 0; 603 } 604 if (cur_vit_mask < 0) { 605 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 606 } else { 607 mask_p[cur_vit_mask / 100] = mask_amt; 608 } 609 } 610 cur_vit_mask -= 100; 611 } 612 613 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 614 | (mask_m[48] << 26) | (mask_m[49] << 24) 615 | (mask_m[50] << 22) | (mask_m[51] << 20) 616 | (mask_m[52] << 18) | (mask_m[53] << 16) 617 | (mask_m[54] << 14) | (mask_m[55] << 12) 618 | (mask_m[56] << 10) | (mask_m[57] << 8) 619 | (mask_m[58] << 6) | (mask_m[59] << 4) 620 | (mask_m[60] << 2) | (mask_m[61] << 0); 621 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 622 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 623 624 tmp_mask = (mask_m[31] << 28) 625 | (mask_m[32] << 26) | (mask_m[33] << 24) 626 | (mask_m[34] << 22) | (mask_m[35] << 20) 627 | (mask_m[36] << 18) | (mask_m[37] << 16) 628 | (mask_m[48] << 14) | (mask_m[39] << 12) 629 | (mask_m[40] << 10) | (mask_m[41] << 8) 630 | (mask_m[42] << 6) | (mask_m[43] << 4) 631 | (mask_m[44] << 2) | (mask_m[45] << 0); 632 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 633 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 634 635 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 636 | (mask_m[18] << 26) | (mask_m[18] << 24) 637 | (mask_m[20] << 22) | (mask_m[20] << 20) 638 | (mask_m[22] << 18) | (mask_m[22] << 16) 639 | (mask_m[24] << 14) | (mask_m[24] << 12) 640 | (mask_m[25] << 10) | (mask_m[26] << 8) 641 | (mask_m[27] << 6) | (mask_m[28] << 4) 642 | (mask_m[29] << 2) | (mask_m[30] << 0); 643 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 644 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 645 646 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 647 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 648 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 649 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 650 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 651 | (mask_m[10] << 10) | (mask_m[11] << 8) 652 | (mask_m[12] << 6) | (mask_m[13] << 4) 653 | (mask_m[14] << 2) | (mask_m[15] << 0); 654 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 655 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 656 657 tmp_mask = (mask_p[15] << 28) 658 | (mask_p[14] << 26) | (mask_p[13] << 24) 659 | (mask_p[12] << 22) | (mask_p[11] << 20) 660 | (mask_p[10] << 18) | (mask_p[ 9] << 16) 661 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 662 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 663 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 664 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 665 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 666 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 667 668 tmp_mask = (mask_p[30] << 28) 669 | (mask_p[29] << 26) | (mask_p[28] << 24) 670 | (mask_p[27] << 22) | (mask_p[26] << 20) 671 | (mask_p[25] << 18) | (mask_p[24] << 16) 672 | (mask_p[23] << 14) | (mask_p[22] << 12) 673 | (mask_p[21] << 10) | (mask_p[20] << 8) 674 | (mask_p[19] << 6) | (mask_p[18] << 4) 675 | (mask_p[17] << 2) | (mask_p[16] << 0); 676 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 677 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 678 679 tmp_mask = (mask_p[45] << 28) 680 | (mask_p[44] << 26) | (mask_p[43] << 24) 681 | (mask_p[42] << 22) | (mask_p[41] << 20) 682 | (mask_p[40] << 18) | (mask_p[39] << 16) 683 | (mask_p[38] << 14) | (mask_p[37] << 12) 684 | (mask_p[36] << 10) | (mask_p[35] << 8) 685 | (mask_p[34] << 6) | (mask_p[33] << 4) 686 | (mask_p[32] << 2) | (mask_p[31] << 0); 687 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 688 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 689 690 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 691 | (mask_p[59] << 26) | (mask_p[58] << 24) 692 | (mask_p[57] << 22) | (mask_p[56] << 20) 693 | (mask_p[55] << 18) | (mask_p[54] << 16) 694 | (mask_p[53] << 14) | (mask_p[52] << 12) 695 | (mask_p[51] << 10) | (mask_p[50] << 8) 696 | (mask_p[49] << 6) | (mask_p[48] << 4) 697 | (mask_p[47] << 2) | (mask_p[46] << 0); 698 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 699 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 700} 701 702/* 703 * Fill all software cached or static hardware state information. 704 * Return failure if capabilities are to come from EEPROM and 705 * cannot be read. 706 */ 707static HAL_BOOL 708ar9280FillCapabilityInfo(struct ath_hal *ah) 709{ 710 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 711 712 if (!ar5416FillCapabilityInfo(ah)) 713 return AH_FALSE; 714 if (AR_SREV_KITE_10_OR_LATER(ah)) 715 pCap->halNumGpioPins = 12; 716 else 717 pCap->halNumGpioPins = 10; 718 pCap->halWowSupport = AH_TRUE; 719 pCap->halWowMatchPatternExact = AH_TRUE; 720#if 0 721 pCap->halWowMatchPatternDword = AH_TRUE; 722#endif 723 pCap->halCSTSupport = AH_TRUE; 724 pCap->halRifsRxSupport = AH_TRUE; 725 pCap->halRifsTxSupport = AH_TRUE; 726 pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */ 727 pCap->halExtChanDfsSupport = AH_TRUE; 728#if 0 729 /* XXX bluetooth */ 730 pCap->halBtCoexSupport = AH_TRUE; 731#endif 732 pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */ 733#if 0 734 pCap->hal4kbSplitTransSupport = AH_FALSE; 735#endif 736 pCap->halRxStbcSupport = 1; 737 pCap->halTxStbcSupport = 1; 738 739 return AH_TRUE; 740} 741 742HAL_BOOL 743ar9280SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings) 744{ 745#define ANTENNA0_CHAINMASK 0x1 746#define ANTENNA1_CHAINMASK 0x2 747 struct ath_hal_5416 *ahp = AH5416(ah); 748 749 /* Antenna selection is done by setting the tx/rx chainmasks approp. */ 750 switch (settings) { 751 case HAL_ANT_FIXED_A: 752 /* Enable first antenna only */ 753 ahp->ah_tx_chainmask = ANTENNA0_CHAINMASK; 754 ahp->ah_rx_chainmask = ANTENNA0_CHAINMASK; 755 break; 756 case HAL_ANT_FIXED_B: 757 /* Enable second antenna only, after checking capability */ 758 if (AH_PRIVATE(ah)->ah_caps.halTxChainMask > ANTENNA1_CHAINMASK) 759 ahp->ah_tx_chainmask = ANTENNA1_CHAINMASK; 760 ahp->ah_rx_chainmask = ANTENNA1_CHAINMASK; 761 break; 762 case HAL_ANT_VARIABLE: 763 /* Restore original chainmask settings */ 764 /* XXX */ 765 ahp->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK; 766 ahp->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK; 767 break; 768 } 769 return AH_TRUE; 770#undef ANTENNA0_CHAINMASK 771#undef ANTENNA1_CHAINMASK 772} 773 774static const char* 775ar9280Probe(uint16_t vendorid, uint16_t devid) 776{ 777 if (vendorid == ATHEROS_VENDOR_ID) { 778 if (devid == AR9280_DEVID_PCI || devid == AR9280_DEVID_PCIE) 779 return "Atheros 9280"; 780 else if (devid == AR9285_DEVID_PCIE) 781 return "Atheros 9285"; 782 } 783 return AH_NULL; 784} 785AH_CHIP(AR9280, ar9280Probe, ar9280Attach); 786