ar9280_attach.c revision 240471
1132718Skan/* 2132718Skan * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting 3132718Skan * Copyright (c) 2008 Atheros Communications, Inc. 4132718Skan * 5132718Skan * Permission to use, copy, modify, and/or distribute this software for any 6132718Skan * purpose with or without fee is hereby granted, provided that the above 7132718Skan * copyright notice and this permission notice appear in all copies. 8132718Skan * 9132718Skan * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10132718Skan * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11132718Skan * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12132718Skan * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13132718Skan * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14132718Skan * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15132718Skan * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16132718Skan * 17132718Skan * $FreeBSD: head/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c 240471 2012-09-13 18:24:13Z adrian $ 18169689Skan */ 19132718Skan#include "opt_ah.h" 20132718Skan 21132718Skan#include "ah.h" 22132718Skan#include "ah_internal.h" 23132718Skan#include "ah_devid.h" 24132718Skan 25169689Skan#include "ah_eeprom_v14.h" /* XXX for tx/rx gain */ 26132718Skan 27132718Skan#include "ar9002/ar9280.h" 28132718Skan#include "ar5416/ar5416reg.h" 29132718Skan#include "ar5416/ar5416phy.h" 30132718Skan 31132718Skan#include "ar9002/ar9280v1.ini" 32132718Skan#include "ar9002/ar9280v2.ini" 33132718Skan#include "ar9002/ar9280_olc.h" 34132718Skan 35132718Skanstatic const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */ 36132718Skan .calName = "IQ", .calType = IQ_MISMATCH_CAL, 37169689Skan .calNumSamples = MIN_CAL_SAMPLES, 38132718Skan .calCountMax = PER_MAX_LOG_COUNT, 39169689Skan .calCollect = ar5416IQCalCollect, 40132718Skan .calPostProc = ar5416IQCalibration 41132718Skan}; 42132718Skanstatic const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */ 43132718Skan .calName = "ADC Gain", .calType = ADC_GAIN_CAL, 44259405Spfg .calNumSamples = MIN_CAL_SAMPLES, 45259405Spfg .calCountMax = PER_MAX_LOG_COUNT, 46132718Skan .calCollect = ar5416AdcGainCalCollect, 47132718Skan .calPostProc = ar5416AdcGainCalibration 48132718Skan}; 49132718Skanstatic const HAL_PERCAL_DATA ar9280_adc_dc_cal = { /* single sample */ 50169689Skan .calName = "ADC DC", .calType = ADC_DC_CAL, 51169689Skan .calNumSamples = MIN_CAL_SAMPLES, 52132718Skan .calCountMax = PER_MAX_LOG_COUNT, 53132718Skan .calCollect = ar5416AdcDcCalCollect, 54132718Skan .calPostProc = ar5416AdcDcCalibration 55132718Skan}; 56169689Skanstatic const HAL_PERCAL_DATA ar9280_adc_init_dc_cal = { 57169689Skan .calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL, 58169689Skan .calNumSamples = MIN_CAL_SAMPLES, 59169689Skan .calCountMax = INIT_LOG_COUNT, 60169689Skan .calCollect = ar5416AdcDcCalCollect, 61169689Skan .calPostProc = ar5416AdcDcCalibration 62169689Skan}; 63169689Skan 64132718Skanstatic void ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, 65132718Skan HAL_BOOL power_off); 66132718Skanstatic void ar9280DisablePCIE(struct ath_hal *ah); 67132718Skanstatic HAL_BOOL ar9280FillCapabilityInfo(struct ath_hal *ah); 68132718Skanstatic void ar9280WriteIni(struct ath_hal *ah, 69132718Skan const struct ieee80211_channel *chan); 70132718Skan 71132718Skanstatic void 72132718Skanar9280AniSetup(struct ath_hal *ah) 73132718Skan{ 74132718Skan /* 75132718Skan * These are the parameters from the AR5416 ANI code; 76132718Skan * they likely need quite a bit of adjustment for the 77132718Skan * AR9280. 78132718Skan */ 79132718Skan static const struct ar5212AniParams aniparams = { 80259405Spfg .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 81259405Spfg .totalSizeDesired = { -55, -55, -55, -55, -62 }, 82259405Spfg .coarseHigh = { -14, -14, -14, -14, -12 }, 83132718Skan .coarseLow = { -64, -64, -64, -64, -70 }, 84132718Skan .firpwr = { -78, -78, -78, -78, -80 }, 85132718Skan .maxSpurImmunityLevel = 2, 86132718Skan .cycPwrThr1 = { 2, 4, 6 }, 87132718Skan .maxFirstepLevel = 2, /* levels 0..2 */ 88132718Skan .firstep = { 0, 4, 8 }, 89132718Skan .ofdmTrigHigh = 500, 90132718Skan .ofdmTrigLow = 200, 91132718Skan .cckTrigHigh = 200, 92132718Skan .cckTrigLow = 100, 93132718Skan .rssiThrHigh = 40, 94132718Skan .rssiThrLow = 7, 95132718Skan .period = 100, 96132718Skan }; 97132718Skan /* NB: disable ANI noise immmunity for reliable RIFS rx */ 98132718Skan AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL); 99132718Skan 100132718Skan /* NB: ANI is not enabled yet */ 101132718Skan ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 102132718Skan} 103132718Skan 104132718Skanvoid 105132718Skanar9280InitPLL(struct ath_hal *ah, const struct ieee80211_channel *chan) 106132718Skan{ 107132718Skan uint32_t pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); 108132718Skan 109132718Skan if (AR_SREV_MERLIN_20(ah) && 110132718Skan chan != AH_NULL && IEEE80211_IS_CHAN_5GHZ(chan)) { 111132718Skan /* 112132718Skan * PLL WAR for Merlin 2.0/2.1 113132718Skan * When doing fast clock, set PLL to 0x142c 114132718Skan * Else, set PLL to 0x2850 to prevent reset-to-reset variation 115132718Skan */ 116169689Skan pll = IS_5GHZ_FAST_CLOCK_EN(ah, chan) ? 0x142c : 0x2850; 117169689Skan if (IEEE80211_IS_CHAN_HALF(chan)) 118169689Skan pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL); 119169689Skan else if (IEEE80211_IS_CHAN_QUARTER(chan)) 120169689Skan pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL); 121169689Skan } else if (AR_SREV_MERLIN_10_OR_LATER(ah)) { 122132718Skan pll = SM(0x5, AR_RTC_SOWL_PLL_REFDIV); 123132718Skan if (chan != AH_NULL) { 124132718Skan if (IEEE80211_IS_CHAN_HALF(chan)) 125132718Skan pll |= SM(0x1, AR_RTC_SOWL_PLL_CLKSEL); 126132718Skan else if (IEEE80211_IS_CHAN_QUARTER(chan)) 127132718Skan pll |= SM(0x2, AR_RTC_SOWL_PLL_CLKSEL); 128169689Skan if (IEEE80211_IS_CHAN_5GHZ(chan)) 129132718Skan pll |= SM(0x28, AR_RTC_SOWL_PLL_DIV); 130132718Skan else 131169689Skan pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV); 132132718Skan } else 133132718Skan pll |= SM(0x2c, AR_RTC_SOWL_PLL_DIV); 134132718Skan } 135169689Skan 136132718Skan OS_REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll); 137132718Skan OS_DELAY(RTC_PLL_SETTLE_DELAY); 138132718Skan OS_REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_SLEEP_DERIVED_CLK); 139132718Skan} 140132718Skan 141132718Skan/* XXX shouldn't be here! */ 142132718Skan#define EEP_MINOR(_ah) \ 143132718Skan (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK) 144132718Skan 145132718Skan/* 146132718Skan * Attach for an AR9280 part. 147132718Skan */ 148132718Skanstatic struct ath_hal * 149132718Skanar9280Attach(uint16_t devid, HAL_SOFTC sc, 150132718Skan HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 151132718Skan HAL_STATUS *status) 152132718Skan{ 153132718Skan struct ath_hal_9280 *ahp9280; 154132718Skan struct ath_hal_5212 *ahp; 155132718Skan struct ath_hal *ah; 156132718Skan uint32_t val; 157132718Skan HAL_STATUS ecode; 158132718Skan HAL_BOOL rfStatus; 159132718Skan int8_t pwr_table_offset; 160132718Skan uint8_t pwr; 161132718Skan 162132718Skan HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 163132718Skan __func__, sc, (void*) st, (void*) sh); 164132718Skan 165132718Skan /* NB: memory is returned zero'd */ 166132718Skan ahp9280 = ath_hal_malloc(sizeof (struct ath_hal_9280)); 167132718Skan if (ahp9280 == AH_NULL) { 168132718Skan HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 169132718Skan "%s: cannot allocate memory for state block\n", __func__); 170132718Skan *status = HAL_ENOMEM; 171132718Skan return AH_NULL; 172132718Skan } 173132718Skan ahp = AH5212(ahp9280); 174132718Skan ah = &ahp->ah_priv.h; 175132718Skan 176132718Skan ar5416InitState(AH5416(ah), devid, sc, st, sh, status); 177132718Skan 178132718Skan /* 179132718Skan * Use the "local" EEPROM data given to us by the higher layers. 180132718Skan * This is a private copy out of system flash. The Linux ath9k 181132718Skan * commit for the initial AR9130 support mentions MMIO flash 182132718Skan * access is "unreliable." -adrian 183132718Skan */ 184132718Skan if (eepromdata != AH_NULL) { 185132718Skan AH_PRIVATE((ah))->ah_eepromRead = ath_hal_EepromDataRead; 186132718Skan AH_PRIVATE((ah))->ah_eepromWrite = NULL; 187259405Spfg ah->ah_eepromdata = eepromdata; 188259405Spfg } 189259405Spfg 190259405Spfg /* XXX override with 9280 specific state */ 191259405Spfg /* override 5416 methods for our needs */ 192259405Spfg AH5416(ah)->ah_initPLL = ar9280InitPLL; 193259405Spfg 194259405Spfg ah->ah_setAntennaSwitch = ar9280SetAntennaSwitch; 195259405Spfg ah->ah_configPCIE = ar9280ConfigPCIE; 196259405Spfg ah->ah_disablePCIE = ar9280DisablePCIE; 197259405Spfg 198259405Spfg AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal; 199259405Spfg AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal; 200259405Spfg AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal; 201259405Spfg AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal; 202259405Spfg AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; 203259405Spfg 204259405Spfg AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate; 205259405Spfg AH5416(ah)->ah_writeIni = ar9280WriteIni; 206259405Spfg AH5416(ah)->ah_olcInit = ar9280olcInit; 207169689Skan AH5416(ah)->ah_olcTempCompensation = ar9280olcTemperatureCompensation; 208132718Skan AH5416(ah)->ah_setPowerCalTable = ar9280SetPowerCalTable; 209132718Skan 210132718Skan AH5416(ah)->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK; 211132718Skan AH5416(ah)->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK; 212132718Skan 213169689Skan if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 214132718Skan /* reset chip */ 215132718Skan HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", 216132718Skan __func__); 217132718Skan ecode = HAL_EIO; 218132718Skan goto bad; 219132718Skan } 220132718Skan 221132718Skan if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 222132718Skan HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 223169689Skan __func__); 224132718Skan ecode = HAL_EIO; 225132718Skan goto bad; 226132718Skan } 227132718Skan /* Read Revisions from Chips before taking out of reset */ 228132718Skan val = OS_REG_READ(ah, AR_SREV); 229132718Skan HALDEBUG(ah, HAL_DEBUG_ATTACH, 230132718Skan "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n", 231132718Skan __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION), 232132718Skan MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION)); 233132718Skan /* NB: include chip type to differentiate from pre-Sowl versions */ 234132718Skan AH_PRIVATE(ah)->ah_macVersion = 235169689Skan (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S; 236132718Skan AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION); 237169689Skan AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0; 238169689Skan 239132718Skan /* setup common ini data; rf backends handle remainder */ 240132718Skan if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 241132718Skan HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v2, 6); 242132718Skan HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v2, 2); 243169689Skan HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 244132718Skan ar9280PciePhy_clkreq_always_on_L1_v2, 2); 245132718Skan HAL_INI_INIT(&ahp9280->ah_ini_xmodes, 246132718Skan ar9280Modes_fast_clock_v2, 3); 247169689Skan } else { 248132718Skan HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v1, 6); 249169689Skan HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v1, 2); 250132718Skan HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 251132718Skan ar9280PciePhy_v1, 2); 252169689Skan } 253132718Skan ar5416AttachPCIE(ah); 254132718Skan 255132718Skan ecode = ath_hal_v14EepromAttach(ah); 256169689Skan if (ecode != HAL_OK) 257132718Skan goto bad; 258132718Skan 259132718Skan if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 260132718Skan HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 261132718Skan ecode = HAL_EIO; 262169689Skan goto bad; 263132718Skan } 264132718Skan 265132718Skan AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 266132718Skan 267132718Skan if (!ar5212ChipTest(ah)) { 268132718Skan HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 269132718Skan __func__); 270132718Skan ecode = HAL_ESELFTEST; 271169689Skan goto bad; 272169689Skan } 273132718Skan 274169689Skan /* 275169689Skan * Set correct Baseband to analog shift 276132718Skan * setting to access analog chips. 277132718Skan */ 278169689Skan OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 279169689Skan 280132718Skan /* Read Radio Chip Rev Extract */ 281132718Skan AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah); 282132718Skan switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 283169689Skan case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */ 284132718Skan case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */ 285132718Skan break; 286169689Skan default: 287132718Skan if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 288132718Skan AH_PRIVATE(ah)->ah_analog5GhzRev = 289132718Skan AR_RAD5133_SREV_MAJOR; 290132718Skan break; 291132718Skan } 292132718Skan#ifdef AH_DEBUG 293132718Skan HALDEBUG(ah, HAL_DEBUG_ANY, 294132718Skan "%s: 5G Radio Chip Rev 0x%02X is not supported by " 295132718Skan "this driver\n", __func__, 296132718Skan AH_PRIVATE(ah)->ah_analog5GhzRev); 297132718Skan ecode = HAL_ENOTSUPP; 298132718Skan goto bad; 299132718Skan#endif 300132718Skan } 301132718Skan rfStatus = ar9280RfAttach(ah, &ecode); 302132718Skan if (!rfStatus) { 303132718Skan HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 304169689Skan __func__, ecode); 305169689Skan goto bad; 306132718Skan } 307132718Skan 308132718Skan /* Enable fixup for AR_AN_TOP2 if necessary */ 309169689Skan /* 310132718Skan * The v14 EEPROM layer returns HAL_EIO if PWDCLKIND isn't supported 311132718Skan * by the EEPROM version. 312132718Skan * 313132718Skan * ath9k checks the EEPROM minor version is >= 0x0a here, instead of 314132718Skan * the abstracted EEPROM access layer. 315132718Skan */ 316132718Skan ecode = ath_hal_eepromGet(ah, AR_EEP_PWDCLKIND, &pwr); 317132718Skan if (AR_SREV_MERLIN_20_OR_LATER(ah) && ecode == HAL_OK && pwr == 0) { 318132718Skan printf("[ath] enabling AN_TOP2_FIXUP\n"); 319132718Skan AH5416(ah)->ah_need_an_top2_fixup = 1; 320169689Skan } 321169689Skan 322132718Skan /* 323132718Skan * Check whether the power table offset isn't the default. 324169689Skan * This can occur with eeprom minor V21 or greater on Merlin. 325169689Skan */ 326132718Skan (void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET, &pwr_table_offset); 327132718Skan if (pwr_table_offset != AR5416_PWR_TABLE_OFFSET_DB) 328132718Skan ath_hal_printf(ah, "[ath]: default pwr offset: %d dBm != EEPROM pwr offset: %d dBm; curves will be adjusted.\n", 329132718Skan AR5416_PWR_TABLE_OFFSET_DB, (int) pwr_table_offset); 330169689Skan 331132718Skan /* XXX check for >= minor ver 17 */ 332132718Skan if (AR_SREV_MERLIN_20(ah)) { 333169689Skan /* setup rxgain table */ 334136527Skan switch (ath_hal_eepromGet(ah, AR_EEP_RXGAIN_TYPE, AH_NULL)) { 335169689Skan case AR5416_EEP_RXGAIN_13dB_BACKOFF: 336132718Skan HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 337132718Skan ar9280Modes_backoff_13db_rxgain_v2, 6); 338132718Skan break; 339169689Skan case AR5416_EEP_RXGAIN_23dB_BACKOFF: 340132718Skan HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 341169689Skan ar9280Modes_backoff_23db_rxgain_v2, 6); 342132718Skan break; 343132718Skan case AR5416_EEP_RXGAIN_ORIG: 344132718Skan HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 345132718Skan ar9280Modes_original_rxgain_v2, 6); 346132718Skan break; 347132718Skan default: 348132718Skan HALASSERT(AH_FALSE); 349132718Skan goto bad; /* XXX ? try to continue */ 350132718Skan } 351132718Skan } 352169689Skan 353169689Skan /* XXX check for >= minor ver 19 */ 354132718Skan if (AR_SREV_MERLIN_20(ah)) { 355132718Skan /* setp txgain table */ 356132718Skan switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) { 357169689Skan case AR5416_EEP_TXGAIN_HIGH_POWER: 358132718Skan HAL_INI_INIT(&ahp9280->ah_ini_txgain, 359132718Skan ar9280Modes_high_power_tx_gain_v2, 6); 360169689Skan break; 361132718Skan case AR5416_EEP_TXGAIN_ORIG: 362169689Skan HAL_INI_INIT(&ahp9280->ah_ini_txgain, 363132718Skan ar9280Modes_original_tx_gain_v2, 6); 364132718Skan break; 365132718Skan default: 366169689Skan HALASSERT(AH_FALSE); 367169689Skan goto bad; /* XXX ? try to continue */ 368169689Skan } 369132718Skan } 370169689Skan 371132718Skan /* 372169689Skan * Got everything we need now to setup the capabilities. 373132718Skan */ 374169689Skan if (!ar9280FillCapabilityInfo(ah)) { 375169689Skan ecode = HAL_EEREAD; 376169689Skan goto bad; 377169689Skan } 378169689Skan 379169689Skan ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 380169689Skan if (ecode != HAL_OK) { 381169689Skan HALDEBUG(ah, HAL_DEBUG_ANY, 382169689Skan "%s: error getting mac address from EEPROM\n", __func__); 383169689Skan goto bad; 384169689Skan } 385169689Skan /* XXX How about the serial number ? */ 386169689Skan /* Read Reg Domain */ 387169689Skan AH_PRIVATE(ah)->ah_currentRD = 388169689Skan ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 389132718Skan AH_PRIVATE(ah)->ah_currentRDext = 390132718Skan ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL); 391132718Skan 392169689Skan /* 393132718Skan * ah_miscMode is populated by ar5416FillCapabilityInfo() 394132718Skan * starting from griffin. Set here to make sure that 395132718Skan * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 396132718Skan * placed into hardware. 397132718Skan */ 398169689Skan if (ahp->ah_miscMode != 0) 399169689Skan OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 400132718Skan 401132718Skan ar9280AniSetup(ah); /* Anti Noise Immunity */ 402169689Skan 403132718Skan /* Setup noise floor min/max/nominal values */ 404132718Skan AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ; 405132718Skan AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ; 406132718Skan AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9280_2GHZ; 407132718Skan AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ; 408132718Skan AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ; 409169689Skan AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9280_5GHZ; 410132718Skan 411132718Skan ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 412132718Skan 413132718Skan HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 414132718Skan 415132718Skan return ah; 416146895Skanbad: 417132718Skan if (ah != AH_NULL) 418132718Skan ah->ah_detach(ah); 419132718Skan if (status) 420132718Skan *status = ecode; 421169689Skan return AH_NULL; 422132718Skan} 423132718Skan 424132718Skanstatic void 425169689Skanar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off) 426169689Skan{ 427132718Skan uint32_t val; 428132718Skan 429132718Skan if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 430132718Skan ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 431132718Skan OS_DELAY(1000); 432169689Skan } 433169689Skan 434169689Skan 435169689Skan /* 436132718Skan * Set PCIe workaround bits 437132718Skan * 438132718Skan * NOTE: 439132718Skan * 440169689Skan * In Merlin and Kite, bit 14 in WA register (disable L1) should only 441132718Skan * be set when device enters D3 and be cleared when device comes back 442132718Skan * to D0. 443132718Skan */ 444132718Skan if (power_off) { /* Power-off */ 445132718Skan OS_REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 446132718Skan 447169689Skan val = OS_REG_READ(ah, AR_WA); 448132718Skan 449169689Skan /* 450132718Skan * Disable bit 6 and 7 before entering D3 to prevent 451132718Skan * system hang. 452169689Skan */ 453132718Skan val &= ~(AR_WA_BIT6 | AR_WA_BIT7); 454132718Skan 455132718Skan /* 456132718Skan * XXX Not sure, is specified in the reference HAL. 457132718Skan */ 458132718Skan val |= AR_WA_BIT22; 459132718Skan 460132718Skan /* 461132718Skan * See above: set AR_WA_D3_L1_DISABLE when entering D3 state. 462132718Skan * 463132718Skan * XXX The reference HAL does it this way - it only sets 464132718Skan * AR_WA_D3_L1_DISABLE if it's set in AR9280_WA_DEFAULT, 465169689Skan * which it (currently) isn't. So the following statement 466132718Skan * is currently a NOP. 467132718Skan */ 468132718Skan if (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE) 469132718Skan val |= AR_WA_D3_L1_DISABLE; 470169689Skan 471169689Skan OS_REG_WRITE(ah, AR_WA, val); 472169689Skan } else { /* Power-on */ 473169689Skan val = AR9280_WA_DEFAULT; 474169689Skan 475169689Skan /* 476169689Skan * See note above: make sure L1_DISABLE is not set. 477169689Skan */ 478169689Skan val &= (~AR_WA_D3_L1_DISABLE); 479169689Skan OS_REG_WRITE(ah, AR_WA, val); 480169689Skan 481169689Skan /* set bit 19 to allow forcing of pcie core into L1 state */ 482169689Skan OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 483169689Skan } 484} 485 486static void 487ar9280DisablePCIE(struct ath_hal *ah) 488{ 489} 490 491static void 492ar9280WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 493{ 494 u_int modesIndex, freqIndex; 495 int regWrites = 0; 496 int i; 497 const HAL_INI_ARRAY *ia; 498 499 /* Setup the indices for the next set of register array writes */ 500 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 501 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 502 freqIndex = 2; 503 if (IEEE80211_IS_CHAN_HT40(chan)) 504 modesIndex = 3; 505 else if (IEEE80211_IS_CHAN_108G(chan)) 506 modesIndex = 5; 507 else 508 modesIndex = 4; 509 } else { 510 freqIndex = 1; 511 if (IEEE80211_IS_CHAN_HT40(chan) || 512 IEEE80211_IS_CHAN_TURBO(chan)) 513 modesIndex = 2; 514 else 515 modesIndex = 1; 516 } 517 518 /* Set correct Baseband to analog shift setting to access analog chips. */ 519 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 520 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 521 522 /* 523 * This is unwound because at the moment, there's a requirement 524 * for Merlin (and later, perhaps) to have a specific bit fixed 525 * in the AR_AN_TOP2 register before writing it. 526 */ 527 ia = &AH5212(ah)->ah_ini_modes; 528#if 0 529 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 530 modesIndex, regWrites); 531#endif 532 HALASSERT(modesIndex < ia->cols); 533 for (i = 0; i < ia->rows; i++) { 534 uint32_t reg = HAL_INI_VAL(ia, i, 0); 535 uint32_t val = HAL_INI_VAL(ia, i, modesIndex); 536 537 if (reg == AR_AN_TOP2 && AH5416(ah)->ah_need_an_top2_fixup) 538 val &= ~AR_AN_TOP2_PWDCLKIND; 539 540 OS_REG_WRITE(ah, reg, val); 541 542 /* Analog shift register delay seems needed for Merlin - PR kern/154220 */ 543 if (reg >= 0x7800 && reg < 0x7900) 544 OS_DELAY(100); 545 546 DMA_YIELD(regWrites); 547 } 548 549 if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 550 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_rxgain, 551 modesIndex, regWrites); 552 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain, 553 modesIndex, regWrites); 554 } 555 /* XXX Merlin 100us delay for shift registers */ 556 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 557 1, regWrites); 558 559 if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { 560 /* 5GHz channels w/ Fast Clock use different modal values */ 561 regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_xmodes, 562 modesIndex, regWrites); 563 } 564} 565 566#define AR_BASE_FREQ_2GHZ 2300 567#define AR_BASE_FREQ_5GHZ 4900 568#define AR_SPUR_FEEQ_BOUND_HT40 19 569#define AR_SPUR_FEEQ_BOUND_HT20 10 570 571void 572ar9280SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 573{ 574 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 575 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 576 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 577 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 578 static int inc[4] = { 0, 100, 0, 0 }; 579 580 int bb_spur = AR_NO_SPUR; 581 int freq; 582 int bin, cur_bin; 583 int bb_spur_off, spur_subchannel_sd; 584 int spur_freq_sd; 585 int spur_delta_phase; 586 int denominator; 587 int upper, lower, cur_vit_mask; 588 int tmp, newVal; 589 int i; 590 CHAN_CENTERS centers; 591 592 int8_t mask_m[123]; 593 int8_t mask_p[123]; 594 int8_t mask_amt; 595 int tmp_mask; 596 int cur_bb_spur; 597 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 598 599 OS_MEMZERO(&mask_m, sizeof(int8_t) * 123); 600 OS_MEMZERO(&mask_p, sizeof(int8_t) * 123); 601 602 ar5416GetChannelCenters(ah, chan, ¢ers); 603 freq = centers.synth_center; 604 605 /* 606 * Need to verify range +/- 9.38 for static ht20 and +/- 18.75 for ht40, 607 * otherwise spur is out-of-band and can be ignored. 608 */ 609 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 610 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 611 /* Get actual spur freq in MHz from EEPROM read value */ 612 if (is2GHz) { 613 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ; 614 } else { 615 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ; 616 } 617 618 if (AR_NO_SPUR == cur_bb_spur) 619 break; 620 cur_bb_spur = cur_bb_spur - freq; 621 622 if (IEEE80211_IS_CHAN_HT40(chan)) { 623 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) && 624 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) { 625 bb_spur = cur_bb_spur; 626 break; 627 } 628 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) && 629 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) { 630 bb_spur = cur_bb_spur; 631 break; 632 } 633 } 634 635 if (AR_NO_SPUR == bb_spur) { 636#if 1 637 /* 638 * MRC CCK can interfere with beacon detection and cause deaf/mute. 639 * Disable MRC CCK for now. 640 */ 641 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 642#else 643 /* Enable MRC CCK if no spur is found in this channel. */ 644 OS_REG_SET_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 645#endif 646 return; 647 } else { 648 /* 649 * For Merlin, spur can break CCK MRC algorithm. Disable CCK MRC if spur 650 * is found in this channel. 651 */ 652 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 653 } 654 655 bin = bb_spur * 320; 656 657 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 658 659 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 660 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 661 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 662 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 663 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), newVal); 664 665 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 666 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 667 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 668 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 669 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 670 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); 671 672 /* Pick control or extn channel to cancel the spur */ 673 if (IEEE80211_IS_CHAN_HT40(chan)) { 674 if (bb_spur < 0) { 675 spur_subchannel_sd = 1; 676 bb_spur_off = bb_spur + 10; 677 } else { 678 spur_subchannel_sd = 0; 679 bb_spur_off = bb_spur - 10; 680 } 681 } else { 682 spur_subchannel_sd = 0; 683 bb_spur_off = bb_spur; 684 } 685 686 /* 687 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 688 * /80 for dyn2040. 689 */ 690 if (IEEE80211_IS_CHAN_HT40(chan)) 691 spur_delta_phase = ((bb_spur * 262144) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 692 else 693 spur_delta_phase = ((bb_spur * 524288) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 694 695 /* 696 * in 11A mode the denominator of spur_freq_sd should be 40 and 697 * it should be 44 in 11G 698 */ 699 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 44 : 40; 700 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff; 701 702 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 703 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 704 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 705 OS_REG_WRITE(ah, AR_PHY_TIMING11, newVal); 706 707 /* Choose to cancel between control and extension channels */ 708 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S; 709 OS_REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); 710 711 /* 712 * ============================================ 713 * Set Pilot and Channel Masks 714 * 715 * pilot mask 1 [31:0] = +6..-26, no 0 bin 716 * pilot mask 2 [19:0] = +26..+7 717 * 718 * channel mask 1 [31:0] = +6..-26, no 0 bin 719 * channel mask 2 [19:0] = +26..+7 720 */ 721 cur_bin = -6000; 722 upper = bin + 100; 723 lower = bin - 100; 724 725 for (i = 0; i < 4; i++) { 726 int pilot_mask = 0; 727 int chan_mask = 0; 728 int bp = 0; 729 for (bp = 0; bp < 30; bp++) { 730 if ((cur_bin > lower) && (cur_bin < upper)) { 731 pilot_mask = pilot_mask | 0x1 << bp; 732 chan_mask = chan_mask | 0x1 << bp; 733 } 734 cur_bin += 100; 735 } 736 cur_bin += inc[i]; 737 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 738 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 739 } 740 741 /* ================================================= 742 * viterbi mask 1 based on channel magnitude 743 * four levels 0-3 744 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 745 * [1 2 2 1] for -9.6 or [1 2 1] for +16 746 * - enable_mask_ppm, all bins move with freq 747 * 748 * - mask_select, 8 bits for rates (reg 67,0x990c) 749 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 750 * choose which mask to use mask or mask2 751 */ 752 753 /* 754 * viterbi mask 2 2nd set for per data rate puncturing 755 * four levels 0-3 756 * - mask_select, 8 bits for rates (reg 67) 757 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 758 * [1 2 2 1] for -9.6 or [1 2 1] for +16 759 */ 760 cur_vit_mask = 6100; 761 upper = bin + 120; 762 lower = bin - 120; 763 764 for (i = 0; i < 123; i++) { 765 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 766 if ((abs(cur_vit_mask - bin)) < 75) { 767 mask_amt = 1; 768 } else { 769 mask_amt = 0; 770 } 771 if (cur_vit_mask < 0) { 772 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 773 } else { 774 mask_p[cur_vit_mask / 100] = mask_amt; 775 } 776 } 777 cur_vit_mask -= 100; 778 } 779 780 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 781 | (mask_m[48] << 26) | (mask_m[49] << 24) 782 | (mask_m[50] << 22) | (mask_m[51] << 20) 783 | (mask_m[52] << 18) | (mask_m[53] << 16) 784 | (mask_m[54] << 14) | (mask_m[55] << 12) 785 | (mask_m[56] << 10) | (mask_m[57] << 8) 786 | (mask_m[58] << 6) | (mask_m[59] << 4) 787 | (mask_m[60] << 2) | (mask_m[61] << 0); 788 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 789 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 790 791 tmp_mask = (mask_m[31] << 28) 792 | (mask_m[32] << 26) | (mask_m[33] << 24) 793 | (mask_m[34] << 22) | (mask_m[35] << 20) 794 | (mask_m[36] << 18) | (mask_m[37] << 16) 795 | (mask_m[48] << 14) | (mask_m[39] << 12) 796 | (mask_m[40] << 10) | (mask_m[41] << 8) 797 | (mask_m[42] << 6) | (mask_m[43] << 4) 798 | (mask_m[44] << 2) | (mask_m[45] << 0); 799 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 800 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 801 802 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 803 | (mask_m[18] << 26) | (mask_m[18] << 24) 804 | (mask_m[20] << 22) | (mask_m[20] << 20) 805 | (mask_m[22] << 18) | (mask_m[22] << 16) 806 | (mask_m[24] << 14) | (mask_m[24] << 12) 807 | (mask_m[25] << 10) | (mask_m[26] << 8) 808 | (mask_m[27] << 6) | (mask_m[28] << 4) 809 | (mask_m[29] << 2) | (mask_m[30] << 0); 810 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 811 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 812 813 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 814 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 815 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 816 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 817 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 818 | (mask_m[10] << 10) | (mask_m[11] << 8) 819 | (mask_m[12] << 6) | (mask_m[13] << 4) 820 | (mask_m[14] << 2) | (mask_m[15] << 0); 821 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 822 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 823 824 tmp_mask = (mask_p[15] << 28) 825 | (mask_p[14] << 26) | (mask_p[13] << 24) 826 | (mask_p[12] << 22) | (mask_p[11] << 20) 827 | (mask_p[10] << 18) | (mask_p[ 9] << 16) 828 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 829 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 830 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 831 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 832 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 833 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 834 835 tmp_mask = (mask_p[30] << 28) 836 | (mask_p[29] << 26) | (mask_p[28] << 24) 837 | (mask_p[27] << 22) | (mask_p[26] << 20) 838 | (mask_p[25] << 18) | (mask_p[24] << 16) 839 | (mask_p[23] << 14) | (mask_p[22] << 12) 840 | (mask_p[21] << 10) | (mask_p[20] << 8) 841 | (mask_p[19] << 6) | (mask_p[18] << 4) 842 | (mask_p[17] << 2) | (mask_p[16] << 0); 843 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 844 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 845 846 tmp_mask = (mask_p[45] << 28) 847 | (mask_p[44] << 26) | (mask_p[43] << 24) 848 | (mask_p[42] << 22) | (mask_p[41] << 20) 849 | (mask_p[40] << 18) | (mask_p[39] << 16) 850 | (mask_p[38] << 14) | (mask_p[37] << 12) 851 | (mask_p[36] << 10) | (mask_p[35] << 8) 852 | (mask_p[34] << 6) | (mask_p[33] << 4) 853 | (mask_p[32] << 2) | (mask_p[31] << 0); 854 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 855 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 856 857 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 858 | (mask_p[59] << 26) | (mask_p[58] << 24) 859 | (mask_p[57] << 22) | (mask_p[56] << 20) 860 | (mask_p[55] << 18) | (mask_p[54] << 16) 861 | (mask_p[53] << 14) | (mask_p[52] << 12) 862 | (mask_p[51] << 10) | (mask_p[50] << 8) 863 | (mask_p[49] << 6) | (mask_p[48] << 4) 864 | (mask_p[47] << 2) | (mask_p[46] << 0); 865 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 866 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 867} 868 869/* 870 * Fill all software cached or static hardware state information. 871 * Return failure if capabilities are to come from EEPROM and 872 * cannot be read. 873 */ 874static HAL_BOOL 875ar9280FillCapabilityInfo(struct ath_hal *ah) 876{ 877 HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 878 879 if (!ar5416FillCapabilityInfo(ah)) 880 return AH_FALSE; 881 pCap->halNumGpioPins = 10; 882 pCap->halWowSupport = AH_TRUE; 883 pCap->halWowMatchPatternExact = AH_TRUE; 884#if 0 885 pCap->halWowMatchPatternDword = AH_TRUE; 886#endif 887 pCap->halCSTSupport = AH_TRUE; 888 pCap->halRifsRxSupport = AH_TRUE; 889 pCap->halRifsTxSupport = AH_TRUE; 890 pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */ 891 pCap->halExtChanDfsSupport = AH_TRUE; 892 pCap->halUseCombinedRadarRssi = AH_TRUE; 893#if 0 894 /* XXX bluetooth */ 895 pCap->halBtCoexSupport = AH_TRUE; 896#endif 897 pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */ 898 pCap->hal4kbSplitTransSupport = AH_FALSE; 899 /* Disable this so Block-ACK works correctly */ 900 pCap->halHasRxSelfLinkedTail = AH_FALSE; 901 pCap->halMbssidAggrSupport = AH_TRUE; 902 pCap->hal4AddrAggrSupport = AH_TRUE; 903 904 if (AR_SREV_MERLIN_20(ah)) { 905 pCap->halPSPollBroken = AH_FALSE; 906 /* 907 * This just enables the support; it doesn't 908 * state 5ghz fast clock will always be used. 909 */ 910 pCap->halSupportsFastClock5GHz = AH_TRUE; 911 } 912 pCap->halRxStbcSupport = 1; 913 pCap->halTxStbcSupport = 1; 914 pCap->halEnhancedDfsSupport = AH_TRUE; 915 916 return AH_TRUE; 917} 918 919/* 920 * This has been disabled - having the HAL flip chainmasks on/off 921 * when attempting to implement 11n disrupts things. For now, just 922 * leave this flipped off and worry about implementing TX diversity 923 * for legacy and MCS0-7 when 11n is fully functioning. 924 */ 925HAL_BOOL 926ar9280SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings) 927{ 928#define ANTENNA0_CHAINMASK 0x1 929#define ANTENNA1_CHAINMASK 0x2 930#if 0 931 struct ath_hal_5416 *ahp = AH5416(ah); 932 933 /* Antenna selection is done by setting the tx/rx chainmasks approp. */ 934 switch (settings) { 935 case HAL_ANT_FIXED_A: 936 /* Enable first antenna only */ 937 ahp->ah_tx_chainmask = ANTENNA0_CHAINMASK; 938 ahp->ah_rx_chainmask = ANTENNA0_CHAINMASK; 939 break; 940 case HAL_ANT_FIXED_B: 941 /* Enable second antenna only, after checking capability */ 942 if (AH_PRIVATE(ah)->ah_caps.halTxChainMask > ANTENNA1_CHAINMASK) 943 ahp->ah_tx_chainmask = ANTENNA1_CHAINMASK; 944 ahp->ah_rx_chainmask = ANTENNA1_CHAINMASK; 945 break; 946 case HAL_ANT_VARIABLE: 947 /* Restore original chainmask settings */ 948 /* XXX */ 949 ahp->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK; 950 ahp->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK; 951 break; 952 } 953 954 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: settings=%d, tx/rx chainmask=%d/%d\n", 955 __func__, settings, ahp->ah_tx_chainmask, ahp->ah_rx_chainmask); 956 957#endif 958 return AH_TRUE; 959#undef ANTENNA0_CHAINMASK 960#undef ANTENNA1_CHAINMASK 961} 962 963static const char* 964ar9280Probe(uint16_t vendorid, uint16_t devid) 965{ 966 if (vendorid == ATHEROS_VENDOR_ID) { 967 if (devid == AR9280_DEVID_PCI) 968 return "Atheros 9220"; 969 if (devid == AR9280_DEVID_PCIE) 970 return "Atheros 9280"; 971 } 972 return AH_NULL; 973} 974AH_CHIP(AR9280, ar9280Probe, ar9280Attach); 975