ar9280_attach.c revision 221875
1189747Ssam/* 2189747Ssam * Copyright (c) 2008-2009 Sam Leffler, Errno Consulting 3189747Ssam * Copyright (c) 2008 Atheros Communications, Inc. 4189747Ssam * 5189747Ssam * Permission to use, copy, modify, and/or distribute this software for any 6189747Ssam * purpose with or without fee is hereby granted, provided that the above 7189747Ssam * copyright notice and this permission notice appear in all copies. 8189747Ssam * 9189747Ssam * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10189747Ssam * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11189747Ssam * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12189747Ssam * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13189747Ssam * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14189747Ssam * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15189747Ssam * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16189747Ssam * 17189747Ssam * $FreeBSD: head/sys/dev/ath/ath_hal/ar9002/ar9280_attach.c 221875 2011-05-14 04:05:23Z adrian $ 18189747Ssam */ 19189747Ssam#include "opt_ah.h" 20189747Ssam 21189747Ssam#include "ah.h" 22189747Ssam#include "ah_internal.h" 23189747Ssam#include "ah_devid.h" 24189747Ssam 25189747Ssam#include "ah_eeprom_v14.h" /* XXX for tx/rx gain */ 26189747Ssam 27217631Sadrian#include "ar9002/ar9280.h" 28189747Ssam#include "ar5416/ar5416reg.h" 29189747Ssam#include "ar5416/ar5416phy.h" 30189747Ssam 31217631Sadrian#include "ar9002/ar9280v1.ini" 32217631Sadrian#include "ar9002/ar9280v2.ini" 33219393Sadrian#include "ar9002/ar9280_olc.h" 34189747Ssam 35189747Ssamstatic const HAL_PERCAL_DATA ar9280_iq_cal = { /* single sample */ 36189747Ssam .calName = "IQ", .calType = IQ_MISMATCH_CAL, 37189747Ssam .calNumSamples = MIN_CAL_SAMPLES, 38189747Ssam .calCountMax = PER_MAX_LOG_COUNT, 39189747Ssam .calCollect = ar5416IQCalCollect, 40189747Ssam .calPostProc = ar5416IQCalibration 41189747Ssam}; 42189747Ssamstatic const HAL_PERCAL_DATA ar9280_adc_gain_cal = { /* single sample */ 43189747Ssam .calName = "ADC Gain", .calType = ADC_GAIN_CAL, 44189747Ssam .calNumSamples = MIN_CAL_SAMPLES, 45189747Ssam .calCountMax = PER_MIN_LOG_COUNT, 46189747Ssam .calCollect = ar5416AdcGainCalCollect, 47189747Ssam .calPostProc = ar5416AdcGainCalibration 48189747Ssam}; 49189747Ssamstatic const HAL_PERCAL_DATA ar9280_adc_dc_cal = { /* single sample */ 50189747Ssam .calName = "ADC DC", .calType = ADC_DC_CAL, 51189747Ssam .calNumSamples = MIN_CAL_SAMPLES, 52189747Ssam .calCountMax = PER_MIN_LOG_COUNT, 53189747Ssam .calCollect = ar5416AdcDcCalCollect, 54189747Ssam .calPostProc = ar5416AdcDcCalibration 55189747Ssam}; 56189747Ssamstatic const HAL_PERCAL_DATA ar9280_adc_init_dc_cal = { 57189747Ssam .calName = "ADC Init DC", .calType = ADC_DC_INIT_CAL, 58189747Ssam .calNumSamples = MIN_CAL_SAMPLES, 59189747Ssam .calCountMax = INIT_LOG_COUNT, 60189747Ssam .calCollect = ar5416AdcDcCalCollect, 61189747Ssam .calPostProc = ar5416AdcDcCalibration 62189747Ssam}; 63189747Ssam 64189747Ssamstatic void ar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 65189747Ssamstatic HAL_BOOL ar9280FillCapabilityInfo(struct ath_hal *ah); 66189747Ssamstatic void ar9280WriteIni(struct ath_hal *ah, 67189747Ssam const struct ieee80211_channel *chan); 68189747Ssam 69189747Ssamstatic void 70189747Ssamar9280AniSetup(struct ath_hal *ah) 71189747Ssam{ 72218764Sadrian /* 73218764Sadrian * These are the parameters from the AR5416 ANI code; 74218764Sadrian * they likely need quite a bit of adjustment for the 75218764Sadrian * AR9280. 76218764Sadrian */ 77218764Sadrian static const struct ar5212AniParams aniparams = { 78218764Sadrian .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 79218764Sadrian .totalSizeDesired = { -55, -55, -55, -55, -62 }, 80218764Sadrian .coarseHigh = { -14, -14, -14, -14, -12 }, 81218764Sadrian .coarseLow = { -64, -64, -64, -64, -70 }, 82218764Sadrian .firpwr = { -78, -78, -78, -78, -80 }, 83218764Sadrian .maxSpurImmunityLevel = 2, 84218764Sadrian .cycPwrThr1 = { 2, 4, 6 }, 85218764Sadrian .maxFirstepLevel = 2, /* levels 0..2 */ 86218764Sadrian .firstep = { 0, 4, 8 }, 87218764Sadrian .ofdmTrigHigh = 500, 88218764Sadrian .ofdmTrigLow = 200, 89218764Sadrian .cckTrigHigh = 200, 90218764Sadrian .cckTrigLow = 100, 91218764Sadrian .rssiThrHigh = 40, 92218764Sadrian .rssiThrLow = 7, 93218764Sadrian .period = 100, 94218764Sadrian }; 95218764Sadrian /* NB: disable ANI noise immmunity for reliable RIFS rx */ 96218764Sadrian AH5416(ah)->ah_ani_function &= ~ HAL_ANI_NOISE_IMMUNITY_LEVEL; 97218764Sadrian 98218764Sadrian /* NB: ANI is not enabled yet */ 99219979Sadrian ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 100189747Ssam} 101189747Ssam 102221875Sadrian/* XXX shouldn't be here! */ 103221875Sadrian#define EEP_MINOR(_ah) \ 104221875Sadrian (AH_PRIVATE(_ah)->ah_eeversion & AR5416_EEP_VER_MINOR_MASK) 105221875Sadrian 106189747Ssam/* 107189747Ssam * Attach for an AR9280 part. 108189747Ssam */ 109189747Ssamstatic struct ath_hal * 110189747Ssamar9280Attach(uint16_t devid, HAL_SOFTC sc, 111217624Sadrian HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 112217624Sadrian HAL_STATUS *status) 113189747Ssam{ 114189747Ssam struct ath_hal_9280 *ahp9280; 115189747Ssam struct ath_hal_5212 *ahp; 116189747Ssam struct ath_hal *ah; 117189747Ssam uint32_t val; 118189747Ssam HAL_STATUS ecode; 119189747Ssam HAL_BOOL rfStatus; 120219393Sadrian int8_t pwr_table_offset; 121219441Sadrian uint8_t pwr; 122189747Ssam 123189747Ssam HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 124189747Ssam __func__, sc, (void*) st, (void*) sh); 125189747Ssam 126189747Ssam /* NB: memory is returned zero'd */ 127189747Ssam ahp9280 = ath_hal_malloc(sizeof (struct ath_hal_9280)); 128189747Ssam if (ahp9280 == AH_NULL) { 129189747Ssam HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 130189747Ssam "%s: cannot allocate memory for state block\n", __func__); 131189747Ssam *status = HAL_ENOMEM; 132189747Ssam return AH_NULL; 133189747Ssam } 134189747Ssam ahp = AH5212(ahp9280); 135189747Ssam ah = &ahp->ah_priv.h; 136189747Ssam 137189747Ssam ar5416InitState(AH5416(ah), devid, sc, st, sh, status); 138189747Ssam 139189747Ssam /* XXX override with 9280 specific state */ 140189747Ssam /* override 5416 methods for our needs */ 141189747Ssam ah->ah_setAntennaSwitch = ar9280SetAntennaSwitch; 142189747Ssam ah->ah_configPCIE = ar9280ConfigPCIE; 143189747Ssam 144189747Ssam AH5416(ah)->ah_cal.iqCalData.calData = &ar9280_iq_cal; 145189747Ssam AH5416(ah)->ah_cal.adcGainCalData.calData = &ar9280_adc_gain_cal; 146189747Ssam AH5416(ah)->ah_cal.adcDcCalData.calData = &ar9280_adc_dc_cal; 147189747Ssam AH5416(ah)->ah_cal.adcDcCalInitData.calData = &ar9280_adc_init_dc_cal; 148189747Ssam AH5416(ah)->ah_cal.suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL; 149189747Ssam 150189747Ssam AH5416(ah)->ah_spurMitigate = ar9280SpurMitigate; 151189747Ssam AH5416(ah)->ah_writeIni = ar9280WriteIni; 152219393Sadrian AH5416(ah)->ah_olcInit = ar9280olcInit; 153219393Sadrian AH5416(ah)->ah_olcTempCompensation = ar9280olcTemperatureCompensation; 154219393Sadrian AH5416(ah)->ah_setPowerCalTable = ar9280SetPowerCalTable; 155219393Sadrian 156189747Ssam AH5416(ah)->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK; 157189747Ssam AH5416(ah)->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK; 158189747Ssam 159189747Ssam if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 160189747Ssam /* reset chip */ 161189747Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", 162189747Ssam __func__); 163189747Ssam ecode = HAL_EIO; 164189747Ssam goto bad; 165189747Ssam } 166189747Ssam 167189747Ssam if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 168189747Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", 169189747Ssam __func__); 170189747Ssam ecode = HAL_EIO; 171189747Ssam goto bad; 172189747Ssam } 173189747Ssam /* Read Revisions from Chips before taking out of reset */ 174189747Ssam val = OS_REG_READ(ah, AR_SREV); 175189747Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, 176189747Ssam "%s: ID 0x%x VERSION 0x%x TYPE 0x%x REVISION 0x%x\n", 177189747Ssam __func__, MS(val, AR_XSREV_ID), MS(val, AR_XSREV_VERSION), 178189747Ssam MS(val, AR_XSREV_TYPE), MS(val, AR_XSREV_REVISION)); 179189747Ssam /* NB: include chip type to differentiate from pre-Sowl versions */ 180189747Ssam AH_PRIVATE(ah)->ah_macVersion = 181189747Ssam (val & AR_XSREV_VERSION) >> AR_XSREV_TYPE_S; 182189747Ssam AH_PRIVATE(ah)->ah_macRev = MS(val, AR_XSREV_REVISION); 183189747Ssam AH_PRIVATE(ah)->ah_ispcie = (val & AR_XSREV_TYPE_HOST_MODE) == 0; 184189747Ssam 185189747Ssam /* setup common ini data; rf backends handle remainder */ 186203882Srpaulo if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 187189747Ssam HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v2, 6); 188189747Ssam HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v2, 2); 189189747Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 190189747Ssam ar9280PciePhy_clkreq_always_on_L1_v2, 2); 191189747Ssam HAL_INI_INIT(&ahp9280->ah_ini_xmodes, 192189747Ssam ar9280Modes_fast_clock_v2, 3); 193189747Ssam } else { 194189747Ssam HAL_INI_INIT(&ahp->ah_ini_modes, ar9280Modes_v1, 6); 195189747Ssam HAL_INI_INIT(&ahp->ah_ini_common, ar9280Common_v1, 2); 196189747Ssam HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, 197189747Ssam ar9280PciePhy_v1, 2); 198189747Ssam } 199189747Ssam ar5416AttachPCIE(ah); 200189747Ssam 201203882Srpaulo ecode = ath_hal_v14EepromAttach(ah); 202189747Ssam if (ecode != HAL_OK) 203189747Ssam goto bad; 204189747Ssam 205189747Ssam if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 206189747Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", __func__); 207189747Ssam ecode = HAL_EIO; 208189747Ssam goto bad; 209189747Ssam } 210189747Ssam 211189747Ssam AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 212189747Ssam 213189747Ssam if (!ar5212ChipTest(ah)) { 214189747Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 215189747Ssam __func__); 216189747Ssam ecode = HAL_ESELFTEST; 217189747Ssam goto bad; 218189747Ssam } 219189747Ssam 220189747Ssam /* 221189747Ssam * Set correct Baseband to analog shift 222189747Ssam * setting to access analog chips. 223189747Ssam */ 224189747Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 225189747Ssam 226189747Ssam /* Read Radio Chip Rev Extract */ 227189747Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah); 228189747Ssam switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 229189747Ssam case AR_RAD2133_SREV_MAJOR: /* Sowl: 2G/3x3 */ 230189747Ssam case AR_RAD5133_SREV_MAJOR: /* Sowl: 2+5G/3x3 */ 231189747Ssam break; 232189747Ssam default: 233189747Ssam if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 234189747Ssam AH_PRIVATE(ah)->ah_analog5GhzRev = 235189747Ssam AR_RAD5133_SREV_MAJOR; 236189747Ssam break; 237189747Ssam } 238189747Ssam#ifdef AH_DEBUG 239189747Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 240189747Ssam "%s: 5G Radio Chip Rev 0x%02X is not supported by " 241189747Ssam "this driver\n", __func__, 242189747Ssam AH_PRIVATE(ah)->ah_analog5GhzRev); 243189747Ssam ecode = HAL_ENOTSUPP; 244189747Ssam goto bad; 245189747Ssam#endif 246189747Ssam } 247189747Ssam rfStatus = ar9280RfAttach(ah, &ecode); 248189747Ssam if (!rfStatus) { 249189747Ssam HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 250189747Ssam __func__, ecode); 251189747Ssam goto bad; 252189747Ssam } 253189747Ssam 254219441Sadrian /* Enable fixup for AR_AN_TOP2 if necessary */ 255219441Sadrian /* 256219441Sadrian * The v14 EEPROM layer returns HAL_EIO if PWDCLKIND isn't supported 257219441Sadrian * by the EEPROM version. 258219441Sadrian * 259219441Sadrian * ath9k checks the EEPROM minor version is >= 0x0a here, instead of 260219441Sadrian * the abstracted EEPROM access layer. 261219441Sadrian */ 262219441Sadrian ecode = ath_hal_eepromGet(ah, AR_EEP_PWDCLKIND, &pwr); 263219441Sadrian if (AR_SREV_MERLIN_20_OR_LATER(ah) && ecode == HAL_OK && pwr == 0) { 264219441Sadrian printf("[ath] enabling AN_TOP2_FIXUP\n"); 265219441Sadrian AH5416(ah)->ah_need_an_top2_fixup = 1; 266219441Sadrian } 267219441Sadrian 268219393Sadrian /* 269219393Sadrian * Check whether the power table offset isn't the default. 270219393Sadrian * This can occur with eeprom minor V21 or greater on Merlin. 271219393Sadrian */ 272219393Sadrian (void) ath_hal_eepromGet(ah, AR_EEP_PWR_TABLE_OFFSET, &pwr_table_offset); 273219445Sadrian if (pwr_table_offset != AR5416_PWR_TABLE_OFFSET_DB) 274219445Sadrian ath_hal_printf(ah, "[ath]: default pwr offset: %d dBm != EEPROM pwr offset: %d dBm; curves will be adjusted.\n", 275219393Sadrian AR5416_PWR_TABLE_OFFSET_DB, (int) pwr_table_offset); 276219393Sadrian 277221875Sadrian /* XXX check for >= minor ver 17 */ 278221875Sadrian if (AR_SREV_MERLIN_20(ah)) { 279189747Ssam /* setup rxgain table */ 280189747Ssam switch (ath_hal_eepromGet(ah, AR_EEP_RXGAIN_TYPE, AH_NULL)) { 281189747Ssam case AR5416_EEP_RXGAIN_13dB_BACKOFF: 282189747Ssam HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 283189747Ssam ar9280Modes_backoff_13db_rxgain_v2, 6); 284189747Ssam break; 285189747Ssam case AR5416_EEP_RXGAIN_23dB_BACKOFF: 286189747Ssam HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 287189747Ssam ar9280Modes_backoff_23db_rxgain_v2, 6); 288189747Ssam break; 289189747Ssam case AR5416_EEP_RXGAIN_ORIG: 290189747Ssam HAL_INI_INIT(&ahp9280->ah_ini_rxgain, 291189747Ssam ar9280Modes_original_rxgain_v2, 6); 292189747Ssam break; 293189747Ssam default: 294189747Ssam HALASSERT(AH_FALSE); 295189747Ssam goto bad; /* XXX ? try to continue */ 296189747Ssam } 297189747Ssam } 298221875Sadrian 299221875Sadrian /* XXX check for >= minor ver 19 */ 300221875Sadrian if (AR_SREV_MERLIN_20(ah)) { 301189747Ssam /* setp txgain table */ 302189747Ssam switch (ath_hal_eepromGet(ah, AR_EEP_TXGAIN_TYPE, AH_NULL)) { 303189747Ssam case AR5416_EEP_TXGAIN_HIGH_POWER: 304189747Ssam HAL_INI_INIT(&ahp9280->ah_ini_txgain, 305189747Ssam ar9280Modes_high_power_tx_gain_v2, 6); 306189747Ssam break; 307189747Ssam case AR5416_EEP_TXGAIN_ORIG: 308189747Ssam HAL_INI_INIT(&ahp9280->ah_ini_txgain, 309189747Ssam ar9280Modes_original_tx_gain_v2, 6); 310189747Ssam break; 311189747Ssam default: 312189747Ssam HALASSERT(AH_FALSE); 313189747Ssam goto bad; /* XXX ? try to continue */ 314189747Ssam } 315189747Ssam } 316189747Ssam 317189747Ssam /* 318189747Ssam * Got everything we need now to setup the capabilities. 319189747Ssam */ 320189747Ssam if (!ar9280FillCapabilityInfo(ah)) { 321189747Ssam ecode = HAL_EEREAD; 322189747Ssam goto bad; 323189747Ssam } 324189747Ssam 325189747Ssam ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 326189747Ssam if (ecode != HAL_OK) { 327189747Ssam HALDEBUG(ah, HAL_DEBUG_ANY, 328189747Ssam "%s: error getting mac address from EEPROM\n", __func__); 329189747Ssam goto bad; 330189747Ssam } 331189747Ssam /* XXX How about the serial number ? */ 332189747Ssam /* Read Reg Domain */ 333189747Ssam AH_PRIVATE(ah)->ah_currentRD = 334189747Ssam ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 335221596Sadrian AH_PRIVATE(ah)->ah_currentRDext = 336221596Sadrian ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL); 337189747Ssam 338189747Ssam /* 339189747Ssam * ah_miscMode is populated by ar5416FillCapabilityInfo() 340189747Ssam * starting from griffin. Set here to make sure that 341189747Ssam * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 342189747Ssam * placed into hardware. 343189747Ssam */ 344189747Ssam if (ahp->ah_miscMode != 0) 345219852Sadrian OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 346189747Ssam 347189747Ssam ar9280AniSetup(ah); /* Anti Noise Immunity */ 348218068Sadrian 349218068Sadrian /* Setup noise floor min/max/nominal values */ 350218068Sadrian AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ; 351218068Sadrian AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ; 352218068Sadrian AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9280_2GHZ; 353218068Sadrian AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ; 354218068Sadrian AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ; 355218068Sadrian AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9280_5GHZ; 356218068Sadrian 357203882Srpaulo ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 358189747Ssam 359189747Ssam HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 360189747Ssam 361189747Ssam return ah; 362189747Ssambad: 363189747Ssam if (ah != AH_NULL) 364189747Ssam ah->ah_detach(ah); 365189747Ssam if (status) 366189747Ssam *status = ecode; 367189747Ssam return AH_NULL; 368189747Ssam} 369189747Ssam 370189747Ssamstatic void 371189747Ssamar9280ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 372189747Ssam{ 373189747Ssam if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 374189747Ssam ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 375189747Ssam OS_DELAY(1000); 376189747Ssam OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 377203882Srpaulo OS_REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT); 378189747Ssam } 379189747Ssam} 380189747Ssam 381189747Ssamstatic void 382189747Ssamar9280WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 383189747Ssam{ 384189747Ssam u_int modesIndex, freqIndex; 385189747Ssam int regWrites = 0; 386219441Sadrian int i; 387219441Sadrian const HAL_INI_ARRAY *ia; 388189747Ssam 389189747Ssam /* Setup the indices for the next set of register array writes */ 390189747Ssam /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 391189747Ssam if (IEEE80211_IS_CHAN_2GHZ(chan)) { 392189747Ssam freqIndex = 2; 393189747Ssam if (IEEE80211_IS_CHAN_HT40(chan)) 394189747Ssam modesIndex = 3; 395189747Ssam else if (IEEE80211_IS_CHAN_108G(chan)) 396189747Ssam modesIndex = 5; 397189747Ssam else 398189747Ssam modesIndex = 4; 399189747Ssam } else { 400189747Ssam freqIndex = 1; 401189747Ssam if (IEEE80211_IS_CHAN_HT40(chan) || 402189747Ssam IEEE80211_IS_CHAN_TURBO(chan)) 403189747Ssam modesIndex = 2; 404189747Ssam else 405189747Ssam modesIndex = 1; 406189747Ssam } 407189747Ssam 408189747Ssam /* Set correct Baseband to analog shift setting to access analog chips. */ 409189747Ssam OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 410189747Ssam OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 411189747Ssam 412219441Sadrian /* 413219441Sadrian * This is unwound because at the moment, there's a requirement 414219441Sadrian * for Merlin (and later, perhaps) to have a specific bit fixed 415219441Sadrian * in the AR_AN_TOP2 register before writing it. 416219441Sadrian */ 417219441Sadrian ia = &AH5212(ah)->ah_ini_modes; 418219441Sadrian#if 0 419189747Ssam regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 420189747Ssam modesIndex, regWrites); 421219441Sadrian#endif 422219441Sadrian HALASSERT(modesIndex < ia->cols); 423219441Sadrian for (i = 0; i < ia->rows; i++) { 424219441Sadrian uint32_t reg = HAL_INI_VAL(ia, i, 0); 425219441Sadrian uint32_t val = HAL_INI_VAL(ia, i, modesIndex); 426219441Sadrian 427219441Sadrian if (reg == AR_AN_TOP2 && AH5416(ah)->ah_need_an_top2_fixup) 428219441Sadrian val &= ~AR_AN_TOP2_PWDCLKIND; 429219441Sadrian 430219441Sadrian OS_REG_WRITE(ah, reg, val); 431219441Sadrian 432219441Sadrian /* Analog shift register delay seems needed for Merlin - PR kern/154220 */ 433219441Sadrian if (reg >= 0x7800 && reg < 0x78a0) 434219441Sadrian OS_DELAY(100); 435219441Sadrian 436219441Sadrian DMA_YIELD(regWrites); 437219441Sadrian } 438219441Sadrian 439189747Ssam if (AR_SREV_MERLIN_20_OR_LATER(ah)) { 440189747Ssam regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_rxgain, 441189747Ssam modesIndex, regWrites); 442189747Ssam regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_txgain, 443189747Ssam modesIndex, regWrites); 444189747Ssam } 445189747Ssam /* XXX Merlin 100us delay for shift registers */ 446189747Ssam regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 447189747Ssam 1, regWrites); 448189747Ssam 449189747Ssam if (AR_SREV_MERLIN_20(ah) && IS_5GHZ_FAST_CLOCK_EN(ah, chan)) { 450189747Ssam /* 5GHz channels w/ Fast Clock use different modal values */ 451189747Ssam regWrites = ath_hal_ini_write(ah, &AH9280(ah)->ah_ini_xmodes, 452189747Ssam modesIndex, regWrites); 453189747Ssam } 454189747Ssam} 455189747Ssam 456189747Ssam#define AR_BASE_FREQ_2GHZ 2300 457189747Ssam#define AR_BASE_FREQ_5GHZ 4900 458189747Ssam#define AR_SPUR_FEEQ_BOUND_HT40 19 459189747Ssam#define AR_SPUR_FEEQ_BOUND_HT20 10 460189747Ssam 461203930Srpaulovoid 462189747Ssamar9280SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 463189747Ssam{ 464189747Ssam static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 465189747Ssam AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 466189747Ssam static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 467189747Ssam AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 468189747Ssam static int inc[4] = { 0, 100, 0, 0 }; 469189747Ssam 470189747Ssam int bb_spur = AR_NO_SPUR; 471189747Ssam int freq; 472189747Ssam int bin, cur_bin; 473189747Ssam int bb_spur_off, spur_subchannel_sd; 474189747Ssam int spur_freq_sd; 475189747Ssam int spur_delta_phase; 476189747Ssam int denominator; 477189747Ssam int upper, lower, cur_vit_mask; 478189747Ssam int tmp, newVal; 479189747Ssam int i; 480189747Ssam CHAN_CENTERS centers; 481189747Ssam 482189747Ssam int8_t mask_m[123]; 483189747Ssam int8_t mask_p[123]; 484189747Ssam int8_t mask_amt; 485189747Ssam int tmp_mask; 486189747Ssam int cur_bb_spur; 487189747Ssam HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 488189747Ssam 489189747Ssam OS_MEMZERO(&mask_m, sizeof(int8_t) * 123); 490189747Ssam OS_MEMZERO(&mask_p, sizeof(int8_t) * 123); 491189747Ssam 492189747Ssam ar5416GetChannelCenters(ah, chan, ¢ers); 493189747Ssam freq = centers.synth_center; 494189747Ssam 495189747Ssam /* 496189747Ssam * Need to verify range +/- 9.38 for static ht20 and +/- 18.75 for ht40, 497189747Ssam * otherwise spur is out-of-band and can be ignored. 498189747Ssam */ 499189747Ssam for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 500189747Ssam cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 501189747Ssam /* Get actual spur freq in MHz from EEPROM read value */ 502189747Ssam if (is2GHz) { 503189747Ssam cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ; 504189747Ssam } else { 505189747Ssam cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ; 506189747Ssam } 507189747Ssam 508189747Ssam if (AR_NO_SPUR == cur_bb_spur) 509189747Ssam break; 510189747Ssam cur_bb_spur = cur_bb_spur - freq; 511189747Ssam 512189747Ssam if (IEEE80211_IS_CHAN_HT40(chan)) { 513189747Ssam if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) && 514189747Ssam (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) { 515189747Ssam bb_spur = cur_bb_spur; 516189747Ssam break; 517189747Ssam } 518189747Ssam } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) && 519189747Ssam (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) { 520189747Ssam bb_spur = cur_bb_spur; 521189747Ssam break; 522189747Ssam } 523189747Ssam } 524189747Ssam 525189747Ssam if (AR_NO_SPUR == bb_spur) { 526189747Ssam#if 1 527189747Ssam /* 528189747Ssam * MRC CCK can interfere with beacon detection and cause deaf/mute. 529189747Ssam * Disable MRC CCK for now. 530189747Ssam */ 531189747Ssam OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 532189747Ssam#else 533189747Ssam /* Enable MRC CCK if no spur is found in this channel. */ 534189747Ssam OS_REG_SET_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 535189747Ssam#endif 536189747Ssam return; 537189747Ssam } else { 538189747Ssam /* 539189747Ssam * For Merlin, spur can break CCK MRC algorithm. Disable CCK MRC if spur 540189747Ssam * is found in this channel. 541189747Ssam */ 542189747Ssam OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK, AR_PHY_FORCE_CLKEN_CCK_MRC_MUX); 543189747Ssam } 544189747Ssam 545189747Ssam bin = bb_spur * 320; 546189747Ssam 547189747Ssam tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 548189747Ssam 549189747Ssam newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 550189747Ssam AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 551189747Ssam AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 552189747Ssam AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 553189747Ssam OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), newVal); 554189747Ssam 555189747Ssam newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 556189747Ssam AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 557189747Ssam AR_PHY_SPUR_REG_MASK_RATE_SELECT | 558189747Ssam AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 559189747Ssam SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 560189747Ssam OS_REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); 561189747Ssam 562189747Ssam /* Pick control or extn channel to cancel the spur */ 563189747Ssam if (IEEE80211_IS_CHAN_HT40(chan)) { 564189747Ssam if (bb_spur < 0) { 565189747Ssam spur_subchannel_sd = 1; 566189747Ssam bb_spur_off = bb_spur + 10; 567189747Ssam } else { 568189747Ssam spur_subchannel_sd = 0; 569189747Ssam bb_spur_off = bb_spur - 10; 570189747Ssam } 571189747Ssam } else { 572189747Ssam spur_subchannel_sd = 0; 573189747Ssam bb_spur_off = bb_spur; 574189747Ssam } 575189747Ssam 576189747Ssam /* 577189747Ssam * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 578189747Ssam * /80 for dyn2040. 579189747Ssam */ 580189747Ssam if (IEEE80211_IS_CHAN_HT40(chan)) 581189747Ssam spur_delta_phase = ((bb_spur * 262144) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 582189747Ssam else 583189747Ssam spur_delta_phase = ((bb_spur * 524288) / 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE; 584189747Ssam 585189747Ssam /* 586189747Ssam * in 11A mode the denominator of spur_freq_sd should be 40 and 587189747Ssam * it should be 44 in 11G 588189747Ssam */ 589189747Ssam denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 44 : 40; 590189747Ssam spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff; 591189747Ssam 592189747Ssam newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 593189747Ssam SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 594189747Ssam SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 595189747Ssam OS_REG_WRITE(ah, AR_PHY_TIMING11, newVal); 596189747Ssam 597189747Ssam /* Choose to cancel between control and extension channels */ 598189747Ssam newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S; 599189747Ssam OS_REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); 600189747Ssam 601189747Ssam /* 602189747Ssam * ============================================ 603189747Ssam * Set Pilot and Channel Masks 604189747Ssam * 605189747Ssam * pilot mask 1 [31:0] = +6..-26, no 0 bin 606189747Ssam * pilot mask 2 [19:0] = +26..+7 607189747Ssam * 608189747Ssam * channel mask 1 [31:0] = +6..-26, no 0 bin 609189747Ssam * channel mask 2 [19:0] = +26..+7 610189747Ssam */ 611189747Ssam cur_bin = -6000; 612189747Ssam upper = bin + 100; 613189747Ssam lower = bin - 100; 614189747Ssam 615189747Ssam for (i = 0; i < 4; i++) { 616189747Ssam int pilot_mask = 0; 617189747Ssam int chan_mask = 0; 618189747Ssam int bp = 0; 619189747Ssam for (bp = 0; bp < 30; bp++) { 620189747Ssam if ((cur_bin > lower) && (cur_bin < upper)) { 621189747Ssam pilot_mask = pilot_mask | 0x1 << bp; 622189747Ssam chan_mask = chan_mask | 0x1 << bp; 623189747Ssam } 624189747Ssam cur_bin += 100; 625189747Ssam } 626189747Ssam cur_bin += inc[i]; 627189747Ssam OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 628189747Ssam OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 629189747Ssam } 630189747Ssam 631189747Ssam /* ================================================= 632189747Ssam * viterbi mask 1 based on channel magnitude 633189747Ssam * four levels 0-3 634189747Ssam * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 635189747Ssam * [1 2 2 1] for -9.6 or [1 2 1] for +16 636189747Ssam * - enable_mask_ppm, all bins move with freq 637189747Ssam * 638189747Ssam * - mask_select, 8 bits for rates (reg 67,0x990c) 639189747Ssam * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 640189747Ssam * choose which mask to use mask or mask2 641189747Ssam */ 642189747Ssam 643189747Ssam /* 644189747Ssam * viterbi mask 2 2nd set for per data rate puncturing 645189747Ssam * four levels 0-3 646189747Ssam * - mask_select, 8 bits for rates (reg 67) 647189747Ssam * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 648189747Ssam * [1 2 2 1] for -9.6 or [1 2 1] for +16 649189747Ssam */ 650189747Ssam cur_vit_mask = 6100; 651189747Ssam upper = bin + 120; 652189747Ssam lower = bin - 120; 653189747Ssam 654189747Ssam for (i = 0; i < 123; i++) { 655189747Ssam if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 656189747Ssam if ((abs(cur_vit_mask - bin)) < 75) { 657189747Ssam mask_amt = 1; 658189747Ssam } else { 659189747Ssam mask_amt = 0; 660189747Ssam } 661189747Ssam if (cur_vit_mask < 0) { 662189747Ssam mask_m[abs(cur_vit_mask / 100)] = mask_amt; 663189747Ssam } else { 664189747Ssam mask_p[cur_vit_mask / 100] = mask_amt; 665189747Ssam } 666189747Ssam } 667189747Ssam cur_vit_mask -= 100; 668189747Ssam } 669189747Ssam 670189747Ssam tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 671189747Ssam | (mask_m[48] << 26) | (mask_m[49] << 24) 672189747Ssam | (mask_m[50] << 22) | (mask_m[51] << 20) 673189747Ssam | (mask_m[52] << 18) | (mask_m[53] << 16) 674189747Ssam | (mask_m[54] << 14) | (mask_m[55] << 12) 675189747Ssam | (mask_m[56] << 10) | (mask_m[57] << 8) 676189747Ssam | (mask_m[58] << 6) | (mask_m[59] << 4) 677189747Ssam | (mask_m[60] << 2) | (mask_m[61] << 0); 678189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 679189747Ssam OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 680189747Ssam 681189747Ssam tmp_mask = (mask_m[31] << 28) 682189747Ssam | (mask_m[32] << 26) | (mask_m[33] << 24) 683189747Ssam | (mask_m[34] << 22) | (mask_m[35] << 20) 684189747Ssam | (mask_m[36] << 18) | (mask_m[37] << 16) 685189747Ssam | (mask_m[48] << 14) | (mask_m[39] << 12) 686189747Ssam | (mask_m[40] << 10) | (mask_m[41] << 8) 687189747Ssam | (mask_m[42] << 6) | (mask_m[43] << 4) 688189747Ssam | (mask_m[44] << 2) | (mask_m[45] << 0); 689189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 690189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 691189747Ssam 692189747Ssam tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 693189747Ssam | (mask_m[18] << 26) | (mask_m[18] << 24) 694189747Ssam | (mask_m[20] << 22) | (mask_m[20] << 20) 695189747Ssam | (mask_m[22] << 18) | (mask_m[22] << 16) 696189747Ssam | (mask_m[24] << 14) | (mask_m[24] << 12) 697189747Ssam | (mask_m[25] << 10) | (mask_m[26] << 8) 698189747Ssam | (mask_m[27] << 6) | (mask_m[28] << 4) 699189747Ssam | (mask_m[29] << 2) | (mask_m[30] << 0); 700189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 701189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 702189747Ssam 703189747Ssam tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 704189747Ssam | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 705189747Ssam | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 706189747Ssam | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 707189747Ssam | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 708189747Ssam | (mask_m[10] << 10) | (mask_m[11] << 8) 709189747Ssam | (mask_m[12] << 6) | (mask_m[13] << 4) 710189747Ssam | (mask_m[14] << 2) | (mask_m[15] << 0); 711189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 712189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 713189747Ssam 714189747Ssam tmp_mask = (mask_p[15] << 28) 715189747Ssam | (mask_p[14] << 26) | (mask_p[13] << 24) 716189747Ssam | (mask_p[12] << 22) | (mask_p[11] << 20) 717189747Ssam | (mask_p[10] << 18) | (mask_p[ 9] << 16) 718189747Ssam | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 719189747Ssam | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 720189747Ssam | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 721189747Ssam | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 722189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 723189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 724189747Ssam 725189747Ssam tmp_mask = (mask_p[30] << 28) 726189747Ssam | (mask_p[29] << 26) | (mask_p[28] << 24) 727189747Ssam | (mask_p[27] << 22) | (mask_p[26] << 20) 728189747Ssam | (mask_p[25] << 18) | (mask_p[24] << 16) 729189747Ssam | (mask_p[23] << 14) | (mask_p[22] << 12) 730189747Ssam | (mask_p[21] << 10) | (mask_p[20] << 8) 731189747Ssam | (mask_p[19] << 6) | (mask_p[18] << 4) 732189747Ssam | (mask_p[17] << 2) | (mask_p[16] << 0); 733189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 734189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 735189747Ssam 736189747Ssam tmp_mask = (mask_p[45] << 28) 737189747Ssam | (mask_p[44] << 26) | (mask_p[43] << 24) 738189747Ssam | (mask_p[42] << 22) | (mask_p[41] << 20) 739189747Ssam | (mask_p[40] << 18) | (mask_p[39] << 16) 740189747Ssam | (mask_p[38] << 14) | (mask_p[37] << 12) 741189747Ssam | (mask_p[36] << 10) | (mask_p[35] << 8) 742189747Ssam | (mask_p[34] << 6) | (mask_p[33] << 4) 743189747Ssam | (mask_p[32] << 2) | (mask_p[31] << 0); 744189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 745189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 746189747Ssam 747189747Ssam tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 748189747Ssam | (mask_p[59] << 26) | (mask_p[58] << 24) 749189747Ssam | (mask_p[57] << 22) | (mask_p[56] << 20) 750189747Ssam | (mask_p[55] << 18) | (mask_p[54] << 16) 751189747Ssam | (mask_p[53] << 14) | (mask_p[52] << 12) 752189747Ssam | (mask_p[51] << 10) | (mask_p[50] << 8) 753189747Ssam | (mask_p[49] << 6) | (mask_p[48] << 4) 754189747Ssam | (mask_p[47] << 2) | (mask_p[46] << 0); 755189747Ssam OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 756189747Ssam OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 757189747Ssam} 758189747Ssam 759189747Ssam/* 760189747Ssam * Fill all software cached or static hardware state information. 761189747Ssam * Return failure if capabilities are to come from EEPROM and 762189747Ssam * cannot be read. 763189747Ssam */ 764189747Ssamstatic HAL_BOOL 765189747Ssamar9280FillCapabilityInfo(struct ath_hal *ah) 766189747Ssam{ 767189747Ssam HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps; 768189747Ssam 769189747Ssam if (!ar5416FillCapabilityInfo(ah)) 770189747Ssam return AH_FALSE; 771203882Srpaulo pCap->halNumGpioPins = 10; 772189747Ssam pCap->halWowSupport = AH_TRUE; 773189747Ssam pCap->halWowMatchPatternExact = AH_TRUE; 774189747Ssam#if 0 775189747Ssam pCap->halWowMatchPatternDword = AH_TRUE; 776189747Ssam#endif 777218150Sadrian /* AR9280 is a 2x2 stream device */ 778218150Sadrian pCap->halTxStreams = 2; 779218150Sadrian pCap->halRxStreams = 2; 780218150Sadrian 781189747Ssam pCap->halCSTSupport = AH_TRUE; 782189747Ssam pCap->halRifsRxSupport = AH_TRUE; 783189747Ssam pCap->halRifsTxSupport = AH_TRUE; 784189747Ssam pCap->halRtsAggrLimit = 64*1024; /* 802.11n max */ 785189747Ssam pCap->halExtChanDfsSupport = AH_TRUE; 786189747Ssam#if 0 787189747Ssam /* XXX bluetooth */ 788189747Ssam pCap->halBtCoexSupport = AH_TRUE; 789189747Ssam#endif 790189747Ssam pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */ 791189747Ssam pCap->hal4kbSplitTransSupport = AH_FALSE; 792220325Sadrian /* Disable this so Block-ACK works correctly */ 793220325Sadrian pCap->halHasRxSelfLinkedTail = AH_FALSE; 794221603Sadrian pCap->halMbssidAggrSupport = AH_TRUE; 795221603Sadrian pCap->hal4AddrAggrSupport = AH_TRUE; 796221603Sadrian 797221667Sadrian if (AR_SREV_MERLIN_20(ah)) { 798221603Sadrian pCap->halPSPollBroken = AH_FALSE; 799221667Sadrian /* 800221667Sadrian * This just enables the support; it doesn't 801221667Sadrian * state 5ghz fast clock will always be used. 802221667Sadrian */ 803221667Sadrian pCap->halSupportsFastClock5GHz = AH_TRUE; 804221667Sadrian } 805189747Ssam pCap->halRxStbcSupport = 1; 806189747Ssam pCap->halTxStbcSupport = 1; 807189747Ssam 808189747Ssam return AH_TRUE; 809189747Ssam} 810189747Ssam 811218708Sadrian/* 812218708Sadrian * This has been disabled - having the HAL flip chainmasks on/off 813218708Sadrian * when attempting to implement 11n disrupts things. For now, just 814218708Sadrian * leave this flipped off and worry about implementing TX diversity 815218708Sadrian * for legacy and MCS0-7 when 11n is fully functioning. 816218708Sadrian */ 817189747SsamHAL_BOOL 818189747Ssamar9280SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING settings) 819189747Ssam{ 820189747Ssam#define ANTENNA0_CHAINMASK 0x1 821189747Ssam#define ANTENNA1_CHAINMASK 0x2 822218708Sadrian#if 0 823189747Ssam struct ath_hal_5416 *ahp = AH5416(ah); 824189747Ssam 825189747Ssam /* Antenna selection is done by setting the tx/rx chainmasks approp. */ 826189747Ssam switch (settings) { 827189747Ssam case HAL_ANT_FIXED_A: 828189747Ssam /* Enable first antenna only */ 829189747Ssam ahp->ah_tx_chainmask = ANTENNA0_CHAINMASK; 830189747Ssam ahp->ah_rx_chainmask = ANTENNA0_CHAINMASK; 831189747Ssam break; 832189747Ssam case HAL_ANT_FIXED_B: 833189747Ssam /* Enable second antenna only, after checking capability */ 834189747Ssam if (AH_PRIVATE(ah)->ah_caps.halTxChainMask > ANTENNA1_CHAINMASK) 835189747Ssam ahp->ah_tx_chainmask = ANTENNA1_CHAINMASK; 836189747Ssam ahp->ah_rx_chainmask = ANTENNA1_CHAINMASK; 837189747Ssam break; 838189747Ssam case HAL_ANT_VARIABLE: 839189747Ssam /* Restore original chainmask settings */ 840189747Ssam /* XXX */ 841217641Sadrian ahp->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK; 842217641Sadrian ahp->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK; 843189747Ssam break; 844189747Ssam } 845217684Sadrian 846217684Sadrian HALDEBUG(ah, HAL_DEBUG_ANY, "%s: settings=%d, tx/rx chainmask=%d/%d\n", 847217684Sadrian __func__, settings, ahp->ah_tx_chainmask, ahp->ah_rx_chainmask); 848217684Sadrian 849218708Sadrian#endif 850189747Ssam return AH_TRUE; 851189747Ssam#undef ANTENNA0_CHAINMASK 852189747Ssam#undef ANTENNA1_CHAINMASK 853189747Ssam} 854189747Ssam 855189747Ssamstatic const char* 856189747Ssamar9280Probe(uint16_t vendorid, uint16_t devid) 857189747Ssam{ 858203882Srpaulo if (vendorid == ATHEROS_VENDOR_ID && 859203882Srpaulo (devid == AR9280_DEVID_PCI || devid == AR9280_DEVID_PCIE)) 860203882Srpaulo return "Atheros 9280"; 861189747Ssam return AH_NULL; 862189747Ssam} 863189747SsamAH_CHIP(AR9280, ar9280Probe, ar9280Attach); 864