ar5416_attach.c revision 247033
1/* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c 247033 2013-02-20 12:14:49Z adrian $ 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23#include "ah_devid.h" 24 25#include "ah_eeprom_v14.h" 26 27#include "ar5416/ar5416.h" 28#include "ar5416/ar5416reg.h" 29#include "ar5416/ar5416phy.h" 30 31#include "ar5416/ar5416.ini" 32 33static void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, 34 HAL_BOOL power_off); 35static void ar5416DisablePCIE(struct ath_hal *ah); 36static void ar5416WriteIni(struct ath_hal *ah, 37 const struct ieee80211_channel *chan); 38static void ar5416SpurMitigate(struct ath_hal *ah, 39 const struct ieee80211_channel *chan); 40 41static void 42ar5416AniSetup(struct ath_hal *ah) 43{ 44 static const struct ar5212AniParams aniparams = { 45 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 46 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 47 .coarseHigh = { -14, -14, -14, -14, -12 }, 48 .coarseLow = { -64, -64, -64, -64, -70 }, 49 .firpwr = { -78, -78, -78, -78, -80 }, 50 .maxSpurImmunityLevel = 7, 51 .cycPwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 }, 52 .maxFirstepLevel = 2, /* levels 0..2 */ 53 .firstep = { 0, 4, 8 }, 54 .ofdmTrigHigh = 500, 55 .ofdmTrigLow = 200, 56 .cckTrigHigh = 200, 57 .cckTrigLow = 100, 58 .rssiThrHigh = 40, 59 .rssiThrLow = 7, 60 .period = 100, 61 }; 62 /* NB: disable ANI noise immmunity for reliable RIFS rx */ 63 AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL); 64 ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 65} 66 67/* 68 * AR5416 doesn't do OLC or temperature compensation. 69 */ 70static void 71ar5416olcInit(struct ath_hal *ah) 72{ 73} 74 75static void 76ar5416olcTempCompensation(struct ath_hal *ah) 77{ 78} 79 80/* 81 * Attach for an AR5416 part. 82 */ 83void 84ar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc, 85 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 86{ 87 struct ath_hal_5212 *ahp; 88 struct ath_hal *ah; 89 90 ahp = &ahp5416->ah_5212; 91 ar5212InitState(ahp, devid, sc, st, sh, status); 92 ah = &ahp->ah_priv.h; 93 94 /* override 5212 methods for our needs */ 95 ah->ah_magic = AR5416_MAGIC; 96 ah->ah_getRateTable = ar5416GetRateTable; 97 ah->ah_detach = ar5416Detach; 98 99 /* Reset functions */ 100 ah->ah_reset = ar5416Reset; 101 ah->ah_phyDisable = ar5416PhyDisable; 102 ah->ah_disable = ar5416Disable; 103 ah->ah_configPCIE = ar5416ConfigPCIE; 104 ah->ah_disablePCIE = ar5416DisablePCIE; 105 ah->ah_perCalibration = ar5416PerCalibration; 106 ah->ah_perCalibrationN = ar5416PerCalibrationN, 107 ah->ah_resetCalValid = ar5416ResetCalValid, 108 ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit; 109 ah->ah_setTxPower = ar5416SetTransmitPower; 110 ah->ah_setBoardValues = ar5416SetBoardValues; 111 112 /* Transmit functions */ 113 ah->ah_stopTxDma = ar5416StopTxDma; 114 ah->ah_setupTxDesc = ar5416SetupTxDesc; 115 ah->ah_setupXTxDesc = ar5416SetupXTxDesc; 116 ah->ah_fillTxDesc = ar5416FillTxDesc; 117 ah->ah_procTxDesc = ar5416ProcTxDesc; 118 ah->ah_getTxCompletionRates = ar5416GetTxCompletionRates; 119 ah->ah_setupTxQueue = ar5416SetupTxQueue; 120 ah->ah_resetTxQueue = ar5416ResetTxQueue; 121 122 /* Receive Functions */ 123 ah->ah_getRxFilter = ar5416GetRxFilter; 124 ah->ah_setRxFilter = ar5416SetRxFilter; 125 ah->ah_stopDmaReceive = ar5416StopDmaReceive; 126 ah->ah_startPcuReceive = ar5416StartPcuReceive; 127 ah->ah_stopPcuReceive = ar5416StopPcuReceive; 128 ah->ah_setupRxDesc = ar5416SetupRxDesc; 129 ah->ah_procRxDesc = ar5416ProcRxDesc; 130 ah->ah_rxMonitor = ar5416RxMonitor; 131 ah->ah_aniPoll = ar5416AniPoll; 132 ah->ah_procMibEvent = ar5416ProcessMibIntr; 133 134 /* Misc Functions */ 135 ah->ah_getCapability = ar5416GetCapability; 136 ah->ah_setCapability = ar5416SetCapability; 137 ah->ah_getDiagState = ar5416GetDiagState; 138 ah->ah_setLedState = ar5416SetLedState; 139 ah->ah_gpioCfgOutput = ar5416GpioCfgOutput; 140 ah->ah_gpioCfgInput = ar5416GpioCfgInput; 141 ah->ah_gpioGet = ar5416GpioGet; 142 ah->ah_gpioSet = ar5416GpioSet; 143 ah->ah_gpioSetIntr = ar5416GpioSetIntr; 144 ah->ah_getTsf64 = ar5416GetTsf64; 145 ah->ah_setTsf64 = ar5416SetTsf64; 146 ah->ah_resetTsf = ar5416ResetTsf; 147 ah->ah_getRfGain = ar5416GetRfgain; 148 ah->ah_setAntennaSwitch = ar5416SetAntennaSwitch; 149 ah->ah_setDecompMask = ar5416SetDecompMask; 150 ah->ah_setCoverageClass = ar5416SetCoverageClass; 151 ah->ah_setQuiet = ar5416SetQuiet; 152 ah->ah_getMibCycleCounts = ar5416GetMibCycleCounts; 153 154 ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry; 155 ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry; 156 157 /* DFS Functions */ 158 ah->ah_enableDfs = ar5416EnableDfs; 159 ah->ah_getDfsThresh = ar5416GetDfsThresh; 160 ah->ah_getDfsDefaultThresh = ar5416GetDfsDefaultThresh; 161 ah->ah_procRadarEvent = ar5416ProcessRadarEvent; 162 ah->ah_isFastClockEnabled = ar5416IsFastClockEnabled; 163 164 /* Spectral Scan Functions */ 165 ah->ah_spectralConfigure = ar5416ConfigureSpectralScan; 166 ah->ah_spectralGetConfig = ar5416GetSpectralParams; 167 ah->ah_spectralStart = ar5416StartSpectralScan; 168 ah->ah_spectralStop = ar5416StopSpectralScan; 169 ah->ah_spectralIsEnabled = ar5416IsSpectralEnabled; 170 ah->ah_spectralIsActive = ar5416IsSpectralActive; 171 172 /* Power Management Functions */ 173 ah->ah_setPowerMode = ar5416SetPowerMode; 174 175 /* Beacon Management Functions */ 176 ah->ah_setBeaconTimers = ar5416SetBeaconTimers; 177 ah->ah_beaconInit = ar5416BeaconInit; 178 ah->ah_setStationBeaconTimers = ar5416SetStaBeaconTimers; 179 ah->ah_resetStationBeaconTimers = ar5416ResetStaBeaconTimers; 180 ah->ah_getNextTBTT = ar5416GetNextTBTT; 181 182 /* 802.11n Functions */ 183 ah->ah_chainTxDesc = ar5416ChainTxDesc; 184 ah->ah_setupFirstTxDesc = ar5416SetupFirstTxDesc; 185 ah->ah_setupLastTxDesc = ar5416SetupLastTxDesc; 186 ah->ah_set11nRateScenario = ar5416Set11nRateScenario; 187 ah->ah_set11nAggrFirst = ar5416Set11nAggrFirst; 188 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle; 189 ah->ah_set11nAggrLast = ar5416Set11nAggrLast; 190 ah->ah_clr11nAggr = ar5416Clr11nAggr; 191 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration; 192 ah->ah_get11nExtBusy = ar5416Get11nExtBusy; 193 ah->ah_set11nMac2040 = ar5416Set11nMac2040; 194 ah->ah_get11nRxClear = ar5416Get11nRxClear; 195 ah->ah_set11nRxClear = ar5416Set11nRxClear; 196 197 /* Interrupt functions */ 198 ah->ah_isInterruptPending = ar5416IsInterruptPending; 199 ah->ah_getPendingInterrupts = ar5416GetPendingInterrupts; 200 ah->ah_setInterrupts = ar5416SetInterrupts; 201 202 /* Bluetooth Coexistence functions */ 203 ah->ah_btCoexSetInfo = ar5416SetBTCoexInfo; 204 ah->ah_btCoexSetConfig = ar5416BTCoexConfig; 205 ah->ah_btCoexSetQcuThresh = ar5416BTCoexSetQcuThresh; 206 ah->ah_btCoexSetWeights = ar5416BTCoexSetWeights; 207 ah->ah_btCoexSetBmissThresh = ar5416BTCoexSetupBmissThresh; 208 ah->ah_btcoexSetParameter = ar5416BTCoexSetParameter; 209 ah->ah_btCoexDisable = ar5416BTCoexDisable; 210 ah->ah_btCoexEnable = ar5416BTCoexEnable; 211 AH5416(ah)->ah_btCoexSetDiversity = ar5416BTCoexAntennaDiversity; 212 213 ahp->ah_priv.ah_getWirelessModes= ar5416GetWirelessModes; 214 ahp->ah_priv.ah_eepromRead = ar5416EepromRead; 215#ifdef AH_SUPPORT_WRITE_EEPROM 216 ahp->ah_priv.ah_eepromWrite = ar5416EepromWrite; 217#endif 218 ahp->ah_priv.ah_getChipPowerLimits = ar5416GetChipPowerLimits; 219 220 /* Internal ops */ 221 AH5416(ah)->ah_writeIni = ar5416WriteIni; 222 AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate; 223 224 /* Internal baseband ops */ 225 AH5416(ah)->ah_initPLL = ar5416InitPLL; 226 227 /* Internal calibration ops */ 228 AH5416(ah)->ah_cal_initcal = ar5416InitCalHardware; 229 230 /* Internal TX power control related operations */ 231 AH5416(ah)->ah_olcInit = ar5416olcInit; 232 AH5416(ah)->ah_olcTempCompensation = ar5416olcTempCompensation; 233 AH5416(ah)->ah_setPowerCalTable = ar5416SetPowerCalTable; 234 235 /* 236 * Start by setting all Owl devices to 2x2 237 */ 238 AH5416(ah)->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK; 239 AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK; 240 241 /* Enable all ANI functions to begin with */ 242 AH5416(ah)->ah_ani_function = 0xffffffff; 243 244 /* Set overridable ANI methods */ 245 AH5212(ah)->ah_aniControl = ar5416AniControl; 246 247 /* Default FIFO Trigger levels */ 248#define AR_FTRIG_512B 0x00000080 // 5 bits total 249 /* AR9285/AR9271 need to use half the TX FIFOs */ 250 if (AR_SREV_KITE(ah) || AR_SREV_9271(ah)) { 251 AH5212(ah)->ah_txTrigLev = (AR_FTRIG_256B >> AR_FTRIG_S); 252 AH5212(ah)->ah_maxTxTrigLev = ((2048 / 64) - 1); 253 } else { 254 AH5212(ah)->ah_txTrigLev = (AR_FTRIG_512B >> AR_FTRIG_S); 255 AH5212(ah)->ah_maxTxTrigLev = ((4096 / 64) - 1); 256 } 257 ath_hal_printf(ah, "%s: trigLev=%d, maxTxTrigLev=%d\n", 258 __func__, 259 AH5212(ah)->ah_txTrigLev, 260 AH5212(ah)->ah_maxTxTrigLev); 261#undef AR_FTRIG_512B 262} 263 264uint32_t 265ar5416GetRadioRev(struct ath_hal *ah) 266{ 267 uint32_t val; 268 int i; 269 270 /* Read Radio Chip Rev Extract */ 271 OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058); 272 for (i = 0; i < 8; i++) 273 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 274 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 275 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 276 return ath_hal_reverseBits(val, 8); 277} 278 279/* 280 * Attach for an AR5416 part. 281 */ 282static struct ath_hal * 283ar5416Attach(uint16_t devid, HAL_SOFTC sc, 284 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 285 HAL_STATUS *status) 286{ 287 struct ath_hal_5416 *ahp5416; 288 struct ath_hal_5212 *ahp; 289 struct ath_hal *ah; 290 uint32_t val; 291 HAL_STATUS ecode; 292 HAL_BOOL rfStatus; 293 294 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 295 __func__, sc, (void*) st, (void*) sh); 296 297 /* NB: memory is returned zero'd */ 298 ahp5416 = ath_hal_malloc(sizeof (struct ath_hal_5416) + 299 /* extra space for Owl 2.1/2.2 WAR */ 300 sizeof(ar5416Addac) 301 ); 302 if (ahp5416 == AH_NULL) { 303 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 304 "%s: cannot allocate memory for state block\n", __func__); 305 *status = HAL_ENOMEM; 306 return AH_NULL; 307 } 308 ar5416InitState(ahp5416, devid, sc, st, sh, status); 309 ahp = &ahp5416->ah_5212; 310 ah = &ahp->ah_priv.h; 311 312 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 313 /* reset chip */ 314 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", __func__); 315 ecode = HAL_EIO; 316 goto bad; 317 } 318 319 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 320 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", __func__); 321 ecode = HAL_EIO; 322 goto bad; 323 } 324 /* Read Revisions from Chips before taking out of reset */ 325 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 326 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 327 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 328 AH_PRIVATE(ah)->ah_ispcie = (devid == AR5416_DEVID_PCIE); 329 330 /* setup common ini data; rf backends handle remainder */ 331 HAL_INI_INIT(&ahp->ah_ini_modes, ar5416Modes, 6); 332 HAL_INI_INIT(&ahp->ah_ini_common, ar5416Common, 2); 333 334 HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain, 3); 335 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0, 2); 336 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1, 2); 337 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2, 2); 338 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3, 3); 339 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6, 3); 340 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7, 2); 341 HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac, 2); 342 343 if (! IS_5416V2_2(ah)) { /* Owl 2.1/2.0 */ 344 ath_hal_printf(ah, "[ath] Enabling CLKDRV workaround for AR5416 < v2.2\n"); 345 struct ini { 346 uint32_t *data; /* NB: !const */ 347 int rows, cols; 348 }; 349 /* override CLKDRV value */ 350 OS_MEMCPY(&AH5416(ah)[1], ar5416Addac, sizeof(ar5416Addac)); 351 AH5416(ah)->ah_ini_addac.data = (uint32_t *) &AH5416(ah)[1]; 352 HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0; 353 } 354 355 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2); 356 ar5416AttachPCIE(ah); 357 358 ecode = ath_hal_v14EepromAttach(ah); 359 if (ecode != HAL_OK) 360 goto bad; 361 362 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 363 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", 364 __func__); 365 ecode = HAL_EIO; 366 goto bad; 367 } 368 369 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 370 371 if (!ar5212ChipTest(ah)) { 372 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 373 __func__); 374 ecode = HAL_ESELFTEST; 375 goto bad; 376 } 377 378 /* 379 * Set correct Baseband to analog shift 380 * setting to access analog chips. 381 */ 382 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 383 384 /* Read Radio Chip Rev Extract */ 385 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah); 386 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 387 case AR_RAD5122_SREV_MAJOR: /* Fowl: 5G/2x2 */ 388 case AR_RAD2122_SREV_MAJOR: /* Fowl: 2+5G/2x2 */ 389 case AR_RAD2133_SREV_MAJOR: /* Fowl: 2G/3x3 */ 390 case AR_RAD5133_SREV_MAJOR: /* Fowl: 2+5G/3x3 */ 391 break; 392 default: 393 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 394 /* 395 * When RF_Silen is used the analog chip is reset. 396 * So when the system boots with radio switch off 397 * the RF chip rev reads back as zero and we need 398 * to use the mac+phy revs to set the radio rev. 399 */ 400 AH_PRIVATE(ah)->ah_analog5GhzRev = 401 AR_RAD5133_SREV_MAJOR; 402 break; 403 } 404 /* NB: silently accept anything in release code per Atheros */ 405#ifdef AH_DEBUG 406 HALDEBUG(ah, HAL_DEBUG_ANY, 407 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 408 "this driver\n", __func__, 409 AH_PRIVATE(ah)->ah_analog5GhzRev); 410 ecode = HAL_ENOTSUPP; 411 goto bad; 412#endif 413 } 414 415 /* 416 * Got everything we need now to setup the capabilities. 417 */ 418 if (!ar5416FillCapabilityInfo(ah)) { 419 ecode = HAL_EEREAD; 420 goto bad; 421 } 422 423 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 424 if (ecode != HAL_OK) { 425 HALDEBUG(ah, HAL_DEBUG_ANY, 426 "%s: error getting mac address from EEPROM\n", __func__); 427 goto bad; 428 } 429 /* XXX How about the serial number ? */ 430 /* Read Reg Domain */ 431 AH_PRIVATE(ah)->ah_currentRD = 432 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 433 AH_PRIVATE(ah)->ah_currentRDext = 434 ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL); 435 436 /* 437 * ah_miscMode is populated by ar5416FillCapabilityInfo() 438 * starting from griffin. Set here to make sure that 439 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 440 * placed into hardware. 441 */ 442 if (ahp->ah_miscMode != 0) 443 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 444 445 rfStatus = ar2133RfAttach(ah, &ecode); 446 if (!rfStatus) { 447 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 448 __func__, ecode); 449 goto bad; 450 } 451 452 ar5416AniSetup(ah); /* Anti Noise Immunity */ 453 454 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; 455 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; 456 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; 457 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; 458 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; 459 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; 460 461 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 462 463 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 464 465 return ah; 466bad: 467 if (ahp) 468 ar5416Detach((struct ath_hal *) ahp); 469 if (status) 470 *status = ecode; 471 return AH_NULL; 472} 473 474void 475ar5416Detach(struct ath_hal *ah) 476{ 477 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 478 479 HALASSERT(ah != AH_NULL); 480 HALASSERT(ah->ah_magic == AR5416_MAGIC); 481 482 /* Make sure that chip is awake before writing to it */ 483 if (! ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 484 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 485 "%s: failed to wake up chip\n", 486 __func__); 487 488 ar5416AniDetach(ah); 489 ar5212RfDetach(ah); 490 ah->ah_disable(ah); 491 ar5416SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 492 ath_hal_eepromDetach(ah); 493 ath_hal_free(ah); 494} 495 496void 497ar5416AttachPCIE(struct ath_hal *ah) 498{ 499 if (AH_PRIVATE(ah)->ah_ispcie) 500 ath_hal_configPCIE(ah, AH_FALSE, AH_FALSE); 501 else 502 ath_hal_disablePCIE(ah); 503} 504 505static void 506ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore, HAL_BOOL power_off) 507{ 508 509 /* This is only applicable for AR5418 (AR5416 PCIe) */ 510 if (! AH_PRIVATE(ah)->ah_ispcie) 511 return; 512 513 if (! restore) { 514 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 515 OS_DELAY(1000); 516 } 517 518 if (power_off) { /* Power-off */ 519 /* clear bit 19 to disable L1 */ 520 OS_REG_CLR_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 521 } else { /* Power-on */ 522 /* Set default WAR values for Owl */ 523 OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT); 524 525 /* set bit 19 to allow forcing of pcie core into L1 state */ 526 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 527 } 528} 529 530/* 531 * Disable PCIe PHY if PCIe isn't used. 532 */ 533static void 534ar5416DisablePCIE(struct ath_hal *ah) 535{ 536 537 /* PCIe? Don't */ 538 if (AH_PRIVATE(ah)->ah_ispcie) 539 return; 540 541 /* .. Only applicable for AR5416v2 or later */ 542 if (! (AR_SREV_OWL(ah) && AR_SREV_OWL_20_OR_LATER(ah))) 543 return; 544 545 OS_REG_WRITE_BUFFER_ENABLE(ah); 546 547 /* 548 * Disable the PCIe PHY. 549 */ 550 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 551 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 552 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 553 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 554 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 555 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 556 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 557 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 558 OS_REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007); 559 560 /* Load the new settings */ 561 OS_REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000); 562 563 OS_REG_WRITE_BUFFER_FLUSH(ah); 564 OS_REG_WRITE_BUFFER_DISABLE(ah); 565} 566 567static void 568ar5416WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 569{ 570 u_int modesIndex, freqIndex; 571 int regWrites = 0; 572 573 /* Setup the indices for the next set of register array writes */ 574 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 575 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 576 freqIndex = 2; 577 if (IEEE80211_IS_CHAN_HT40(chan)) 578 modesIndex = 3; 579 else if (IEEE80211_IS_CHAN_108G(chan)) 580 modesIndex = 5; 581 else 582 modesIndex = 4; 583 } else { 584 freqIndex = 1; 585 if (IEEE80211_IS_CHAN_HT40(chan) || 586 IEEE80211_IS_CHAN_TURBO(chan)) 587 modesIndex = 2; 588 else 589 modesIndex = 1; 590 } 591 592 /* Set correct Baseband to analog shift setting to access analog chips. */ 593 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 594 595 /* 596 * Write addac shifts 597 */ 598 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 599 600 /* NB: only required for Sowl */ 601 if (AR_SREV_SOWL(ah)) 602 ar5416EepromSetAddac(ah, chan); 603 604 regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1, 605 regWrites); 606 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 607 608 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 609 modesIndex, regWrites); 610 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 611 1, regWrites); 612 613 /* XXX updated regWrites? */ 614 AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites); 615} 616 617/* 618 * Convert to baseband spur frequency given input channel frequency 619 * and compute register settings below. 620 */ 621 622static void 623ar5416SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 624{ 625 uint16_t freq = ath_hal_gethwchannel(ah, chan); 626 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 627 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 628 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 629 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 630 static const int inc[4] = { 0, 100, 0, 0 }; 631 632 int bb_spur = AR_NO_SPUR; 633 int bin, cur_bin; 634 int spur_freq_sd; 635 int spur_delta_phase; 636 int denominator; 637 int upper, lower, cur_vit_mask; 638 int tmp, new; 639 int i; 640 641 int8_t mask_m[123]; 642 int8_t mask_p[123]; 643 int8_t mask_amt; 644 int tmp_mask; 645 int cur_bb_spur; 646 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 647 648 OS_MEMZERO(mask_m, sizeof(mask_m)); 649 OS_MEMZERO(mask_p, sizeof(mask_p)); 650 651 /* 652 * Need to verify range +/- 9.5 for static ht20, otherwise spur 653 * is out-of-band and can be ignored. 654 */ 655 /* XXX ath9k changes */ 656 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 657 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 658 if (AR_NO_SPUR == cur_bb_spur) 659 break; 660 cur_bb_spur = cur_bb_spur - (freq * 10); 661 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { 662 bb_spur = cur_bb_spur; 663 break; 664 } 665 } 666 if (AR_NO_SPUR == bb_spur) 667 return; 668 669 bin = bb_spur * 32; 670 671 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 672 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 673 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 674 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 675 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 676 677 OS_REG_WRITE_BUFFER_ENABLE(ah); 678 679 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new); 680 681 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 682 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 683 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 684 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 685 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 686 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new); 687 /* 688 * Should offset bb_spur by +/- 10 MHz for dynamic 2040 MHz 689 * config, no offset for HT20. 690 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 691 * /80 for dyn2040. 692 */ 693 spur_delta_phase = ((bb_spur * 524288) / 100) & 694 AR_PHY_TIMING11_SPUR_DELTA_PHASE; 695 /* 696 * in 11A mode the denominator of spur_freq_sd should be 40 and 697 * it should be 44 in 11G 698 */ 699 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 440 : 400; 700 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; 701 702 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 703 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 704 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 705 OS_REG_WRITE(ah, AR_PHY_TIMING11, new); 706 707 708 /* 709 * ============================================ 710 * pilot mask 1 [31:0] = +6..-26, no 0 bin 711 * pilot mask 2 [19:0] = +26..+7 712 * 713 * channel mask 1 [31:0] = +6..-26, no 0 bin 714 * channel mask 2 [19:0] = +26..+7 715 */ 716 //cur_bin = -26; 717 cur_bin = -6000; 718 upper = bin + 100; 719 lower = bin - 100; 720 721 for (i = 0; i < 4; i++) { 722 int pilot_mask = 0; 723 int chan_mask = 0; 724 int bp = 0; 725 for (bp = 0; bp < 30; bp++) { 726 if ((cur_bin > lower) && (cur_bin < upper)) { 727 pilot_mask = pilot_mask | 0x1 << bp; 728 chan_mask = chan_mask | 0x1 << bp; 729 } 730 cur_bin += 100; 731 } 732 cur_bin += inc[i]; 733 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 734 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 735 } 736 737 /* ================================================= 738 * viterbi mask 1 based on channel magnitude 739 * four levels 0-3 740 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 741 * [1 2 2 1] for -9.6 or [1 2 1] for +16 742 * - enable_mask_ppm, all bins move with freq 743 * 744 * - mask_select, 8 bits for rates (reg 67,0x990c) 745 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 746 * choose which mask to use mask or mask2 747 */ 748 749 /* 750 * viterbi mask 2 2nd set for per data rate puncturing 751 * four levels 0-3 752 * - mask_select, 8 bits for rates (reg 67) 753 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 754 * [1 2 2 1] for -9.6 or [1 2 1] for +16 755 */ 756 cur_vit_mask = 6100; 757 upper = bin + 120; 758 lower = bin - 120; 759 760 for (i = 0; i < 123; i++) { 761 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 762 if ((abs(cur_vit_mask - bin)) < 75) { 763 mask_amt = 1; 764 } else { 765 mask_amt = 0; 766 } 767 if (cur_vit_mask < 0) { 768 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 769 } else { 770 mask_p[cur_vit_mask / 100] = mask_amt; 771 } 772 } 773 cur_vit_mask -= 100; 774 } 775 776 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 777 | (mask_m[48] << 26) | (mask_m[49] << 24) 778 | (mask_m[50] << 22) | (mask_m[51] << 20) 779 | (mask_m[52] << 18) | (mask_m[53] << 16) 780 | (mask_m[54] << 14) | (mask_m[55] << 12) 781 | (mask_m[56] << 10) | (mask_m[57] << 8) 782 | (mask_m[58] << 6) | (mask_m[59] << 4) 783 | (mask_m[60] << 2) | (mask_m[61] << 0); 784 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 785 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 786 787 tmp_mask = (mask_m[31] << 28) 788 | (mask_m[32] << 26) | (mask_m[33] << 24) 789 | (mask_m[34] << 22) | (mask_m[35] << 20) 790 | (mask_m[36] << 18) | (mask_m[37] << 16) 791 | (mask_m[48] << 14) | (mask_m[39] << 12) 792 | (mask_m[40] << 10) | (mask_m[41] << 8) 793 | (mask_m[42] << 6) | (mask_m[43] << 4) 794 | (mask_m[44] << 2) | (mask_m[45] << 0); 795 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 796 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 797 798 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 799 | (mask_m[18] << 26) | (mask_m[18] << 24) 800 | (mask_m[20] << 22) | (mask_m[20] << 20) 801 | (mask_m[22] << 18) | (mask_m[22] << 16) 802 | (mask_m[24] << 14) | (mask_m[24] << 12) 803 | (mask_m[25] << 10) | (mask_m[26] << 8) 804 | (mask_m[27] << 6) | (mask_m[28] << 4) 805 | (mask_m[29] << 2) | (mask_m[30] << 0); 806 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 807 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 808 809 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 810 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 811 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 812 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 813 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 814 | (mask_m[10] << 10) | (mask_m[11] << 8) 815 | (mask_m[12] << 6) | (mask_m[13] << 4) 816 | (mask_m[14] << 2) | (mask_m[15] << 0); 817 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 818 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 819 820 tmp_mask = (mask_p[15] << 28) 821 | (mask_p[14] << 26) | (mask_p[13] << 24) 822 | (mask_p[12] << 22) | (mask_p[11] << 20) 823 | (mask_p[10] << 18) | (mask_p[ 9] << 16) 824 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 825 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 826 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 827 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 828 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 829 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 830 831 tmp_mask = (mask_p[30] << 28) 832 | (mask_p[29] << 26) | (mask_p[28] << 24) 833 | (mask_p[27] << 22) | (mask_p[26] << 20) 834 | (mask_p[25] << 18) | (mask_p[24] << 16) 835 | (mask_p[23] << 14) | (mask_p[22] << 12) 836 | (mask_p[21] << 10) | (mask_p[20] << 8) 837 | (mask_p[19] << 6) | (mask_p[18] << 4) 838 | (mask_p[17] << 2) | (mask_p[16] << 0); 839 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 840 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 841 842 tmp_mask = (mask_p[45] << 28) 843 | (mask_p[44] << 26) | (mask_p[43] << 24) 844 | (mask_p[42] << 22) | (mask_p[41] << 20) 845 | (mask_p[40] << 18) | (mask_p[39] << 16) 846 | (mask_p[38] << 14) | (mask_p[37] << 12) 847 | (mask_p[36] << 10) | (mask_p[35] << 8) 848 | (mask_p[34] << 6) | (mask_p[33] << 4) 849 | (mask_p[32] << 2) | (mask_p[31] << 0); 850 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 851 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 852 853 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 854 | (mask_p[59] << 26) | (mask_p[58] << 24) 855 | (mask_p[57] << 22) | (mask_p[56] << 20) 856 | (mask_p[55] << 18) | (mask_p[54] << 16) 857 | (mask_p[53] << 14) | (mask_p[52] << 12) 858 | (mask_p[51] << 10) | (mask_p[50] << 8) 859 | (mask_p[49] << 6) | (mask_p[48] << 4) 860 | (mask_p[47] << 2) | (mask_p[46] << 0); 861 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 862 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 863 864 OS_REG_WRITE_BUFFER_FLUSH(ah); 865 OS_REG_WRITE_BUFFER_DISABLE(ah); 866} 867 868/* 869 * Fill all software cached or static hardware state information. 870 * Return failure if capabilities are to come from EEPROM and 871 * cannot be read. 872 */ 873HAL_BOOL 874ar5416FillCapabilityInfo(struct ath_hal *ah) 875{ 876 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 877 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 878 uint16_t val; 879 880 /* Construct wireless mode from EEPROM */ 881 pCap->halWirelessModes = 0; 882 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 883 pCap->halWirelessModes |= HAL_MODE_11A 884 | HAL_MODE_11NA_HT20 885 | HAL_MODE_11NA_HT40PLUS 886 | HAL_MODE_11NA_HT40MINUS 887 ; 888 } 889 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE)) { 890 pCap->halWirelessModes |= HAL_MODE_11G 891 | HAL_MODE_11NG_HT20 892 | HAL_MODE_11NG_HT40PLUS 893 | HAL_MODE_11NG_HT40MINUS 894 ; 895 pCap->halWirelessModes |= HAL_MODE_11A 896 | HAL_MODE_11NA_HT20 897 | HAL_MODE_11NA_HT40PLUS 898 | HAL_MODE_11NA_HT40MINUS 899 ; 900 } 901 902 pCap->halLow2GhzChan = 2312; 903 pCap->halHigh2GhzChan = 2732; 904 905 pCap->halLow5GhzChan = 4915; 906 pCap->halHigh5GhzChan = 6100; 907 908 pCap->halCipherCkipSupport = AH_FALSE; 909 pCap->halCipherTkipSupport = AH_TRUE; 910 pCap->halCipherAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 911 912 pCap->halMicCkipSupport = AH_FALSE; 913 pCap->halMicTkipSupport = AH_TRUE; 914 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 915 /* 916 * Starting with Griffin TX+RX mic keys can be combined 917 * in one key cache slot. 918 */ 919 pCap->halTkipMicTxRxKeySupport = AH_TRUE; 920 pCap->halChanSpreadSupport = AH_TRUE; 921 pCap->halSleepAfterBeaconBroken = AH_TRUE; 922 923 pCap->halCompressSupport = AH_FALSE; 924 pCap->halBurstSupport = AH_TRUE; 925 /* 926 * This is disabled for now; the net80211 layer needs to be 927 * taught when it is and isn't appropriate to enable FF processing 928 * with 802.11n NICs (it tries to enable both A-MPDU and 929 * fast frames, with very tragic crash-y results.) 930 */ 931 pCap->halFastFramesSupport = AH_FALSE; 932 pCap->halChapTuningSupport = AH_TRUE; 933 pCap->halTurboPrimeSupport = AH_TRUE; 934 935 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 936 937 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 938 pCap->halNumMRRetries = 4; /* Hardware supports 4 MRR */ 939 pCap->halNumTxMaps = 1; /* Single TX ptr per descr */ 940 pCap->halVEOLSupport = AH_TRUE; 941 pCap->halBssIdMaskSupport = AH_TRUE; 942 pCap->halMcastKeySrchSupport = AH_TRUE; /* Works on AR5416 and later */ 943 pCap->halTsfAddSupport = AH_TRUE; 944 pCap->hal4AddrAggrSupport = AH_FALSE; /* Broken in Owl */ 945 pCap->halSpectralScanSupport = AH_FALSE; /* AR9280 and later */ 946 947 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 948 pCap->halTotalQueues = val; 949 else 950 pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 951 952 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 953 pCap->halKeyCacheSize = val; 954 else 955 pCap->halKeyCacheSize = AR5416_KEYTABLE_SIZE; 956 957 /* XXX Which chips? */ 958 pCap->halChanHalfRate = AH_TRUE; 959 pCap->halChanQuarterRate = AH_TRUE; 960 961 pCap->halTstampPrecision = 32; 962 pCap->halHwPhyCounterSupport = AH_TRUE; 963 pCap->halIntrMask = HAL_INT_COMMON 964 | HAL_INT_RX 965 | HAL_INT_TX 966 | HAL_INT_FATAL 967 | HAL_INT_BNR 968 | HAL_INT_BMISC 969 | HAL_INT_DTIMSYNC 970 | HAL_INT_TSFOOR 971 | HAL_INT_CST 972 | HAL_INT_GTT 973 ; 974 975 pCap->halFastCCSupport = AH_TRUE; 976 pCap->halNumGpioPins = 14; 977 pCap->halWowSupport = AH_FALSE; 978 pCap->halWowMatchPatternExact = AH_FALSE; 979 pCap->halBtCoexSupport = AH_FALSE; /* XXX need support */ 980 pCap->halAutoSleepSupport = AH_FALSE; 981 pCap->hal4kbSplitTransSupport = AH_TRUE; 982 /* Disable this so Block-ACK works correctly */ 983 pCap->halHasRxSelfLinkedTail = AH_FALSE; 984#if 0 /* XXX not yet */ 985 pCap->halNumAntCfg2GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_2GHZ); 986 pCap->halNumAntCfg5GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_5GHZ); 987#endif 988 pCap->halHTSupport = AH_TRUE; 989 pCap->halTxChainMask = ath_hal_eepromGet(ah, AR_EEP_TXMASK, AH_NULL); 990 /* XXX CB71 uses GPIO 0 to indicate 3 rx chains */ 991 pCap->halRxChainMask = ath_hal_eepromGet(ah, AR_EEP_RXMASK, AH_NULL); 992 /* AR5416 may have 3 antennas but is a 2x2 stream device */ 993 pCap->halTxStreams = 2; 994 pCap->halRxStreams = 2; 995 996 /* 997 * If the TX or RX chainmask has less than 2 chains active, 998 * mark it as a 1-stream device for the relevant stream. 999 */ 1000 if (owl_get_ntxchains(pCap->halTxChainMask) == 1) 1001 pCap->halTxStreams = 1; 1002 /* XXX Eww */ 1003 if (owl_get_ntxchains(pCap->halRxChainMask) == 1) 1004 pCap->halRxStreams = 1; 1005 pCap->halRtsAggrLimit = 8*1024; /* Owl 2.0 limit */ 1006 pCap->halMbssidAggrSupport = AH_FALSE; /* Broken on Owl */ 1007 pCap->halForcePpmSupport = AH_TRUE; 1008 pCap->halEnhancedPmSupport = AH_TRUE; 1009 pCap->halBssidMatchSupport = AH_TRUE; 1010 pCap->halGTTSupport = AH_TRUE; 1011 pCap->halCSTSupport = AH_TRUE; 1012 pCap->halEnhancedDfsSupport = AH_FALSE; 1013 /* Hardware supports 32 bit TSF values in the RX descriptor */ 1014 pCap->halHasLongRxDescTsf = AH_TRUE; 1015 /* 1016 * BB Read WAR: this is only for AR5008/AR9001 NICs 1017 * It is also set individually in the AR91xx attach functions. 1018 */ 1019 if (AR_SREV_OWL(ah)) 1020 pCap->halHasBBReadWar = AH_TRUE; 1021 1022 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 1023 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 1024 /* NB: enabled by default */ 1025 ahpriv->ah_rfkillEnabled = AH_TRUE; 1026 pCap->halRfSilentSupport = AH_TRUE; 1027 } 1028 1029 /* 1030 * The MAC will mark frames as RXed if there's a descriptor 1031 * to write them to. So if it hits a self-linked final descriptor, 1032 * it'll keep ACKing frames even though they're being silently 1033 * dropped. Thus, this particular feature of the driver can't 1034 * be used for 802.11n devices. 1035 */ 1036 ahpriv->ah_rxornIsFatal = AH_FALSE; 1037 1038 /* 1039 * If it's a PCI NIC, ask the HAL OS layer to serialise 1040 * register access, or SMP machines may cause the hardware 1041 * to hang. This is applicable to AR5416 and AR9220; I'm not 1042 * sure about AR9160 or AR9227. 1043 */ 1044 if (! AH_PRIVATE(ah)->ah_ispcie) 1045 pCap->halSerialiseRegWar = 1; 1046 1047 return AH_TRUE; 1048} 1049 1050static const char* 1051ar5416Probe(uint16_t vendorid, uint16_t devid) 1052{ 1053 if (vendorid == ATHEROS_VENDOR_ID) { 1054 if (devid == AR5416_DEVID_PCI) 1055 return "Atheros 5416"; 1056 if (devid == AR5416_DEVID_PCIE) 1057 return "Atheros 5418"; 1058 } 1059 return AH_NULL; 1060} 1061AH_CHIP(AR5416, ar5416Probe, ar5416Attach); 1062