ar5416_attach.c revision 235957
170657Sobrien/* 270657Sobrien * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 370657Sobrien * Copyright (c) 2002-2008 Atheros Communications, Inc. 470657Sobrien * 570657Sobrien * Permission to use, copy, modify, and/or distribute this software for any 670657Sobrien * purpose with or without fee is hereby granted, provided that the above 770657Sobrien * copyright notice and this permission notice appear in all copies. 870657Sobrien * 970657Sobrien * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 1070657Sobrien * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 1170657Sobrien * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 1270657Sobrien * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 1370657Sobrien * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 1470657Sobrien * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 1570657Sobrien * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 1670657Sobrien * 1770657Sobrien * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c 235957 2012-05-25 02:07:59Z adrian $ 1870657Sobrien */ 1970657Sobrien#include "opt_ah.h" 2070657Sobrien 2170657Sobrien#include "ah.h" 2270657Sobrien#include "ah_internal.h" 2370657Sobrien#include "ah_devid.h" 2470657Sobrien 2570657Sobrien#include "ah_eeprom_v14.h" 2670657Sobrien 2770657Sobrien#include "ar5416/ar5416.h" 2870657Sobrien#include "ar5416/ar5416reg.h" 2970657Sobrien#include "ar5416/ar5416phy.h" 3070657Sobrien 3170657Sobrien#include "ar5416/ar5416.ini" 3270657Sobrien 3370657Sobrienstatic void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 3470657Sobrienstatic void ar5416DisablePCIE(struct ath_hal *ah); 3570657Sobrienstatic void ar5416WriteIni(struct ath_hal *ah, 3670657Sobrien const struct ieee80211_channel *chan); 3770657Sobrienstatic void ar5416SpurMitigate(struct ath_hal *ah, 3870657Sobrien const struct ieee80211_channel *chan); 3970657Sobrien 4070657Sobrienstatic void 4170657Sobrienar5416AniSetup(struct ath_hal *ah) 4270657Sobrien{ 4370657Sobrien static const struct ar5212AniParams aniparams = { 4470657Sobrien .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 4570657Sobrien .totalSizeDesired = { -55, -55, -55, -55, -62 }, 4670657Sobrien .coarseHigh = { -14, -14, -14, -14, -12 }, 4770657Sobrien .coarseLow = { -64, -64, -64, -64, -70 }, 4870657Sobrien .firpwr = { -78, -78, -78, -78, -80 }, 4970657Sobrien .maxSpurImmunityLevel = 2, 5080740Smp .cycPwrThr1 = { 2, 4, 6 }, 5180740Smp .maxFirstepLevel = 2, /* levels 0..2 */ 5280740Smp .firstep = { 0, 4, 8 }, 5370657Sobrien .ofdmTrigHigh = 500, 5470657Sobrien .ofdmTrigLow = 200, 5570657Sobrien .cckTrigHigh = 200, 5670657Sobrien .cckTrigLow = 100, 5770657Sobrien .rssiThrHigh = 40, 5870657Sobrien .rssiThrLow = 7, 5970657Sobrien .period = 100, 6070657Sobrien }; 6170657Sobrien /* NB: disable ANI noise immmunity for reliable RIFS rx */ 6270657Sobrien AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL); 6370657Sobrien ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 6470657Sobrien} 6570657Sobrien 6670657Sobrien/* 6770657Sobrien * AR5416 doesn't do OLC or temperature compensation. 6870657Sobrien */ 6970657Sobrienstatic void 7070657Sobrienar5416olcInit(struct ath_hal *ah) 7180740Smp{ 7270657Sobrien} 7370657Sobrien 7470657Sobrienstatic void 7570657Sobrienar5416olcTempCompensation(struct ath_hal *ah) 7680740Smp{ 7770657Sobrien} 7870657Sobrien 7970657Sobrien/* 8070657Sobrien * Attach for an AR5416 part. 8170657Sobrien */ 8270657Sobrienvoid 8380740Smpar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc, 8470657Sobrien HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 8570657Sobrien{ 8670657Sobrien struct ath_hal_5212 *ahp; 8770657Sobrien struct ath_hal *ah; 8870657Sobrien 8970657Sobrien ahp = &ahp5416->ah_5212; 9070657Sobrien ar5212InitState(ahp, devid, sc, st, sh, status); 9170657Sobrien ah = &ahp->ah_priv.h; 9270657Sobrien 9370657Sobrien /* override 5212 methods for our needs */ 9470657Sobrien ah->ah_magic = AR5416_MAGIC; 9570657Sobrien ah->ah_getRateTable = ar5416GetRateTable; 9670657Sobrien ah->ah_detach = ar5416Detach; 9770657Sobrien 9870657Sobrien /* Reset functions */ 9970657Sobrien ah->ah_reset = ar5416Reset; 10070657Sobrien ah->ah_phyDisable = ar5416PhyDisable; 10170657Sobrien ah->ah_disable = ar5416Disable; 10270657Sobrien ah->ah_configPCIE = ar5416ConfigPCIE; 10370657Sobrien ah->ah_disablePCIE = ar5416DisablePCIE; 10470657Sobrien ah->ah_perCalibration = ar5416PerCalibration; 10570657Sobrien ah->ah_perCalibrationN = ar5416PerCalibrationN, 10670657Sobrien ah->ah_resetCalValid = ar5416ResetCalValid, 10770657Sobrien ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit; 10870657Sobrien ah->ah_setTxPower = ar5416SetTransmitPower; 10970657Sobrien ah->ah_setBoardValues = ar5416SetBoardValues; 11070657Sobrien 11170657Sobrien /* Transmit functions */ 11270657Sobrien ah->ah_stopTxDma = ar5416StopTxDma; 11380740Smp ah->ah_setupTxDesc = ar5416SetupTxDesc; 11470657Sobrien ah->ah_setupXTxDesc = ar5416SetupXTxDesc; 11570657Sobrien ah->ah_fillTxDesc = ar5416FillTxDesc; 11670657Sobrien ah->ah_procTxDesc = ar5416ProcTxDesc; 11770657Sobrien ah->ah_getTxCompletionRates = ar5416GetTxCompletionRates; 11870657Sobrien ah->ah_setupTxQueue = ar5416SetupTxQueue; 11970657Sobrien ah->ah_resetTxQueue = ar5416ResetTxQueue; 12070657Sobrien 12170657Sobrien /* Receive Functions */ 12270657Sobrien ah->ah_getRxFilter = ar5416GetRxFilter; 12370657Sobrien ah->ah_setRxFilter = ar5416SetRxFilter; 12470657Sobrien ah->ah_stopDmaReceive = ar5416StopDmaReceive; 12570657Sobrien ah->ah_startPcuReceive = ar5416StartPcuReceive; 12670657Sobrien ah->ah_stopPcuReceive = ar5416StopPcuReceive; 12770657Sobrien ah->ah_setupRxDesc = ar5416SetupRxDesc; 12870657Sobrien ah->ah_procRxDesc = ar5416ProcRxDesc; 129 ah->ah_rxMonitor = ar5416RxMonitor; 130 ah->ah_aniPoll = ar5416AniPoll; 131 ah->ah_procMibEvent = ar5416ProcessMibIntr; 132 133 /* Misc Functions */ 134 ah->ah_getCapability = ar5416GetCapability; 135 ah->ah_setCapability = ar5416SetCapability; 136 ah->ah_getDiagState = ar5416GetDiagState; 137 ah->ah_setLedState = ar5416SetLedState; 138 ah->ah_gpioCfgOutput = ar5416GpioCfgOutput; 139 ah->ah_gpioCfgInput = ar5416GpioCfgInput; 140 ah->ah_gpioGet = ar5416GpioGet; 141 ah->ah_gpioSet = ar5416GpioSet; 142 ah->ah_gpioSetIntr = ar5416GpioSetIntr; 143 ah->ah_getTsf64 = ar5416GetTsf64; 144 ah->ah_resetTsf = ar5416ResetTsf; 145 ah->ah_getRfGain = ar5416GetRfgain; 146 ah->ah_setAntennaSwitch = ar5416SetAntennaSwitch; 147 ah->ah_setDecompMask = ar5416SetDecompMask; 148 ah->ah_setCoverageClass = ar5416SetCoverageClass; 149 ah->ah_setQuiet = ar5416SetQuiet; 150 ah->ah_getMibCycleCounts = ar5416GetMibCycleCounts; 151 152 ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry; 153 ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry; 154 155 /* DFS Functions */ 156 ah->ah_enableDfs = ar5416EnableDfs; 157 ah->ah_getDfsThresh = ar5416GetDfsThresh; 158 ah->ah_procRadarEvent = ar5416ProcessRadarEvent; 159 ah->ah_isFastClockEnabled = ar5416IsFastClockEnabled; 160 161 /* Power Management Functions */ 162 ah->ah_setPowerMode = ar5416SetPowerMode; 163 164 /* Beacon Management Functions */ 165 ah->ah_setBeaconTimers = ar5416SetBeaconTimers; 166 ah->ah_beaconInit = ar5416BeaconInit; 167 ah->ah_setStationBeaconTimers = ar5416SetStaBeaconTimers; 168 ah->ah_resetStationBeaconTimers = ar5416ResetStaBeaconTimers; 169 ah->ah_getNextTBTT = ar5416GetNextTBTT; 170 171 /* 802.11n Functions */ 172 ah->ah_chainTxDesc = ar5416ChainTxDesc; 173 ah->ah_setupFirstTxDesc = ar5416SetupFirstTxDesc; 174 ah->ah_setupLastTxDesc = ar5416SetupLastTxDesc; 175 ah->ah_set11nRateScenario = ar5416Set11nRateScenario; 176 ah->ah_set11nAggrFirst = ar5416Set11nAggrFirst; 177 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle; 178 ah->ah_set11nAggrLast = ar5416Set11nAggrLast; 179 ah->ah_clr11nAggr = ar5416Clr11nAggr; 180 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration; 181 ah->ah_get11nExtBusy = ar5416Get11nExtBusy; 182 ah->ah_set11nMac2040 = ar5416Set11nMac2040; 183 ah->ah_get11nRxClear = ar5416Get11nRxClear; 184 ah->ah_set11nRxClear = ar5416Set11nRxClear; 185 186 /* Interrupt functions */ 187 ah->ah_isInterruptPending = ar5416IsInterruptPending; 188 ah->ah_getPendingInterrupts = ar5416GetPendingInterrupts; 189 ah->ah_setInterrupts = ar5416SetInterrupts; 190 191 ahp->ah_priv.ah_getWirelessModes= ar5416GetWirelessModes; 192 ahp->ah_priv.ah_eepromRead = ar5416EepromRead; 193#ifdef AH_SUPPORT_WRITE_EEPROM 194 ahp->ah_priv.ah_eepromWrite = ar5416EepromWrite; 195#endif 196 ahp->ah_priv.ah_getChipPowerLimits = ar5416GetChipPowerLimits; 197 198 /* Internal ops */ 199 AH5416(ah)->ah_writeIni = ar5416WriteIni; 200 AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate; 201 202 /* Internal baseband ops */ 203 AH5416(ah)->ah_initPLL = ar5416InitPLL; 204 205 /* Internal calibration ops */ 206 AH5416(ah)->ah_cal_initcal = ar5416InitCalHardware; 207 208 /* Internal TX power control related operations */ 209 AH5416(ah)->ah_olcInit = ar5416olcInit; 210 AH5416(ah)->ah_olcTempCompensation = ar5416olcTempCompensation; 211 AH5416(ah)->ah_setPowerCalTable = ar5416SetPowerCalTable; 212 213 /* 214 * Start by setting all Owl devices to 2x2 215 */ 216 AH5416(ah)->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK; 217 AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK; 218 219 /* Enable all ANI functions to begin with */ 220 AH5416(ah)->ah_ani_function = 0xffffffff; 221 222 /* Set overridable ANI methods */ 223 AH5212(ah)->ah_aniControl = ar5416AniControl; 224} 225 226uint32_t 227ar5416GetRadioRev(struct ath_hal *ah) 228{ 229 uint32_t val; 230 int i; 231 232 /* Read Radio Chip Rev Extract */ 233 OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058); 234 for (i = 0; i < 8; i++) 235 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 236 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 237 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 238 return ath_hal_reverseBits(val, 8); 239} 240 241/* 242 * Attach for an AR5416 part. 243 */ 244static struct ath_hal * 245ar5416Attach(uint16_t devid, HAL_SOFTC sc, 246 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 247 HAL_STATUS *status) 248{ 249 struct ath_hal_5416 *ahp5416; 250 struct ath_hal_5212 *ahp; 251 struct ath_hal *ah; 252 uint32_t val; 253 HAL_STATUS ecode; 254 HAL_BOOL rfStatus; 255 256 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 257 __func__, sc, (void*) st, (void*) sh); 258 259 /* NB: memory is returned zero'd */ 260 ahp5416 = ath_hal_malloc(sizeof (struct ath_hal_5416) + 261 /* extra space for Owl 2.1/2.2 WAR */ 262 sizeof(ar5416Addac) 263 ); 264 if (ahp5416 == AH_NULL) { 265 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 266 "%s: cannot allocate memory for state block\n", __func__); 267 *status = HAL_ENOMEM; 268 return AH_NULL; 269 } 270 ar5416InitState(ahp5416, devid, sc, st, sh, status); 271 ahp = &ahp5416->ah_5212; 272 ah = &ahp->ah_priv.h; 273 274 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 275 /* reset chip */ 276 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", __func__); 277 ecode = HAL_EIO; 278 goto bad; 279 } 280 281 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 282 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", __func__); 283 ecode = HAL_EIO; 284 goto bad; 285 } 286 /* Read Revisions from Chips before taking out of reset */ 287 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 288 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 289 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 290 AH_PRIVATE(ah)->ah_ispcie = (devid == AR5416_DEVID_PCIE); 291 292 /* setup common ini data; rf backends handle remainder */ 293 HAL_INI_INIT(&ahp->ah_ini_modes, ar5416Modes, 6); 294 HAL_INI_INIT(&ahp->ah_ini_common, ar5416Common, 2); 295 296 HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain, 3); 297 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0, 2); 298 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1, 2); 299 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2, 2); 300 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3, 3); 301 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6, 3); 302 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7, 2); 303 HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac, 2); 304 305 if (! IS_5416V2_2(ah)) { /* Owl 2.1/2.0 */ 306 ath_hal_printf(ah, "[ath] Enabling CLKDRV workaround for AR5416 < v2.2\n"); 307 struct ini { 308 uint32_t *data; /* NB: !const */ 309 int rows, cols; 310 }; 311 /* override CLKDRV value */ 312 OS_MEMCPY(&AH5416(ah)[1], ar5416Addac, sizeof(ar5416Addac)); 313 AH5416(ah)->ah_ini_addac.data = (uint32_t *) &AH5416(ah)[1]; 314 HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0; 315 } 316 317 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2); 318 ar5416AttachPCIE(ah); 319 320 ecode = ath_hal_v14EepromAttach(ah); 321 if (ecode != HAL_OK) 322 goto bad; 323 324 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 325 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", 326 __func__); 327 ecode = HAL_EIO; 328 goto bad; 329 } 330 331 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 332 333 if (!ar5212ChipTest(ah)) { 334 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 335 __func__); 336 ecode = HAL_ESELFTEST; 337 goto bad; 338 } 339 340 /* 341 * Set correct Baseband to analog shift 342 * setting to access analog chips. 343 */ 344 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 345 346 /* Read Radio Chip Rev Extract */ 347 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5416GetRadioRev(ah); 348 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 349 case AR_RAD5122_SREV_MAJOR: /* Fowl: 5G/2x2 */ 350 case AR_RAD2122_SREV_MAJOR: /* Fowl: 2+5G/2x2 */ 351 case AR_RAD2133_SREV_MAJOR: /* Fowl: 2G/3x3 */ 352 case AR_RAD5133_SREV_MAJOR: /* Fowl: 2+5G/3x3 */ 353 break; 354 default: 355 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 356 /* 357 * When RF_Silen is used the analog chip is reset. 358 * So when the system boots with radio switch off 359 * the RF chip rev reads back as zero and we need 360 * to use the mac+phy revs to set the radio rev. 361 */ 362 AH_PRIVATE(ah)->ah_analog5GhzRev = 363 AR_RAD5133_SREV_MAJOR; 364 break; 365 } 366 /* NB: silently accept anything in release code per Atheros */ 367#ifdef AH_DEBUG 368 HALDEBUG(ah, HAL_DEBUG_ANY, 369 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 370 "this driver\n", __func__, 371 AH_PRIVATE(ah)->ah_analog5GhzRev); 372 ecode = HAL_ENOTSUPP; 373 goto bad; 374#endif 375 } 376 377 /* 378 * Got everything we need now to setup the capabilities. 379 */ 380 if (!ar5416FillCapabilityInfo(ah)) { 381 ecode = HAL_EEREAD; 382 goto bad; 383 } 384 385 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 386 if (ecode != HAL_OK) { 387 HALDEBUG(ah, HAL_DEBUG_ANY, 388 "%s: error getting mac address from EEPROM\n", __func__); 389 goto bad; 390 } 391 /* XXX How about the serial number ? */ 392 /* Read Reg Domain */ 393 AH_PRIVATE(ah)->ah_currentRD = 394 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 395 AH_PRIVATE(ah)->ah_currentRDext = 396 ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL); 397 398 /* 399 * ah_miscMode is populated by ar5416FillCapabilityInfo() 400 * starting from griffin. Set here to make sure that 401 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 402 * placed into hardware. 403 */ 404 if (ahp->ah_miscMode != 0) 405 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 406 407 rfStatus = ar2133RfAttach(ah, &ecode); 408 if (!rfStatus) { 409 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 410 __func__, ecode); 411 goto bad; 412 } 413 414 ar5416AniSetup(ah); /* Anti Noise Immunity */ 415 416 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; 417 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; 418 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; 419 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; 420 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; 421 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; 422 423 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 424 425 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 426 427 return ah; 428bad: 429 if (ahp) 430 ar5416Detach((struct ath_hal *) ahp); 431 if (status) 432 *status = ecode; 433 return AH_NULL; 434} 435 436void 437ar5416Detach(struct ath_hal *ah) 438{ 439 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 440 441 HALASSERT(ah != AH_NULL); 442 HALASSERT(ah->ah_magic == AR5416_MAGIC); 443 444 /* Make sure that chip is awake before writing to it */ 445 if (! ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 446 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 447 "%s: failed to wake up chip\n", 448 __func__); 449 450 ar5416AniDetach(ah); 451 ar5212RfDetach(ah); 452 ah->ah_disable(ah); 453 ar5416SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 454 ath_hal_eepromDetach(ah); 455 ath_hal_free(ah); 456} 457 458void 459ar5416AttachPCIE(struct ath_hal *ah) 460{ 461 if (AH_PRIVATE(ah)->ah_ispcie) 462 ath_hal_configPCIE(ah, AH_FALSE); 463 else 464 ath_hal_disablePCIE(ah); 465} 466 467static void 468ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 469{ 470 if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 471 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 472 OS_DELAY(1000); 473 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 474 OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT); 475 } 476} 477 478static void 479ar5416DisablePCIE(struct ath_hal *ah) 480{ 481 /* XXX TODO */ 482} 483 484static void 485ar5416WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 486{ 487 u_int modesIndex, freqIndex; 488 int regWrites = 0; 489 490 /* Setup the indices for the next set of register array writes */ 491 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 492 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 493 freqIndex = 2; 494 if (IEEE80211_IS_CHAN_HT40(chan)) 495 modesIndex = 3; 496 else if (IEEE80211_IS_CHAN_108G(chan)) 497 modesIndex = 5; 498 else 499 modesIndex = 4; 500 } else { 501 freqIndex = 1; 502 if (IEEE80211_IS_CHAN_HT40(chan) || 503 IEEE80211_IS_CHAN_TURBO(chan)) 504 modesIndex = 2; 505 else 506 modesIndex = 1; 507 } 508 509 /* Set correct Baseband to analog shift setting to access analog chips. */ 510 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 511 512 /* 513 * Write addac shifts 514 */ 515 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 516 517 /* NB: only required for Sowl */ 518 if (AR_SREV_SOWL(ah)) 519 ar5416EepromSetAddac(ah, chan); 520 521 regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1, 522 regWrites); 523 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 524 525 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 526 modesIndex, regWrites); 527 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 528 1, regWrites); 529 530 /* XXX updated regWrites? */ 531 AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites); 532} 533 534/* 535 * Convert to baseband spur frequency given input channel frequency 536 * and compute register settings below. 537 */ 538 539static void 540ar5416SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 541{ 542 uint16_t freq = ath_hal_gethwchannel(ah, chan); 543 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 544 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 545 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 546 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 547 static const int inc[4] = { 0, 100, 0, 0 }; 548 549 int bb_spur = AR_NO_SPUR; 550 int bin, cur_bin; 551 int spur_freq_sd; 552 int spur_delta_phase; 553 int denominator; 554 int upper, lower, cur_vit_mask; 555 int tmp, new; 556 int i; 557 558 int8_t mask_m[123]; 559 int8_t mask_p[123]; 560 int8_t mask_amt; 561 int tmp_mask; 562 int cur_bb_spur; 563 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 564 565 OS_MEMZERO(mask_m, sizeof(mask_m)); 566 OS_MEMZERO(mask_p, sizeof(mask_p)); 567 568 /* 569 * Need to verify range +/- 9.5 for static ht20, otherwise spur 570 * is out-of-band and can be ignored. 571 */ 572 /* XXX ath9k changes */ 573 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 574 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 575 if (AR_NO_SPUR == cur_bb_spur) 576 break; 577 cur_bb_spur = cur_bb_spur - (freq * 10); 578 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { 579 bb_spur = cur_bb_spur; 580 break; 581 } 582 } 583 if (AR_NO_SPUR == bb_spur) 584 return; 585 586 bin = bb_spur * 32; 587 588 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 589 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 590 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 591 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 592 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 593 594 OS_REG_WRITE_BUFFER_ENABLE(ah); 595 596 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new); 597 598 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 599 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 600 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 601 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 602 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 603 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new); 604 /* 605 * Should offset bb_spur by +/- 10 MHz for dynamic 2040 MHz 606 * config, no offset for HT20. 607 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 608 * /80 for dyn2040. 609 */ 610 spur_delta_phase = ((bb_spur * 524288) / 100) & 611 AR_PHY_TIMING11_SPUR_DELTA_PHASE; 612 /* 613 * in 11A mode the denominator of spur_freq_sd should be 40 and 614 * it should be 44 in 11G 615 */ 616 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 440 : 400; 617 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; 618 619 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 620 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 621 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 622 OS_REG_WRITE(ah, AR_PHY_TIMING11, new); 623 624 625 /* 626 * ============================================ 627 * pilot mask 1 [31:0] = +6..-26, no 0 bin 628 * pilot mask 2 [19:0] = +26..+7 629 * 630 * channel mask 1 [31:0] = +6..-26, no 0 bin 631 * channel mask 2 [19:0] = +26..+7 632 */ 633 //cur_bin = -26; 634 cur_bin = -6000; 635 upper = bin + 100; 636 lower = bin - 100; 637 638 for (i = 0; i < 4; i++) { 639 int pilot_mask = 0; 640 int chan_mask = 0; 641 int bp = 0; 642 for (bp = 0; bp < 30; bp++) { 643 if ((cur_bin > lower) && (cur_bin < upper)) { 644 pilot_mask = pilot_mask | 0x1 << bp; 645 chan_mask = chan_mask | 0x1 << bp; 646 } 647 cur_bin += 100; 648 } 649 cur_bin += inc[i]; 650 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 651 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 652 } 653 654 /* ================================================= 655 * viterbi mask 1 based on channel magnitude 656 * four levels 0-3 657 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 658 * [1 2 2 1] for -9.6 or [1 2 1] for +16 659 * - enable_mask_ppm, all bins move with freq 660 * 661 * - mask_select, 8 bits for rates (reg 67,0x990c) 662 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 663 * choose which mask to use mask or mask2 664 */ 665 666 /* 667 * viterbi mask 2 2nd set for per data rate puncturing 668 * four levels 0-3 669 * - mask_select, 8 bits for rates (reg 67) 670 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 671 * [1 2 2 1] for -9.6 or [1 2 1] for +16 672 */ 673 cur_vit_mask = 6100; 674 upper = bin + 120; 675 lower = bin - 120; 676 677 for (i = 0; i < 123; i++) { 678 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 679 if ((abs(cur_vit_mask - bin)) < 75) { 680 mask_amt = 1; 681 } else { 682 mask_amt = 0; 683 } 684 if (cur_vit_mask < 0) { 685 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 686 } else { 687 mask_p[cur_vit_mask / 100] = mask_amt; 688 } 689 } 690 cur_vit_mask -= 100; 691 } 692 693 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 694 | (mask_m[48] << 26) | (mask_m[49] << 24) 695 | (mask_m[50] << 22) | (mask_m[51] << 20) 696 | (mask_m[52] << 18) | (mask_m[53] << 16) 697 | (mask_m[54] << 14) | (mask_m[55] << 12) 698 | (mask_m[56] << 10) | (mask_m[57] << 8) 699 | (mask_m[58] << 6) | (mask_m[59] << 4) 700 | (mask_m[60] << 2) | (mask_m[61] << 0); 701 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 702 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 703 704 tmp_mask = (mask_m[31] << 28) 705 | (mask_m[32] << 26) | (mask_m[33] << 24) 706 | (mask_m[34] << 22) | (mask_m[35] << 20) 707 | (mask_m[36] << 18) | (mask_m[37] << 16) 708 | (mask_m[48] << 14) | (mask_m[39] << 12) 709 | (mask_m[40] << 10) | (mask_m[41] << 8) 710 | (mask_m[42] << 6) | (mask_m[43] << 4) 711 | (mask_m[44] << 2) | (mask_m[45] << 0); 712 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 713 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 714 715 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 716 | (mask_m[18] << 26) | (mask_m[18] << 24) 717 | (mask_m[20] << 22) | (mask_m[20] << 20) 718 | (mask_m[22] << 18) | (mask_m[22] << 16) 719 | (mask_m[24] << 14) | (mask_m[24] << 12) 720 | (mask_m[25] << 10) | (mask_m[26] << 8) 721 | (mask_m[27] << 6) | (mask_m[28] << 4) 722 | (mask_m[29] << 2) | (mask_m[30] << 0); 723 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 724 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 725 726 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 727 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 728 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 729 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 730 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 731 | (mask_m[10] << 10) | (mask_m[11] << 8) 732 | (mask_m[12] << 6) | (mask_m[13] << 4) 733 | (mask_m[14] << 2) | (mask_m[15] << 0); 734 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 735 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 736 737 tmp_mask = (mask_p[15] << 28) 738 | (mask_p[14] << 26) | (mask_p[13] << 24) 739 | (mask_p[12] << 22) | (mask_p[11] << 20) 740 | (mask_p[10] << 18) | (mask_p[ 9] << 16) 741 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 742 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 743 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 744 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 745 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 746 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 747 748 tmp_mask = (mask_p[30] << 28) 749 | (mask_p[29] << 26) | (mask_p[28] << 24) 750 | (mask_p[27] << 22) | (mask_p[26] << 20) 751 | (mask_p[25] << 18) | (mask_p[24] << 16) 752 | (mask_p[23] << 14) | (mask_p[22] << 12) 753 | (mask_p[21] << 10) | (mask_p[20] << 8) 754 | (mask_p[19] << 6) | (mask_p[18] << 4) 755 | (mask_p[17] << 2) | (mask_p[16] << 0); 756 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 757 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 758 759 tmp_mask = (mask_p[45] << 28) 760 | (mask_p[44] << 26) | (mask_p[43] << 24) 761 | (mask_p[42] << 22) | (mask_p[41] << 20) 762 | (mask_p[40] << 18) | (mask_p[39] << 16) 763 | (mask_p[38] << 14) | (mask_p[37] << 12) 764 | (mask_p[36] << 10) | (mask_p[35] << 8) 765 | (mask_p[34] << 6) | (mask_p[33] << 4) 766 | (mask_p[32] << 2) | (mask_p[31] << 0); 767 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 768 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 769 770 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 771 | (mask_p[59] << 26) | (mask_p[58] << 24) 772 | (mask_p[57] << 22) | (mask_p[56] << 20) 773 | (mask_p[55] << 18) | (mask_p[54] << 16) 774 | (mask_p[53] << 14) | (mask_p[52] << 12) 775 | (mask_p[51] << 10) | (mask_p[50] << 8) 776 | (mask_p[49] << 6) | (mask_p[48] << 4) 777 | (mask_p[47] << 2) | (mask_p[46] << 0); 778 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 779 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 780 781 OS_REG_WRITE_BUFFER_FLUSH(ah); 782 OS_REG_WRITE_BUFFER_DISABLE(ah); 783} 784 785/* 786 * Fill all software cached or static hardware state information. 787 * Return failure if capabilities are to come from EEPROM and 788 * cannot be read. 789 */ 790HAL_BOOL 791ar5416FillCapabilityInfo(struct ath_hal *ah) 792{ 793 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 794 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 795 uint16_t val; 796 797 /* Construct wireless mode from EEPROM */ 798 pCap->halWirelessModes = 0; 799 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 800 pCap->halWirelessModes |= HAL_MODE_11A 801 | HAL_MODE_11NA_HT20 802 | HAL_MODE_11NA_HT40PLUS 803 | HAL_MODE_11NA_HT40MINUS 804 ; 805 } 806 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE)) { 807 pCap->halWirelessModes |= HAL_MODE_11G 808 | HAL_MODE_11NG_HT20 809 | HAL_MODE_11NG_HT40PLUS 810 | HAL_MODE_11NG_HT40MINUS 811 ; 812 pCap->halWirelessModes |= HAL_MODE_11A 813 | HAL_MODE_11NA_HT20 814 | HAL_MODE_11NA_HT40PLUS 815 | HAL_MODE_11NA_HT40MINUS 816 ; 817 } 818 819 pCap->halLow2GhzChan = 2312; 820 pCap->halHigh2GhzChan = 2732; 821 822 pCap->halLow5GhzChan = 4915; 823 pCap->halHigh5GhzChan = 6100; 824 825 pCap->halCipherCkipSupport = AH_FALSE; 826 pCap->halCipherTkipSupport = AH_TRUE; 827 pCap->halCipherAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 828 829 pCap->halMicCkipSupport = AH_FALSE; 830 pCap->halMicTkipSupport = AH_TRUE; 831 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 832 /* 833 * Starting with Griffin TX+RX mic keys can be combined 834 * in one key cache slot. 835 */ 836 pCap->halTkipMicTxRxKeySupport = AH_TRUE; 837 pCap->halChanSpreadSupport = AH_TRUE; 838 pCap->halSleepAfterBeaconBroken = AH_TRUE; 839 840 pCap->halCompressSupport = AH_FALSE; 841 pCap->halBurstSupport = AH_TRUE; 842 pCap->halFastFramesSupport = AH_FALSE; /* XXX? */ 843 pCap->halChapTuningSupport = AH_TRUE; 844 pCap->halTurboPrimeSupport = AH_TRUE; 845 846 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 847 848 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 849 pCap->halVEOLSupport = AH_TRUE; 850 pCap->halBssIdMaskSupport = AH_TRUE; 851 pCap->halMcastKeySrchSupport = AH_TRUE; /* Works on AR5416 and later */ 852 pCap->halTsfAddSupport = AH_TRUE; 853 pCap->hal4AddrAggrSupport = AH_FALSE; /* Broken in Owl */ 854 855 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 856 pCap->halTotalQueues = val; 857 else 858 pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 859 860 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 861 pCap->halKeyCacheSize = val; 862 else 863 pCap->halKeyCacheSize = AR5416_KEYTABLE_SIZE; 864 865 /* XXX not needed */ 866 pCap->halChanHalfRate = AH_FALSE; /* XXX ? */ 867 pCap->halChanQuarterRate = AH_FALSE; /* XXX ? */ 868 869 pCap->halTstampPrecision = 32; 870 pCap->halHwPhyCounterSupport = AH_TRUE; 871 pCap->halIntrMask = HAL_INT_COMMON 872 | HAL_INT_RX 873 | HAL_INT_TX 874 | HAL_INT_FATAL 875 | HAL_INT_BNR 876 | HAL_INT_BMISC 877 | HAL_INT_DTIMSYNC 878 | HAL_INT_TSFOOR 879 | HAL_INT_CST 880 | HAL_INT_GTT 881 ; 882 883 pCap->halFastCCSupport = AH_TRUE; 884 pCap->halNumGpioPins = 14; 885 pCap->halWowSupport = AH_FALSE; 886 pCap->halWowMatchPatternExact = AH_FALSE; 887 pCap->halBtCoexSupport = AH_FALSE; /* XXX need support */ 888 pCap->halAutoSleepSupport = AH_FALSE; 889 pCap->hal4kbSplitTransSupport = AH_TRUE; 890 /* Disable this so Block-ACK works correctly */ 891 pCap->halHasRxSelfLinkedTail = AH_FALSE; 892#if 0 /* XXX not yet */ 893 pCap->halNumAntCfg2GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_2GHZ); 894 pCap->halNumAntCfg5GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_5GHZ); 895#endif 896 pCap->halHTSupport = AH_TRUE; 897 pCap->halTxChainMask = ath_hal_eepromGet(ah, AR_EEP_TXMASK, AH_NULL); 898 /* XXX CB71 uses GPIO 0 to indicate 3 rx chains */ 899 pCap->halRxChainMask = ath_hal_eepromGet(ah, AR_EEP_RXMASK, AH_NULL); 900 /* AR5416 may have 3 antennas but is a 2x2 stream device */ 901 pCap->halTxStreams = 2; 902 pCap->halRxStreams = 2; 903 904 /* 905 * If the TX or RX chainmask has less than 2 chains active, 906 * mark it as a 1-stream device for the relevant stream. 907 */ 908 if (owl_get_ntxchains(pCap->halTxChainMask) == 1) 909 pCap->halTxStreams = 1; 910 /* XXX Eww */ 911 if (owl_get_ntxchains(pCap->halRxChainMask) == 1) 912 pCap->halRxStreams = 1; 913 pCap->halRtsAggrLimit = 8*1024; /* Owl 2.0 limit */ 914 pCap->halMbssidAggrSupport = AH_FALSE; /* Broken on Owl */ 915 pCap->halForcePpmSupport = AH_TRUE; 916 pCap->halEnhancedPmSupport = AH_TRUE; 917 pCap->halBssidMatchSupport = AH_TRUE; 918 pCap->halGTTSupport = AH_TRUE; 919 pCap->halCSTSupport = AH_TRUE; 920 pCap->halEnhancedDfsSupport = AH_FALSE; 921 /* Hardware supports 32 bit TSF values in the RX descriptor */ 922 pCap->halHasLongRxDescTsf = AH_TRUE; 923 /* 924 * BB Read WAR: this is only for AR5008/AR9001 NICs 925 * It is also set individually in the AR91xx attach functions. 926 */ 927 if (AR_SREV_OWL(ah)) 928 pCap->halHasBBReadWar = AH_TRUE; 929 930 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 931 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 932 /* NB: enabled by default */ 933 ahpriv->ah_rfkillEnabled = AH_TRUE; 934 pCap->halRfSilentSupport = AH_TRUE; 935 } 936 937 /* 938 * The MAC will mark frames as RXed if there's a descriptor 939 * to write them to. So if it hits a self-linked final descriptor, 940 * it'll keep ACKing frames even though they're being silently 941 * dropped. Thus, this particular feature of the driver can't 942 * be used for 802.11n devices. 943 */ 944 ahpriv->ah_rxornIsFatal = AH_FALSE; 945 946 /* 947 * If it's a PCI NIC, ask the HAL OS layer to serialise 948 * register access, or SMP machines may cause the hardware 949 * to hang. This is applicable to AR5416 and AR9220; I'm not 950 * sure about AR9160 or AR9227. 951 */ 952 if (! AH_PRIVATE(ah)->ah_ispcie) 953 pCap->halSerialiseRegWar = 1; 954 955 return AH_TRUE; 956} 957 958static const char* 959ar5416Probe(uint16_t vendorid, uint16_t devid) 960{ 961 if (vendorid == ATHEROS_VENDOR_ID) { 962 if (devid == AR5416_DEVID_PCI) 963 return "Atheros 5416"; 964 if (devid == AR5416_DEVID_PCIE) 965 return "Atheros 5418"; 966 } 967 return AH_NULL; 968} 969AH_CHIP(AR5416, ar5416Probe, ar5416Attach); 970