ar5416_attach.c revision 224512
1/* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c 224512 2011-07-30 13:25:11Z adrian $ 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23#include "ah_devid.h" 24 25#include "ah_eeprom_v14.h" 26 27#include "ar5416/ar5416.h" 28#include "ar5416/ar5416reg.h" 29#include "ar5416/ar5416phy.h" 30 31#include "ar5416/ar5416.ini" 32 33static void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 34static void ar5416WriteIni(struct ath_hal *ah, 35 const struct ieee80211_channel *chan); 36static void ar5416SpurMitigate(struct ath_hal *ah, 37 const struct ieee80211_channel *chan); 38 39static void 40ar5416AniSetup(struct ath_hal *ah) 41{ 42 static const struct ar5212AniParams aniparams = { 43 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 44 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 45 .coarseHigh = { -14, -14, -14, -14, -12 }, 46 .coarseLow = { -64, -64, -64, -64, -70 }, 47 .firpwr = { -78, -78, -78, -78, -80 }, 48 .maxSpurImmunityLevel = 2, 49 .cycPwrThr1 = { 2, 4, 6 }, 50 .maxFirstepLevel = 2, /* levels 0..2 */ 51 .firstep = { 0, 4, 8 }, 52 .ofdmTrigHigh = 500, 53 .ofdmTrigLow = 200, 54 .cckTrigHigh = 200, 55 .cckTrigLow = 100, 56 .rssiThrHigh = 40, 57 .rssiThrLow = 7, 58 .period = 100, 59 }; 60 /* NB: disable ANI noise immmunity for reliable RIFS rx */ 61 AH5416(ah)->ah_ani_function &= ~(1 << HAL_ANI_NOISE_IMMUNITY_LEVEL); 62 ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 63} 64 65/* 66 * AR5416 doesn't do OLC or temperature compensation. 67 */ 68static void 69ar5416olcInit(struct ath_hal *ah) 70{ 71} 72 73static void 74ar5416olcTempCompensation(struct ath_hal *ah) 75{ 76} 77 78/* 79 * Attach for an AR5416 part. 80 */ 81void 82ar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc, 83 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 84{ 85 struct ath_hal_5212 *ahp; 86 struct ath_hal *ah; 87 88 ahp = &ahp5416->ah_5212; 89 ar5212InitState(ahp, devid, sc, st, sh, status); 90 ah = &ahp->ah_priv.h; 91 92 /* override 5212 methods for our needs */ 93 ah->ah_magic = AR5416_MAGIC; 94 ah->ah_getRateTable = ar5416GetRateTable; 95 ah->ah_detach = ar5416Detach; 96 97 /* Reset functions */ 98 ah->ah_reset = ar5416Reset; 99 ah->ah_phyDisable = ar5416PhyDisable; 100 ah->ah_disable = ar5416Disable; 101 ah->ah_configPCIE = ar5416ConfigPCIE; 102 ah->ah_perCalibration = ar5416PerCalibration; 103 ah->ah_perCalibrationN = ar5416PerCalibrationN, 104 ah->ah_resetCalValid = ar5416ResetCalValid, 105 ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit; 106 ah->ah_setTxPower = ar5416SetTransmitPower; 107 ah->ah_setBoardValues = ar5416SetBoardValues; 108 109 /* Transmit functions */ 110 ah->ah_stopTxDma = ar5416StopTxDma; 111 ah->ah_setupTxDesc = ar5416SetupTxDesc; 112 ah->ah_setupXTxDesc = ar5416SetupXTxDesc; 113 ah->ah_fillTxDesc = ar5416FillTxDesc; 114 ah->ah_procTxDesc = ar5416ProcTxDesc; 115 ah->ah_getTxCompletionRates = ar5416GetTxCompletionRates; 116 ah->ah_setupTxQueue = ar5416SetupTxQueue; 117 ah->ah_resetTxQueue = ar5416ResetTxQueue; 118 119 /* Receive Functions */ 120 ah->ah_getRxFilter = ar5416GetRxFilter; 121 ah->ah_setRxFilter = ar5416SetRxFilter; 122 ah->ah_startPcuReceive = ar5416StartPcuReceive; 123 ah->ah_stopPcuReceive = ar5416StopPcuReceive; 124 ah->ah_setupRxDesc = ar5416SetupRxDesc; 125 ah->ah_procRxDesc = ar5416ProcRxDesc; 126 ah->ah_rxMonitor = ar5416RxMonitor; 127 ah->ah_aniPoll = ar5416AniPoll; 128 ah->ah_procMibEvent = ar5416ProcessMibIntr; 129 130 /* Misc Functions */ 131 ah->ah_getCapability = ar5416GetCapability; 132 ah->ah_getDiagState = ar5416GetDiagState; 133 ah->ah_setLedState = ar5416SetLedState; 134 ah->ah_gpioCfgOutput = ar5416GpioCfgOutput; 135 ah->ah_gpioCfgInput = ar5416GpioCfgInput; 136 ah->ah_gpioGet = ar5416GpioGet; 137 ah->ah_gpioSet = ar5416GpioSet; 138 ah->ah_gpioSetIntr = ar5416GpioSetIntr; 139 ah->ah_resetTsf = ar5416ResetTsf; 140 ah->ah_getRfGain = ar5416GetRfgain; 141 ah->ah_setAntennaSwitch = ar5416SetAntennaSwitch; 142 ah->ah_setDecompMask = ar5416SetDecompMask; 143 ah->ah_setCoverageClass = ar5416SetCoverageClass; 144 ah->ah_setQuiet = ar5416SetQuiet; 145 146 ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry; 147 ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry; 148 149 /* DFS Functions */ 150 ah->ah_enableDfs = ar5416EnableDfs; 151 ah->ah_getDfsThresh = ar5416GetDfsThresh; 152 ah->ah_procRadarEvent = ar5416ProcessRadarEvent; 153 154 /* Power Management Functions */ 155 ah->ah_setPowerMode = ar5416SetPowerMode; 156 157 /* Beacon Management Functions */ 158 ah->ah_setBeaconTimers = ar5416SetBeaconTimers; 159 ah->ah_beaconInit = ar5416BeaconInit; 160 ah->ah_setStationBeaconTimers = ar5416SetStaBeaconTimers; 161 ah->ah_resetStationBeaconTimers = ar5416ResetStaBeaconTimers; 162 163 /* 802.11n Functions */ 164 ah->ah_chainTxDesc = ar5416ChainTxDesc; 165 ah->ah_setupFirstTxDesc = ar5416SetupFirstTxDesc; 166 ah->ah_setupLastTxDesc = ar5416SetupLastTxDesc; 167 ah->ah_set11nRateScenario = ar5416Set11nRateScenario; 168 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle; 169 ah->ah_clr11nAggr = ar5416Clr11nAggr; 170 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration; 171 ah->ah_get11nExtBusy = ar5416Get11nExtBusy; 172 ah->ah_set11nMac2040 = ar5416Set11nMac2040; 173 ah->ah_get11nRxClear = ar5416Get11nRxClear; 174 ah->ah_set11nRxClear = ar5416Set11nRxClear; 175 176 /* Interrupt functions */ 177 ah->ah_isInterruptPending = ar5416IsInterruptPending; 178 ah->ah_getPendingInterrupts = ar5416GetPendingInterrupts; 179 ah->ah_setInterrupts = ar5416SetInterrupts; 180 181 ahp->ah_priv.ah_getWirelessModes= ar5416GetWirelessModes; 182 ahp->ah_priv.ah_eepromRead = ar5416EepromRead; 183#ifdef AH_SUPPORT_WRITE_EEPROM 184 ahp->ah_priv.ah_eepromWrite = ar5416EepromWrite; 185#endif 186 ahp->ah_priv.ah_getChipPowerLimits = ar5416GetChipPowerLimits; 187 188 /* Internal ops */ 189 AH5416(ah)->ah_writeIni = ar5416WriteIni; 190 AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate; 191 192 /* Internal baseband ops */ 193 AH5416(ah)->ah_initPLL = ar5416InitPLL; 194 195 /* Internal calibration ops */ 196 AH5416(ah)->ah_cal_initcal = ar5416InitCalHardware; 197 198 /* Internal TX power control related operations */ 199 AH5416(ah)->ah_olcInit = ar5416olcInit; 200 AH5416(ah)->ah_olcTempCompensation = ar5416olcTempCompensation; 201 AH5416(ah)->ah_setPowerCalTable = ar5416SetPowerCalTable; 202 203 /* 204 * Start by setting all Owl devices to 2x2 205 */ 206 AH5416(ah)->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK; 207 AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK; 208 209 /* Enable all ANI functions to begin with */ 210 AH5416(ah)->ah_ani_function = 0xffffffff; 211 212 /* Set overridable ANI methods */ 213 AH5212(ah)->ah_aniControl = ar5416AniControl; 214} 215 216uint32_t 217ar5416GetRadioRev(struct ath_hal *ah) 218{ 219 uint32_t val; 220 int i; 221 222 /* Read Radio Chip Rev Extract */ 223 OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058); 224 for (i = 0; i < 8; i++) 225 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 226 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 227 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 228 return ath_hal_reverseBits(val, 8); 229} 230 231/* 232 * Attach for an AR5416 part. 233 */ 234static struct ath_hal * 235ar5416Attach(uint16_t devid, HAL_SOFTC sc, 236 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 237 HAL_STATUS *status) 238{ 239 struct ath_hal_5416 *ahp5416; 240 struct ath_hal_5212 *ahp; 241 struct ath_hal *ah; 242 uint32_t val; 243 HAL_STATUS ecode; 244 HAL_BOOL rfStatus; 245 246 HALDEBUG_G(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 247 __func__, sc, (void*) st, (void*) sh); 248 249 /* NB: memory is returned zero'd */ 250 ahp5416 = ath_hal_malloc(sizeof (struct ath_hal_5416) + 251 /* extra space for Owl 2.1/2.2 WAR */ 252 sizeof(ar5416Addac) 253 ); 254 if (ahp5416 == AH_NULL) { 255 HALDEBUG_G(AH_NULL, HAL_DEBUG_ANY, 256 "%s: cannot allocate memory for state block\n", __func__); 257 *status = HAL_ENOMEM; 258 return AH_NULL; 259 } 260 ar5416InitState(ahp5416, devid, sc, st, sh, status); 261 ahp = &ahp5416->ah_5212; 262 ah = &ahp->ah_priv.h; 263 264 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 265 /* reset chip */ 266 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", __func__); 267 ecode = HAL_EIO; 268 goto bad; 269 } 270 271 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 272 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", __func__); 273 ecode = HAL_EIO; 274 goto bad; 275 } 276 /* Read Revisions from Chips before taking out of reset */ 277 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 278 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 279 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 280 AH_PRIVATE(ah)->ah_ispcie = (devid == AR5416_DEVID_PCIE); 281 282 /* setup common ini data; rf backends handle remainder */ 283 HAL_INI_INIT(&ahp->ah_ini_modes, ar5416Modes, 6); 284 HAL_INI_INIT(&ahp->ah_ini_common, ar5416Common, 2); 285 286 HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain, 3); 287 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0, 2); 288 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1, 2); 289 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2, 2); 290 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3, 3); 291 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6, 3); 292 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7, 2); 293 HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac, 2); 294 295 if (! IS_5416V2_2(ah)) { /* Owl 2.1/2.0 */ 296 ath_hal_printf(ah, "[ath] Enabling CLKDRV workaround for AR5416 < v2.2\n"); 297 struct ini { 298 uint32_t *data; /* NB: !const */ 299 int rows, cols; 300 }; 301 /* override CLKDRV value */ 302 OS_MEMCPY(&AH5416(ah)[1], ar5416Addac, sizeof(ar5416Addac)); 303 AH5416(ah)->ah_ini_addac.data = (uint32_t *) &AH5416(ah)[1]; 304 HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0; 305 } 306 307 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2); 308 ar5416AttachPCIE(ah); 309 310 ecode = ath_hal_v14EepromAttach(ah); 311 if (ecode != HAL_OK) 312 goto bad; 313 314 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 315 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", 316 __func__); 317 ecode = HAL_EIO; 318 goto bad; 319 } 320 321 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 322 323 if (!ar5212ChipTest(ah)) { 324 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 325 __func__); 326 ecode = HAL_ESELFTEST; 327 goto bad; 328 } 329 330 /* 331 * Set correct Baseband to analog shift 332 * setting to access analog chips. 333 */ 334 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 335 336 /* Read Radio Chip Rev Extract */ 337 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah); 338 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 339 case AR_RAD5122_SREV_MAJOR: /* Fowl: 5G/2x2 */ 340 case AR_RAD2122_SREV_MAJOR: /* Fowl: 2+5G/2x2 */ 341 case AR_RAD2133_SREV_MAJOR: /* Fowl: 2G/3x3 */ 342 case AR_RAD5133_SREV_MAJOR: /* Fowl: 2+5G/3x3 */ 343 break; 344 default: 345 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 346 /* 347 * When RF_Silen is used the analog chip is reset. 348 * So when the system boots with radio switch off 349 * the RF chip rev reads back as zero and we need 350 * to use the mac+phy revs to set the radio rev. 351 */ 352 AH_PRIVATE(ah)->ah_analog5GhzRev = 353 AR_RAD5133_SREV_MAJOR; 354 break; 355 } 356 /* NB: silently accept anything in release code per Atheros */ 357#ifdef AH_DEBUG 358 HALDEBUG(ah, HAL_DEBUG_ANY, 359 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 360 "this driver\n", __func__, 361 AH_PRIVATE(ah)->ah_analog5GhzRev); 362 ecode = HAL_ENOTSUPP; 363 goto bad; 364#endif 365 } 366 367 /* 368 * Got everything we need now to setup the capabilities. 369 */ 370 if (!ar5416FillCapabilityInfo(ah)) { 371 ecode = HAL_EEREAD; 372 goto bad; 373 } 374 375 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 376 if (ecode != HAL_OK) { 377 HALDEBUG(ah, HAL_DEBUG_ANY, 378 "%s: error getting mac address from EEPROM\n", __func__); 379 goto bad; 380 } 381 /* XXX How about the serial number ? */ 382 /* Read Reg Domain */ 383 AH_PRIVATE(ah)->ah_currentRD = 384 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 385 AH_PRIVATE(ah)->ah_currentRDext = 386 ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL); 387 388 /* 389 * ah_miscMode is populated by ar5416FillCapabilityInfo() 390 * starting from griffin. Set here to make sure that 391 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 392 * placed into hardware. 393 */ 394 if (ahp->ah_miscMode != 0) 395 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 396 397 rfStatus = ar2133RfAttach(ah, &ecode); 398 if (!rfStatus) { 399 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 400 __func__, ecode); 401 goto bad; 402 } 403 404 ar5416AniSetup(ah); /* Anti Noise Immunity */ 405 406 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; 407 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; 408 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; 409 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; 410 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; 411 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; 412 413 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 414 415 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 416 417 return ah; 418bad: 419 if (ahp) 420 ar5416Detach((struct ath_hal *) ahp); 421 if (status) 422 *status = ecode; 423 return AH_NULL; 424} 425 426void 427ar5416Detach(struct ath_hal *ah) 428{ 429 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 430 431 HALASSERT(ah != AH_NULL); 432 HALASSERT(ah->ah_magic == AR5416_MAGIC); 433 434 /* Make sure that chip is awake before writing to it */ 435 if (! ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) 436 HALDEBUG(ah, HAL_DEBUG_UNMASKABLE, 437 "%s: failed to wake up chip\n", 438 __func__); 439 440 ar5416AniDetach(ah); 441 ar5212RfDetach(ah); 442 ah->ah_disable(ah); 443 ar5416SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 444 ath_hal_eepromDetach(ah); 445 ath_hal_free(ah); 446} 447 448void 449ar5416AttachPCIE(struct ath_hal *ah) 450{ 451 if (AH_PRIVATE(ah)->ah_ispcie) 452 ath_hal_configPCIE(ah, AH_FALSE); 453 else 454 ath_hal_disablePCIE(ah); 455} 456 457static void 458ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 459{ 460 if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 461 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 462 OS_DELAY(1000); 463 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 464 OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT); 465 } 466} 467 468static void 469ar5416WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 470{ 471 u_int modesIndex, freqIndex; 472 int regWrites = 0; 473 474 /* Setup the indices for the next set of register array writes */ 475 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 476 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 477 freqIndex = 2; 478 if (IEEE80211_IS_CHAN_HT40(chan)) 479 modesIndex = 3; 480 else if (IEEE80211_IS_CHAN_108G(chan)) 481 modesIndex = 5; 482 else 483 modesIndex = 4; 484 } else { 485 freqIndex = 1; 486 if (IEEE80211_IS_CHAN_HT40(chan) || 487 IEEE80211_IS_CHAN_TURBO(chan)) 488 modesIndex = 2; 489 else 490 modesIndex = 1; 491 } 492 493 /* Set correct Baseband to analog shift setting to access analog chips. */ 494 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 495 496 /* 497 * Write addac shifts 498 */ 499 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 500 501 /* NB: only required for Sowl */ 502 if (AR_SREV_SOWL(ah)) 503 ar5416EepromSetAddac(ah, chan); 504 505 regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1, 506 regWrites); 507 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 508 509 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 510 modesIndex, regWrites); 511 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 512 1, regWrites); 513 514 /* XXX updated regWrites? */ 515 AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites); 516} 517 518/* 519 * Convert to baseband spur frequency given input channel frequency 520 * and compute register settings below. 521 */ 522 523static void 524ar5416SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 525{ 526 uint16_t freq = ath_hal_gethwchannel(ah, chan); 527 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 528 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 529 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 530 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 531 static const int inc[4] = { 0, 100, 0, 0 }; 532 533 int bb_spur = AR_NO_SPUR; 534 int bin, cur_bin; 535 int spur_freq_sd; 536 int spur_delta_phase; 537 int denominator; 538 int upper, lower, cur_vit_mask; 539 int tmp, new; 540 int i; 541 542 int8_t mask_m[123]; 543 int8_t mask_p[123]; 544 int8_t mask_amt; 545 int tmp_mask; 546 int cur_bb_spur; 547 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 548 549 OS_MEMZERO(mask_m, sizeof(mask_m)); 550 OS_MEMZERO(mask_p, sizeof(mask_p)); 551 552 /* 553 * Need to verify range +/- 9.5 for static ht20, otherwise spur 554 * is out-of-band and can be ignored. 555 */ 556 /* XXX ath9k changes */ 557 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 558 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 559 if (AR_NO_SPUR == cur_bb_spur) 560 break; 561 cur_bb_spur = cur_bb_spur - (freq * 10); 562 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { 563 bb_spur = cur_bb_spur; 564 break; 565 } 566 } 567 if (AR_NO_SPUR == bb_spur) 568 return; 569 570 bin = bb_spur * 32; 571 572 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 573 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 574 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 575 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 576 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 577 578 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new); 579 580 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 581 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 582 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 583 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 584 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 585 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new); 586 /* 587 * Should offset bb_spur by +/- 10 MHz for dynamic 2040 MHz 588 * config, no offset for HT20. 589 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 590 * /80 for dyn2040. 591 */ 592 spur_delta_phase = ((bb_spur * 524288) / 100) & 593 AR_PHY_TIMING11_SPUR_DELTA_PHASE; 594 /* 595 * in 11A mode the denominator of spur_freq_sd should be 40 and 596 * it should be 44 in 11G 597 */ 598 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 440 : 400; 599 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; 600 601 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 602 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 603 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 604 OS_REG_WRITE(ah, AR_PHY_TIMING11, new); 605 606 607 /* 608 * ============================================ 609 * pilot mask 1 [31:0] = +6..-26, no 0 bin 610 * pilot mask 2 [19:0] = +26..+7 611 * 612 * channel mask 1 [31:0] = +6..-26, no 0 bin 613 * channel mask 2 [19:0] = +26..+7 614 */ 615 //cur_bin = -26; 616 cur_bin = -6000; 617 upper = bin + 100; 618 lower = bin - 100; 619 620 for (i = 0; i < 4; i++) { 621 int pilot_mask = 0; 622 int chan_mask = 0; 623 int bp = 0; 624 for (bp = 0; bp < 30; bp++) { 625 if ((cur_bin > lower) && (cur_bin < upper)) { 626 pilot_mask = pilot_mask | 0x1 << bp; 627 chan_mask = chan_mask | 0x1 << bp; 628 } 629 cur_bin += 100; 630 } 631 cur_bin += inc[i]; 632 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 633 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 634 } 635 636 /* ================================================= 637 * viterbi mask 1 based on channel magnitude 638 * four levels 0-3 639 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 640 * [1 2 2 1] for -9.6 or [1 2 1] for +16 641 * - enable_mask_ppm, all bins move with freq 642 * 643 * - mask_select, 8 bits for rates (reg 67,0x990c) 644 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 645 * choose which mask to use mask or mask2 646 */ 647 648 /* 649 * viterbi mask 2 2nd set for per data rate puncturing 650 * four levels 0-3 651 * - mask_select, 8 bits for rates (reg 67) 652 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 653 * [1 2 2 1] for -9.6 or [1 2 1] for +16 654 */ 655 cur_vit_mask = 6100; 656 upper = bin + 120; 657 lower = bin - 120; 658 659 for (i = 0; i < 123; i++) { 660 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 661 if ((abs(cur_vit_mask - bin)) < 75) { 662 mask_amt = 1; 663 } else { 664 mask_amt = 0; 665 } 666 if (cur_vit_mask < 0) { 667 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 668 } else { 669 mask_p[cur_vit_mask / 100] = mask_amt; 670 } 671 } 672 cur_vit_mask -= 100; 673 } 674 675 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 676 | (mask_m[48] << 26) | (mask_m[49] << 24) 677 | (mask_m[50] << 22) | (mask_m[51] << 20) 678 | (mask_m[52] << 18) | (mask_m[53] << 16) 679 | (mask_m[54] << 14) | (mask_m[55] << 12) 680 | (mask_m[56] << 10) | (mask_m[57] << 8) 681 | (mask_m[58] << 6) | (mask_m[59] << 4) 682 | (mask_m[60] << 2) | (mask_m[61] << 0); 683 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 684 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 685 686 tmp_mask = (mask_m[31] << 28) 687 | (mask_m[32] << 26) | (mask_m[33] << 24) 688 | (mask_m[34] << 22) | (mask_m[35] << 20) 689 | (mask_m[36] << 18) | (mask_m[37] << 16) 690 | (mask_m[48] << 14) | (mask_m[39] << 12) 691 | (mask_m[40] << 10) | (mask_m[41] << 8) 692 | (mask_m[42] << 6) | (mask_m[43] << 4) 693 | (mask_m[44] << 2) | (mask_m[45] << 0); 694 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 695 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 696 697 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 698 | (mask_m[18] << 26) | (mask_m[18] << 24) 699 | (mask_m[20] << 22) | (mask_m[20] << 20) 700 | (mask_m[22] << 18) | (mask_m[22] << 16) 701 | (mask_m[24] << 14) | (mask_m[24] << 12) 702 | (mask_m[25] << 10) | (mask_m[26] << 8) 703 | (mask_m[27] << 6) | (mask_m[28] << 4) 704 | (mask_m[29] << 2) | (mask_m[30] << 0); 705 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 706 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 707 708 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 709 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 710 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 711 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 712 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 713 | (mask_m[10] << 10) | (mask_m[11] << 8) 714 | (mask_m[12] << 6) | (mask_m[13] << 4) 715 | (mask_m[14] << 2) | (mask_m[15] << 0); 716 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 717 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 718 719 tmp_mask = (mask_p[15] << 28) 720 | (mask_p[14] << 26) | (mask_p[13] << 24) 721 | (mask_p[12] << 22) | (mask_p[11] << 20) 722 | (mask_p[10] << 18) | (mask_p[ 9] << 16) 723 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 724 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 725 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 726 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 727 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 728 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 729 730 tmp_mask = (mask_p[30] << 28) 731 | (mask_p[29] << 26) | (mask_p[28] << 24) 732 | (mask_p[27] << 22) | (mask_p[26] << 20) 733 | (mask_p[25] << 18) | (mask_p[24] << 16) 734 | (mask_p[23] << 14) | (mask_p[22] << 12) 735 | (mask_p[21] << 10) | (mask_p[20] << 8) 736 | (mask_p[19] << 6) | (mask_p[18] << 4) 737 | (mask_p[17] << 2) | (mask_p[16] << 0); 738 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 739 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 740 741 tmp_mask = (mask_p[45] << 28) 742 | (mask_p[44] << 26) | (mask_p[43] << 24) 743 | (mask_p[42] << 22) | (mask_p[41] << 20) 744 | (mask_p[40] << 18) | (mask_p[39] << 16) 745 | (mask_p[38] << 14) | (mask_p[37] << 12) 746 | (mask_p[36] << 10) | (mask_p[35] << 8) 747 | (mask_p[34] << 6) | (mask_p[33] << 4) 748 | (mask_p[32] << 2) | (mask_p[31] << 0); 749 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 750 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 751 752 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 753 | (mask_p[59] << 26) | (mask_p[58] << 24) 754 | (mask_p[57] << 22) | (mask_p[56] << 20) 755 | (mask_p[55] << 18) | (mask_p[54] << 16) 756 | (mask_p[53] << 14) | (mask_p[52] << 12) 757 | (mask_p[51] << 10) | (mask_p[50] << 8) 758 | (mask_p[49] << 6) | (mask_p[48] << 4) 759 | (mask_p[47] << 2) | (mask_p[46] << 0); 760 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 761 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 762} 763 764/* 765 * Fill all software cached or static hardware state information. 766 * Return failure if capabilities are to come from EEPROM and 767 * cannot be read. 768 */ 769HAL_BOOL 770ar5416FillCapabilityInfo(struct ath_hal *ah) 771{ 772 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 773 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 774 uint16_t val; 775 776 /* Construct wireless mode from EEPROM */ 777 pCap->halWirelessModes = 0; 778 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 779 pCap->halWirelessModes |= HAL_MODE_11A 780 | HAL_MODE_11NA_HT20 781 | HAL_MODE_11NA_HT40PLUS 782 | HAL_MODE_11NA_HT40MINUS 783 ; 784 } 785 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE)) { 786 pCap->halWirelessModes |= HAL_MODE_11G 787 | HAL_MODE_11NG_HT20 788 | HAL_MODE_11NG_HT40PLUS 789 | HAL_MODE_11NG_HT40MINUS 790 ; 791 pCap->halWirelessModes |= HAL_MODE_11A 792 | HAL_MODE_11NA_HT20 793 | HAL_MODE_11NA_HT40PLUS 794 | HAL_MODE_11NA_HT40MINUS 795 ; 796 } 797 798 pCap->halLow2GhzChan = 2312; 799 pCap->halHigh2GhzChan = 2732; 800 801 pCap->halLow5GhzChan = 4915; 802 pCap->halHigh5GhzChan = 6100; 803 804 pCap->halCipherCkipSupport = AH_FALSE; 805 pCap->halCipherTkipSupport = AH_TRUE; 806 pCap->halCipherAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 807 808 pCap->halMicCkipSupport = AH_FALSE; 809 pCap->halMicTkipSupport = AH_TRUE; 810 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 811 /* 812 * Starting with Griffin TX+RX mic keys can be combined 813 * in one key cache slot. 814 */ 815 pCap->halTkipMicTxRxKeySupport = AH_TRUE; 816 pCap->halChanSpreadSupport = AH_TRUE; 817 pCap->halSleepAfterBeaconBroken = AH_TRUE; 818 819 pCap->halCompressSupport = AH_FALSE; 820 pCap->halBurstSupport = AH_TRUE; 821 pCap->halFastFramesSupport = AH_FALSE; /* XXX? */ 822 pCap->halChapTuningSupport = AH_TRUE; 823 pCap->halTurboPrimeSupport = AH_TRUE; 824 825 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 826 827 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 828 pCap->halVEOLSupport = AH_TRUE; 829 pCap->halBssIdMaskSupport = AH_TRUE; 830 pCap->halMcastKeySrchSupport = AH_TRUE; /* Works on AR5416 and later */ 831 pCap->halTsfAddSupport = AH_TRUE; 832 pCap->hal4AddrAggrSupport = AH_FALSE; /* Broken in Owl */ 833 834 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 835 pCap->halTotalQueues = val; 836 else 837 pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 838 839 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 840 pCap->halKeyCacheSize = val; 841 else 842 pCap->halKeyCacheSize = AR5416_KEYTABLE_SIZE; 843 844 /* XXX not needed */ 845 pCap->halChanHalfRate = AH_FALSE; /* XXX ? */ 846 pCap->halChanQuarterRate = AH_FALSE; /* XXX ? */ 847 848 pCap->halTstampPrecision = 32; 849 pCap->halHwPhyCounterSupport = AH_TRUE; 850 pCap->halIntrMask = HAL_INT_COMMON 851 | HAL_INT_RX 852 | HAL_INT_TX 853 | HAL_INT_FATAL 854 | HAL_INT_BNR 855 | HAL_INT_BMISC 856 | HAL_INT_DTIMSYNC 857 | HAL_INT_TSFOOR 858 | HAL_INT_CST 859 | HAL_INT_GTT 860 ; 861 862 pCap->halFastCCSupport = AH_TRUE; 863 pCap->halNumGpioPins = 6; 864 pCap->halWowSupport = AH_FALSE; 865 pCap->halWowMatchPatternExact = AH_FALSE; 866 pCap->halBtCoexSupport = AH_FALSE; /* XXX need support */ 867 pCap->halAutoSleepSupport = AH_FALSE; 868 pCap->hal4kbSplitTransSupport = AH_TRUE; 869 /* Disable this so Block-ACK works correctly */ 870 pCap->halHasRxSelfLinkedTail = AH_FALSE; 871#if 0 /* XXX not yet */ 872 pCap->halNumAntCfg2GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_2GHZ); 873 pCap->halNumAntCfg5GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_5GHZ); 874#endif 875 pCap->halHTSupport = AH_TRUE; 876 pCap->halTxChainMask = ath_hal_eepromGet(ah, AR_EEP_TXMASK, AH_NULL); 877 /* XXX CB71 uses GPIO 0 to indicate 3 rx chains */ 878 pCap->halRxChainMask = ath_hal_eepromGet(ah, AR_EEP_RXMASK, AH_NULL); 879 /* AR5416 may have 3 antennas but is a 2x2 stream device */ 880 pCap->halTxStreams = 2; 881 pCap->halRxStreams = 2; 882 pCap->halRtsAggrLimit = 8*1024; /* Owl 2.0 limit */ 883 pCap->halMbssidAggrSupport = AH_FALSE; /* Broken on Owl */ 884 pCap->halForcePpmSupport = AH_TRUE; 885 pCap->halEnhancedPmSupport = AH_TRUE; 886 pCap->halBssidMatchSupport = AH_TRUE; 887 pCap->halGTTSupport = AH_TRUE; 888 pCap->halCSTSupport = AH_TRUE; 889 pCap->halEnhancedDfsSupport = AH_FALSE; 890 891 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 892 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 893 /* NB: enabled by default */ 894 ahpriv->ah_rfkillEnabled = AH_TRUE; 895 pCap->halRfSilentSupport = AH_TRUE; 896 } 897 898 ahpriv->ah_rxornIsFatal = AH_FALSE; 899 900 return AH_TRUE; 901} 902 903static const char* 904ar5416Probe(uint16_t vendorid, uint16_t devid) 905{ 906 if (vendorid == ATHEROS_VENDOR_ID && 907 (devid == AR5416_DEVID_PCI || devid == AR5416_DEVID_PCIE)) 908 return "Atheros 5416"; 909 return AH_NULL; 910} 911AH_CHIP(AR5416, ar5416Probe, ar5416Attach); 912