ar5416_attach.c revision 221603
1/* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c 221603 2011-05-07 15:30:23Z adrian $ 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23#include "ah_devid.h" 24 25#include "ah_eeprom_v14.h" 26 27#include "ar5416/ar5416.h" 28#include "ar5416/ar5416reg.h" 29#include "ar5416/ar5416phy.h" 30 31#include "ar5416/ar5416.ini" 32 33static void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 34static void ar5416WriteIni(struct ath_hal *ah, 35 const struct ieee80211_channel *chan); 36static void ar5416SpurMitigate(struct ath_hal *ah, 37 const struct ieee80211_channel *chan); 38 39static void 40ar5416AniSetup(struct ath_hal *ah) 41{ 42 static const struct ar5212AniParams aniparams = { 43 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 44 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 45 .coarseHigh = { -14, -14, -14, -14, -12 }, 46 .coarseLow = { -64, -64, -64, -64, -70 }, 47 .firpwr = { -78, -78, -78, -78, -80 }, 48 .maxSpurImmunityLevel = 2, 49 .cycPwrThr1 = { 2, 4, 6 }, 50 .maxFirstepLevel = 2, /* levels 0..2 */ 51 .firstep = { 0, 4, 8 }, 52 .ofdmTrigHigh = 500, 53 .ofdmTrigLow = 200, 54 .cckTrigHigh = 200, 55 .cckTrigLow = 100, 56 .rssiThrHigh = 40, 57 .rssiThrLow = 7, 58 .period = 100, 59 }; 60 /* NB: disable ANI noise immmunity for reliable RIFS rx */ 61 AH5416(ah)->ah_ani_function &= ~ HAL_ANI_NOISE_IMMUNITY_LEVEL; 62 ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 63} 64 65/* 66 * AR5416 doesn't do OLC or temperature compensation. 67 */ 68static void 69ar5416olcInit(struct ath_hal *ah) 70{ 71} 72 73static void 74ar5416olcTempCompensation(struct ath_hal *ah) 75{ 76} 77 78/* 79 * Attach for an AR5416 part. 80 */ 81void 82ar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc, 83 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 84{ 85 struct ath_hal_5212 *ahp; 86 struct ath_hal *ah; 87 88 ahp = &ahp5416->ah_5212; 89 ar5212InitState(ahp, devid, sc, st, sh, status); 90 ah = &ahp->ah_priv.h; 91 92 /* override 5212 methods for our needs */ 93 ah->ah_magic = AR5416_MAGIC; 94 ah->ah_getRateTable = ar5416GetRateTable; 95 ah->ah_detach = ar5416Detach; 96 97 /* Reset functions */ 98 ah->ah_reset = ar5416Reset; 99 ah->ah_phyDisable = ar5416PhyDisable; 100 ah->ah_disable = ar5416Disable; 101 ah->ah_configPCIE = ar5416ConfigPCIE; 102 ah->ah_perCalibration = ar5416PerCalibration; 103 ah->ah_perCalibrationN = ar5416PerCalibrationN, 104 ah->ah_resetCalValid = ar5416ResetCalValid, 105 ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit; 106 ah->ah_setTxPower = ar5416SetTransmitPower; 107 ah->ah_setBoardValues = ar5416SetBoardValues; 108 109 /* Transmit functions */ 110 ah->ah_stopTxDma = ar5416StopTxDma; 111 ah->ah_setupTxDesc = ar5416SetupTxDesc; 112 ah->ah_setupXTxDesc = ar5416SetupXTxDesc; 113 ah->ah_fillTxDesc = ar5416FillTxDesc; 114 ah->ah_procTxDesc = ar5416ProcTxDesc; 115 ah->ah_getTxCompletionRates = ar5416GetTxCompletionRates; 116 ah->ah_setupTxQueue = ar5416SetupTxQueue; 117 ah->ah_resetTxQueue = ar5416ResetTxQueue; 118 119 /* Receive Functions */ 120 ah->ah_startPcuReceive = ar5416StartPcuReceive; 121 ah->ah_stopPcuReceive = ar5416StopPcuReceive; 122 ah->ah_setupRxDesc = ar5416SetupRxDesc; 123 ah->ah_procRxDesc = ar5416ProcRxDesc; 124 ah->ah_rxMonitor = ar5416RxMonitor; 125 ah->ah_aniPoll = ar5416AniPoll; 126 ah->ah_procMibEvent = ar5416ProcessMibIntr; 127 128 /* Misc Functions */ 129 ah->ah_getCapability = ar5416GetCapability; 130 ah->ah_getDiagState = ar5416GetDiagState; 131 ah->ah_setLedState = ar5416SetLedState; 132 ah->ah_gpioCfgOutput = ar5416GpioCfgOutput; 133 ah->ah_gpioCfgInput = ar5416GpioCfgInput; 134 ah->ah_gpioGet = ar5416GpioGet; 135 ah->ah_gpioSet = ar5416GpioSet; 136 ah->ah_gpioSetIntr = ar5416GpioSetIntr; 137 ah->ah_resetTsf = ar5416ResetTsf; 138 ah->ah_getRfGain = ar5416GetRfgain; 139 ah->ah_setAntennaSwitch = ar5416SetAntennaSwitch; 140 ah->ah_setDecompMask = ar5416SetDecompMask; 141 ah->ah_setCoverageClass = ar5416SetCoverageClass; 142 143 ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry; 144 ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry; 145 146 /* Power Management Functions */ 147 ah->ah_setPowerMode = ar5416SetPowerMode; 148 149 /* Beacon Management Functions */ 150 ah->ah_setBeaconTimers = ar5416SetBeaconTimers; 151 ah->ah_beaconInit = ar5416BeaconInit; 152 ah->ah_setStationBeaconTimers = ar5416SetStaBeaconTimers; 153 ah->ah_resetStationBeaconTimers = ar5416ResetStaBeaconTimers; 154 155 /* 802.11n Functions */ 156 ah->ah_chainTxDesc = ar5416ChainTxDesc; 157 ah->ah_setupFirstTxDesc = ar5416SetupFirstTxDesc; 158 ah->ah_setupLastTxDesc = ar5416SetupLastTxDesc; 159 ah->ah_set11nRateScenario = ar5416Set11nRateScenario; 160 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle; 161 ah->ah_clr11nAggr = ar5416Clr11nAggr; 162 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration; 163 ah->ah_get11nExtBusy = ar5416Get11nExtBusy; 164 ah->ah_set11nMac2040 = ar5416Set11nMac2040; 165 ah->ah_get11nRxClear = ar5416Get11nRxClear; 166 ah->ah_set11nRxClear = ar5416Set11nRxClear; 167 168 /* Interrupt functions */ 169 ah->ah_isInterruptPending = ar5416IsInterruptPending; 170 ah->ah_getPendingInterrupts = ar5416GetPendingInterrupts; 171 ah->ah_setInterrupts = ar5416SetInterrupts; 172 173 ahp->ah_priv.ah_getWirelessModes= ar5416GetWirelessModes; 174 ahp->ah_priv.ah_eepromRead = ar5416EepromRead; 175#ifdef AH_SUPPORT_WRITE_EEPROM 176 ahp->ah_priv.ah_eepromWrite = ar5416EepromWrite; 177#endif 178 ahp->ah_priv.ah_getChipPowerLimits = ar5416GetChipPowerLimits; 179 180 /* Internal ops */ 181 AH5416(ah)->ah_writeIni = ar5416WriteIni; 182 AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate; 183 184 /* Internal baseband ops */ 185 AH5416(ah)->ah_initPLL = ar5416InitPLL; 186 187 /* Internal calibration ops */ 188 AH5416(ah)->ah_cal_initcal = ar5416InitCalHardware; 189 190 /* Internal TX power control related operations */ 191 AH5416(ah)->ah_olcInit = ar5416olcInit; 192 AH5416(ah)->ah_olcTempCompensation = ar5416olcTempCompensation; 193 AH5416(ah)->ah_setPowerCalTable = ar5416SetPowerCalTable; 194 195 /* 196 * Start by setting all Owl devices to 2x2 197 */ 198 AH5416(ah)->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK; 199 AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK; 200 201 /* Enable all ANI functions to begin with */ 202 AH5416(ah)->ah_ani_function = HAL_ANI_ALL; 203} 204 205uint32_t 206ar5416GetRadioRev(struct ath_hal *ah) 207{ 208 uint32_t val; 209 int i; 210 211 /* Read Radio Chip Rev Extract */ 212 OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058); 213 for (i = 0; i < 8; i++) 214 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 215 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 216 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 217 return ath_hal_reverseBits(val, 8); 218} 219 220/* 221 * Attach for an AR5416 part. 222 */ 223static struct ath_hal * 224ar5416Attach(uint16_t devid, HAL_SOFTC sc, 225 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 226 HAL_STATUS *status) 227{ 228 struct ath_hal_5416 *ahp5416; 229 struct ath_hal_5212 *ahp; 230 struct ath_hal *ah; 231 uint32_t val; 232 HAL_STATUS ecode; 233 HAL_BOOL rfStatus; 234 235 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 236 __func__, sc, (void*) st, (void*) sh); 237 238 /* NB: memory is returned zero'd */ 239 ahp5416 = ath_hal_malloc(sizeof (struct ath_hal_5416) + 240 /* extra space for Owl 2.1/2.2 WAR */ 241 sizeof(ar5416Addac) 242 ); 243 if (ahp5416 == AH_NULL) { 244 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 245 "%s: cannot allocate memory for state block\n", __func__); 246 *status = HAL_ENOMEM; 247 return AH_NULL; 248 } 249 ar5416InitState(ahp5416, devid, sc, st, sh, status); 250 ahp = &ahp5416->ah_5212; 251 ah = &ahp->ah_priv.h; 252 253 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 254 /* reset chip */ 255 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", __func__); 256 ecode = HAL_EIO; 257 goto bad; 258 } 259 260 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 261 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", __func__); 262 ecode = HAL_EIO; 263 goto bad; 264 } 265 /* Read Revisions from Chips before taking out of reset */ 266 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 267 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 268 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 269 AH_PRIVATE(ah)->ah_ispcie = (devid == AR5416_DEVID_PCIE); 270 271 /* setup common ini data; rf backends handle remainder */ 272 HAL_INI_INIT(&ahp->ah_ini_modes, ar5416Modes, 6); 273 HAL_INI_INIT(&ahp->ah_ini_common, ar5416Common, 2); 274 275 HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain, 3); 276 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0, 2); 277 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1, 2); 278 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2, 2); 279 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3, 3); 280 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6, 3); 281 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7, 2); 282 HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac, 2); 283 284 if (! IS_5416V2_2(ah)) { /* Owl 2.1/2.0 */ 285 ath_hal_printf(ah, "[ath] Enabling CLKDRV workaround for AR5416 < v2.2\n"); 286 struct ini { 287 uint32_t *data; /* NB: !const */ 288 int rows, cols; 289 }; 290 /* override CLKDRV value */ 291 OS_MEMCPY(&AH5416(ah)[1], ar5416Addac, sizeof(ar5416Addac)); 292 AH5416(ah)->ah_ini_addac.data = (uint32_t *) &AH5416(ah)[1]; 293 HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0; 294 } 295 296 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2); 297 ar5416AttachPCIE(ah); 298 299 ecode = ath_hal_v14EepromAttach(ah); 300 if (ecode != HAL_OK) 301 goto bad; 302 303 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 304 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", 305 __func__); 306 ecode = HAL_EIO; 307 goto bad; 308 } 309 310 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 311 312 if (!ar5212ChipTest(ah)) { 313 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 314 __func__); 315 ecode = HAL_ESELFTEST; 316 goto bad; 317 } 318 319 /* 320 * Set correct Baseband to analog shift 321 * setting to access analog chips. 322 */ 323 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 324 325 /* Read Radio Chip Rev Extract */ 326 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah); 327 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 328 case AR_RAD5122_SREV_MAJOR: /* Fowl: 5G/2x2 */ 329 case AR_RAD2122_SREV_MAJOR: /* Fowl: 2+5G/2x2 */ 330 case AR_RAD2133_SREV_MAJOR: /* Fowl: 2G/3x3 */ 331 case AR_RAD5133_SREV_MAJOR: /* Fowl: 2+5G/3x3 */ 332 break; 333 default: 334 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 335 /* 336 * When RF_Silen is used the analog chip is reset. 337 * So when the system boots with radio switch off 338 * the RF chip rev reads back as zero and we need 339 * to use the mac+phy revs to set the radio rev. 340 */ 341 AH_PRIVATE(ah)->ah_analog5GhzRev = 342 AR_RAD5133_SREV_MAJOR; 343 break; 344 } 345 /* NB: silently accept anything in release code per Atheros */ 346#ifdef AH_DEBUG 347 HALDEBUG(ah, HAL_DEBUG_ANY, 348 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 349 "this driver\n", __func__, 350 AH_PRIVATE(ah)->ah_analog5GhzRev); 351 ecode = HAL_ENOTSUPP; 352 goto bad; 353#endif 354 } 355 356 /* 357 * Got everything we need now to setup the capabilities. 358 */ 359 if (!ar5416FillCapabilityInfo(ah)) { 360 ecode = HAL_EEREAD; 361 goto bad; 362 } 363 364 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 365 if (ecode != HAL_OK) { 366 HALDEBUG(ah, HAL_DEBUG_ANY, 367 "%s: error getting mac address from EEPROM\n", __func__); 368 goto bad; 369 } 370 /* XXX How about the serial number ? */ 371 /* Read Reg Domain */ 372 AH_PRIVATE(ah)->ah_currentRD = 373 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 374 AH_PRIVATE(ah)->ah_currentRDext = 375 ath_hal_eepromGet(ah, AR_EEP_REGDMN_1, AH_NULL); 376 377 /* 378 * ah_miscMode is populated by ar5416FillCapabilityInfo() 379 * starting from griffin. Set here to make sure that 380 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 381 * placed into hardware. 382 */ 383 if (ahp->ah_miscMode != 0) 384 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 385 386 rfStatus = ar2133RfAttach(ah, &ecode); 387 if (!rfStatus) { 388 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 389 __func__, ecode); 390 goto bad; 391 } 392 393 ar5416AniSetup(ah); /* Anti Noise Immunity */ 394 395 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; 396 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; 397 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; 398 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; 399 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; 400 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; 401 402 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 403 404 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 405 406 return ah; 407bad: 408 if (ahp) 409 ar5416Detach((struct ath_hal *) ahp); 410 if (status) 411 *status = ecode; 412 return AH_NULL; 413} 414 415void 416ar5416Detach(struct ath_hal *ah) 417{ 418 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 419 420 HALASSERT(ah != AH_NULL); 421 HALASSERT(ah->ah_magic == AR5416_MAGIC); 422 423 ar5416AniDetach(ah); 424 ar5212RfDetach(ah); 425 ah->ah_disable(ah); 426 ar5416SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 427 ath_hal_eepromDetach(ah); 428 ath_hal_free(ah); 429} 430 431void 432ar5416AttachPCIE(struct ath_hal *ah) 433{ 434 if (AH_PRIVATE(ah)->ah_ispcie) 435 ath_hal_configPCIE(ah, AH_FALSE); 436 else 437 ath_hal_disablePCIE(ah); 438} 439 440static void 441ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 442{ 443 if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 444 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 445 OS_DELAY(1000); 446 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 447 OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT); 448 } 449} 450 451static void 452ar5416WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 453{ 454 u_int modesIndex, freqIndex; 455 int regWrites = 0; 456 457 /* Setup the indices for the next set of register array writes */ 458 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 459 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 460 freqIndex = 2; 461 if (IEEE80211_IS_CHAN_HT40(chan)) 462 modesIndex = 3; 463 else if (IEEE80211_IS_CHAN_108G(chan)) 464 modesIndex = 5; 465 else 466 modesIndex = 4; 467 } else { 468 freqIndex = 1; 469 if (IEEE80211_IS_CHAN_HT40(chan) || 470 IEEE80211_IS_CHAN_TURBO(chan)) 471 modesIndex = 2; 472 else 473 modesIndex = 1; 474 } 475 476 /* Set correct Baseband to analog shift setting to access analog chips. */ 477 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 478 479 /* 480 * Write addac shifts 481 */ 482 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 483 484 /* NB: only required for Sowl */ 485 if (AR_SREV_SOWL(ah)) 486 ar5416EepromSetAddac(ah, chan); 487 488 regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1, 489 regWrites); 490 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 491 492 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 493 modesIndex, regWrites); 494 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 495 1, regWrites); 496 497 /* XXX updated regWrites? */ 498 AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites); 499} 500 501/* 502 * Convert to baseband spur frequency given input channel frequency 503 * and compute register settings below. 504 */ 505 506static void 507ar5416SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 508{ 509 uint16_t freq = ath_hal_gethwchannel(ah, chan); 510 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 511 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 512 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 513 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 514 static const int inc[4] = { 0, 100, 0, 0 }; 515 516 int bb_spur = AR_NO_SPUR; 517 int bin, cur_bin; 518 int spur_freq_sd; 519 int spur_delta_phase; 520 int denominator; 521 int upper, lower, cur_vit_mask; 522 int tmp, new; 523 int i; 524 525 int8_t mask_m[123]; 526 int8_t mask_p[123]; 527 int8_t mask_amt; 528 int tmp_mask; 529 int cur_bb_spur; 530 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 531 532 OS_MEMZERO(mask_m, sizeof(mask_m)); 533 OS_MEMZERO(mask_p, sizeof(mask_p)); 534 535 /* 536 * Need to verify range +/- 9.5 for static ht20, otherwise spur 537 * is out-of-band and can be ignored. 538 */ 539 /* XXX ath9k changes */ 540 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 541 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 542 if (AR_NO_SPUR == cur_bb_spur) 543 break; 544 cur_bb_spur = cur_bb_spur - (freq * 10); 545 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { 546 bb_spur = cur_bb_spur; 547 break; 548 } 549 } 550 if (AR_NO_SPUR == bb_spur) 551 return; 552 553 bin = bb_spur * 32; 554 555 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 556 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 557 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 558 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 559 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 560 561 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new); 562 563 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 564 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 565 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 566 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 567 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 568 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new); 569 /* 570 * Should offset bb_spur by +/- 10 MHz for dynamic 2040 MHz 571 * config, no offset for HT20. 572 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 573 * /80 for dyn2040. 574 */ 575 spur_delta_phase = ((bb_spur * 524288) / 100) & 576 AR_PHY_TIMING11_SPUR_DELTA_PHASE; 577 /* 578 * in 11A mode the denominator of spur_freq_sd should be 40 and 579 * it should be 44 in 11G 580 */ 581 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 440 : 400; 582 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; 583 584 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 585 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 586 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 587 OS_REG_WRITE(ah, AR_PHY_TIMING11, new); 588 589 590 /* 591 * ============================================ 592 * pilot mask 1 [31:0] = +6..-26, no 0 bin 593 * pilot mask 2 [19:0] = +26..+7 594 * 595 * channel mask 1 [31:0] = +6..-26, no 0 bin 596 * channel mask 2 [19:0] = +26..+7 597 */ 598 //cur_bin = -26; 599 cur_bin = -6000; 600 upper = bin + 100; 601 lower = bin - 100; 602 603 for (i = 0; i < 4; i++) { 604 int pilot_mask = 0; 605 int chan_mask = 0; 606 int bp = 0; 607 for (bp = 0; bp < 30; bp++) { 608 if ((cur_bin > lower) && (cur_bin < upper)) { 609 pilot_mask = pilot_mask | 0x1 << bp; 610 chan_mask = chan_mask | 0x1 << bp; 611 } 612 cur_bin += 100; 613 } 614 cur_bin += inc[i]; 615 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 616 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 617 } 618 619 /* ================================================= 620 * viterbi mask 1 based on channel magnitude 621 * four levels 0-3 622 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 623 * [1 2 2 1] for -9.6 or [1 2 1] for +16 624 * - enable_mask_ppm, all bins move with freq 625 * 626 * - mask_select, 8 bits for rates (reg 67,0x990c) 627 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 628 * choose which mask to use mask or mask2 629 */ 630 631 /* 632 * viterbi mask 2 2nd set for per data rate puncturing 633 * four levels 0-3 634 * - mask_select, 8 bits for rates (reg 67) 635 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 636 * [1 2 2 1] for -9.6 or [1 2 1] for +16 637 */ 638 cur_vit_mask = 6100; 639 upper = bin + 120; 640 lower = bin - 120; 641 642 for (i = 0; i < 123; i++) { 643 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 644 if ((abs(cur_vit_mask - bin)) < 75) { 645 mask_amt = 1; 646 } else { 647 mask_amt = 0; 648 } 649 if (cur_vit_mask < 0) { 650 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 651 } else { 652 mask_p[cur_vit_mask / 100] = mask_amt; 653 } 654 } 655 cur_vit_mask -= 100; 656 } 657 658 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 659 | (mask_m[48] << 26) | (mask_m[49] << 24) 660 | (mask_m[50] << 22) | (mask_m[51] << 20) 661 | (mask_m[52] << 18) | (mask_m[53] << 16) 662 | (mask_m[54] << 14) | (mask_m[55] << 12) 663 | (mask_m[56] << 10) | (mask_m[57] << 8) 664 | (mask_m[58] << 6) | (mask_m[59] << 4) 665 | (mask_m[60] << 2) | (mask_m[61] << 0); 666 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 667 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 668 669 tmp_mask = (mask_m[31] << 28) 670 | (mask_m[32] << 26) | (mask_m[33] << 24) 671 | (mask_m[34] << 22) | (mask_m[35] << 20) 672 | (mask_m[36] << 18) | (mask_m[37] << 16) 673 | (mask_m[48] << 14) | (mask_m[39] << 12) 674 | (mask_m[40] << 10) | (mask_m[41] << 8) 675 | (mask_m[42] << 6) | (mask_m[43] << 4) 676 | (mask_m[44] << 2) | (mask_m[45] << 0); 677 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 678 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 679 680 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 681 | (mask_m[18] << 26) | (mask_m[18] << 24) 682 | (mask_m[20] << 22) | (mask_m[20] << 20) 683 | (mask_m[22] << 18) | (mask_m[22] << 16) 684 | (mask_m[24] << 14) | (mask_m[24] << 12) 685 | (mask_m[25] << 10) | (mask_m[26] << 8) 686 | (mask_m[27] << 6) | (mask_m[28] << 4) 687 | (mask_m[29] << 2) | (mask_m[30] << 0); 688 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 689 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 690 691 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 692 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 693 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 694 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 695 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 696 | (mask_m[10] << 10) | (mask_m[11] << 8) 697 | (mask_m[12] << 6) | (mask_m[13] << 4) 698 | (mask_m[14] << 2) | (mask_m[15] << 0); 699 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 700 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 701 702 tmp_mask = (mask_p[15] << 28) 703 | (mask_p[14] << 26) | (mask_p[13] << 24) 704 | (mask_p[12] << 22) | (mask_p[11] << 20) 705 | (mask_p[10] << 18) | (mask_p[ 9] << 16) 706 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 707 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 708 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 709 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 710 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 711 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 712 713 tmp_mask = (mask_p[30] << 28) 714 | (mask_p[29] << 26) | (mask_p[28] << 24) 715 | (mask_p[27] << 22) | (mask_p[26] << 20) 716 | (mask_p[25] << 18) | (mask_p[24] << 16) 717 | (mask_p[23] << 14) | (mask_p[22] << 12) 718 | (mask_p[21] << 10) | (mask_p[20] << 8) 719 | (mask_p[19] << 6) | (mask_p[18] << 4) 720 | (mask_p[17] << 2) | (mask_p[16] << 0); 721 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 722 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 723 724 tmp_mask = (mask_p[45] << 28) 725 | (mask_p[44] << 26) | (mask_p[43] << 24) 726 | (mask_p[42] << 22) | (mask_p[41] << 20) 727 | (mask_p[40] << 18) | (mask_p[39] << 16) 728 | (mask_p[38] << 14) | (mask_p[37] << 12) 729 | (mask_p[36] << 10) | (mask_p[35] << 8) 730 | (mask_p[34] << 6) | (mask_p[33] << 4) 731 | (mask_p[32] << 2) | (mask_p[31] << 0); 732 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 733 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 734 735 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 736 | (mask_p[59] << 26) | (mask_p[58] << 24) 737 | (mask_p[57] << 22) | (mask_p[56] << 20) 738 | (mask_p[55] << 18) | (mask_p[54] << 16) 739 | (mask_p[53] << 14) | (mask_p[52] << 12) 740 | (mask_p[51] << 10) | (mask_p[50] << 8) 741 | (mask_p[49] << 6) | (mask_p[48] << 4) 742 | (mask_p[47] << 2) | (mask_p[46] << 0); 743 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 744 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 745} 746 747/* 748 * Fill all software cached or static hardware state information. 749 * Return failure if capabilities are to come from EEPROM and 750 * cannot be read. 751 */ 752HAL_BOOL 753ar5416FillCapabilityInfo(struct ath_hal *ah) 754{ 755 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 756 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 757 uint16_t val; 758 759 /* Construct wireless mode from EEPROM */ 760 pCap->halWirelessModes = 0; 761 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 762 pCap->halWirelessModes |= HAL_MODE_11A 763 | HAL_MODE_11NA_HT20 764 | HAL_MODE_11NA_HT40PLUS 765 | HAL_MODE_11NA_HT40MINUS 766 ; 767 } 768 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE)) { 769 pCap->halWirelessModes |= HAL_MODE_11G 770 | HAL_MODE_11NG_HT20 771 | HAL_MODE_11NG_HT40PLUS 772 | HAL_MODE_11NG_HT40MINUS 773 ; 774 pCap->halWirelessModes |= HAL_MODE_11A 775 | HAL_MODE_11NA_HT20 776 | HAL_MODE_11NA_HT40PLUS 777 | HAL_MODE_11NA_HT40MINUS 778 ; 779 } 780 781 pCap->halLow2GhzChan = 2312; 782 pCap->halHigh2GhzChan = 2732; 783 784 pCap->halLow5GhzChan = 4915; 785 pCap->halHigh5GhzChan = 6100; 786 787 pCap->halCipherCkipSupport = AH_FALSE; 788 pCap->halCipherTkipSupport = AH_TRUE; 789 pCap->halCipherAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 790 791 pCap->halMicCkipSupport = AH_FALSE; 792 pCap->halMicTkipSupport = AH_TRUE; 793 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 794 /* 795 * Starting with Griffin TX+RX mic keys can be combined 796 * in one key cache slot. 797 */ 798 pCap->halTkipMicTxRxKeySupport = AH_TRUE; 799 pCap->halChanSpreadSupport = AH_TRUE; 800 pCap->halSleepAfterBeaconBroken = AH_TRUE; 801 802 pCap->halCompressSupport = AH_FALSE; 803 pCap->halBurstSupport = AH_TRUE; 804 pCap->halFastFramesSupport = AH_FALSE; /* XXX? */ 805 pCap->halChapTuningSupport = AH_TRUE; 806 pCap->halTurboPrimeSupport = AH_TRUE; 807 808 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 809 810 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 811 pCap->halVEOLSupport = AH_TRUE; 812 pCap->halBssIdMaskSupport = AH_TRUE; 813 pCap->halMcastKeySrchSupport = AH_FALSE; 814 pCap->halTsfAddSupport = AH_TRUE; 815 pCap->hal4AddrAggrSupport = AH_FALSE; /* Broken in Owl */ 816 817 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 818 pCap->halTotalQueues = val; 819 else 820 pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 821 822 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 823 pCap->halKeyCacheSize = val; 824 else 825 pCap->halKeyCacheSize = AR5416_KEYTABLE_SIZE; 826 827 /* XXX not needed */ 828 pCap->halChanHalfRate = AH_FALSE; /* XXX ? */ 829 pCap->halChanQuarterRate = AH_FALSE; /* XXX ? */ 830 831 pCap->halTstampPrecision = 32; 832 pCap->halHwPhyCounterSupport = AH_TRUE; 833 pCap->halIntrMask = HAL_INT_COMMON 834 | HAL_INT_RX 835 | HAL_INT_TX 836 | HAL_INT_FATAL 837 | HAL_INT_BNR 838 | HAL_INT_BMISC 839 | HAL_INT_DTIMSYNC 840 | HAL_INT_TSFOOR 841 | HAL_INT_CST 842 | HAL_INT_GTT 843 ; 844 845 pCap->halFastCCSupport = AH_TRUE; 846 pCap->halNumGpioPins = 6; 847 pCap->halWowSupport = AH_FALSE; 848 pCap->halWowMatchPatternExact = AH_FALSE; 849 pCap->halBtCoexSupport = AH_FALSE; /* XXX need support */ 850 pCap->halAutoSleepSupport = AH_FALSE; 851 pCap->hal4kbSplitTransSupport = AH_TRUE; 852 /* Disable this so Block-ACK works correctly */ 853 pCap->halHasRxSelfLinkedTail = AH_FALSE; 854#if 0 /* XXX not yet */ 855 pCap->halNumAntCfg2GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_2GHZ); 856 pCap->halNumAntCfg5GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_5GHZ); 857#endif 858 pCap->halHTSupport = AH_TRUE; 859 pCap->halTxChainMask = ath_hal_eepromGet(ah, AR_EEP_TXMASK, AH_NULL); 860 /* XXX CB71 uses GPIO 0 to indicate 3 rx chains */ 861 pCap->halRxChainMask = ath_hal_eepromGet(ah, AR_EEP_RXMASK, AH_NULL); 862 /* AR5416 may have 3 antennas but is a 2x2 stream device */ 863 pCap->halTxStreams = 2; 864 pCap->halRxStreams = 2; 865 pCap->halRtsAggrLimit = 8*1024; /* Owl 2.0 limit */ 866 pCap->halMbssidAggrSupport = AH_FALSE; /* Broken on Owl */ 867 pCap->halForcePpmSupport = AH_TRUE; 868 pCap->halEnhancedPmSupport = AH_TRUE; 869 pCap->halBssidMatchSupport = AH_TRUE; 870 pCap->halGTTSupport = AH_TRUE; 871 pCap->halCSTSupport = AH_TRUE; 872 873 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 874 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 875 /* NB: enabled by default */ 876 ahpriv->ah_rfkillEnabled = AH_TRUE; 877 pCap->halRfSilentSupport = AH_TRUE; 878 } 879 880 ahpriv->ah_rxornIsFatal = AH_FALSE; 881 882 return AH_TRUE; 883} 884 885static const char* 886ar5416Probe(uint16_t vendorid, uint16_t devid) 887{ 888 if (vendorid == ATHEROS_VENDOR_ID && 889 (devid == AR5416_DEVID_PCI || devid == AR5416_DEVID_PCIE)) 890 return "Atheros 5416"; 891 return AH_NULL; 892} 893AH_CHIP(AR5416, ar5416Probe, ar5416Attach); 894