ar5416_attach.c revision 219979
1/* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c 219979 2011-03-25 00:40:08Z adrian $ 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23#include "ah_devid.h" 24 25#include "ah_eeprom_v14.h" 26 27#include "ar5416/ar5416.h" 28#include "ar5416/ar5416reg.h" 29#include "ar5416/ar5416phy.h" 30 31#include "ar5416/ar5416.ini" 32 33static void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 34static void ar5416WriteIni(struct ath_hal *ah, 35 const struct ieee80211_channel *chan); 36static void ar5416SpurMitigate(struct ath_hal *ah, 37 const struct ieee80211_channel *chan); 38 39static void 40ar5416AniSetup(struct ath_hal *ah) 41{ 42 static const struct ar5212AniParams aniparams = { 43 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 44 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 45 .coarseHigh = { -14, -14, -14, -14, -12 }, 46 .coarseLow = { -64, -64, -64, -64, -70 }, 47 .firpwr = { -78, -78, -78, -78, -80 }, 48 .maxSpurImmunityLevel = 2, 49 .cycPwrThr1 = { 2, 4, 6 }, 50 .maxFirstepLevel = 2, /* levels 0..2 */ 51 .firstep = { 0, 4, 8 }, 52 .ofdmTrigHigh = 500, 53 .ofdmTrigLow = 200, 54 .cckTrigHigh = 200, 55 .cckTrigLow = 100, 56 .rssiThrHigh = 40, 57 .rssiThrLow = 7, 58 .period = 100, 59 }; 60 /* NB: disable ANI noise immmunity for reliable RIFS rx */ 61 AH5416(ah)->ah_ani_function &= ~ HAL_ANI_NOISE_IMMUNITY_LEVEL; 62 ar5416AniAttach(ah, &aniparams, &aniparams, AH_TRUE); 63} 64 65/* 66 * AR5416 doesn't do OLC or temperature compensation. 67 */ 68static void 69ar5416olcInit(struct ath_hal *ah) 70{ 71} 72 73static void 74ar5416olcTempCompensation(struct ath_hal *ah) 75{ 76} 77 78/* 79 * Attach for an AR5416 part. 80 */ 81void 82ar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc, 83 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 84{ 85 struct ath_hal_5212 *ahp; 86 struct ath_hal *ah; 87 88 ahp = &ahp5416->ah_5212; 89 ar5212InitState(ahp, devid, sc, st, sh, status); 90 ah = &ahp->ah_priv.h; 91 92 /* override 5212 methods for our needs */ 93 ah->ah_magic = AR5416_MAGIC; 94 ah->ah_getRateTable = ar5416GetRateTable; 95 ah->ah_detach = ar5416Detach; 96 97 /* Reset functions */ 98 ah->ah_reset = ar5416Reset; 99 ah->ah_phyDisable = ar5416PhyDisable; 100 ah->ah_disable = ar5416Disable; 101 ah->ah_configPCIE = ar5416ConfigPCIE; 102 ah->ah_perCalibration = ar5416PerCalibration; 103 ah->ah_perCalibrationN = ar5416PerCalibrationN, 104 ah->ah_resetCalValid = ar5416ResetCalValid, 105 ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit; 106 ah->ah_setTxPower = ar5416SetTransmitPower; 107 ah->ah_setBoardValues = ar5416SetBoardValues; 108 109 /* Transmit functions */ 110 ah->ah_stopTxDma = ar5416StopTxDma; 111 ah->ah_setupTxDesc = ar5416SetupTxDesc; 112 ah->ah_setupXTxDesc = ar5416SetupXTxDesc; 113 ah->ah_fillTxDesc = ar5416FillTxDesc; 114 ah->ah_procTxDesc = ar5416ProcTxDesc; 115 ah->ah_getTxCompletionRates = ar5416GetTxCompletionRates; 116 ah->ah_setupTxQueue = ar5416SetupTxQueue; 117 ah->ah_resetTxQueue = ar5416ResetTxQueue; 118 119 /* Receive Functions */ 120 ah->ah_startPcuReceive = ar5416StartPcuReceive; 121 ah->ah_stopPcuReceive = ar5416StopPcuReceive; 122 ah->ah_setupRxDesc = ar5416SetupRxDesc; 123 ah->ah_procRxDesc = ar5416ProcRxDesc; 124 ah->ah_rxMonitor = ar5416RxMonitor; 125 ah->ah_aniPoll = ar5416AniPoll; 126 ah->ah_procMibEvent = ar5416ProcessMibIntr; 127 128 /* Misc Functions */ 129 ah->ah_getCapability = ar5416GetCapability; 130 ah->ah_getDiagState = ar5416GetDiagState; 131 ah->ah_setLedState = ar5416SetLedState; 132 ah->ah_gpioCfgOutput = ar5416GpioCfgOutput; 133 ah->ah_gpioCfgInput = ar5416GpioCfgInput; 134 ah->ah_gpioGet = ar5416GpioGet; 135 ah->ah_gpioSet = ar5416GpioSet; 136 ah->ah_gpioSetIntr = ar5416GpioSetIntr; 137 ah->ah_resetTsf = ar5416ResetTsf; 138 ah->ah_getRfGain = ar5416GetRfgain; 139 ah->ah_setAntennaSwitch = ar5416SetAntennaSwitch; 140 ah->ah_setDecompMask = ar5416SetDecompMask; 141 ah->ah_setCoverageClass = ar5416SetCoverageClass; 142 143 ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry; 144 ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry; 145 146 /* Power Management Functions */ 147 ah->ah_setPowerMode = ar5416SetPowerMode; 148 149 /* Beacon Management Functions */ 150 ah->ah_setBeaconTimers = ar5416SetBeaconTimers; 151 ah->ah_beaconInit = ar5416BeaconInit; 152 ah->ah_setStationBeaconTimers = ar5416SetStaBeaconTimers; 153 ah->ah_resetStationBeaconTimers = ar5416ResetStaBeaconTimers; 154 155 /* 802.11n Functions */ 156 ah->ah_chainTxDesc = ar5416ChainTxDesc; 157 ah->ah_setupFirstTxDesc = ar5416SetupFirstTxDesc; 158 ah->ah_setupLastTxDesc = ar5416SetupLastTxDesc; 159 ah->ah_set11nRateScenario = ar5416Set11nRateScenario; 160 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle; 161 ah->ah_clr11nAggr = ar5416Clr11nAggr; 162 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration; 163 ah->ah_get11nExtBusy = ar5416Get11nExtBusy; 164 ah->ah_set11nMac2040 = ar5416Set11nMac2040; 165 ah->ah_get11nRxClear = ar5416Get11nRxClear; 166 ah->ah_set11nRxClear = ar5416Set11nRxClear; 167 168 /* Interrupt functions */ 169 ah->ah_isInterruptPending = ar5416IsInterruptPending; 170 ah->ah_getPendingInterrupts = ar5416GetPendingInterrupts; 171 ah->ah_setInterrupts = ar5416SetInterrupts; 172 173 ahp->ah_priv.ah_getWirelessModes= ar5416GetWirelessModes; 174 ahp->ah_priv.ah_eepromRead = ar5416EepromRead; 175#ifdef AH_SUPPORT_WRITE_EEPROM 176 ahp->ah_priv.ah_eepromWrite = ar5416EepromWrite; 177#endif 178 ahp->ah_priv.ah_getChipPowerLimits = ar5416GetChipPowerLimits; 179 180 /* Internal ops */ 181 AH5416(ah)->ah_writeIni = ar5416WriteIni; 182 AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate; 183 184 /* Internal calibration ops */ 185 AH5416(ah)->ah_cal_initcal = ar5416InitCalHardware; 186 187 /* Internal TX power control related operations */ 188 AH5416(ah)->ah_olcInit = ar5416olcInit; 189 AH5416(ah)->ah_olcTempCompensation = ar5416olcTempCompensation; 190 AH5416(ah)->ah_setPowerCalTable = ar5416SetPowerCalTable; 191 192 /* 193 * Start by setting all Owl devices to 2x2 194 */ 195 AH5416(ah)->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK; 196 AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK; 197 198 /* Enable all ANI functions to begin with */ 199 AH5416(ah)->ah_ani_function = HAL_ANI_ALL; 200} 201 202uint32_t 203ar5416GetRadioRev(struct ath_hal *ah) 204{ 205 uint32_t val; 206 int i; 207 208 /* Read Radio Chip Rev Extract */ 209 OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058); 210 for (i = 0; i < 8; i++) 211 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 212 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 213 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 214 return ath_hal_reverseBits(val, 8); 215} 216 217/* 218 * Attach for an AR5416 part. 219 */ 220static struct ath_hal * 221ar5416Attach(uint16_t devid, HAL_SOFTC sc, 222 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 223 HAL_STATUS *status) 224{ 225 struct ath_hal_5416 *ahp5416; 226 struct ath_hal_5212 *ahp; 227 struct ath_hal *ah; 228 uint32_t val; 229 HAL_STATUS ecode; 230 HAL_BOOL rfStatus; 231 232 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 233 __func__, sc, (void*) st, (void*) sh); 234 235 /* NB: memory is returned zero'd */ 236 ahp5416 = ath_hal_malloc(sizeof (struct ath_hal_5416) + 237 /* extra space for Owl 2.1/2.2 WAR */ 238 sizeof(ar5416Addac) 239 ); 240 if (ahp5416 == AH_NULL) { 241 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 242 "%s: cannot allocate memory for state block\n", __func__); 243 *status = HAL_ENOMEM; 244 return AH_NULL; 245 } 246 ar5416InitState(ahp5416, devid, sc, st, sh, status); 247 ahp = &ahp5416->ah_5212; 248 ah = &ahp->ah_priv.h; 249 250 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 251 /* reset chip */ 252 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", __func__); 253 ecode = HAL_EIO; 254 goto bad; 255 } 256 257 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 258 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", __func__); 259 ecode = HAL_EIO; 260 goto bad; 261 } 262 /* Read Revisions from Chips before taking out of reset */ 263 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 264 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 265 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 266 AH_PRIVATE(ah)->ah_ispcie = (devid == AR5416_DEVID_PCIE); 267 268 /* setup common ini data; rf backends handle remainder */ 269 HAL_INI_INIT(&ahp->ah_ini_modes, ar5416Modes, 6); 270 HAL_INI_INIT(&ahp->ah_ini_common, ar5416Common, 2); 271 272 HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain, 3); 273 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0, 2); 274 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1, 2); 275 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2, 2); 276 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3, 3); 277 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6, 3); 278 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7, 2); 279 HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac, 2); 280 281 if (! IS_5416V2_2(ah)) { /* Owl 2.1/2.0 */ 282 ath_hal_printf(ah, "[ath] Enabling CLKDRV workaround for AR5416 < v2.2\n"); 283 struct ini { 284 uint32_t *data; /* NB: !const */ 285 int rows, cols; 286 }; 287 /* override CLKDRV value */ 288 OS_MEMCPY(&AH5416(ah)[1], ar5416Addac, sizeof(ar5416Addac)); 289 AH5416(ah)->ah_ini_addac.data = (uint32_t *) &AH5416(ah)[1]; 290 HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0; 291 } 292 293 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2); 294 ar5416AttachPCIE(ah); 295 296 ecode = ath_hal_v14EepromAttach(ah); 297 if (ecode != HAL_OK) 298 goto bad; 299 300 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 301 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", 302 __func__); 303 ecode = HAL_EIO; 304 goto bad; 305 } 306 307 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 308 309 if (!ar5212ChipTest(ah)) { 310 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 311 __func__); 312 ecode = HAL_ESELFTEST; 313 goto bad; 314 } 315 316 /* 317 * Set correct Baseband to analog shift 318 * setting to access analog chips. 319 */ 320 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 321 322 /* Read Radio Chip Rev Extract */ 323 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah); 324 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 325 case AR_RAD5122_SREV_MAJOR: /* Fowl: 5G/2x2 */ 326 case AR_RAD2122_SREV_MAJOR: /* Fowl: 2+5G/2x2 */ 327 case AR_RAD2133_SREV_MAJOR: /* Fowl: 2G/3x3 */ 328 case AR_RAD5133_SREV_MAJOR: /* Fowl: 2+5G/3x3 */ 329 break; 330 default: 331 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 332 /* 333 * When RF_Silen is used the analog chip is reset. 334 * So when the system boots with radio switch off 335 * the RF chip rev reads back as zero and we need 336 * to use the mac+phy revs to set the radio rev. 337 */ 338 AH_PRIVATE(ah)->ah_analog5GhzRev = 339 AR_RAD5133_SREV_MAJOR; 340 break; 341 } 342 /* NB: silently accept anything in release code per Atheros */ 343#ifdef AH_DEBUG 344 HALDEBUG(ah, HAL_DEBUG_ANY, 345 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 346 "this driver\n", __func__, 347 AH_PRIVATE(ah)->ah_analog5GhzRev); 348 ecode = HAL_ENOTSUPP; 349 goto bad; 350#endif 351 } 352 353 /* 354 * Got everything we need now to setup the capabilities. 355 */ 356 if (!ar5416FillCapabilityInfo(ah)) { 357 ecode = HAL_EEREAD; 358 goto bad; 359 } 360 361 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 362 if (ecode != HAL_OK) { 363 HALDEBUG(ah, HAL_DEBUG_ANY, 364 "%s: error getting mac address from EEPROM\n", __func__); 365 goto bad; 366 } 367 /* XXX How about the serial number ? */ 368 /* Read Reg Domain */ 369 AH_PRIVATE(ah)->ah_currentRD = 370 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 371 372 /* 373 * ah_miscMode is populated by ar5416FillCapabilityInfo() 374 * starting from griffin. Set here to make sure that 375 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 376 * placed into hardware. 377 */ 378 if (ahp->ah_miscMode != 0) 379 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode); 380 381 rfStatus = ar2133RfAttach(ah, &ecode); 382 if (!rfStatus) { 383 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 384 __func__, ecode); 385 goto bad; 386 } 387 388 ar5416AniSetup(ah); /* Anti Noise Immunity */ 389 390 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; 391 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; 392 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; 393 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; 394 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; 395 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; 396 397 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 398 399 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 400 401 return ah; 402bad: 403 if (ahp) 404 ar5416Detach((struct ath_hal *) ahp); 405 if (status) 406 *status = ecode; 407 return AH_NULL; 408} 409 410void 411ar5416Detach(struct ath_hal *ah) 412{ 413 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 414 415 HALASSERT(ah != AH_NULL); 416 HALASSERT(ah->ah_magic == AR5416_MAGIC); 417 418 ar5416AniDetach(ah); 419 ar5212RfDetach(ah); 420 ah->ah_disable(ah); 421 ar5416SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 422 ath_hal_eepromDetach(ah); 423 ath_hal_free(ah); 424} 425 426void 427ar5416AttachPCIE(struct ath_hal *ah) 428{ 429 if (AH_PRIVATE(ah)->ah_ispcie) 430 ath_hal_configPCIE(ah, AH_FALSE); 431 else 432 ath_hal_disablePCIE(ah); 433} 434 435static void 436ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 437{ 438 if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 439 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 440 OS_DELAY(1000); 441 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 442 OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT); 443 } 444} 445 446static void 447ar5416WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 448{ 449 u_int modesIndex, freqIndex; 450 int regWrites = 0; 451 452 /* Setup the indices for the next set of register array writes */ 453 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 454 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 455 freqIndex = 2; 456 if (IEEE80211_IS_CHAN_HT40(chan)) 457 modesIndex = 3; 458 else if (IEEE80211_IS_CHAN_108G(chan)) 459 modesIndex = 5; 460 else 461 modesIndex = 4; 462 } else { 463 freqIndex = 1; 464 if (IEEE80211_IS_CHAN_HT40(chan) || 465 IEEE80211_IS_CHAN_TURBO(chan)) 466 modesIndex = 2; 467 else 468 modesIndex = 1; 469 } 470 471 /* Set correct Baseband to analog shift setting to access analog chips. */ 472 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 473 474 /* 475 * Write addac shifts 476 */ 477 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 478 479 /* NB: only required for Sowl */ 480 if (AR_SREV_SOWL(ah)) 481 ar5416EepromSetAddac(ah, chan); 482 483 regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1, 484 regWrites); 485 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 486 487 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 488 modesIndex, regWrites); 489 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 490 1, regWrites); 491 492 /* XXX updated regWrites? */ 493 AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites); 494} 495 496/* 497 * Convert to baseband spur frequency given input channel frequency 498 * and compute register settings below. 499 */ 500 501static void 502ar5416SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 503{ 504 uint16_t freq = ath_hal_gethwchannel(ah, chan); 505 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 506 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 507 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 508 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 509 static const int inc[4] = { 0, 100, 0, 0 }; 510 511 int bb_spur = AR_NO_SPUR; 512 int bin, cur_bin; 513 int spur_freq_sd; 514 int spur_delta_phase; 515 int denominator; 516 int upper, lower, cur_vit_mask; 517 int tmp, new; 518 int i; 519 520 int8_t mask_m[123]; 521 int8_t mask_p[123]; 522 int8_t mask_amt; 523 int tmp_mask; 524 int cur_bb_spur; 525 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 526 527 OS_MEMZERO(mask_m, sizeof(mask_m)); 528 OS_MEMZERO(mask_p, sizeof(mask_p)); 529 530 /* 531 * Need to verify range +/- 9.5 for static ht20, otherwise spur 532 * is out-of-band and can be ignored. 533 */ 534 /* XXX ath9k changes */ 535 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 536 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 537 if (AR_NO_SPUR == cur_bb_spur) 538 break; 539 cur_bb_spur = cur_bb_spur - (freq * 10); 540 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { 541 bb_spur = cur_bb_spur; 542 break; 543 } 544 } 545 if (AR_NO_SPUR == bb_spur) 546 return; 547 548 bin = bb_spur * 32; 549 550 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 551 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 552 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 553 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 554 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 555 556 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new); 557 558 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 559 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 560 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 561 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 562 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 563 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new); 564 /* 565 * Should offset bb_spur by +/- 10 MHz for dynamic 2040 MHz 566 * config, no offset for HT20. 567 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 568 * /80 for dyn2040. 569 */ 570 spur_delta_phase = ((bb_spur * 524288) / 100) & 571 AR_PHY_TIMING11_SPUR_DELTA_PHASE; 572 /* 573 * in 11A mode the denominator of spur_freq_sd should be 40 and 574 * it should be 44 in 11G 575 */ 576 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 440 : 400; 577 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; 578 579 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 580 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 581 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 582 OS_REG_WRITE(ah, AR_PHY_TIMING11, new); 583 584 585 /* 586 * ============================================ 587 * pilot mask 1 [31:0] = +6..-26, no 0 bin 588 * pilot mask 2 [19:0] = +26..+7 589 * 590 * channel mask 1 [31:0] = +6..-26, no 0 bin 591 * channel mask 2 [19:0] = +26..+7 592 */ 593 //cur_bin = -26; 594 cur_bin = -6000; 595 upper = bin + 100; 596 lower = bin - 100; 597 598 for (i = 0; i < 4; i++) { 599 int pilot_mask = 0; 600 int chan_mask = 0; 601 int bp = 0; 602 for (bp = 0; bp < 30; bp++) { 603 if ((cur_bin > lower) && (cur_bin < upper)) { 604 pilot_mask = pilot_mask | 0x1 << bp; 605 chan_mask = chan_mask | 0x1 << bp; 606 } 607 cur_bin += 100; 608 } 609 cur_bin += inc[i]; 610 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 611 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 612 } 613 614 /* ================================================= 615 * viterbi mask 1 based on channel magnitude 616 * four levels 0-3 617 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 618 * [1 2 2 1] for -9.6 or [1 2 1] for +16 619 * - enable_mask_ppm, all bins move with freq 620 * 621 * - mask_select, 8 bits for rates (reg 67,0x990c) 622 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 623 * choose which mask to use mask or mask2 624 */ 625 626 /* 627 * viterbi mask 2 2nd set for per data rate puncturing 628 * four levels 0-3 629 * - mask_select, 8 bits for rates (reg 67) 630 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 631 * [1 2 2 1] for -9.6 or [1 2 1] for +16 632 */ 633 cur_vit_mask = 6100; 634 upper = bin + 120; 635 lower = bin - 120; 636 637 for (i = 0; i < 123; i++) { 638 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 639 if ((abs(cur_vit_mask - bin)) < 75) { 640 mask_amt = 1; 641 } else { 642 mask_amt = 0; 643 } 644 if (cur_vit_mask < 0) { 645 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 646 } else { 647 mask_p[cur_vit_mask / 100] = mask_amt; 648 } 649 } 650 cur_vit_mask -= 100; 651 } 652 653 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 654 | (mask_m[48] << 26) | (mask_m[49] << 24) 655 | (mask_m[50] << 22) | (mask_m[51] << 20) 656 | (mask_m[52] << 18) | (mask_m[53] << 16) 657 | (mask_m[54] << 14) | (mask_m[55] << 12) 658 | (mask_m[56] << 10) | (mask_m[57] << 8) 659 | (mask_m[58] << 6) | (mask_m[59] << 4) 660 | (mask_m[60] << 2) | (mask_m[61] << 0); 661 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 662 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 663 664 tmp_mask = (mask_m[31] << 28) 665 | (mask_m[32] << 26) | (mask_m[33] << 24) 666 | (mask_m[34] << 22) | (mask_m[35] << 20) 667 | (mask_m[36] << 18) | (mask_m[37] << 16) 668 | (mask_m[48] << 14) | (mask_m[39] << 12) 669 | (mask_m[40] << 10) | (mask_m[41] << 8) 670 | (mask_m[42] << 6) | (mask_m[43] << 4) 671 | (mask_m[44] << 2) | (mask_m[45] << 0); 672 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 673 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 674 675 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 676 | (mask_m[18] << 26) | (mask_m[18] << 24) 677 | (mask_m[20] << 22) | (mask_m[20] << 20) 678 | (mask_m[22] << 18) | (mask_m[22] << 16) 679 | (mask_m[24] << 14) | (mask_m[24] << 12) 680 | (mask_m[25] << 10) | (mask_m[26] << 8) 681 | (mask_m[27] << 6) | (mask_m[28] << 4) 682 | (mask_m[29] << 2) | (mask_m[30] << 0); 683 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 684 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 685 686 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 687 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 688 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 689 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 690 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 691 | (mask_m[10] << 10) | (mask_m[11] << 8) 692 | (mask_m[12] << 6) | (mask_m[13] << 4) 693 | (mask_m[14] << 2) | (mask_m[15] << 0); 694 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 695 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 696 697 tmp_mask = (mask_p[15] << 28) 698 | (mask_p[14] << 26) | (mask_p[13] << 24) 699 | (mask_p[12] << 22) | (mask_p[11] << 20) 700 | (mask_p[10] << 18) | (mask_p[ 9] << 16) 701 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 702 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 703 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 704 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 705 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 706 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 707 708 tmp_mask = (mask_p[30] << 28) 709 | (mask_p[29] << 26) | (mask_p[28] << 24) 710 | (mask_p[27] << 22) | (mask_p[26] << 20) 711 | (mask_p[25] << 18) | (mask_p[24] << 16) 712 | (mask_p[23] << 14) | (mask_p[22] << 12) 713 | (mask_p[21] << 10) | (mask_p[20] << 8) 714 | (mask_p[19] << 6) | (mask_p[18] << 4) 715 | (mask_p[17] << 2) | (mask_p[16] << 0); 716 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 717 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 718 719 tmp_mask = (mask_p[45] << 28) 720 | (mask_p[44] << 26) | (mask_p[43] << 24) 721 | (mask_p[42] << 22) | (mask_p[41] << 20) 722 | (mask_p[40] << 18) | (mask_p[39] << 16) 723 | (mask_p[38] << 14) | (mask_p[37] << 12) 724 | (mask_p[36] << 10) | (mask_p[35] << 8) 725 | (mask_p[34] << 6) | (mask_p[33] << 4) 726 | (mask_p[32] << 2) | (mask_p[31] << 0); 727 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 728 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 729 730 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 731 | (mask_p[59] << 26) | (mask_p[58] << 24) 732 | (mask_p[57] << 22) | (mask_p[56] << 20) 733 | (mask_p[55] << 18) | (mask_p[54] << 16) 734 | (mask_p[53] << 14) | (mask_p[52] << 12) 735 | (mask_p[51] << 10) | (mask_p[50] << 8) 736 | (mask_p[49] << 6) | (mask_p[48] << 4) 737 | (mask_p[47] << 2) | (mask_p[46] << 0); 738 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 739 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 740} 741 742/* 743 * Fill all software cached or static hardware state information. 744 * Return failure if capabilities are to come from EEPROM and 745 * cannot be read. 746 */ 747HAL_BOOL 748ar5416FillCapabilityInfo(struct ath_hal *ah) 749{ 750 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 751 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 752 uint16_t val; 753 754 /* Construct wireless mode from EEPROM */ 755 pCap->halWirelessModes = 0; 756 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 757 pCap->halWirelessModes |= HAL_MODE_11A 758 | HAL_MODE_11NA_HT20 759 | HAL_MODE_11NA_HT40PLUS 760 | HAL_MODE_11NA_HT40MINUS 761 ; 762 } 763 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE)) { 764 pCap->halWirelessModes |= HAL_MODE_11G 765 | HAL_MODE_11NG_HT20 766 | HAL_MODE_11NG_HT40PLUS 767 | HAL_MODE_11NG_HT40MINUS 768 ; 769 pCap->halWirelessModes |= HAL_MODE_11A 770 | HAL_MODE_11NA_HT20 771 | HAL_MODE_11NA_HT40PLUS 772 | HAL_MODE_11NA_HT40MINUS 773 ; 774 } 775 776 pCap->halLow2GhzChan = 2312; 777 pCap->halHigh2GhzChan = 2732; 778 779 pCap->halLow5GhzChan = 4915; 780 pCap->halHigh5GhzChan = 6100; 781 782 pCap->halCipherCkipSupport = AH_FALSE; 783 pCap->halCipherTkipSupport = AH_TRUE; 784 pCap->halCipherAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 785 786 pCap->halMicCkipSupport = AH_FALSE; 787 pCap->halMicTkipSupport = AH_TRUE; 788 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 789 /* 790 * Starting with Griffin TX+RX mic keys can be combined 791 * in one key cache slot. 792 */ 793 pCap->halTkipMicTxRxKeySupport = AH_TRUE; 794 pCap->halChanSpreadSupport = AH_TRUE; 795 pCap->halSleepAfterBeaconBroken = AH_TRUE; 796 797 pCap->halCompressSupport = AH_FALSE; 798 pCap->halBurstSupport = AH_TRUE; 799 pCap->halFastFramesSupport = AH_FALSE; /* XXX? */ 800 pCap->halChapTuningSupport = AH_TRUE; 801 pCap->halTurboPrimeSupport = AH_TRUE; 802 803 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 804 805 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 806 pCap->halVEOLSupport = AH_TRUE; 807 pCap->halBssIdMaskSupport = AH_TRUE; 808 pCap->halMcastKeySrchSupport = AH_FALSE; 809 pCap->halTsfAddSupport = AH_TRUE; 810 811 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 812 pCap->halTotalQueues = val; 813 else 814 pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 815 816 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 817 pCap->halKeyCacheSize = val; 818 else 819 pCap->halKeyCacheSize = AR5416_KEYTABLE_SIZE; 820 821 /* XXX not needed */ 822 pCap->halChanHalfRate = AH_FALSE; /* XXX ? */ 823 pCap->halChanQuarterRate = AH_FALSE; /* XXX ? */ 824 825 pCap->halTstampPrecision = 32; 826 pCap->halHwPhyCounterSupport = AH_TRUE; 827 pCap->halIntrMask = HAL_INT_COMMON 828 | HAL_INT_RX 829 | HAL_INT_TX 830 | HAL_INT_FATAL 831 | HAL_INT_BNR 832 | HAL_INT_BMISC 833 | HAL_INT_DTIMSYNC 834 | HAL_INT_TSFOOR 835 | HAL_INT_CST 836 | HAL_INT_GTT 837 ; 838 839 pCap->halFastCCSupport = AH_TRUE; 840 pCap->halNumGpioPins = 6; 841 pCap->halWowSupport = AH_FALSE; 842 pCap->halWowMatchPatternExact = AH_FALSE; 843 pCap->halBtCoexSupport = AH_FALSE; /* XXX need support */ 844 pCap->halAutoSleepSupport = AH_FALSE; 845 pCap->hal4kbSplitTransSupport = AH_TRUE; 846#if 0 /* XXX not yet */ 847 pCap->halNumAntCfg2GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_2GHZ); 848 pCap->halNumAntCfg5GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_5GHZ); 849#endif 850 pCap->halHTSupport = AH_TRUE; 851 pCap->halTxChainMask = ath_hal_eepromGet(ah, AR_EEP_TXMASK, AH_NULL); 852 /* XXX CB71 uses GPIO 0 to indicate 3 rx chains */ 853 pCap->halRxChainMask = ath_hal_eepromGet(ah, AR_EEP_RXMASK, AH_NULL); 854 /* AR5416 may have 3 antennas but is a 2x2 stream device */ 855 pCap->halTxStreams = 2; 856 pCap->halRxStreams = 2; 857 pCap->halRtsAggrLimit = 8*1024; /* Owl 2.0 limit */ 858 pCap->halMbssidAggrSupport = AH_TRUE; 859 pCap->halForcePpmSupport = AH_TRUE; 860 pCap->halEnhancedPmSupport = AH_TRUE; 861 pCap->halBssidMatchSupport = AH_TRUE; 862 863 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 864 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 865 /* NB: enabled by default */ 866 ahpriv->ah_rfkillEnabled = AH_TRUE; 867 pCap->halRfSilentSupport = AH_TRUE; 868 } 869 870 ahpriv->ah_rxornIsFatal = AH_FALSE; 871 872 return AH_TRUE; 873} 874 875static const char* 876ar5416Probe(uint16_t vendorid, uint16_t devid) 877{ 878 if (vendorid == ATHEROS_VENDOR_ID && 879 (devid == AR5416_DEVID_PCI || devid == AR5416_DEVID_PCIE)) 880 return "Atheros 5416"; 881 return AH_NULL; 882} 883AH_CHIP(AR5416, ar5416Probe, ar5416Attach); 884