ar5416_attach.c revision 218762
1/* 2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 3 * Copyright (c) 2002-2008 Atheros Communications, Inc. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $FreeBSD: head/sys/dev/ath/ath_hal/ar5416/ar5416_attach.c 218762 2011-02-17 05:30:38Z adrian $ 18 */ 19#include "opt_ah.h" 20 21#include "ah.h" 22#include "ah_internal.h" 23#include "ah_devid.h" 24 25#include "ah_eeprom_v14.h" 26 27#include "ar5416/ar5416.h" 28#include "ar5416/ar5416reg.h" 29#include "ar5416/ar5416phy.h" 30 31#include "ar5416/ar5416.ini" 32 33static void ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore); 34static void ar5416WriteIni(struct ath_hal *ah, 35 const struct ieee80211_channel *chan); 36static void ar5416SpurMitigate(struct ath_hal *ah, 37 const struct ieee80211_channel *chan); 38 39static void 40ar5416AniSetup(struct ath_hal *ah) 41{ 42 static const struct ar5212AniParams aniparams = { 43 .maxNoiseImmunityLevel = 4, /* levels 0..4 */ 44 .totalSizeDesired = { -55, -55, -55, -55, -62 }, 45 .coarseHigh = { -14, -14, -14, -14, -12 }, 46 .coarseLow = { -64, -64, -64, -64, -70 }, 47 .firpwr = { -78, -78, -78, -78, -80 }, 48 .maxSpurImmunityLevel = 2, 49 .cycPwrThr1 = { 2, 4, 6 }, 50 .maxFirstepLevel = 2, /* levels 0..2 */ 51 .firstep = { 0, 4, 8 }, 52 .ofdmTrigHigh = 500, 53 .ofdmTrigLow = 200, 54 .cckTrigHigh = 200, 55 .cckTrigLow = 100, 56 .rssiThrHigh = 40, 57 .rssiThrLow = 7, 58 .period = 100, 59 }; 60 /* NB: ANI is not enabled yet */ 61 ar5416AniAttach(ah, &aniparams, &aniparams, AH_FALSE); 62} 63 64/* 65 * Attach for an AR5416 part. 66 */ 67void 68ar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc, 69 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, HAL_STATUS *status) 70{ 71 struct ath_hal_5212 *ahp; 72 struct ath_hal *ah; 73 74 ahp = &ahp5416->ah_5212; 75 ar5212InitState(ahp, devid, sc, st, sh, status); 76 ah = &ahp->ah_priv.h; 77 78 /* override 5212 methods for our needs */ 79 ah->ah_magic = AR5416_MAGIC; 80 ah->ah_getRateTable = ar5416GetRateTable; 81 ah->ah_detach = ar5416Detach; 82 83 /* Reset functions */ 84 ah->ah_reset = ar5416Reset; 85 ah->ah_phyDisable = ar5416PhyDisable; 86 ah->ah_disable = ar5416Disable; 87 ah->ah_configPCIE = ar5416ConfigPCIE; 88 ah->ah_perCalibration = ar5416PerCalibration; 89 ah->ah_perCalibrationN = ar5416PerCalibrationN, 90 ah->ah_resetCalValid = ar5416ResetCalValid, 91 ah->ah_setTxPowerLimit = ar5416SetTxPowerLimit; 92 ah->ah_setTxPower = ar5416SetTransmitPower; 93 ah->ah_setBoardValues = ar5416SetBoardValues; 94 95 /* Transmit functions */ 96 ah->ah_stopTxDma = ar5416StopTxDma; 97 ah->ah_setupTxDesc = ar5416SetupTxDesc; 98 ah->ah_setupXTxDesc = ar5416SetupXTxDesc; 99 ah->ah_fillTxDesc = ar5416FillTxDesc; 100 ah->ah_procTxDesc = ar5416ProcTxDesc; 101 ah->ah_getTxCompletionRates = ar5416GetTxCompletionRates; 102 103 /* Receive Functions */ 104 ah->ah_startPcuReceive = ar5416StartPcuReceive; 105 ah->ah_stopPcuReceive = ar5416StopPcuReceive; 106 ah->ah_setupRxDesc = ar5416SetupRxDesc; 107 ah->ah_procRxDesc = ar5416ProcRxDesc; 108 ah->ah_rxMonitor = ar5416RxMonitor; 109 ah->ah_aniPoll = ar5416AniPoll; 110 ah->ah_procMibEvent = ar5416ProcessMibIntr; 111 112 /* Misc Functions */ 113 ah->ah_getCapability = ar5416GetCapability; 114 ah->ah_getDiagState = ar5416GetDiagState; 115 ah->ah_setLedState = ar5416SetLedState; 116 ah->ah_gpioCfgOutput = ar5416GpioCfgOutput; 117 ah->ah_gpioCfgInput = ar5416GpioCfgInput; 118 ah->ah_gpioGet = ar5416GpioGet; 119 ah->ah_gpioSet = ar5416GpioSet; 120 ah->ah_gpioSetIntr = ar5416GpioSetIntr; 121 ah->ah_resetTsf = ar5416ResetTsf; 122 ah->ah_getRfGain = ar5416GetRfgain; 123 ah->ah_setAntennaSwitch = ar5416SetAntennaSwitch; 124 ah->ah_setDecompMask = ar5416SetDecompMask; 125 ah->ah_setCoverageClass = ar5416SetCoverageClass; 126 127 ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry; 128 ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry; 129 130 /* Power Management Functions */ 131 ah->ah_setPowerMode = ar5416SetPowerMode; 132 133 /* Beacon Management Functions */ 134 ah->ah_setBeaconTimers = ar5416SetBeaconTimers; 135 ah->ah_beaconInit = ar5416BeaconInit; 136 ah->ah_setStationBeaconTimers = ar5416SetStaBeaconTimers; 137 ah->ah_resetStationBeaconTimers = ar5416ResetStaBeaconTimers; 138 139 /* 802.11n Functions */ 140 ah->ah_chainTxDesc = ar5416ChainTxDesc; 141 ah->ah_setupFirstTxDesc = ar5416SetupFirstTxDesc; 142 ah->ah_setupLastTxDesc = ar5416SetupLastTxDesc; 143 ah->ah_set11nRateScenario = ar5416Set11nRateScenario; 144 ah->ah_set11nAggrMiddle = ar5416Set11nAggrMiddle; 145 ah->ah_clr11nAggr = ar5416Clr11nAggr; 146 ah->ah_set11nBurstDuration = ar5416Set11nBurstDuration; 147 ah->ah_get11nExtBusy = ar5416Get11nExtBusy; 148 ah->ah_set11nMac2040 = ar5416Set11nMac2040; 149 ah->ah_get11nRxClear = ar5416Get11nRxClear; 150 ah->ah_set11nRxClear = ar5416Set11nRxClear; 151 152 /* Interrupt functions */ 153 ah->ah_isInterruptPending = ar5416IsInterruptPending; 154 ah->ah_getPendingInterrupts = ar5416GetPendingInterrupts; 155 ah->ah_setInterrupts = ar5416SetInterrupts; 156 157 ahp->ah_priv.ah_getWirelessModes= ar5416GetWirelessModes; 158 ahp->ah_priv.ah_eepromRead = ar5416EepromRead; 159#ifdef AH_SUPPORT_WRITE_EEPROM 160 ahp->ah_priv.ah_eepromWrite = ar5416EepromWrite; 161#endif 162 ahp->ah_priv.ah_getChipPowerLimits = ar5416GetChipPowerLimits; 163 164 AH5416(ah)->ah_writeIni = ar5416WriteIni; 165 AH5416(ah)->ah_spurMitigate = ar5416SpurMitigate; 166 /* 167 * Start by setting all Owl devices to 2x2 168 */ 169 AH5416(ah)->ah_rx_chainmask = AR5416_DEFAULT_RXCHAINMASK; 170 AH5416(ah)->ah_tx_chainmask = AR5416_DEFAULT_TXCHAINMASK; 171} 172 173uint32_t 174ar5416GetRadioRev(struct ath_hal *ah) 175{ 176 uint32_t val; 177 int i; 178 179 /* Read Radio Chip Rev Extract */ 180 OS_REG_WRITE(ah, AR_PHY(0x36), 0x00007058); 181 for (i = 0; i < 8; i++) 182 OS_REG_WRITE(ah, AR_PHY(0x20), 0x00010000); 183 val = (OS_REG_READ(ah, AR_PHY(256)) >> 24) & 0xff; 184 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4); 185 return ath_hal_reverseBits(val, 8); 186} 187 188/* 189 * Attach for an AR5416 part. 190 */ 191static struct ath_hal * 192ar5416Attach(uint16_t devid, HAL_SOFTC sc, 193 HAL_BUS_TAG st, HAL_BUS_HANDLE sh, uint16_t *eepromdata, 194 HAL_STATUS *status) 195{ 196 struct ath_hal_5416 *ahp5416; 197 struct ath_hal_5212 *ahp; 198 struct ath_hal *ah; 199 uint32_t val; 200 HAL_STATUS ecode; 201 HAL_BOOL rfStatus; 202 203 HALDEBUG(AH_NULL, HAL_DEBUG_ATTACH, "%s: sc %p st %p sh %p\n", 204 __func__, sc, (void*) st, (void*) sh); 205 206 /* NB: memory is returned zero'd */ 207 ahp5416 = ath_hal_malloc(sizeof (struct ath_hal_5416) + 208 /* extra space for Owl 2.1/2.2 WAR */ 209 sizeof(ar5416Addac) 210 ); 211 if (ahp5416 == AH_NULL) { 212 HALDEBUG(AH_NULL, HAL_DEBUG_ANY, 213 "%s: cannot allocate memory for state block\n", __func__); 214 *status = HAL_ENOMEM; 215 return AH_NULL; 216 } 217 ar5416InitState(ahp5416, devid, sc, st, sh, status); 218 ahp = &ahp5416->ah_5212; 219 ah = &ahp->ah_priv.h; 220 221 if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { 222 /* reset chip */ 223 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't reset chip\n", __func__); 224 ecode = HAL_EIO; 225 goto bad; 226 } 227 228 if (!ar5416SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE)) { 229 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: couldn't wakeup chip\n", __func__); 230 ecode = HAL_EIO; 231 goto bad; 232 } 233 /* Read Revisions from Chips before taking out of reset */ 234 val = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID; 235 AH_PRIVATE(ah)->ah_macVersion = val >> AR_SREV_ID_S; 236 AH_PRIVATE(ah)->ah_macRev = val & AR_SREV_REVISION; 237 AH_PRIVATE(ah)->ah_ispcie = (devid == AR5416_DEVID_PCIE); 238 239 /* setup common ini data; rf backends handle remainder */ 240 HAL_INI_INIT(&ahp->ah_ini_modes, ar5416Modes, 6); 241 HAL_INI_INIT(&ahp->ah_ini_common, ar5416Common, 2); 242 243 HAL_INI_INIT(&AH5416(ah)->ah_ini_bb_rfgain, ar5416BB_RfGain, 3); 244 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank0, ar5416Bank0, 2); 245 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank1, ar5416Bank1, 2); 246 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank2, ar5416Bank2, 2); 247 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank3, ar5416Bank3, 3); 248 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank6, ar5416Bank6, 3); 249 HAL_INI_INIT(&AH5416(ah)->ah_ini_bank7, ar5416Bank7, 2); 250 HAL_INI_INIT(&AH5416(ah)->ah_ini_addac, ar5416Addac, 2); 251 252 if (!IS_5416V2_2(ah)) { /* Owl 2.1/2.0 */ 253 struct ini { 254 uint32_t *data; /* NB: !const */ 255 int rows, cols; 256 }; 257 /* override CLKDRV value */ 258 OS_MEMCPY(&AH5416(ah)[1], ar5416Addac, sizeof(ar5416Addac)); 259 AH5416(ah)->ah_ini_addac.data = (uint32_t *) &AH5416(ah)[1]; 260 HAL_INI_VAL((struct ini *)&AH5416(ah)->ah_ini_addac, 31, 1) = 0; 261 } 262 263 HAL_INI_INIT(&AH5416(ah)->ah_ini_pcieserdes, ar5416PciePhy, 2); 264 ar5416AttachPCIE(ah); 265 266 ecode = ath_hal_v14EepromAttach(ah); 267 if (ecode != HAL_OK) 268 goto bad; 269 270 if (!ar5416ChipReset(ah, AH_NULL)) { /* reset chip */ 271 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n", 272 __func__); 273 ecode = HAL_EIO; 274 goto bad; 275 } 276 277 AH_PRIVATE(ah)->ah_phyRev = OS_REG_READ(ah, AR_PHY_CHIP_ID); 278 279 if (!ar5212ChipTest(ah)) { 280 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: hardware self-test failed\n", 281 __func__); 282 ecode = HAL_ESELFTEST; 283 goto bad; 284 } 285 286 /* 287 * Set correct Baseband to analog shift 288 * setting to access analog chips. 289 */ 290 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 291 292 /* Read Radio Chip Rev Extract */ 293 AH_PRIVATE(ah)->ah_analog5GhzRev = ar5212GetRadioRev(ah); 294 switch (AH_PRIVATE(ah)->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR) { 295 case AR_RAD5122_SREV_MAJOR: /* Fowl: 5G/2x2 */ 296 case AR_RAD2122_SREV_MAJOR: /* Fowl: 2+5G/2x2 */ 297 case AR_RAD2133_SREV_MAJOR: /* Fowl: 2G/3x3 */ 298 case AR_RAD5133_SREV_MAJOR: /* Fowl: 2+5G/3x3 */ 299 break; 300 default: 301 if (AH_PRIVATE(ah)->ah_analog5GhzRev == 0) { 302 /* 303 * When RF_Silen is used the analog chip is reset. 304 * So when the system boots with radio switch off 305 * the RF chip rev reads back as zero and we need 306 * to use the mac+phy revs to set the radio rev. 307 */ 308 AH_PRIVATE(ah)->ah_analog5GhzRev = 309 AR_RAD5133_SREV_MAJOR; 310 break; 311 } 312 /* NB: silently accept anything in release code per Atheros */ 313#ifdef AH_DEBUG 314 HALDEBUG(ah, HAL_DEBUG_ANY, 315 "%s: 5G Radio Chip Rev 0x%02X is not supported by " 316 "this driver\n", __func__, 317 AH_PRIVATE(ah)->ah_analog5GhzRev); 318 ecode = HAL_ENOTSUPP; 319 goto bad; 320#endif 321 } 322 323 /* 324 * Got everything we need now to setup the capabilities. 325 */ 326 if (!ar5416FillCapabilityInfo(ah)) { 327 ecode = HAL_EEREAD; 328 goto bad; 329 } 330 331 ecode = ath_hal_eepromGet(ah, AR_EEP_MACADDR, ahp->ah_macaddr); 332 if (ecode != HAL_OK) { 333 HALDEBUG(ah, HAL_DEBUG_ANY, 334 "%s: error getting mac address from EEPROM\n", __func__); 335 goto bad; 336 } 337 /* XXX How about the serial number ? */ 338 /* Read Reg Domain */ 339 AH_PRIVATE(ah)->ah_currentRD = 340 ath_hal_eepromGet(ah, AR_EEP_REGDMN_0, AH_NULL); 341 342 /* 343 * ah_miscMode is populated by ar5416FillCapabilityInfo() 344 * starting from griffin. Set here to make sure that 345 * AR_MISC_MODE_MIC_NEW_LOC_ENABLE is set before a GTK is 346 * placed into hardware. 347 */ 348 if (ahp->ah_miscMode != 0) 349 OS_REG_WRITE(ah, AR_MISC_MODE, ahp->ah_miscMode); 350 351 rfStatus = ar2133RfAttach(ah, &ecode); 352 if (!rfStatus) { 353 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: RF setup failed, status %u\n", 354 __func__, ecode); 355 goto bad; 356 } 357 358 ar5416AniSetup(ah); /* Anti Noise Immunity */ 359 360 AH5416(ah)->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ; 361 AH5416(ah)->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ; 362 AH5416(ah)->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ; 363 AH5416(ah)->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ; 364 AH5416(ah)->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ; 365 AH5416(ah)->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ; 366 367 ar5416InitNfHistBuff(AH5416(ah)->ah_cal.nfCalHist); 368 369 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s: return\n", __func__); 370 371 return ah; 372bad: 373 if (ahp) 374 ar5416Detach((struct ath_hal *) ahp); 375 if (status) 376 *status = ecode; 377 return AH_NULL; 378} 379 380void 381ar5416Detach(struct ath_hal *ah) 382{ 383 HALDEBUG(ah, HAL_DEBUG_ATTACH, "%s:\n", __func__); 384 385 HALASSERT(ah != AH_NULL); 386 HALASSERT(ah->ah_magic == AR5416_MAGIC); 387 388 ar5416AniDetach(ah); 389 ar5212RfDetach(ah); 390 ah->ah_disable(ah); 391 ar5416SetPowerMode(ah, HAL_PM_FULL_SLEEP, AH_TRUE); 392 ath_hal_eepromDetach(ah); 393 ath_hal_free(ah); 394} 395 396void 397ar5416AttachPCIE(struct ath_hal *ah) 398{ 399 if (AH_PRIVATE(ah)->ah_ispcie) 400 ath_hal_configPCIE(ah, AH_FALSE); 401 else 402 ath_hal_disablePCIE(ah); 403} 404 405static void 406ar5416ConfigPCIE(struct ath_hal *ah, HAL_BOOL restore) 407{ 408 if (AH_PRIVATE(ah)->ah_ispcie && !restore) { 409 ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_pcieserdes, 1, 0); 410 OS_DELAY(1000); 411 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); 412 OS_REG_WRITE(ah, AR_WA, AR_WA_DEFAULT); 413 } 414} 415 416static void 417ar5416WriteIni(struct ath_hal *ah, const struct ieee80211_channel *chan) 418{ 419 u_int modesIndex, freqIndex; 420 int regWrites = 0; 421 422 /* Setup the indices for the next set of register array writes */ 423 /* XXX Ignore 11n dynamic mode on the AR5416 for the moment */ 424 if (IEEE80211_IS_CHAN_2GHZ(chan)) { 425 freqIndex = 2; 426 if (IEEE80211_IS_CHAN_HT40(chan)) 427 modesIndex = 3; 428 else if (IEEE80211_IS_CHAN_108G(chan)) 429 modesIndex = 5; 430 else 431 modesIndex = 4; 432 } else { 433 freqIndex = 1; 434 if (IEEE80211_IS_CHAN_HT40(chan) || 435 IEEE80211_IS_CHAN_TURBO(chan)) 436 modesIndex = 2; 437 else 438 modesIndex = 1; 439 } 440 441 /* Set correct Baseband to analog shift setting to access analog chips. */ 442 OS_REG_WRITE(ah, AR_PHY(0), 0x00000007); 443 444 /* 445 * Write addac shifts 446 */ 447 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO); 448#if 0 449 /* NB: only required for Sowl */ 450 ar5416EepromSetAddac(ah, chan); 451#endif 452 regWrites = ath_hal_ini_write(ah, &AH5416(ah)->ah_ini_addac, 1, 453 regWrites); 454 OS_REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC); 455 456 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_modes, 457 modesIndex, regWrites); 458 regWrites = ath_hal_ini_write(ah, &AH5212(ah)->ah_ini_common, 459 1, regWrites); 460 461 /* XXX updated regWrites? */ 462 AH5212(ah)->ah_rfHal->writeRegs(ah, modesIndex, freqIndex, regWrites); 463} 464 465/* 466 * Convert to baseband spur frequency given input channel frequency 467 * and compute register settings below. 468 */ 469 470static void 471ar5416SpurMitigate(struct ath_hal *ah, const struct ieee80211_channel *chan) 472{ 473 uint16_t freq = ath_hal_gethwchannel(ah, chan); 474 static const int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8, 475 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60 }; 476 static const int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10, 477 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60 }; 478 static const int inc[4] = { 0, 100, 0, 0 }; 479 480 int bb_spur = AR_NO_SPUR; 481 int bin, cur_bin; 482 int spur_freq_sd; 483 int spur_delta_phase; 484 int denominator; 485 int upper, lower, cur_vit_mask; 486 int tmp, new; 487 int i; 488 489 int8_t mask_m[123]; 490 int8_t mask_p[123]; 491 int8_t mask_amt; 492 int tmp_mask; 493 int cur_bb_spur; 494 HAL_BOOL is2GHz = IEEE80211_IS_CHAN_2GHZ(chan); 495 496 OS_MEMZERO(mask_m, sizeof(mask_m)); 497 OS_MEMZERO(mask_p, sizeof(mask_p)); 498 499 /* 500 * Need to verify range +/- 9.5 for static ht20, otherwise spur 501 * is out-of-band and can be ignored. 502 */ 503 /* XXX ath9k changes */ 504 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) { 505 cur_bb_spur = ath_hal_getSpurChan(ah, i, is2GHz); 506 if (AR_NO_SPUR == cur_bb_spur) 507 break; 508 cur_bb_spur = cur_bb_spur - (freq * 10); 509 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) { 510 bb_spur = cur_bb_spur; 511 break; 512 } 513 } 514 if (AR_NO_SPUR == bb_spur) 515 return; 516 517 bin = bb_spur * 32; 518 519 tmp = OS_REG_READ(ah, AR_PHY_TIMING_CTRL4_CHAIN(0)); 520 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI | 521 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER | 522 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK | 523 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK); 524 525 OS_REG_WRITE(ah, AR_PHY_TIMING_CTRL4_CHAIN(0), new); 526 527 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL | 528 AR_PHY_SPUR_REG_ENABLE_MASK_PPM | 529 AR_PHY_SPUR_REG_MASK_RATE_SELECT | 530 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI | 531 SM(AR5416_SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); 532 OS_REG_WRITE(ah, AR_PHY_SPUR_REG, new); 533 /* 534 * Should offset bb_spur by +/- 10 MHz for dynamic 2040 MHz 535 * config, no offset for HT20. 536 * spur_delta_phase = bb_spur/40 * 2**21 for static ht20, 537 * /80 for dyn2040. 538 */ 539 spur_delta_phase = ((bb_spur * 524288) / 100) & 540 AR_PHY_TIMING11_SPUR_DELTA_PHASE; 541 /* 542 * in 11A mode the denominator of spur_freq_sd should be 40 and 543 * it should be 44 in 11G 544 */ 545 denominator = IEEE80211_IS_CHAN_2GHZ(chan) ? 440 : 400; 546 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff; 547 548 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC | 549 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | 550 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); 551 OS_REG_WRITE(ah, AR_PHY_TIMING11, new); 552 553 554 /* 555 * ============================================ 556 * pilot mask 1 [31:0] = +6..-26, no 0 bin 557 * pilot mask 2 [19:0] = +26..+7 558 * 559 * channel mask 1 [31:0] = +6..-26, no 0 bin 560 * channel mask 2 [19:0] = +26..+7 561 */ 562 //cur_bin = -26; 563 cur_bin = -6000; 564 upper = bin + 100; 565 lower = bin - 100; 566 567 for (i = 0; i < 4; i++) { 568 int pilot_mask = 0; 569 int chan_mask = 0; 570 int bp = 0; 571 for (bp = 0; bp < 30; bp++) { 572 if ((cur_bin > lower) && (cur_bin < upper)) { 573 pilot_mask = pilot_mask | 0x1 << bp; 574 chan_mask = chan_mask | 0x1 << bp; 575 } 576 cur_bin += 100; 577 } 578 cur_bin += inc[i]; 579 OS_REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 580 OS_REG_WRITE(ah, chan_mask_reg[i], chan_mask); 581 } 582 583 /* ================================================= 584 * viterbi mask 1 based on channel magnitude 585 * four levels 0-3 586 * - mask (-27 to 27) (reg 64,0x9900 to 67,0x990c) 587 * [1 2 2 1] for -9.6 or [1 2 1] for +16 588 * - enable_mask_ppm, all bins move with freq 589 * 590 * - mask_select, 8 bits for rates (reg 67,0x990c) 591 * - mask_rate_cntl, 8 bits for rates (reg 67,0x990c) 592 * choose which mask to use mask or mask2 593 */ 594 595 /* 596 * viterbi mask 2 2nd set for per data rate puncturing 597 * four levels 0-3 598 * - mask_select, 8 bits for rates (reg 67) 599 * - mask (-27 to 27) (reg 98,0x9988 to 101,0x9994) 600 * [1 2 2 1] for -9.6 or [1 2 1] for +16 601 */ 602 cur_vit_mask = 6100; 603 upper = bin + 120; 604 lower = bin - 120; 605 606 for (i = 0; i < 123; i++) { 607 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) { 608 if ((abs(cur_vit_mask - bin)) < 75) { 609 mask_amt = 1; 610 } else { 611 mask_amt = 0; 612 } 613 if (cur_vit_mask < 0) { 614 mask_m[abs(cur_vit_mask / 100)] = mask_amt; 615 } else { 616 mask_p[cur_vit_mask / 100] = mask_amt; 617 } 618 } 619 cur_vit_mask -= 100; 620 } 621 622 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28) 623 | (mask_m[48] << 26) | (mask_m[49] << 24) 624 | (mask_m[50] << 22) | (mask_m[51] << 20) 625 | (mask_m[52] << 18) | (mask_m[53] << 16) 626 | (mask_m[54] << 14) | (mask_m[55] << 12) 627 | (mask_m[56] << 10) | (mask_m[57] << 8) 628 | (mask_m[58] << 6) | (mask_m[59] << 4) 629 | (mask_m[60] << 2) | (mask_m[61] << 0); 630 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask); 631 OS_REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask); 632 633 tmp_mask = (mask_m[31] << 28) 634 | (mask_m[32] << 26) | (mask_m[33] << 24) 635 | (mask_m[34] << 22) | (mask_m[35] << 20) 636 | (mask_m[36] << 18) | (mask_m[37] << 16) 637 | (mask_m[48] << 14) | (mask_m[39] << 12) 638 | (mask_m[40] << 10) | (mask_m[41] << 8) 639 | (mask_m[42] << 6) | (mask_m[43] << 4) 640 | (mask_m[44] << 2) | (mask_m[45] << 0); 641 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask); 642 OS_REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask); 643 644 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28) 645 | (mask_m[18] << 26) | (mask_m[18] << 24) 646 | (mask_m[20] << 22) | (mask_m[20] << 20) 647 | (mask_m[22] << 18) | (mask_m[22] << 16) 648 | (mask_m[24] << 14) | (mask_m[24] << 12) 649 | (mask_m[25] << 10) | (mask_m[26] << 8) 650 | (mask_m[27] << 6) | (mask_m[28] << 4) 651 | (mask_m[29] << 2) | (mask_m[30] << 0); 652 OS_REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask); 653 OS_REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask); 654 655 tmp_mask = (mask_m[ 0] << 30) | (mask_m[ 1] << 28) 656 | (mask_m[ 2] << 26) | (mask_m[ 3] << 24) 657 | (mask_m[ 4] << 22) | (mask_m[ 5] << 20) 658 | (mask_m[ 6] << 18) | (mask_m[ 7] << 16) 659 | (mask_m[ 8] << 14) | (mask_m[ 9] << 12) 660 | (mask_m[10] << 10) | (mask_m[11] << 8) 661 | (mask_m[12] << 6) | (mask_m[13] << 4) 662 | (mask_m[14] << 2) | (mask_m[15] << 0); 663 OS_REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask); 664 OS_REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask); 665 666 tmp_mask = (mask_p[15] << 28) 667 | (mask_p[14] << 26) | (mask_p[13] << 24) 668 | (mask_p[12] << 22) | (mask_p[11] << 20) 669 | (mask_p[10] << 18) | (mask_p[ 9] << 16) 670 | (mask_p[ 8] << 14) | (mask_p[ 7] << 12) 671 | (mask_p[ 6] << 10) | (mask_p[ 5] << 8) 672 | (mask_p[ 4] << 6) | (mask_p[ 3] << 4) 673 | (mask_p[ 2] << 2) | (mask_p[ 1] << 0); 674 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask); 675 OS_REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask); 676 677 tmp_mask = (mask_p[30] << 28) 678 | (mask_p[29] << 26) | (mask_p[28] << 24) 679 | (mask_p[27] << 22) | (mask_p[26] << 20) 680 | (mask_p[25] << 18) | (mask_p[24] << 16) 681 | (mask_p[23] << 14) | (mask_p[22] << 12) 682 | (mask_p[21] << 10) | (mask_p[20] << 8) 683 | (mask_p[19] << 6) | (mask_p[18] << 4) 684 | (mask_p[17] << 2) | (mask_p[16] << 0); 685 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask); 686 OS_REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask); 687 688 tmp_mask = (mask_p[45] << 28) 689 | (mask_p[44] << 26) | (mask_p[43] << 24) 690 | (mask_p[42] << 22) | (mask_p[41] << 20) 691 | (mask_p[40] << 18) | (mask_p[39] << 16) 692 | (mask_p[38] << 14) | (mask_p[37] << 12) 693 | (mask_p[36] << 10) | (mask_p[35] << 8) 694 | (mask_p[34] << 6) | (mask_p[33] << 4) 695 | (mask_p[32] << 2) | (mask_p[31] << 0); 696 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask); 697 OS_REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask); 698 699 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28) 700 | (mask_p[59] << 26) | (mask_p[58] << 24) 701 | (mask_p[57] << 22) | (mask_p[56] << 20) 702 | (mask_p[55] << 18) | (mask_p[54] << 16) 703 | (mask_p[53] << 14) | (mask_p[52] << 12) 704 | (mask_p[51] << 10) | (mask_p[50] << 8) 705 | (mask_p[49] << 6) | (mask_p[48] << 4) 706 | (mask_p[47] << 2) | (mask_p[46] << 0); 707 OS_REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask); 708 OS_REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask); 709} 710 711/* 712 * Fill all software cached or static hardware state information. 713 * Return failure if capabilities are to come from EEPROM and 714 * cannot be read. 715 */ 716HAL_BOOL 717ar5416FillCapabilityInfo(struct ath_hal *ah) 718{ 719 struct ath_hal_private *ahpriv = AH_PRIVATE(ah); 720 HAL_CAPABILITIES *pCap = &ahpriv->ah_caps; 721 uint16_t val; 722 723 /* Construct wireless mode from EEPROM */ 724 pCap->halWirelessModes = 0; 725 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) { 726 pCap->halWirelessModes |= HAL_MODE_11A 727 | HAL_MODE_11NA_HT20 728 | HAL_MODE_11NA_HT40PLUS 729 | HAL_MODE_11NA_HT40MINUS 730 ; 731 } 732 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE)) { 733 pCap->halWirelessModes |= HAL_MODE_11G 734 | HAL_MODE_11NG_HT20 735 | HAL_MODE_11NG_HT40PLUS 736 | HAL_MODE_11NG_HT40MINUS 737 ; 738 pCap->halWirelessModes |= HAL_MODE_11A 739 | HAL_MODE_11NA_HT20 740 | HAL_MODE_11NA_HT40PLUS 741 | HAL_MODE_11NA_HT40MINUS 742 ; 743 } 744 745 pCap->halLow2GhzChan = 2312; 746 pCap->halHigh2GhzChan = 2732; 747 748 pCap->halLow5GhzChan = 4915; 749 pCap->halHigh5GhzChan = 6100; 750 751 pCap->halCipherCkipSupport = AH_FALSE; 752 pCap->halCipherTkipSupport = AH_TRUE; 753 pCap->halCipherAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 754 755 pCap->halMicCkipSupport = AH_FALSE; 756 pCap->halMicTkipSupport = AH_TRUE; 757 pCap->halMicAesCcmSupport = ath_hal_eepromGetFlag(ah, AR_EEP_AES); 758 /* 759 * Starting with Griffin TX+RX mic keys can be combined 760 * in one key cache slot. 761 */ 762 pCap->halTkipMicTxRxKeySupport = AH_TRUE; 763 pCap->halChanSpreadSupport = AH_TRUE; 764 pCap->halSleepAfterBeaconBroken = AH_TRUE; 765 766 pCap->halCompressSupport = AH_FALSE; 767 pCap->halBurstSupport = AH_TRUE; 768 pCap->halFastFramesSupport = AH_FALSE; /* XXX? */ 769 pCap->halChapTuningSupport = AH_TRUE; 770 pCap->halTurboPrimeSupport = AH_TRUE; 771 772 pCap->halTurboGSupport = pCap->halWirelessModes & HAL_MODE_108G; 773 774 pCap->halPSPollBroken = AH_TRUE; /* XXX fixed in later revs? */ 775 pCap->halVEOLSupport = AH_TRUE; 776 pCap->halBssIdMaskSupport = AH_TRUE; 777 pCap->halMcastKeySrchSupport = AH_FALSE; 778 pCap->halTsfAddSupport = AH_TRUE; 779 780 if (ath_hal_eepromGet(ah, AR_EEP_MAXQCU, &val) == HAL_OK) 781 pCap->halTotalQueues = val; 782 else 783 pCap->halTotalQueues = HAL_NUM_TX_QUEUES; 784 785 if (ath_hal_eepromGet(ah, AR_EEP_KCENTRIES, &val) == HAL_OK) 786 pCap->halKeyCacheSize = val; 787 else 788 pCap->halKeyCacheSize = AR5416_KEYTABLE_SIZE; 789 790 /* XXX not needed */ 791 pCap->halChanHalfRate = AH_FALSE; /* XXX ? */ 792 pCap->halChanQuarterRate = AH_FALSE; /* XXX ? */ 793 794 pCap->halTstampPrecision = 32; 795 pCap->halHwPhyCounterSupport = AH_TRUE; 796 pCap->halIntrMask = HAL_INT_COMMON 797 | HAL_INT_RX 798 | HAL_INT_TX 799 | HAL_INT_FATAL 800 | HAL_INT_BNR 801 | HAL_INT_BMISC 802 | HAL_INT_DTIMSYNC 803 | HAL_INT_TSFOOR 804 | HAL_INT_CST 805 | HAL_INT_GTT 806 ; 807 808 pCap->halFastCCSupport = AH_TRUE; 809 pCap->halNumGpioPins = 6; 810 pCap->halWowSupport = AH_FALSE; 811 pCap->halWowMatchPatternExact = AH_FALSE; 812 pCap->halBtCoexSupport = AH_FALSE; /* XXX need support */ 813 pCap->halAutoSleepSupport = AH_FALSE; 814 pCap->hal4kbSplitTransSupport = AH_TRUE; 815#if 0 /* XXX not yet */ 816 pCap->halNumAntCfg2GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_2GHZ); 817 pCap->halNumAntCfg5GHz = ar5416GetNumAntConfig(ahp, HAL_FREQ_BAND_5GHZ); 818#endif 819 pCap->halHTSupport = AH_TRUE; 820 pCap->halTxChainMask = ath_hal_eepromGet(ah, AR_EEP_TXMASK, AH_NULL); 821 /* XXX CB71 uses GPIO 0 to indicate 3 rx chains */ 822 pCap->halRxChainMask = ath_hal_eepromGet(ah, AR_EEP_RXMASK, AH_NULL); 823 /* AR5416 may have 3 antennas but is a 2x2 stream device */ 824 pCap->halTxStreams = 2; 825 pCap->halRxStreams = 2; 826 pCap->halRtsAggrLimit = 8*1024; /* Owl 2.0 limit */ 827 pCap->halMbssidAggrSupport = AH_TRUE; 828 pCap->halForcePpmSupport = AH_TRUE; 829 pCap->halEnhancedPmSupport = AH_TRUE; 830 pCap->halBssidMatchSupport = AH_TRUE; 831 832 if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) && 833 ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) { 834 /* NB: enabled by default */ 835 ahpriv->ah_rfkillEnabled = AH_TRUE; 836 pCap->halRfSilentSupport = AH_TRUE; 837 } 838 839 ahpriv->ah_rxornIsFatal = AH_FALSE; 840 841 return AH_TRUE; 842} 843 844static const char* 845ar5416Probe(uint16_t vendorid, uint16_t devid) 846{ 847 if (vendorid == ATHEROS_VENDOR_ID && 848 (devid == AR5416_DEVID_PCI || devid == AR5416_DEVID_PCIE)) 849 return "Atheros 5416"; 850 return AH_NULL; 851} 852AH_CHIP(AR5416, ar5416Probe, ar5416Attach); 853