1139749Simp/*- 252417Sluoqi * Copyright (c) 1994 Charles Hannum. 352417Sluoqi * Copyright (c) 1994 Jarle Greipsland. 452417Sluoqi * All rights reserved. 552417Sluoqi * 652417Sluoqi * Redistribution and use in source and binary forms, with or without 752417Sluoqi * modification, are permitted provided that the following conditions 852417Sluoqi * are met: 952417Sluoqi * 1. Redistributions of source code must retain the above copyright 1052417Sluoqi * notice, this list of conditions and the following disclaimer. 1152417Sluoqi * 2. Redistributions in binary form must reproduce the above copyright 1252417Sluoqi * notice, this list of conditions and the following disclaimer in the 1352417Sluoqi * documentation and/or other materials provided with the distribution. 1452417Sluoqi * 3. All advertising materials mentioning features or use of this software 1552417Sluoqi * must display the following acknowledgement: 1652417Sluoqi * This product includes software developed by Jarle Greipsland 1752417Sluoqi * 4. The name of the author may not be used to endorse or promote products 1852417Sluoqi * derived from this software without specific prior written permission. 1952417Sluoqi * 2052417Sluoqi * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 2152417Sluoqi * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 2252417Sluoqi * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 2352417Sluoqi * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 2452417Sluoqi * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 2552417Sluoqi * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 2652417Sluoqi * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2752417Sluoqi * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 2852417Sluoqi * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 2952417Sluoqi * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3052417Sluoqi * POSSIBILITY OF SUCH DAMAGE. 3152417Sluoqi * 3252417Sluoqi * $FreeBSD$ 3352417Sluoqi */ 3452417Sluoqi 3552417Sluoqi#define SCSISEQ 0x00 /* SCSI sequence control */ 3652417Sluoqi#define SXFRCTL0 0x01 /* SCSI transfer control 0 */ 3752417Sluoqi#define SXFRCTL1 0x02 /* SCSI transfer control 1 */ 3852417Sluoqi#define SCSISIGI 0x03 /* SCSI signal in */ 3952417Sluoqi#define SCSISIGO 0x03 /* SCSI signal out */ 4052417Sluoqi#define SCSIRATE 0x04 /* SCSI rate control */ 4152417Sluoqi#define SCSIID 0x05 /* SCSI ID */ 4252417Sluoqi#define SELID 0x05 /* Selection/Reselection ID */ 4352417Sluoqi#define SCSIDAT 0x06 /* SCSI Latched Data */ 4452417Sluoqi#define SCSIBUS 0x07 /* SCSI Data Bus*/ 4552417Sluoqi#define STCNT0 0x08 /* SCSI transfer count */ 4652417Sluoqi#define STCNT1 0x09 4752417Sluoqi#define STCNT2 0x0a 4852417Sluoqi#define CLRSINT0 0x0b /* Clear SCSI interrupts 0 */ 4952417Sluoqi#define SSTAT0 0x0b /* SCSI interrupt status 0 */ 5052417Sluoqi#define CLRSINT1 0x0c /* Clear SCSI interrupts 1 */ 5152417Sluoqi#define SSTAT1 0x0c /* SCSI status 1 */ 5252417Sluoqi#define SSTAT2 0x0d /* SCSI status 2 */ 5352417Sluoqi#define SCSITEST 0x0e /* SCSI test control */ 5452417Sluoqi#define SSTAT3 0x0e /* SCSI status 3 */ 5552417Sluoqi#define CLRSERR 0x0f /* Clear SCSI errors */ 5652417Sluoqi#define SSTAT4 0x0f /* SCSI status 4 */ 5752417Sluoqi#define SIMODE0 0x10 /* SCSI interrupt mode 0 */ 5852417Sluoqi#define SIMODE1 0x11 /* SCSI interrupt mode 1 */ 5952417Sluoqi#define DMACNTRL0 0x12 /* DMA control 0 */ 6052417Sluoqi#define DMACNTRL1 0x13 /* DMA control 1 */ 6152417Sluoqi#define DMASTAT 0x14 /* DMA status */ 6252417Sluoqi#define FIFOSTAT 0x15 /* FIFO status */ 6352417Sluoqi#define DMADATA 0x16 /* DMA data */ 6452417Sluoqi#define DMADATAL 0x16 /* DMA data low byte */ 6552417Sluoqi#define DMADATAH 0x17 /* DMA data high byte */ 6652417Sluoqi#define BRSTCNTRL 0x18 /* Burst Control */ 6752417Sluoqi#define DMADATALONG 0x18 6852417Sluoqi#define PORTA 0x1a /* Port A */ 6952417Sluoqi#define PORTB 0x1b /* Port B */ 7052417Sluoqi#define REV 0x1c /* Revision (001 for 6360) */ 7152417Sluoqi#define STACK 0x1d /* Stack */ 7252417Sluoqi#define TEST 0x1e /* Test register */ 7352417Sluoqi#define ID 0x1f /* ID register */ 7452417Sluoqi 7592370Sluoqi#define IDSTRING_AIC6360 "(C)1991ADAPTECAIC6360 " 7692370Sluoqi#define IDSTRING_AIC6370 "(C)1994ADAPTECAIC6370" 7792370Sluoqi#define IDSTRING_GM82C700 "(C)1993 GoldStarGM82C700 " 7852417Sluoqi 7952417Sluoqi/* What all the bits do */ 8052417Sluoqi 8152417Sluoqi/* SCSISEQ */ 8252417Sluoqi#define TEMODEO 0x80 8352417Sluoqi#define ENSELO 0x40 8452417Sluoqi#define ENSELI 0x20 8552417Sluoqi#define ENRESELI 0x10 8652417Sluoqi#define ENAUTOATNO 0x08 8752417Sluoqi#define ENAUTOATNI 0x04 8852417Sluoqi#define ENAUTOATNP 0x02 8952417Sluoqi#define SCSIRSTO 0x01 9052417Sluoqi 9152417Sluoqi/* SXFRCTL0 */ 9252417Sluoqi#define SCSIEN 0x80 9352417Sluoqi#define DMAEN 0x40 9452417Sluoqi#define CHEN 0x20 9552417Sluoqi#define CLRSTCNT 0x10 9652417Sluoqi#define SPIOEN 0x08 9752417Sluoqi#define CLRCH 0x02 9852417Sluoqi 9952417Sluoqi/* SXFRCTL1 */ 10052417Sluoqi#define BITBUCKET 0x80 10152417Sluoqi#define SWRAPEN 0x40 10252417Sluoqi#define ENSPCHK 0x20 10352417Sluoqi#define STIMESEL1 0x10 10452417Sluoqi#define STIMESEL0 0x08 10552417Sluoqi#define STIMO_256ms 0x00 10652417Sluoqi#define STIMO_128ms 0x08 10752417Sluoqi#define STIMO_64ms 0x10 10852417Sluoqi#define STIMO_32ms 0x18 10952417Sluoqi#define ENSTIMER 0x04 11052417Sluoqi#define BYTEALIGN 0x02 11152417Sluoqi 11252417Sluoqi/* SCSISIGI */ 11352417Sluoqi#define CDI 0x80 11452417Sluoqi#define IOI 0x40 11552417Sluoqi#define MSGI 0x20 11652417Sluoqi#define ATNI 0x10 11752417Sluoqi#define SELI 0x08 11852417Sluoqi#define BSYI 0x04 11952417Sluoqi#define REQI 0x02 12052417Sluoqi#define ACKI 0x01 12152417Sluoqi 12252417Sluoqi/* Important! The 3 most significant bits of this register, in initiator mode, 12352417Sluoqi * represents the "expected" SCSI bus phase and can be used to trigger phase 12452417Sluoqi * mismatch and phase change interrupts. But more important: If there is a 12552417Sluoqi * phase mismatch the chip will not transfer any data! This is actually a nice 12652417Sluoqi * feature as it gives us a bit more control over what is happening when we are 12752417Sluoqi * bursting data (in) through the FIFOs and the phase suddenly changes from 12852417Sluoqi * DATA IN to STATUS or MESSAGE IN. The transfer will stop and wait for the 12952417Sluoqi * proper phase to be set in this register instead of dumping the bits into the 13052417Sluoqi * FIFOs. 13152417Sluoqi */ 13252417Sluoqi/* SCSISIGO */ 13352417Sluoqi#define CDO 0x80 13452417Sluoqi#define IOO 0x40 13552417Sluoqi#define MSGO 0x20 13652417Sluoqi#define ATNO 0x10 13752417Sluoqi#define SELO 0x08 13852417Sluoqi#define BSYO 0x04 13952417Sluoqi#define REQO 0x02 14052417Sluoqi#define ACKO 0x01 14152417Sluoqi 14252417Sluoqi/* Information transfer phases */ 14352417Sluoqi#define PH_DATAOUT (0) 14452417Sluoqi#define PH_DATAIN (IOI) 14552417Sluoqi#define PH_CMD (CDI) 14652417Sluoqi#define PH_STAT (CDI|IOI) 14752417Sluoqi#define PH_MSGOUT (MSGI|CDI) 14852417Sluoqi#define PH_MSGIN (MSGI|CDI|IOI) 14952417Sluoqi#define PH_MASK (MSGI|CDI|IOI) 15052417Sluoqi 15152417Sluoqi/* SCSIRATE */ 15252417Sluoqi#define SXFR2 0x40 15352417Sluoqi#define SXFR1 0x20 15452417Sluoqi#define SXFR0 0x10 15552417Sluoqi#define SOFS3 0x08 15652417Sluoqi#define SOFS2 0x04 15752417Sluoqi#define SOFS1 0x02 15852417Sluoqi#define SOFS0 0x01 15952417Sluoqi 16052417Sluoqi/* SCSI ID */ 16152417Sluoqi#define OID2 0x40 16252417Sluoqi#define OID1 0x20 16352417Sluoqi#define OID0 0x10 16452417Sluoqi#define OID_S 4 /* shift value */ 16552417Sluoqi#define TID2 0x04 16652417Sluoqi#define TID1 0x02 16752417Sluoqi#define TID0 0x01 16852417Sluoqi#define SCSI_ID_MASK 0x7 16952417Sluoqi 17052417Sluoqi/* SCSI selection/reselection ID (both target *and* initiator) */ 17152417Sluoqi#define SELID7 0x80 17252417Sluoqi#define SELID6 0x40 17352417Sluoqi#define SELID5 0x20 17452417Sluoqi#define SELID4 0x10 17552417Sluoqi#define SELID3 0x08 17652417Sluoqi#define SELID2 0x04 17752417Sluoqi#define SELID1 0x02 17852417Sluoqi#define SELID0 0x01 17952417Sluoqi 18052417Sluoqi/* CLRSINT0 Clears what? (interrupt and/or status bit) */ 18152417Sluoqi#define SETSDONE 0x80 18252417Sluoqi#define CLRSELDO 0x40 /* I */ 18352417Sluoqi#define CLRSELDI 0x20 /* I+ */ 18452417Sluoqi#define CLRSELINGO 0x10 /* I */ 18552417Sluoqi#define CLRSWRAP 0x08 /* I+S */ 18652417Sluoqi#define CLRSDONE 0x04 /* I+S */ 18752417Sluoqi#define CLRSPIORDY 0x02 /* I */ 18852417Sluoqi#define CLRDMADONE 0x01 /* I */ 18952417Sluoqi 19052417Sluoqi/* SSTAT0 Howto clear */ 19152417Sluoqi#define TARGET 0x80 19252417Sluoqi#define SELDO 0x40 /* Selfclearing */ 19352417Sluoqi#define SELDI 0x20 /* Selfclearing when CLRSELDI is set */ 19452417Sluoqi#define SELINGO 0x10 /* Selfclearing */ 19552417Sluoqi#define SWRAP 0x08 /* CLRSWAP */ 19652417Sluoqi#define SDONE 0x04 /* Not used in initiator mode */ 19752417Sluoqi#define SPIORDY 0x02 /* Selfclearing (op on SCSIDAT) */ 19852417Sluoqi#define DMADONE 0x01 /* Selfclearing (all FIFOs empty & T/C */ 19952417Sluoqi 20052417Sluoqi/* CLRSINT1 Clears what? */ 20152417Sluoqi#define CLRSELTIMO 0x80 /* I+S */ 20252417Sluoqi#define CLRATNO 0x40 20352417Sluoqi#define CLRSCSIRSTI 0x20 /* I+S */ 20452417Sluoqi#define CLRBUSFREE 0x08 /* I+S */ 20552417Sluoqi#define CLRSCSIPERR 0x04 /* I+S */ 20652417Sluoqi#define CLRPHASECHG 0x02 /* I+S */ 20752417Sluoqi#define CLRREQINIT 0x01 /* I+S */ 20852417Sluoqi 20952417Sluoqi/* SSTAT1 How to clear? When set?*/ 21052417Sluoqi#define SELTO 0x80 /* C select out timeout */ 21152417Sluoqi#define ATNTARG 0x40 /* Not used in initiator mode */ 21252417Sluoqi#define SCSIRSTI 0x20 /* C RST asserted */ 21352417Sluoqi#define PHASEMIS 0x10 /* Selfclearing */ 21452417Sluoqi#define BUSFREE 0x08 /* C bus free condition */ 21552417Sluoqi#define SCSIPERR 0x04 /* C parity error on inbound data */ 21652417Sluoqi#define PHASECHG 0x02 /* C phase in SCSISIGI doesn't match */ 21752417Sluoqi#define REQINIT 0x01 /* C or ACK asserting edge of REQ */ 21852417Sluoqi 21952417Sluoqi/* SSTAT2 */ 22052417Sluoqi#define SOFFSET 0x20 22152417Sluoqi#define SEMPTY 0x10 22252417Sluoqi#define SFULL 0x08 22352417Sluoqi#define SFCNT2 0x04 22452417Sluoqi#define SFCNT1 0x02 22552417Sluoqi#define SFCNT0 0x01 22652417Sluoqi 22752417Sluoqi/* SCSITEST */ 22852417Sluoqi#define SCTESTU 0x08 22952417Sluoqi#define SCTESTD 0x04 23052417Sluoqi#define STCTEST 0x01 23152417Sluoqi 23252417Sluoqi/* SSTAT3 */ 23352417Sluoqi#define SCSICNT3 0x80 23452417Sluoqi#define SCSICNT2 0x40 23552417Sluoqi#define SCSICNT1 0x20 23652417Sluoqi#define SCSICNT0 0x10 23752417Sluoqi#define OFFCNT3 0x08 23852417Sluoqi#define OFFCNT2 0x04 23952417Sluoqi#define OFFCNT1 0x02 24052417Sluoqi#define OFFCNT0 0x01 24152417Sluoqi 24252417Sluoqi/* CLRSERR */ 24352417Sluoqi#define CLRSYNCERR 0x04 24452417Sluoqi#define CLRFWERR 0x02 24552417Sluoqi#define CLRFRERR 0x01 24652417Sluoqi 24752417Sluoqi/* SSTAT4 */ 24852417Sluoqi#define SYNCERR 0x04 24952417Sluoqi#define FWERR 0x02 25052417Sluoqi#define FRERR 0x01 25152417Sluoqi 25252417Sluoqi/* SIMODE0 */ 25352417Sluoqi#define ENSELDO 0x40 25452417Sluoqi#define ENSELDI 0x20 25552417Sluoqi#define ENSELINGO 0x10 25652417Sluoqi#define ENSWRAP 0x08 25752417Sluoqi#define ENSDONE 0x04 25852417Sluoqi#define ENSPIORDY 0x02 25952417Sluoqi#define ENDMADONE 0x01 26052417Sluoqi 26152417Sluoqi/* SIMODE1 */ 26252417Sluoqi#define ENSELTIMO 0x80 26352417Sluoqi#define ENATNTARG 0x40 26452417Sluoqi#define ENSCSIRST 0x20 26552417Sluoqi#define ENPHASEMIS 0x10 26652417Sluoqi#define ENBUSFREE 0x08 26752417Sluoqi#define ENSCSIPERR 0x04 26852417Sluoqi#define ENPHASECHG 0x02 26952417Sluoqi#define ENREQINIT 0x01 27052417Sluoqi 27152417Sluoqi/* DMACNTRL0 */ 27252417Sluoqi#define ENDMA 0x80 27352417Sluoqi#define B8MODE 0x40 27452417Sluoqi#define DMA 0x20 27552417Sluoqi#define DWORDPIO 0x10 27652417Sluoqi#define WRITE 0x08 27752417Sluoqi#define INTEN 0x04 27852417Sluoqi#define RSTFIFO 0x02 27952417Sluoqi#define SWINT 0x01 28052417Sluoqi 28152417Sluoqi/* DMACNTRL1 */ 28252417Sluoqi#define PWRDWN 0x80 28352417Sluoqi#define ENSTK32 0x40 28452417Sluoqi#define STK4 0x10 28552417Sluoqi#define STK3 0x08 28652417Sluoqi#define STK2 0x04 28752417Sluoqi#define STK1 0x02 28852417Sluoqi#define STK0 0x01 28952417Sluoqi 29052417Sluoqi/* DMASTAT */ 29152417Sluoqi#define ATDONE 0x80 29252417Sluoqi#define WORDRDY 0x40 29352417Sluoqi#define INTSTAT 0x20 29452417Sluoqi#define DFIFOFULL 0x10 29552417Sluoqi#define DFIFOEMP 0x08 29652417Sluoqi#define DFIFOHF 0x04 29752417Sluoqi#define DWORDRDY 0x02 29852417Sluoqi 29952417Sluoqi/* BRSTCNTRL */ 30052417Sluoqi#define BON3 0x80 30152417Sluoqi#define BON2 0x40 30252417Sluoqi#define BON1 0x20 30352417Sluoqi#define BON0 0x10 30452417Sluoqi#define BOFF3 0x08 30552417Sluoqi#define BOFF2 0x04 30652417Sluoqi#define BOFF1 0x02 30752417Sluoqi#define BOFF0 0x01 30852417Sluoqi 30952417Sluoqi/* TEST */ 31052417Sluoqi#define BOFFTMR 0x40 31152417Sluoqi#define BONTMR 0x20 31252417Sluoqi#define STCNTH 0x10 31352417Sluoqi#define STCNTM 0x08 31452417Sluoqi#define STCNTL 0x04 31552417Sluoqi#define SCSIBLK 0x02 31652417Sluoqi#define DMABLK 0x01 31752417Sluoqi 31852417Sluoqi/* PORTA */ 31952417Sluoqi#define PORTA_ID(a) ((a) & 7) 32052417Sluoqi#define PORTA_IRQ(a) ((((a) >> 3) & 3) + 9) 32152417Sluoqi#define PORTA_DRQ(a) ((((a) >> 5) & 3) ? (((a) >> 5) & 3) + 4 : 0) 32252417Sluoqi#define PORTA_PARITY(a) ((a) & 0x80) 32352417Sluoqi 32452417Sluoqi/* PORTB */ 32574370Sken#define PORTB_EXTTRAN(b)((b) & 1) 32652417Sluoqi#define PORTB_DISC(b) ((b) & 4) 32752417Sluoqi#define PORTB_SYNC(b) ((b) & 8) 32874370Sken#define PORTB_FSYNC(b) ((b) & 0x10) 32952417Sluoqi#define PORTB_BOOT(b) ((b) & 0x40) 33052417Sluoqi#define PORTB_DMA(b) ((b) & 0x80) 33152417Sluoqi 33252417Sluoqi/* How to behave on the (E)ISA bus when/if DMAing (on<<4) + off in us */ 33352417Sluoqi#define EISA_BRST_TIM ((15<<4) + 1) /* 15us on, 1us off */ 33452417Sluoqi 33552417Sluoqi#define FIFOSIZE 128 336