1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-uahcx-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon uahcx. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_UAHCX_DEFS_H__ 53232812Sjmallett#define __CVMX_UAHCX_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallettstatic inline uint64_t CVMX_UAHCX_EHCI_ASYNCLISTADDR(unsigned long block_id) 57215976Sjmallett{ 58215976Sjmallett if (!( 59232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 60232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 61232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 62232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 63232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 64215976Sjmallett cvmx_warn("CVMX_UAHCX_EHCI_ASYNCLISTADDR(%lu) is invalid on this chip\n", block_id); 65215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000028ull); 66215976Sjmallett} 67215976Sjmallett#else 68215976Sjmallett#define CVMX_UAHCX_EHCI_ASYNCLISTADDR(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000028ull)) 69215976Sjmallett#endif 70215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 71215976Sjmallettstatic inline uint64_t CVMX_UAHCX_EHCI_CONFIGFLAG(unsigned long block_id) 72215976Sjmallett{ 73215976Sjmallett if (!( 74232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 75232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 76232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 77232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 78232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 79215976Sjmallett cvmx_warn("CVMX_UAHCX_EHCI_CONFIGFLAG(%lu) is invalid on this chip\n", block_id); 80215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000050ull); 81215976Sjmallett} 82215976Sjmallett#else 83215976Sjmallett#define CVMX_UAHCX_EHCI_CONFIGFLAG(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000050ull)) 84215976Sjmallett#endif 85215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 86215976Sjmallettstatic inline uint64_t CVMX_UAHCX_EHCI_CTRLDSSEGMENT(unsigned long block_id) 87215976Sjmallett{ 88215976Sjmallett if (!( 89232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 90232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 91232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 92232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 93232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 94215976Sjmallett cvmx_warn("CVMX_UAHCX_EHCI_CTRLDSSEGMENT(%lu) is invalid on this chip\n", block_id); 95215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000020ull); 96215976Sjmallett} 97215976Sjmallett#else 98215976Sjmallett#define CVMX_UAHCX_EHCI_CTRLDSSEGMENT(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000020ull)) 99215976Sjmallett#endif 100215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 101215976Sjmallettstatic inline uint64_t CVMX_UAHCX_EHCI_FRINDEX(unsigned long block_id) 102215976Sjmallett{ 103215976Sjmallett if (!( 104232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 105232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 106232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 107232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 108232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 109215976Sjmallett cvmx_warn("CVMX_UAHCX_EHCI_FRINDEX(%lu) is invalid on this chip\n", block_id); 110215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F000000001Cull); 111215976Sjmallett} 112215976Sjmallett#else 113215976Sjmallett#define CVMX_UAHCX_EHCI_FRINDEX(block_id) (CVMX_ADD_IO_SEG(0x00016F000000001Cull)) 114215976Sjmallett#endif 115215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 116215976Sjmallettstatic inline uint64_t CVMX_UAHCX_EHCI_HCCAPBASE(unsigned long block_id) 117215976Sjmallett{ 118215976Sjmallett if (!( 119232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 120232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 121232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 122232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 123232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 124215976Sjmallett cvmx_warn("CVMX_UAHCX_EHCI_HCCAPBASE(%lu) is invalid on this chip\n", block_id); 125215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000000ull); 126215976Sjmallett} 127215976Sjmallett#else 128215976Sjmallett#define CVMX_UAHCX_EHCI_HCCAPBASE(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000000ull)) 129215976Sjmallett#endif 130215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 131215976Sjmallettstatic inline uint64_t CVMX_UAHCX_EHCI_HCCPARAMS(unsigned long block_id) 132215976Sjmallett{ 133215976Sjmallett if (!( 134232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 135232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 136232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 137232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 138232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 139215976Sjmallett cvmx_warn("CVMX_UAHCX_EHCI_HCCPARAMS(%lu) is invalid on this chip\n", block_id); 140215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000008ull); 141215976Sjmallett} 142215976Sjmallett#else 143215976Sjmallett#define CVMX_UAHCX_EHCI_HCCPARAMS(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000008ull)) 144215976Sjmallett#endif 145215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 146215976Sjmallettstatic inline uint64_t CVMX_UAHCX_EHCI_HCSPARAMS(unsigned long block_id) 147215976Sjmallett{ 148215976Sjmallett if (!( 149232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 150232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 151232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 152232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 153232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 154215976Sjmallett cvmx_warn("CVMX_UAHCX_EHCI_HCSPARAMS(%lu) is invalid on this chip\n", block_id); 155215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000004ull); 156215976Sjmallett} 157215976Sjmallett#else 158215976Sjmallett#define CVMX_UAHCX_EHCI_HCSPARAMS(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000004ull)) 159215976Sjmallett#endif 160215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 161215976Sjmallettstatic inline uint64_t CVMX_UAHCX_EHCI_INSNREG00(unsigned long block_id) 162215976Sjmallett{ 163215976Sjmallett if (!( 164232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 165232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 166232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 167232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 168232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 169215976Sjmallett cvmx_warn("CVMX_UAHCX_EHCI_INSNREG00(%lu) is invalid on this chip\n", block_id); 170215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000090ull); 171215976Sjmallett} 172215976Sjmallett#else 173215976Sjmallett#define CVMX_UAHCX_EHCI_INSNREG00(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000090ull)) 174215976Sjmallett#endif 175215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 176215976Sjmallettstatic inline uint64_t CVMX_UAHCX_EHCI_INSNREG03(unsigned long block_id) 177215976Sjmallett{ 178215976Sjmallett if (!( 179232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 180232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 181232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 182232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 183232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 184215976Sjmallett cvmx_warn("CVMX_UAHCX_EHCI_INSNREG03(%lu) is invalid on this chip\n", block_id); 185215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F000000009Cull); 186215976Sjmallett} 187215976Sjmallett#else 188215976Sjmallett#define CVMX_UAHCX_EHCI_INSNREG03(block_id) (CVMX_ADD_IO_SEG(0x00016F000000009Cull)) 189215976Sjmallett#endif 190215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 191215976Sjmallettstatic inline uint64_t CVMX_UAHCX_EHCI_INSNREG04(unsigned long block_id) 192215976Sjmallett{ 193215976Sjmallett if (!( 194232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 195232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 196232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 197232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 198232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 199215976Sjmallett cvmx_warn("CVMX_UAHCX_EHCI_INSNREG04(%lu) is invalid on this chip\n", block_id); 200215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F00000000A0ull); 201215976Sjmallett} 202215976Sjmallett#else 203215976Sjmallett#define CVMX_UAHCX_EHCI_INSNREG04(block_id) (CVMX_ADD_IO_SEG(0x00016F00000000A0ull)) 204215976Sjmallett#endif 205215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 206215976Sjmallettstatic inline uint64_t CVMX_UAHCX_EHCI_INSNREG06(unsigned long block_id) 207215976Sjmallett{ 208215976Sjmallett if (!( 209232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 210232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 211232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 212232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 213232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 214215976Sjmallett cvmx_warn("CVMX_UAHCX_EHCI_INSNREG06(%lu) is invalid on this chip\n", block_id); 215215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F00000000E8ull); 216215976Sjmallett} 217215976Sjmallett#else 218215976Sjmallett#define CVMX_UAHCX_EHCI_INSNREG06(block_id) (CVMX_ADD_IO_SEG(0x00016F00000000E8ull)) 219215976Sjmallett#endif 220215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 221215976Sjmallettstatic inline uint64_t CVMX_UAHCX_EHCI_INSNREG07(unsigned long block_id) 222215976Sjmallett{ 223215976Sjmallett if (!( 224232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 225232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 226232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 227232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 228232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 229215976Sjmallett cvmx_warn("CVMX_UAHCX_EHCI_INSNREG07(%lu) is invalid on this chip\n", block_id); 230215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F00000000ECull); 231215976Sjmallett} 232215976Sjmallett#else 233215976Sjmallett#define CVMX_UAHCX_EHCI_INSNREG07(block_id) (CVMX_ADD_IO_SEG(0x00016F00000000ECull)) 234215976Sjmallett#endif 235215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 236215976Sjmallettstatic inline uint64_t CVMX_UAHCX_EHCI_PERIODICLISTBASE(unsigned long block_id) 237215976Sjmallett{ 238215976Sjmallett if (!( 239232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 240232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 241232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 242232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 243232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 244215976Sjmallett cvmx_warn("CVMX_UAHCX_EHCI_PERIODICLISTBASE(%lu) is invalid on this chip\n", block_id); 245215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000024ull); 246215976Sjmallett} 247215976Sjmallett#else 248215976Sjmallett#define CVMX_UAHCX_EHCI_PERIODICLISTBASE(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000024ull)) 249215976Sjmallett#endif 250215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 251215976Sjmallettstatic inline uint64_t CVMX_UAHCX_EHCI_PORTSCX(unsigned long offset, unsigned long block_id) 252215976Sjmallett{ 253215976Sjmallett if (!( 254232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0)))) || 255232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0)))) || 256232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0)))) || 257232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0)))) || 258232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0)))))) 259215976Sjmallett cvmx_warn("CVMX_UAHCX_EHCI_PORTSCX(%lu,%lu) is invalid on this chip\n", offset, block_id); 260215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000050ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 4; 261215976Sjmallett} 262215976Sjmallett#else 263215976Sjmallett#define CVMX_UAHCX_EHCI_PORTSCX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0000000050ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 4) 264215976Sjmallett#endif 265215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 266215976Sjmallettstatic inline uint64_t CVMX_UAHCX_EHCI_USBCMD(unsigned long block_id) 267215976Sjmallett{ 268215976Sjmallett if (!( 269232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 270232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 271232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 272232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 273232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 274215976Sjmallett cvmx_warn("CVMX_UAHCX_EHCI_USBCMD(%lu) is invalid on this chip\n", block_id); 275215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000010ull); 276215976Sjmallett} 277215976Sjmallett#else 278215976Sjmallett#define CVMX_UAHCX_EHCI_USBCMD(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000010ull)) 279215976Sjmallett#endif 280215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 281215976Sjmallettstatic inline uint64_t CVMX_UAHCX_EHCI_USBINTR(unsigned long block_id) 282215976Sjmallett{ 283215976Sjmallett if (!( 284232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 285232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 286232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 287232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 288232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 289215976Sjmallett cvmx_warn("CVMX_UAHCX_EHCI_USBINTR(%lu) is invalid on this chip\n", block_id); 290215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000018ull); 291215976Sjmallett} 292215976Sjmallett#else 293215976Sjmallett#define CVMX_UAHCX_EHCI_USBINTR(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000018ull)) 294215976Sjmallett#endif 295215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 296215976Sjmallettstatic inline uint64_t CVMX_UAHCX_EHCI_USBSTS(unsigned long block_id) 297215976Sjmallett{ 298215976Sjmallett if (!( 299232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 300232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 301232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 302232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 303232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 304215976Sjmallett cvmx_warn("CVMX_UAHCX_EHCI_USBSTS(%lu) is invalid on this chip\n", block_id); 305215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000014ull); 306215976Sjmallett} 307215976Sjmallett#else 308215976Sjmallett#define CVMX_UAHCX_EHCI_USBSTS(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000014ull)) 309215976Sjmallett#endif 310215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 311215976Sjmallettstatic inline uint64_t CVMX_UAHCX_OHCI0_HCBULKCURRENTED(unsigned long block_id) 312215976Sjmallett{ 313215976Sjmallett if (!( 314232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 315232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 316232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 317232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 318232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 319215976Sjmallett cvmx_warn("CVMX_UAHCX_OHCI0_HCBULKCURRENTED(%lu) is invalid on this chip\n", block_id); 320215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F000000042Cull); 321215976Sjmallett} 322215976Sjmallett#else 323215976Sjmallett#define CVMX_UAHCX_OHCI0_HCBULKCURRENTED(block_id) (CVMX_ADD_IO_SEG(0x00016F000000042Cull)) 324215976Sjmallett#endif 325215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 326215976Sjmallettstatic inline uint64_t CVMX_UAHCX_OHCI0_HCBULKHEADED(unsigned long block_id) 327215976Sjmallett{ 328215976Sjmallett if (!( 329232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 330232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 331232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 332232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 333232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 334215976Sjmallett cvmx_warn("CVMX_UAHCX_OHCI0_HCBULKHEADED(%lu) is invalid on this chip\n", block_id); 335215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000428ull); 336215976Sjmallett} 337215976Sjmallett#else 338215976Sjmallett#define CVMX_UAHCX_OHCI0_HCBULKHEADED(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000428ull)) 339215976Sjmallett#endif 340215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 341215976Sjmallettstatic inline uint64_t CVMX_UAHCX_OHCI0_HCCOMMANDSTATUS(unsigned long block_id) 342215976Sjmallett{ 343215976Sjmallett if (!( 344232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 345232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 346232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 347232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 348232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 349215976Sjmallett cvmx_warn("CVMX_UAHCX_OHCI0_HCCOMMANDSTATUS(%lu) is invalid on this chip\n", block_id); 350215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000408ull); 351215976Sjmallett} 352215976Sjmallett#else 353215976Sjmallett#define CVMX_UAHCX_OHCI0_HCCOMMANDSTATUS(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000408ull)) 354215976Sjmallett#endif 355215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 356215976Sjmallettstatic inline uint64_t CVMX_UAHCX_OHCI0_HCCONTROL(unsigned long block_id) 357215976Sjmallett{ 358215976Sjmallett if (!( 359232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 360232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 361232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 362232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 363232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 364215976Sjmallett cvmx_warn("CVMX_UAHCX_OHCI0_HCCONTROL(%lu) is invalid on this chip\n", block_id); 365215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000404ull); 366215976Sjmallett} 367215976Sjmallett#else 368215976Sjmallett#define CVMX_UAHCX_OHCI0_HCCONTROL(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000404ull)) 369215976Sjmallett#endif 370215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 371215976Sjmallettstatic inline uint64_t CVMX_UAHCX_OHCI0_HCCONTROLCURRENTED(unsigned long block_id) 372215976Sjmallett{ 373215976Sjmallett if (!( 374232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 375232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 376232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 377232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 378232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 379215976Sjmallett cvmx_warn("CVMX_UAHCX_OHCI0_HCCONTROLCURRENTED(%lu) is invalid on this chip\n", block_id); 380215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000424ull); 381215976Sjmallett} 382215976Sjmallett#else 383215976Sjmallett#define CVMX_UAHCX_OHCI0_HCCONTROLCURRENTED(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000424ull)) 384215976Sjmallett#endif 385215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 386215976Sjmallettstatic inline uint64_t CVMX_UAHCX_OHCI0_HCCONTROLHEADED(unsigned long block_id) 387215976Sjmallett{ 388215976Sjmallett if (!( 389232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 390232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 391232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 392232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 393232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 394215976Sjmallett cvmx_warn("CVMX_UAHCX_OHCI0_HCCONTROLHEADED(%lu) is invalid on this chip\n", block_id); 395215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000420ull); 396215976Sjmallett} 397215976Sjmallett#else 398215976Sjmallett#define CVMX_UAHCX_OHCI0_HCCONTROLHEADED(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000420ull)) 399215976Sjmallett#endif 400215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 401215976Sjmallettstatic inline uint64_t CVMX_UAHCX_OHCI0_HCDONEHEAD(unsigned long block_id) 402215976Sjmallett{ 403215976Sjmallett if (!( 404232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 405232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 406232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 407232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 408232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 409215976Sjmallett cvmx_warn("CVMX_UAHCX_OHCI0_HCDONEHEAD(%lu) is invalid on this chip\n", block_id); 410215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000430ull); 411215976Sjmallett} 412215976Sjmallett#else 413215976Sjmallett#define CVMX_UAHCX_OHCI0_HCDONEHEAD(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000430ull)) 414215976Sjmallett#endif 415215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 416215976Sjmallettstatic inline uint64_t CVMX_UAHCX_OHCI0_HCFMINTERVAL(unsigned long block_id) 417215976Sjmallett{ 418215976Sjmallett if (!( 419232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 420232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 421232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 422232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 423232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 424215976Sjmallett cvmx_warn("CVMX_UAHCX_OHCI0_HCFMINTERVAL(%lu) is invalid on this chip\n", block_id); 425215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000434ull); 426215976Sjmallett} 427215976Sjmallett#else 428215976Sjmallett#define CVMX_UAHCX_OHCI0_HCFMINTERVAL(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000434ull)) 429215976Sjmallett#endif 430215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 431215976Sjmallettstatic inline uint64_t CVMX_UAHCX_OHCI0_HCFMNUMBER(unsigned long block_id) 432215976Sjmallett{ 433215976Sjmallett if (!( 434232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 435232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 436232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 437232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 438232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 439215976Sjmallett cvmx_warn("CVMX_UAHCX_OHCI0_HCFMNUMBER(%lu) is invalid on this chip\n", block_id); 440215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F000000043Cull); 441215976Sjmallett} 442215976Sjmallett#else 443215976Sjmallett#define CVMX_UAHCX_OHCI0_HCFMNUMBER(block_id) (CVMX_ADD_IO_SEG(0x00016F000000043Cull)) 444215976Sjmallett#endif 445215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 446215976Sjmallettstatic inline uint64_t CVMX_UAHCX_OHCI0_HCFMREMAINING(unsigned long block_id) 447215976Sjmallett{ 448215976Sjmallett if (!( 449232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 450232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 451232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 452232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 453232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 454215976Sjmallett cvmx_warn("CVMX_UAHCX_OHCI0_HCFMREMAINING(%lu) is invalid on this chip\n", block_id); 455215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000438ull); 456215976Sjmallett} 457215976Sjmallett#else 458215976Sjmallett#define CVMX_UAHCX_OHCI0_HCFMREMAINING(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000438ull)) 459215976Sjmallett#endif 460215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 461215976Sjmallettstatic inline uint64_t CVMX_UAHCX_OHCI0_HCHCCA(unsigned long block_id) 462215976Sjmallett{ 463215976Sjmallett if (!( 464232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 465232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 466232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 467232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 468232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 469215976Sjmallett cvmx_warn("CVMX_UAHCX_OHCI0_HCHCCA(%lu) is invalid on this chip\n", block_id); 470215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000418ull); 471215976Sjmallett} 472215976Sjmallett#else 473215976Sjmallett#define CVMX_UAHCX_OHCI0_HCHCCA(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000418ull)) 474215976Sjmallett#endif 475215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 476215976Sjmallettstatic inline uint64_t CVMX_UAHCX_OHCI0_HCINTERRUPTDISABLE(unsigned long block_id) 477215976Sjmallett{ 478215976Sjmallett if (!( 479232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 480232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 481232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 482232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 483232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 484215976Sjmallett cvmx_warn("CVMX_UAHCX_OHCI0_HCINTERRUPTDISABLE(%lu) is invalid on this chip\n", block_id); 485215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000414ull); 486215976Sjmallett} 487215976Sjmallett#else 488215976Sjmallett#define CVMX_UAHCX_OHCI0_HCINTERRUPTDISABLE(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000414ull)) 489215976Sjmallett#endif 490215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 491215976Sjmallettstatic inline uint64_t CVMX_UAHCX_OHCI0_HCINTERRUPTENABLE(unsigned long block_id) 492215976Sjmallett{ 493215976Sjmallett if (!( 494232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 495232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 496232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 497232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 498232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 499215976Sjmallett cvmx_warn("CVMX_UAHCX_OHCI0_HCINTERRUPTENABLE(%lu) is invalid on this chip\n", block_id); 500215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000410ull); 501215976Sjmallett} 502215976Sjmallett#else 503215976Sjmallett#define CVMX_UAHCX_OHCI0_HCINTERRUPTENABLE(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000410ull)) 504215976Sjmallett#endif 505215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 506215976Sjmallettstatic inline uint64_t CVMX_UAHCX_OHCI0_HCINTERRUPTSTATUS(unsigned long block_id) 507215976Sjmallett{ 508215976Sjmallett if (!( 509232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 510232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 511232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 512232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 513232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 514215976Sjmallett cvmx_warn("CVMX_UAHCX_OHCI0_HCINTERRUPTSTATUS(%lu) is invalid on this chip\n", block_id); 515215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F000000040Cull); 516215976Sjmallett} 517215976Sjmallett#else 518215976Sjmallett#define CVMX_UAHCX_OHCI0_HCINTERRUPTSTATUS(block_id) (CVMX_ADD_IO_SEG(0x00016F000000040Cull)) 519215976Sjmallett#endif 520215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 521215976Sjmallettstatic inline uint64_t CVMX_UAHCX_OHCI0_HCLSTHRESHOLD(unsigned long block_id) 522215976Sjmallett{ 523215976Sjmallett if (!( 524232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 525232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 526232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 527232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 528232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 529215976Sjmallett cvmx_warn("CVMX_UAHCX_OHCI0_HCLSTHRESHOLD(%lu) is invalid on this chip\n", block_id); 530215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000444ull); 531215976Sjmallett} 532215976Sjmallett#else 533215976Sjmallett#define CVMX_UAHCX_OHCI0_HCLSTHRESHOLD(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000444ull)) 534215976Sjmallett#endif 535215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 536215976Sjmallettstatic inline uint64_t CVMX_UAHCX_OHCI0_HCPERIODCURRENTED(unsigned long block_id) 537215976Sjmallett{ 538215976Sjmallett if (!( 539232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 540232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 541232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 542232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 543232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 544215976Sjmallett cvmx_warn("CVMX_UAHCX_OHCI0_HCPERIODCURRENTED(%lu) is invalid on this chip\n", block_id); 545215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F000000041Cull); 546215976Sjmallett} 547215976Sjmallett#else 548215976Sjmallett#define CVMX_UAHCX_OHCI0_HCPERIODCURRENTED(block_id) (CVMX_ADD_IO_SEG(0x00016F000000041Cull)) 549215976Sjmallett#endif 550215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 551215976Sjmallettstatic inline uint64_t CVMX_UAHCX_OHCI0_HCPERIODICSTART(unsigned long block_id) 552215976Sjmallett{ 553215976Sjmallett if (!( 554232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 555232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 556232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 557232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 558232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 559215976Sjmallett cvmx_warn("CVMX_UAHCX_OHCI0_HCPERIODICSTART(%lu) is invalid on this chip\n", block_id); 560215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000440ull); 561215976Sjmallett} 562215976Sjmallett#else 563215976Sjmallett#define CVMX_UAHCX_OHCI0_HCPERIODICSTART(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000440ull)) 564215976Sjmallett#endif 565215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 566215976Sjmallettstatic inline uint64_t CVMX_UAHCX_OHCI0_HCREVISION(unsigned long block_id) 567215976Sjmallett{ 568215976Sjmallett if (!( 569232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 570232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 571232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 572232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 573232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 574215976Sjmallett cvmx_warn("CVMX_UAHCX_OHCI0_HCREVISION(%lu) is invalid on this chip\n", block_id); 575215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000400ull); 576215976Sjmallett} 577215976Sjmallett#else 578215976Sjmallett#define CVMX_UAHCX_OHCI0_HCREVISION(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000400ull)) 579215976Sjmallett#endif 580215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 581215976Sjmallettstatic inline uint64_t CVMX_UAHCX_OHCI0_HCRHDESCRIPTORA(unsigned long block_id) 582215976Sjmallett{ 583215976Sjmallett if (!( 584232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 585232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 586232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 587232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 588232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 589215976Sjmallett cvmx_warn("CVMX_UAHCX_OHCI0_HCRHDESCRIPTORA(%lu) is invalid on this chip\n", block_id); 590215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000448ull); 591215976Sjmallett} 592215976Sjmallett#else 593215976Sjmallett#define CVMX_UAHCX_OHCI0_HCRHDESCRIPTORA(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000448ull)) 594215976Sjmallett#endif 595215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 596215976Sjmallettstatic inline uint64_t CVMX_UAHCX_OHCI0_HCRHDESCRIPTORB(unsigned long block_id) 597215976Sjmallett{ 598215976Sjmallett if (!( 599232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 600232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 601232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 602232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 603232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 604215976Sjmallett cvmx_warn("CVMX_UAHCX_OHCI0_HCRHDESCRIPTORB(%lu) is invalid on this chip\n", block_id); 605215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F000000044Cull); 606215976Sjmallett} 607215976Sjmallett#else 608215976Sjmallett#define CVMX_UAHCX_OHCI0_HCRHDESCRIPTORB(block_id) (CVMX_ADD_IO_SEG(0x00016F000000044Cull)) 609215976Sjmallett#endif 610215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 611215976Sjmallettstatic inline uint64_t CVMX_UAHCX_OHCI0_HCRHPORTSTATUSX(unsigned long offset, unsigned long block_id) 612215976Sjmallett{ 613215976Sjmallett if (!( 614232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0)))) || 615232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0)))) || 616232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0)))) || 617232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0)))) || 618232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((((offset >= 1) && (offset <= 2))) && ((block_id == 0)))))) 619215976Sjmallett cvmx_warn("CVMX_UAHCX_OHCI0_HCRHPORTSTATUSX(%lu,%lu) is invalid on this chip\n", offset, block_id); 620215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000450ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 4; 621215976Sjmallett} 622215976Sjmallett#else 623215976Sjmallett#define CVMX_UAHCX_OHCI0_HCRHPORTSTATUSX(offset, block_id) (CVMX_ADD_IO_SEG(0x00016F0000000450ull) + (((offset) & 3) + ((block_id) & 0) * 0x0ull) * 4) 624215976Sjmallett#endif 625215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 626215976Sjmallettstatic inline uint64_t CVMX_UAHCX_OHCI0_HCRHSTATUS(unsigned long block_id) 627215976Sjmallett{ 628215976Sjmallett if (!( 629232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 630232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 631232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 632232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 633232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 634215976Sjmallett cvmx_warn("CVMX_UAHCX_OHCI0_HCRHSTATUS(%lu) is invalid on this chip\n", block_id); 635215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000450ull); 636215976Sjmallett} 637215976Sjmallett#else 638215976Sjmallett#define CVMX_UAHCX_OHCI0_HCRHSTATUS(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000450ull)) 639215976Sjmallett#endif 640215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 641215976Sjmallettstatic inline uint64_t CVMX_UAHCX_OHCI0_INSNREG06(unsigned long block_id) 642215976Sjmallett{ 643215976Sjmallett if (!( 644232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 645232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 646232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 647232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 648232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 649215976Sjmallett cvmx_warn("CVMX_UAHCX_OHCI0_INSNREG06(%lu) is invalid on this chip\n", block_id); 650215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F0000000498ull); 651215976Sjmallett} 652215976Sjmallett#else 653215976Sjmallett#define CVMX_UAHCX_OHCI0_INSNREG06(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000498ull)) 654215976Sjmallett#endif 655215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 656215976Sjmallettstatic inline uint64_t CVMX_UAHCX_OHCI0_INSNREG07(unsigned long block_id) 657215976Sjmallett{ 658215976Sjmallett if (!( 659232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id == 0))) || 660232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id == 0))) || 661232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id == 0))) || 662232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id == 0))) || 663232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id == 0))))) 664215976Sjmallett cvmx_warn("CVMX_UAHCX_OHCI0_INSNREG07(%lu) is invalid on this chip\n", block_id); 665215976Sjmallett return CVMX_ADD_IO_SEG(0x00016F000000049Cull); 666215976Sjmallett} 667215976Sjmallett#else 668215976Sjmallett#define CVMX_UAHCX_OHCI0_INSNREG07(block_id) (CVMX_ADD_IO_SEG(0x00016F000000049Cull)) 669215976Sjmallett#endif 670215976Sjmallett 671215976Sjmallett/** 672215976Sjmallett * cvmx_uahc#_ehci_asynclistaddr 673215976Sjmallett * 674215976Sjmallett * ASYNCLISTADDR = Current Asynchronous List Address Register 675215976Sjmallett * 676215976Sjmallett * This 32-bit register contains the address of the next asynchronous queue head to be executed. If the host 677215976Sjmallett * controller is in 64-bit mode (as indicated by a one in 64-bit Addressing Capability field in the 678215976Sjmallett * HCCPARAMS register), then the most significant 32 bits of every control data structure address comes from 679215976Sjmallett * the CTRLDSSEGMENT register (See Section 2.3.5). Bits [4:0] of this register cannot be modified by system 680215976Sjmallett * software and will always return a zero when read. The memory structure referenced by this physical memory 681215976Sjmallett * pointer is assumed to be 32-byte (cache line) aligned. 682215976Sjmallett */ 683232812Sjmallettunion cvmx_uahcx_ehci_asynclistaddr { 684215976Sjmallett uint32_t u32; 685232812Sjmallett struct cvmx_uahcx_ehci_asynclistaddr_s { 686232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 687215976Sjmallett uint32_t lpl : 27; /**< Link Pointer Low (LPL). These bits correspond to memory address signals [31:5], 688215976Sjmallett respectively. This field may only reference a Queue Head (QH). */ 689215976Sjmallett uint32_t reserved_0_4 : 5; 690215976Sjmallett#else 691215976Sjmallett uint32_t reserved_0_4 : 5; 692215976Sjmallett uint32_t lpl : 27; 693215976Sjmallett#endif 694215976Sjmallett } s; 695232812Sjmallett struct cvmx_uahcx_ehci_asynclistaddr_s cn61xx; 696215976Sjmallett struct cvmx_uahcx_ehci_asynclistaddr_s cn63xx; 697215976Sjmallett struct cvmx_uahcx_ehci_asynclistaddr_s cn63xxp1; 698232812Sjmallett struct cvmx_uahcx_ehci_asynclistaddr_s cn66xx; 699232812Sjmallett struct cvmx_uahcx_ehci_asynclistaddr_s cn68xx; 700232812Sjmallett struct cvmx_uahcx_ehci_asynclistaddr_s cn68xxp1; 701232812Sjmallett struct cvmx_uahcx_ehci_asynclistaddr_s cnf71xx; 702215976Sjmallett}; 703215976Sjmalletttypedef union cvmx_uahcx_ehci_asynclistaddr cvmx_uahcx_ehci_asynclistaddr_t; 704215976Sjmallett 705215976Sjmallett/** 706215976Sjmallett * cvmx_uahc#_ehci_configflag 707215976Sjmallett * 708215976Sjmallett * CONFIGFLAG = Configure Flag Register 709215976Sjmallett * This register is in the auxiliary power well. It is only reset by hardware when the auxiliary power is initially 710215976Sjmallett * applied or in response to a host controller reset. 711215976Sjmallett */ 712232812Sjmallettunion cvmx_uahcx_ehci_configflag { 713215976Sjmallett uint32_t u32; 714232812Sjmallett struct cvmx_uahcx_ehci_configflag_s { 715232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 716215976Sjmallett uint32_t reserved_1_31 : 31; 717215976Sjmallett uint32_t cf : 1; /**< Configure Flag (CF) .Host software sets this bit as the last action in 718215976Sjmallett its process of configuring the Host Controller (see Section 4.1). This bit controls the 719215976Sjmallett default port-routing control logic. Bit values and side-effects are listed below. 720215976Sjmallett 0b: Port routing control logic default-routes each port to an implementation 721215976Sjmallett dependent classic host controller. 722215976Sjmallett 1b: Port routing control logic default-routes all ports to this host controller. */ 723215976Sjmallett#else 724215976Sjmallett uint32_t cf : 1; 725215976Sjmallett uint32_t reserved_1_31 : 31; 726215976Sjmallett#endif 727215976Sjmallett } s; 728232812Sjmallett struct cvmx_uahcx_ehci_configflag_s cn61xx; 729215976Sjmallett struct cvmx_uahcx_ehci_configflag_s cn63xx; 730215976Sjmallett struct cvmx_uahcx_ehci_configflag_s cn63xxp1; 731232812Sjmallett struct cvmx_uahcx_ehci_configflag_s cn66xx; 732232812Sjmallett struct cvmx_uahcx_ehci_configflag_s cn68xx; 733232812Sjmallett struct cvmx_uahcx_ehci_configflag_s cn68xxp1; 734232812Sjmallett struct cvmx_uahcx_ehci_configflag_s cnf71xx; 735215976Sjmallett}; 736215976Sjmalletttypedef union cvmx_uahcx_ehci_configflag cvmx_uahcx_ehci_configflag_t; 737215976Sjmallett 738215976Sjmallett/** 739215976Sjmallett * cvmx_uahc#_ehci_ctrldssegment 740215976Sjmallett * 741215976Sjmallett * CTRLDSSEGMENT = Control Data Structure Segment Register 742215976Sjmallett * 743215976Sjmallett * This 32-bit register corresponds to the most significant address bits [63:32] for all EHCI data structures. If 744215976Sjmallett * the 64-bit Addressing Capability field in HCCPARAMS is a zero, then this register is not used. Software 745215976Sjmallett * cannot write to it and a read from this register will return zeros. 746215976Sjmallett * 747215976Sjmallett * If the 64-bit Addressing Capability field in HCCPARAMS is a one, then this register is used with the link 748215976Sjmallett * pointers to construct 64-bit addresses to EHCI control data structures. This register is concatenated with the 749215976Sjmallett * link pointer from either the PERIODICLISTBASE, ASYNCLISTADDR, or any control data structure link 750215976Sjmallett * field to construct a 64-bit address. 751215976Sjmallett * 752215976Sjmallett * This register allows the host software to locate all control data structures within the same 4 Gigabyte 753215976Sjmallett * memory segment. 754215976Sjmallett */ 755232812Sjmallettunion cvmx_uahcx_ehci_ctrldssegment { 756215976Sjmallett uint32_t u32; 757232812Sjmallett struct cvmx_uahcx_ehci_ctrldssegment_s { 758232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 759215976Sjmallett uint32_t ctrldsseg : 32; /**< Control Data Strucute Semgent Address Bit [63:32] */ 760215976Sjmallett#else 761215976Sjmallett uint32_t ctrldsseg : 32; 762215976Sjmallett#endif 763215976Sjmallett } s; 764232812Sjmallett struct cvmx_uahcx_ehci_ctrldssegment_s cn61xx; 765215976Sjmallett struct cvmx_uahcx_ehci_ctrldssegment_s cn63xx; 766215976Sjmallett struct cvmx_uahcx_ehci_ctrldssegment_s cn63xxp1; 767232812Sjmallett struct cvmx_uahcx_ehci_ctrldssegment_s cn66xx; 768232812Sjmallett struct cvmx_uahcx_ehci_ctrldssegment_s cn68xx; 769232812Sjmallett struct cvmx_uahcx_ehci_ctrldssegment_s cn68xxp1; 770232812Sjmallett struct cvmx_uahcx_ehci_ctrldssegment_s cnf71xx; 771215976Sjmallett}; 772215976Sjmalletttypedef union cvmx_uahcx_ehci_ctrldssegment cvmx_uahcx_ehci_ctrldssegment_t; 773215976Sjmallett 774215976Sjmallett/** 775215976Sjmallett * cvmx_uahc#_ehci_frindex 776215976Sjmallett * 777215976Sjmallett * FRINDEX = Frame Index Register 778215976Sjmallett * This register is used by the host controller to index into the periodic frame list. The register updates every 779215976Sjmallett * 125 microseconds (once each micro-frame). Bits [N:3] are used to select a particular entry in the Periodic 780215976Sjmallett * Frame List during periodic schedule execution. The number of bits used for the index depends on the size of 781215976Sjmallett * the frame list as set by system software in the Frame List Size field in the USBCMD register. 782215976Sjmallett * This register cannot be written unless the Host Controller is in the Halted state as indicated by the 783215976Sjmallett * HCHalted bit. A write to this register while the Run/Stop bit is set to a one (USBCMD register) produces 784215976Sjmallett * undefined results. Writes to this register also affect the SOF value. 785215976Sjmallett */ 786232812Sjmallettunion cvmx_uahcx_ehci_frindex { 787215976Sjmallett uint32_t u32; 788232812Sjmallett struct cvmx_uahcx_ehci_frindex_s { 789232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 790215976Sjmallett uint32_t reserved_14_31 : 18; 791215976Sjmallett uint32_t fi : 14; /**< Frame Index. The value in this register increments at the end of each time frame (e.g. 792215976Sjmallett micro-frame). Bits [N:3] are used for the Frame List current index. This means that each 793215976Sjmallett location of the frame list is accessed 8 times (frames or micro-frames) before moving to 794215976Sjmallett the next index. The following illustrates values of N based on the value of the Frame List 795215976Sjmallett Size field in the USBCMD register. 796215976Sjmallett USBCMD[Frame List Size] Number Elements N 797215976Sjmallett 00b (1024) 12 798215976Sjmallett 01b (512) 11 799215976Sjmallett 10b (256) 10 800215976Sjmallett 11b Reserved */ 801215976Sjmallett#else 802215976Sjmallett uint32_t fi : 14; 803215976Sjmallett uint32_t reserved_14_31 : 18; 804215976Sjmallett#endif 805215976Sjmallett } s; 806232812Sjmallett struct cvmx_uahcx_ehci_frindex_s cn61xx; 807215976Sjmallett struct cvmx_uahcx_ehci_frindex_s cn63xx; 808215976Sjmallett struct cvmx_uahcx_ehci_frindex_s cn63xxp1; 809232812Sjmallett struct cvmx_uahcx_ehci_frindex_s cn66xx; 810232812Sjmallett struct cvmx_uahcx_ehci_frindex_s cn68xx; 811232812Sjmallett struct cvmx_uahcx_ehci_frindex_s cn68xxp1; 812232812Sjmallett struct cvmx_uahcx_ehci_frindex_s cnf71xx; 813215976Sjmallett}; 814215976Sjmalletttypedef union cvmx_uahcx_ehci_frindex cvmx_uahcx_ehci_frindex_t; 815215976Sjmallett 816215976Sjmallett/** 817215976Sjmallett * cvmx_uahc#_ehci_hccapbase 818215976Sjmallett * 819215976Sjmallett * HCCAPBASE = Host Controller BASE Capability Register 820215976Sjmallett * 821215976Sjmallett */ 822232812Sjmallettunion cvmx_uahcx_ehci_hccapbase { 823215976Sjmallett uint32_t u32; 824232812Sjmallett struct cvmx_uahcx_ehci_hccapbase_s { 825232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 826215976Sjmallett uint32_t hciversion : 16; /**< Host Controller Interface Version Number */ 827215976Sjmallett uint32_t reserved_8_15 : 8; 828215976Sjmallett uint32_t caplength : 8; /**< Capabitlity Registers Length */ 829215976Sjmallett#else 830215976Sjmallett uint32_t caplength : 8; 831215976Sjmallett uint32_t reserved_8_15 : 8; 832215976Sjmallett uint32_t hciversion : 16; 833215976Sjmallett#endif 834215976Sjmallett } s; 835232812Sjmallett struct cvmx_uahcx_ehci_hccapbase_s cn61xx; 836215976Sjmallett struct cvmx_uahcx_ehci_hccapbase_s cn63xx; 837215976Sjmallett struct cvmx_uahcx_ehci_hccapbase_s cn63xxp1; 838232812Sjmallett struct cvmx_uahcx_ehci_hccapbase_s cn66xx; 839232812Sjmallett struct cvmx_uahcx_ehci_hccapbase_s cn68xx; 840232812Sjmallett struct cvmx_uahcx_ehci_hccapbase_s cn68xxp1; 841232812Sjmallett struct cvmx_uahcx_ehci_hccapbase_s cnf71xx; 842215976Sjmallett}; 843215976Sjmalletttypedef union cvmx_uahcx_ehci_hccapbase cvmx_uahcx_ehci_hccapbase_t; 844215976Sjmallett 845215976Sjmallett/** 846215976Sjmallett * cvmx_uahc#_ehci_hccparams 847215976Sjmallett * 848215976Sjmallett * HCCPARAMS = Host Controller Capability Parameters 849215976Sjmallett * Multiple Mode control (time-base bit functionality), addressing capability 850215976Sjmallett */ 851232812Sjmallettunion cvmx_uahcx_ehci_hccparams { 852215976Sjmallett uint32_t u32; 853232812Sjmallett struct cvmx_uahcx_ehci_hccparams_s { 854232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 855215976Sjmallett uint32_t reserved_16_31 : 16; 856215976Sjmallett uint32_t eecp : 8; /**< EHCI Extended Capabilities Pointer. Default = Implementation Dependent. 857215976Sjmallett This optional field indicates the existence of a capabilities list. A value of 00h indicates 858215976Sjmallett no extended capabilities are implemented. A non-zero value in this register indicates the 859215976Sjmallett offset in PCI configuration space of the first EHCI extended capability. The pointer value 860215976Sjmallett must be 40h or greater if implemented to maintain the consistency of the PCI header 861215976Sjmallett defined for this class of device. */ 862215976Sjmallett uint32_t ist : 4; /**< Isochronous Scheduling Threshold. Default = implementation dependent. This field 863215976Sjmallett indicates, relative to the current position of the executing host controller, where software 864215976Sjmallett can reliably update the isochronous schedule. When bit [7] is zero, the value of the least 865215976Sjmallett significant 3 bits indicates the number of micro-frames a host controller can hold a set of 866215976Sjmallett isochronous data structures (one or more) before flushing the state. When bit [7] is a 867215976Sjmallett one, then host software assumes the host controller may cache an isochronous data 868215976Sjmallett structure for an entire frame. Refer to Section 4.7.2.1 for details on how software uses 869215976Sjmallett this information for scheduling isochronous transfers. */ 870215976Sjmallett uint32_t reserved_3_3 : 1; 871215976Sjmallett uint32_t aspc : 1; /**< Asynchronous Schedule Park Capability. Default = Implementation dependent. If this 872215976Sjmallett bit is set to a one, then the host controller supports the park feature for high-speed 873215976Sjmallett queue heads in the Asynchronous Schedule. The feature can be disabled or enabled 874215976Sjmallett and set to a specific level by using the Asynchronous Schedule Park Mode Enable and 875215976Sjmallett Asynchronous Schedule Park Mode Count fields in the USBCMD register. */ 876215976Sjmallett uint32_t pflf : 1; /**< Programmable Frame List Flag. Default = Implementation dependent. If this bit is set 877215976Sjmallett to a zero, then system software must use a frame list length of 1024 elements with this 878215976Sjmallett host controller. The USBCMD register Frame List Size field is a read-only register and 879215976Sjmallett should be set to zero. 880215976Sjmallett If set to a one, then system software can specify and use a smaller frame list and 881215976Sjmallett configure the host controller via the USBCMD register Frame List Size field. The frame 882215976Sjmallett list must always be aligned on a 4K page boundary. This requirement ensures that the 883215976Sjmallett frame list is always physically contiguous. */ 884215976Sjmallett uint32_t ac64 : 1; /**< 64-bit Addressing Capability1 . This field documents the addressing range capability of 885215976Sjmallett this implementation. The value of this field determines whether software should use the 886215976Sjmallett data structures defined in Section 3 (32-bit) or those defined in Appendix B (64-bit). 887215976Sjmallett Values for this field have the following interpretation: 888215976Sjmallett - 0: data structures using 32-bit address memory pointers 889215976Sjmallett - 1: data structures using 64-bit address memory pointers */ 890215976Sjmallett#else 891215976Sjmallett uint32_t ac64 : 1; 892215976Sjmallett uint32_t pflf : 1; 893215976Sjmallett uint32_t aspc : 1; 894215976Sjmallett uint32_t reserved_3_3 : 1; 895215976Sjmallett uint32_t ist : 4; 896215976Sjmallett uint32_t eecp : 8; 897215976Sjmallett uint32_t reserved_16_31 : 16; 898215976Sjmallett#endif 899215976Sjmallett } s; 900232812Sjmallett struct cvmx_uahcx_ehci_hccparams_s cn61xx; 901215976Sjmallett struct cvmx_uahcx_ehci_hccparams_s cn63xx; 902215976Sjmallett struct cvmx_uahcx_ehci_hccparams_s cn63xxp1; 903232812Sjmallett struct cvmx_uahcx_ehci_hccparams_s cn66xx; 904232812Sjmallett struct cvmx_uahcx_ehci_hccparams_s cn68xx; 905232812Sjmallett struct cvmx_uahcx_ehci_hccparams_s cn68xxp1; 906232812Sjmallett struct cvmx_uahcx_ehci_hccparams_s cnf71xx; 907215976Sjmallett}; 908215976Sjmalletttypedef union cvmx_uahcx_ehci_hccparams cvmx_uahcx_ehci_hccparams_t; 909215976Sjmallett 910215976Sjmallett/** 911215976Sjmallett * cvmx_uahc#_ehci_hcsparams 912215976Sjmallett * 913215976Sjmallett * HCSPARAMS = Host Controller Structural Parameters 914215976Sjmallett * This is a set of fields that are structural parameters: Number of downstream ports, etc. 915215976Sjmallett */ 916232812Sjmallettunion cvmx_uahcx_ehci_hcsparams { 917215976Sjmallett uint32_t u32; 918232812Sjmallett struct cvmx_uahcx_ehci_hcsparams_s { 919232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 920215976Sjmallett uint32_t reserved_24_31 : 8; 921215976Sjmallett uint32_t dpn : 4; /**< Debug Port Number. Optional. This register identifies which of the host controller ports 922215976Sjmallett is the debug port. The value is the port number (one-based) of the debug port. A nonzero 923215976Sjmallett value in this field indicates the presence of a debug port. The value in this register 924215976Sjmallett must not be greater than N_PORTS (see below). */ 925215976Sjmallett uint32_t reserved_17_19 : 3; 926215976Sjmallett uint32_t p_indicator : 1; /**< Port Indicator. This bit indicates whether the ports support port 927215976Sjmallett indicator control. When this bit is a one, the port status and control 928215976Sjmallett registers include a read/writeable field for controlling the state of 929215976Sjmallett the port indicator. */ 930215976Sjmallett uint32_t n_cc : 4; /**< Number of Companion Controller. This field indicates the number of 931215976Sjmallett companion controllers associated with this USB 2.0 host controller. 932215976Sjmallett A zero in this field indicates there are no companion host controllers. 933215976Sjmallett Port-ownership hand-off is not supported. Only high-speed devices are 934215976Sjmallett supported on the host controller root ports. 935215976Sjmallett A value larger than zero in this field indicates there are companion USB 1.1 host 936215976Sjmallett controller(s). Port-ownership hand-offs are supported. High, Full-and Low-speed 937215976Sjmallett devices are supported on the host controller root ports. */ 938215976Sjmallett uint32_t n_pcc : 4; /**< Number of Ports per Companion Controller (N_PCC). This field indicates 939215976Sjmallett the number of ports supported per companion host controller. It is used to 940215976Sjmallett indicate the port routing configuration to system software. */ 941215976Sjmallett uint32_t prr : 1; /**< Port Routing Rules. This field indicates the method used by this implementation for 942215976Sjmallett how all ports are mapped to companion controllers. The value of this field has 943215976Sjmallett the following interpretation: 944215976Sjmallett 0 The first N_PCC ports are routed to the lowest numbered function 945215976Sjmallett companion host controller, the next N_PCC port are routed to the next 946215976Sjmallett lowest function companion controller, and so on. 947215976Sjmallett 1 The port routing is explicitly enumerated by the first N_PORTS elements 948215976Sjmallett of the HCSP-PORTROUTE array. */ 949215976Sjmallett uint32_t reserved_5_6 : 2; 950215976Sjmallett uint32_t ppc : 1; /**< Port Power Control. This field indicates whether the host controller 951215976Sjmallett implementation includes port power control. A one in this bit indicates the ports have 952215976Sjmallett port power switches. A zero in this bit indicates the port do not have port power 953215976Sjmallett switches. The value of this field affects the functionality of the Port Power field 954215976Sjmallett in each port status and control register (see Section 2.3.8). */ 955215976Sjmallett uint32_t n_ports : 4; /**< This field specifies the number of physical downstream ports implemented 956215976Sjmallett on this host controller. The value of this field determines how many port registers are 957215976Sjmallett addressable in the Operational Register Space (see Table 2-8). Valid values are in the 958215976Sjmallett range of 1H to FH. A zero in this field is undefined. */ 959215976Sjmallett#else 960215976Sjmallett uint32_t n_ports : 4; 961215976Sjmallett uint32_t ppc : 1; 962215976Sjmallett uint32_t reserved_5_6 : 2; 963215976Sjmallett uint32_t prr : 1; 964215976Sjmallett uint32_t n_pcc : 4; 965215976Sjmallett uint32_t n_cc : 4; 966215976Sjmallett uint32_t p_indicator : 1; 967215976Sjmallett uint32_t reserved_17_19 : 3; 968215976Sjmallett uint32_t dpn : 4; 969215976Sjmallett uint32_t reserved_24_31 : 8; 970215976Sjmallett#endif 971215976Sjmallett } s; 972232812Sjmallett struct cvmx_uahcx_ehci_hcsparams_s cn61xx; 973215976Sjmallett struct cvmx_uahcx_ehci_hcsparams_s cn63xx; 974215976Sjmallett struct cvmx_uahcx_ehci_hcsparams_s cn63xxp1; 975232812Sjmallett struct cvmx_uahcx_ehci_hcsparams_s cn66xx; 976232812Sjmallett struct cvmx_uahcx_ehci_hcsparams_s cn68xx; 977232812Sjmallett struct cvmx_uahcx_ehci_hcsparams_s cn68xxp1; 978232812Sjmallett struct cvmx_uahcx_ehci_hcsparams_s cnf71xx; 979215976Sjmallett}; 980215976Sjmalletttypedef union cvmx_uahcx_ehci_hcsparams cvmx_uahcx_ehci_hcsparams_t; 981215976Sjmallett 982215976Sjmallett/** 983215976Sjmallett * cvmx_uahc#_ehci_insnreg00 984215976Sjmallett * 985215976Sjmallett * EHCI_INSNREG00 = EHCI Programmable Microframe Base Value Register (Synopsys Speicific) 986215976Sjmallett * This register allows you to change the microframe length value (default is microframe SOF = 125 s) to reduce the simulation time. 987215976Sjmallett */ 988232812Sjmallettunion cvmx_uahcx_ehci_insnreg00 { 989215976Sjmallett uint32_t u32; 990232812Sjmallett struct cvmx_uahcx_ehci_insnreg00_s { 991232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 992215976Sjmallett uint32_t reserved_14_31 : 18; 993215976Sjmallett uint32_t mfmc : 13; /**< For byte interface (8-bits), <13:1> is used as the 1-microframe counter. 994215976Sjmallett For word interface (16_bits> <12:1> is used as the 1-microframe counter with word 995215976Sjmallett interface (16-bits). */ 996215976Sjmallett uint32_t en : 1; /**< Writing 1b1 enables this register. 997215976Sjmallett Note: Do not enable this register for the gate-level netlist */ 998215976Sjmallett#else 999215976Sjmallett uint32_t en : 1; 1000215976Sjmallett uint32_t mfmc : 13; 1001215976Sjmallett uint32_t reserved_14_31 : 18; 1002215976Sjmallett#endif 1003215976Sjmallett } s; 1004232812Sjmallett struct cvmx_uahcx_ehci_insnreg00_s cn61xx; 1005215976Sjmallett struct cvmx_uahcx_ehci_insnreg00_s cn63xx; 1006215976Sjmallett struct cvmx_uahcx_ehci_insnreg00_s cn63xxp1; 1007232812Sjmallett struct cvmx_uahcx_ehci_insnreg00_s cn66xx; 1008232812Sjmallett struct cvmx_uahcx_ehci_insnreg00_s cn68xx; 1009232812Sjmallett struct cvmx_uahcx_ehci_insnreg00_s cn68xxp1; 1010232812Sjmallett struct cvmx_uahcx_ehci_insnreg00_s cnf71xx; 1011215976Sjmallett}; 1012215976Sjmalletttypedef union cvmx_uahcx_ehci_insnreg00 cvmx_uahcx_ehci_insnreg00_t; 1013215976Sjmallett 1014215976Sjmallett/** 1015215976Sjmallett * cvmx_uahc#_ehci_insnreg03 1016215976Sjmallett * 1017215976Sjmallett * EHCI_INSNREG03 = EHCI Timing Adjust Register (Synopsys Speicific) 1018215976Sjmallett * This register allows you to change the timing of Phy Tx turnaround delay etc. 1019215976Sjmallett */ 1020232812Sjmallettunion cvmx_uahcx_ehci_insnreg03 { 1021215976Sjmallett uint32_t u32; 1022232812Sjmallett struct cvmx_uahcx_ehci_insnreg03_s { 1023232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1024215976Sjmallett uint32_t reserved_13_31 : 19; 1025215976Sjmallett uint32_t txtx_tadao : 3; /**< Tx-Tx turnaround Delay Add on. This field specifies the extra delays in phy_clks to 1026215976Sjmallett be added to the "Transmit to Transmit turnaround delay" value maintained in the core. 1027215976Sjmallett The default value of this register field is 0. This default value of 0 is sufficient 1028215976Sjmallett for most PHYs. But for some PHYs which puts wait states during the token packet, it 1029215976Sjmallett may be required to program a value greater than 0 to meet the transmit to transmit 1030215976Sjmallett minimum turnaround time. The recommendation to use the default value of 0 and change 1031215976Sjmallett it only if there is an issue with minimum transmit-to- transmit turnaround time. This 1032215976Sjmallett value should be programmed during core initialization and should not be changed afterwards. */ 1033215976Sjmallett uint32_t reserved_9_9 : 1; 1034215976Sjmallett uint32_t ta_off : 8; /**< Time-Available Offset. This value indicates the additional number of bytes to be 1035215976Sjmallett accommodated for the time-available calculation. The USB traffic on the bus can be started 1036215976Sjmallett only when sufficient time is available to complete the packet within the EOF1 point. Refer 1037215976Sjmallett to the USB 2.0 specification for details of the EOF1 point. This time-available 1038215976Sjmallett calculation is done in the hardware, and can be further offset by programming a value in 1039215976Sjmallett this location. 1040215976Sjmallett Note: Time-available calculation is added for future flexibility. The application is not 1041215976Sjmallett required to program this field by default. */ 1042215976Sjmallett uint32_t reserved_0_0 : 1; 1043215976Sjmallett#else 1044215976Sjmallett uint32_t reserved_0_0 : 1; 1045215976Sjmallett uint32_t ta_off : 8; 1046215976Sjmallett uint32_t reserved_9_9 : 1; 1047215976Sjmallett uint32_t txtx_tadao : 3; 1048215976Sjmallett uint32_t reserved_13_31 : 19; 1049215976Sjmallett#endif 1050215976Sjmallett } s; 1051232812Sjmallett struct cvmx_uahcx_ehci_insnreg03_s cn61xx; 1052215976Sjmallett struct cvmx_uahcx_ehci_insnreg03_s cn63xx; 1053215976Sjmallett struct cvmx_uahcx_ehci_insnreg03_s cn63xxp1; 1054232812Sjmallett struct cvmx_uahcx_ehci_insnreg03_s cn66xx; 1055232812Sjmallett struct cvmx_uahcx_ehci_insnreg03_s cn68xx; 1056232812Sjmallett struct cvmx_uahcx_ehci_insnreg03_s cn68xxp1; 1057232812Sjmallett struct cvmx_uahcx_ehci_insnreg03_s cnf71xx; 1058215976Sjmallett}; 1059215976Sjmalletttypedef union cvmx_uahcx_ehci_insnreg03 cvmx_uahcx_ehci_insnreg03_t; 1060215976Sjmallett 1061215976Sjmallett/** 1062215976Sjmallett * cvmx_uahc#_ehci_insnreg04 1063215976Sjmallett * 1064215976Sjmallett * EHCI_INSNREG04 = EHCI Debug Register (Synopsys Speicific) 1065215976Sjmallett * This register is used only for debug purposes. 1066215976Sjmallett */ 1067232812Sjmallettunion cvmx_uahcx_ehci_insnreg04 { 1068215976Sjmallett uint32_t u32; 1069232812Sjmallett struct cvmx_uahcx_ehci_insnreg04_s { 1070232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1071215976Sjmallett uint32_t reserved_6_31 : 26; 1072215976Sjmallett uint32_t auto_dis : 1; /**< Automatic feature disable. 1073215976Sjmallett 1'b0: 0 by default, the automatic feature is enabled. The Suspend signal is deasserted 1074215976Sjmallett (logic level 1'b1) when run/stop is reset by software, but the hchalted bit is not 1075215976Sjmallett yet set. 1076215976Sjmallett 1'b1: Disables the automatic feature, which takes all ports out of suspend when software 1077215976Sjmallett clears the run/stop bit. This is for backward compatibility. 1078215976Sjmallett This bit has an added functionality in release 2.80a and later. For systems where the host 1079215976Sjmallett is halted without waking up all ports out of suspend, the port can become stuck because 1080215976Sjmallett the PHYCLK is not running when the halt is programmed. To avoid this, the DWC H20AHB host 1081215976Sjmallett core automatically pulls ports out of suspend when the host is halted by software. This bit 1082215976Sjmallett is used to disable this automatic function. */ 1083215976Sjmallett uint32_t nakrf_dis : 1; /**< NAK Reload Fix Disable. 1084215976Sjmallett 1b0: NAK reload fix enabled. 1085215976Sjmallett 1b1: NAK reload fix disabled. (Incorrect NAK reload transition at the end of a microframe 1086215976Sjmallett for backward compatibility with Release 2.40c. For more information see the USB 2.0 1087215976Sjmallett Host-AHB Release Notes. */ 1088215976Sjmallett uint32_t reserved_3_3 : 1; 1089215976Sjmallett uint32_t pesd : 1; /**< Scales down port enumeration time. 1090215976Sjmallett 1'b1: scale down enabled 1091215976Sjmallett 1'b0: scale downd disabled 1092215976Sjmallett This is for simulation only. */ 1093215976Sjmallett uint32_t hcp_fw : 1; /**< HCCPARAMS Field Writeable. 1094215976Sjmallett 1'b1: The HCCPARAMS register's bits 17, 15:4, and 2:0 become writable. 1095215976Sjmallett 1'b0: The HCCPARAMS register's bits 17, 15:4, and 2:0 are not writable. */ 1096215976Sjmallett uint32_t hcp_rw : 1; /**< HCCPARAMS Reigster Writeable. 1097215976Sjmallett 1'b1: The HCCPARAMS register becomes writable. 1098215976Sjmallett 1'b0: The HCCPARAMS register is not writable. */ 1099215976Sjmallett#else 1100215976Sjmallett uint32_t hcp_rw : 1; 1101215976Sjmallett uint32_t hcp_fw : 1; 1102215976Sjmallett uint32_t pesd : 1; 1103215976Sjmallett uint32_t reserved_3_3 : 1; 1104215976Sjmallett uint32_t nakrf_dis : 1; 1105215976Sjmallett uint32_t auto_dis : 1; 1106215976Sjmallett uint32_t reserved_6_31 : 26; 1107215976Sjmallett#endif 1108215976Sjmallett } s; 1109232812Sjmallett struct cvmx_uahcx_ehci_insnreg04_s cn61xx; 1110215976Sjmallett struct cvmx_uahcx_ehci_insnreg04_s cn63xx; 1111215976Sjmallett struct cvmx_uahcx_ehci_insnreg04_s cn63xxp1; 1112232812Sjmallett struct cvmx_uahcx_ehci_insnreg04_s cn66xx; 1113232812Sjmallett struct cvmx_uahcx_ehci_insnreg04_s cn68xx; 1114232812Sjmallett struct cvmx_uahcx_ehci_insnreg04_s cn68xxp1; 1115232812Sjmallett struct cvmx_uahcx_ehci_insnreg04_s cnf71xx; 1116215976Sjmallett}; 1117215976Sjmalletttypedef union cvmx_uahcx_ehci_insnreg04 cvmx_uahcx_ehci_insnreg04_t; 1118215976Sjmallett 1119215976Sjmallett/** 1120215976Sjmallett * cvmx_uahc#_ehci_insnreg06 1121215976Sjmallett * 1122215976Sjmallett * EHCI_INSNREG06 = EHCI AHB Error Status Register (Synopsys Speicific) 1123215976Sjmallett * This register contains AHB Error Status. 1124215976Sjmallett */ 1125232812Sjmallettunion cvmx_uahcx_ehci_insnreg06 { 1126215976Sjmallett uint32_t u32; 1127232812Sjmallett struct cvmx_uahcx_ehci_insnreg06_s { 1128232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1129215976Sjmallett uint32_t vld : 1; /**< AHB Error Captured. Indicator that an AHB error was encountered and values were captured. 1130215976Sjmallett To clear this field the application must write a 0 to it. */ 1131215976Sjmallett uint32_t reserved_0_30 : 31; 1132215976Sjmallett#else 1133215976Sjmallett uint32_t reserved_0_30 : 31; 1134215976Sjmallett uint32_t vld : 1; 1135215976Sjmallett#endif 1136215976Sjmallett } s; 1137232812Sjmallett struct cvmx_uahcx_ehci_insnreg06_s cn61xx; 1138215976Sjmallett struct cvmx_uahcx_ehci_insnreg06_s cn63xx; 1139215976Sjmallett struct cvmx_uahcx_ehci_insnreg06_s cn63xxp1; 1140232812Sjmallett struct cvmx_uahcx_ehci_insnreg06_s cn66xx; 1141232812Sjmallett struct cvmx_uahcx_ehci_insnreg06_s cn68xx; 1142232812Sjmallett struct cvmx_uahcx_ehci_insnreg06_s cn68xxp1; 1143232812Sjmallett struct cvmx_uahcx_ehci_insnreg06_s cnf71xx; 1144215976Sjmallett}; 1145215976Sjmalletttypedef union cvmx_uahcx_ehci_insnreg06 cvmx_uahcx_ehci_insnreg06_t; 1146215976Sjmallett 1147215976Sjmallett/** 1148215976Sjmallett * cvmx_uahc#_ehci_insnreg07 1149215976Sjmallett * 1150215976Sjmallett * EHCI_INSNREG07 = EHCI AHB Error Address Register (Synopsys Speicific) 1151215976Sjmallett * This register contains AHB Error Status. 1152215976Sjmallett */ 1153232812Sjmallettunion cvmx_uahcx_ehci_insnreg07 { 1154215976Sjmallett uint32_t u32; 1155232812Sjmallett struct cvmx_uahcx_ehci_insnreg07_s { 1156232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1157215976Sjmallett uint32_t err_addr : 32; /**< AHB Master Error Address. AHB address of the control phase at which the AHB error occurred */ 1158215976Sjmallett#else 1159215976Sjmallett uint32_t err_addr : 32; 1160215976Sjmallett#endif 1161215976Sjmallett } s; 1162232812Sjmallett struct cvmx_uahcx_ehci_insnreg07_s cn61xx; 1163215976Sjmallett struct cvmx_uahcx_ehci_insnreg07_s cn63xx; 1164215976Sjmallett struct cvmx_uahcx_ehci_insnreg07_s cn63xxp1; 1165232812Sjmallett struct cvmx_uahcx_ehci_insnreg07_s cn66xx; 1166232812Sjmallett struct cvmx_uahcx_ehci_insnreg07_s cn68xx; 1167232812Sjmallett struct cvmx_uahcx_ehci_insnreg07_s cn68xxp1; 1168232812Sjmallett struct cvmx_uahcx_ehci_insnreg07_s cnf71xx; 1169215976Sjmallett}; 1170215976Sjmalletttypedef union cvmx_uahcx_ehci_insnreg07 cvmx_uahcx_ehci_insnreg07_t; 1171215976Sjmallett 1172215976Sjmallett/** 1173215976Sjmallett * cvmx_uahc#_ehci_periodiclistbase 1174215976Sjmallett * 1175215976Sjmallett * PERIODICLISTBASE = Periodic Frame List Base Address Register 1176215976Sjmallett * 1177215976Sjmallett * This 32-bit register contains the beginning address of the Periodic Frame List in the system memory. If the 1178215976Sjmallett * host controller is in 64-bit mode (as indicated by a one in the 64-bit Addressing Capability field in the 1179215976Sjmallett * HCCSPARAMS register), then the most significant 32 bits of every control data structure address comes 1180215976Sjmallett * from the CTRLDSSEGMENT register (see Section 2.3.5). System software loads this register prior to 1181215976Sjmallett * starting the schedule execution by the Host Controller (see 4.1). The memory structure referenced by this 1182215976Sjmallett * physical memory pointer is assumed to be 4-Kbyte aligned. The contents of this register are combined with 1183215976Sjmallett * the Frame Index Register (FRINDEX) to enable the Host Controller to step through the Periodic Frame List 1184215976Sjmallett * in sequence. 1185215976Sjmallett */ 1186232812Sjmallettunion cvmx_uahcx_ehci_periodiclistbase { 1187215976Sjmallett uint32_t u32; 1188232812Sjmallett struct cvmx_uahcx_ehci_periodiclistbase_s { 1189232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1190215976Sjmallett uint32_t baddr : 20; /**< Base Address (Low). These bits correspond to memory address signals [31:12],respectively. */ 1191215976Sjmallett uint32_t reserved_0_11 : 12; 1192215976Sjmallett#else 1193215976Sjmallett uint32_t reserved_0_11 : 12; 1194215976Sjmallett uint32_t baddr : 20; 1195215976Sjmallett#endif 1196215976Sjmallett } s; 1197232812Sjmallett struct cvmx_uahcx_ehci_periodiclistbase_s cn61xx; 1198215976Sjmallett struct cvmx_uahcx_ehci_periodiclistbase_s cn63xx; 1199215976Sjmallett struct cvmx_uahcx_ehci_periodiclistbase_s cn63xxp1; 1200232812Sjmallett struct cvmx_uahcx_ehci_periodiclistbase_s cn66xx; 1201232812Sjmallett struct cvmx_uahcx_ehci_periodiclistbase_s cn68xx; 1202232812Sjmallett struct cvmx_uahcx_ehci_periodiclistbase_s cn68xxp1; 1203232812Sjmallett struct cvmx_uahcx_ehci_periodiclistbase_s cnf71xx; 1204215976Sjmallett}; 1205215976Sjmalletttypedef union cvmx_uahcx_ehci_periodiclistbase cvmx_uahcx_ehci_periodiclistbase_t; 1206215976Sjmallett 1207215976Sjmallett/** 1208215976Sjmallett * cvmx_uahc#_ehci_portsc# 1209215976Sjmallett * 1210215976Sjmallett * PORTSCX = Port X Status and Control Register 1211215976Sjmallett * Default: 00002000h (w/PPC set to one); 00003000h (w/PPC set to a zero) 1212215976Sjmallett */ 1213232812Sjmallettunion cvmx_uahcx_ehci_portscx { 1214215976Sjmallett uint32_t u32; 1215232812Sjmallett struct cvmx_uahcx_ehci_portscx_s { 1216232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1217215976Sjmallett uint32_t reserved_23_31 : 9; 1218215976Sjmallett uint32_t wkoc_e : 1; /**< Wake on Over-current Enable.Writing this bit to a 1219215976Sjmallett one enables the port to be sensitive to over-current conditions as wake-up events. 1220215976Sjmallett This field is zero if Port Power is zero. */ 1221215976Sjmallett uint32_t wkdscnnt_e : 1; /**< Wake on Disconnect Enable. Writing this bit to a one enables the port to be 1222215976Sjmallett sensitive to device disconnects as wake-up events. 1223215976Sjmallett This field is zero if Port Power is zero. */ 1224215976Sjmallett uint32_t wkcnnt_e : 1; /**< Wake on Connect Enable. Writing this bit to a one enables the port to be 1225215976Sjmallett sensitive to device connects as wake-up events. 1226215976Sjmallett This field is zero if Port Power is zero. */ 1227215976Sjmallett uint32_t ptc : 4; /**< Port Test Control. When this field is zero, the port is NOT 1228215976Sjmallett operating in a test mode. A non-zero value indicates that it is operating 1229215976Sjmallett in test mode and the specific test mode is indicated by the specific value. 1230215976Sjmallett The encoding of the test mode bits are (0110b - 1111b are reserved): 1231215976Sjmallett Bits Test Mode 1232215976Sjmallett 0000b Test mode not enabled 1233215976Sjmallett 0001b Test J_STATE 1234215976Sjmallett 0010b Test K_STATE 1235215976Sjmallett 0011b Test SE0_NAK 1236215976Sjmallett 0100b Test Packet 1237215976Sjmallett 0101b Test FORCE_ENABLE */ 1238215976Sjmallett uint32_t pic : 2; /**< Port Indicator Control. Writing to these bits has no effect if the 1239215976Sjmallett P_INDICATOR bit in the HCSPARAMS register is a zero. If P_INDICATOR bit is a one, 1240215976Sjmallett then the bit encodings are: 1241215976Sjmallett Bit Value Meaning 1242215976Sjmallett 00b Port indicators are off 1243215976Sjmallett 01b Amber 1244215976Sjmallett 10b Green 1245215976Sjmallett 11b Undefined 1246215976Sjmallett This field is zero if Port Power is zero. */ 1247215976Sjmallett uint32_t po : 1; /**< Port Owner.This bit unconditionally goes to a 0b when the 1248215976Sjmallett Configured bit in the CONFIGFLAG register makes a 0b to 1b transition. This bit 1249215976Sjmallett unconditionally goes to 1b whenever the Configured bit is zero. 1250215976Sjmallett System software uses this field to release ownership of the port to a selected host 1251215976Sjmallett controller (in the event that the attached device is not a high-speed device). Software 1252215976Sjmallett writes a one to this bit when the attached device is not a high-speed device. A one in 1253215976Sjmallett this bit means that a companion host controller owns and controls the port. */ 1254215976Sjmallett uint32_t pp : 1; /**< Port Power. The function of this bit depends on the value of the Port 1255215976Sjmallett Power Control (PPC) field in the HCSPARAMS register. The behavior is as follows: 1256215976Sjmallett PPC PP Operation 1257215976Sjmallett 0b 1b RO - Host controller does not have port power control switches. 1258215976Sjmallett Each port is hard-wired to power. 1259215976Sjmallett 1b 1b/0b R/W - Host controller has port power control switches. This bit 1260215976Sjmallett represents the current setting of the switch (0 = off, 1 = on). When 1261215976Sjmallett power is not available on a port (i.e. PP equals a 0), the port is 1262215976Sjmallett nonfunctional and will not report attaches, detaches, etc. 1263215976Sjmallett When an over-current condition is detected on a powered port and PPC is a one, the PP 1264215976Sjmallett bit in each affected port may be transitioned by the host controller from a 1 to 0 1265215976Sjmallett (removing power from the port). */ 1266215976Sjmallett uint32_t lsts : 2; /**< Line Status.These bits reflect the current logical levels of the D+ (bit 11) and D(bit 10) 1267215976Sjmallett signal lines. These bits are used for detection of low-speed USB devices prior to 1268215976Sjmallett the port reset and enable sequence. This field is valid only when the port enable bit is 1269215976Sjmallett zero and the current connect status bit is set to a one. 1270215976Sjmallett The encoding of the bits are: 1271215976Sjmallett Bits[11:10] USB State Interpretation 1272215976Sjmallett 00b SE0 Not Low-speed device, perform EHCI reset 1273215976Sjmallett 10b J-state Not Low-speed device, perform EHCI reset 1274215976Sjmallett 01b K-state Low-speed device, release ownership of port 1275215976Sjmallett 11b Undefined Not Low-speed device, perform EHCI reset. 1276215976Sjmallett This value of this field is undefined if Port Power is zero. */ 1277215976Sjmallett uint32_t reserved_9_9 : 1; 1278215976Sjmallett uint32_t prst : 1; /**< Port Reset.1=Port is in Reset. 0=Port is not in Reset. Default = 0. When 1279215976Sjmallett software writes a one to this bit (from a zero), the bus reset sequence as defined in the 1280215976Sjmallett USB Specification Revision 2.0 is started. Software writes a zero to this bit to terminate 1281215976Sjmallett the bus reset sequence. Software must keep this bit at a one long enough to ensure the 1282215976Sjmallett reset sequence, as specified in the USB Specification Revision 2.0, completes. Note: 1283215976Sjmallett when software writes this bit to a one, it must also write a zero to the Port Enable bit. 1284215976Sjmallett Note that when software writes a zero to this bit there may be a delay before the bit 1285215976Sjmallett status changes to a zero. The bit status will not read as a zero until after the reset has 1286215976Sjmallett completed. If the port is in high-speed mode after reset is complete, the host controller 1287215976Sjmallett will automatically enable this port (e.g. set the Port Enable bit to a one). A host controller 1288215976Sjmallett must terminate the reset and stabilize the state of the port within 2 milliseconds of 1289215976Sjmallett software transitioning this bit from a one to a zero. For example: if the port detects that 1290215976Sjmallett the attached device is high-speed during reset, then the host controller must have the 1291215976Sjmallett port in the enabled state within 2ms of software writing this bit to a zero. 1292215976Sjmallett The HCHalted bit in the USBSTS register should be a zero before software attempts to 1293215976Sjmallett use this bit. The host controller may hold Port Reset asserted to a one when the 1294215976Sjmallett HCHalted bit is a one. 1295215976Sjmallett This field is zero if Port Power is zero. */ 1296215976Sjmallett uint32_t spd : 1; /**< Suspend. 1=Port in suspend state. 0=Port not in suspend state. Default = 0. Port 1297215976Sjmallett Enabled Bit and Suspend bit of this register define the port states as follows: 1298215976Sjmallett Bits [Port Enabled, Suspend] Port State 1299215976Sjmallett 0X Disable 1300215976Sjmallett 10 Enable 1301215976Sjmallett 11 Suspend 1302215976Sjmallett When in suspend state, downstream propagation of data is blocked on this port, except 1303215976Sjmallett for port reset. The blocking occurs at the end of the current transaction, if a transaction 1304215976Sjmallett was in progress when this bit was written to 1. In the suspend state, the port is sensitive 1305215976Sjmallett to resume detection. Note that the bit status does not change until the port is 1306215976Sjmallett suspended and that there may be a delay in suspending a port if there is a transaction 1307215976Sjmallett currently in progress on the USB. 1308215976Sjmallett A write of zero to this bit is ignored by the host controller. The host controller will 1309215976Sjmallett unconditionally set this bit to a zero when: 1310215976Sjmallett . Software sets the Force Port Resume bit to a zero (from a one). 1311215976Sjmallett . Software sets the Port Reset bit to a one (from a zero). 1312215976Sjmallett If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is 1313215976Sjmallett a zero) the results are undefined. 1314215976Sjmallett This field is zero if Port Power is zero. */ 1315215976Sjmallett uint32_t fpr : 1; /**< Force Port Resume. 1316215976Sjmallett 1= Resume detected/driven on port. 0=No resume (Kstate) 1317215976Sjmallett detected/driven on port. Default = 0. This functionality defined for manipulating 1318215976Sjmallett this bit depends on the value of the Suspend bit. For example, if the port is not 1319215976Sjmallett suspended (Suspend and Enabled bits are a one) and software transitions this bit to a 1320215976Sjmallett one, then the effects on the bus are undefined. 1321215976Sjmallett Software sets this bit to a 1 to drive resume signaling. The Host Controller sets this bit to 1322215976Sjmallett a 1 if a J-to-K transition is detected while the port is in the Suspend state. When this bit 1323215976Sjmallett transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in 1324215976Sjmallett the USBSTS register is also set to a one. If software sets this bit to a one, the host 1325215976Sjmallett controller must not set the Port Change Detect bit. 1326215976Sjmallett Note that when the EHCI controller owns the port, the resume sequence follows the 1327215976Sjmallett defined sequence documented in the USB Specification Revision 2.0. The resume 1328215976Sjmallett signaling (Full-speed 'K') is driven on the port as long as this bit remains a one. Software 1329215976Sjmallett must appropriately time the Resume and set this bit to a zero when the appropriate 1330215976Sjmallett amount of time has elapsed. Writing a zero (from one) causes the port to return to high- 1331215976Sjmallett speed mode (forcing the bus below the port into a high-speed idle). This bit will remain a 1332215976Sjmallett one until the port has switched to the high-speed idle. The host controller must complete 1333215976Sjmallett this transition within 2 milliseconds of software setting this bit to a zero. 1334215976Sjmallett This field is zero if Port Power is zero. */ 1335215976Sjmallett uint32_t occ : 1; /**< Over-current Change. 1=This bit gets set to a one when there is a change to Over-current Active. 1336215976Sjmallett Software clears this bit by writing a one to this bit position. */ 1337215976Sjmallett uint32_t oca : 1; /**< Over-current Active. 1=This port currently has an over-current condition. 0=This port does not 1338215976Sjmallett have an over-current condition. This bit will automatically transition from a one to a zero when 1339215976Sjmallett the over current condition is removed. */ 1340215976Sjmallett uint32_t pedc : 1; /**< Port Enable/Disable Change. 1=Port enabled/disabled status has changed. 1341215976Sjmallett 0=No change. Default = 0. For the root hub, this bit gets set to a one only when a port is 1342215976Sjmallett disabled due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of 1343215976Sjmallett the USB Specification for the definition of a Port Error). Software clears this bit by writing 1344215976Sjmallett a 1 to it. 1345215976Sjmallett This field is zero if Port Power is zero. */ 1346215976Sjmallett uint32_t ped : 1; /**< Port Enabled/Disabled. 1=Enable. 0=Disable. Ports can only be 1347215976Sjmallett enabled by the host controller as a part of the reset and enable. Software cannot enable 1348215976Sjmallett a port by writing a one to this field. The host controller will only set this bit to a one when 1349215976Sjmallett the reset sequence determines that the attached device is a high-speed device. 1350215976Sjmallett Ports can be disabled by either a fault condition (disconnect event or other fault 1351215976Sjmallett condition) or by host software. Note that the bit status does not change until the port 1352215976Sjmallett state actually changes. There may be a delay in disabling or enabling a port due to other 1353215976Sjmallett host controller and bus events. See Section 4.2 for full details on port reset and enable. 1354215976Sjmallett When the port is disabled (0b) downstream propagation of data is blocked on this port, 1355215976Sjmallett except for reset. 1356215976Sjmallett This field is zero if Port Power is zero. */ 1357215976Sjmallett uint32_t csc : 1; /**< Connect Status Change. 1=Change in Current Connect Status. 0=No change. Indicates a change 1358215976Sjmallett has occurred in the port's Current Connect Status. The host controller sets this bit for all 1359215976Sjmallett changes to the port device connect status, even if system software has not cleared an existing 1360215976Sjmallett connect status change. For example, the insertion status changes twice before system software 1361215976Sjmallett has cleared the changed condition, hub hardware will be setting an already-set bit 1362215976Sjmallett (i.e., the bit will remain set). Software sets this bit to 0 by writing a 1 to it. 1363215976Sjmallett This field is zero if Port Power is zero. */ 1364215976Sjmallett uint32_t ccs : 1; /**< Current Connect Status. 1=Device is present on port. 0=No device is present. 1365215976Sjmallett This value reflects the current state of the port, and may not correspond 1366215976Sjmallett directly to the event that caused the Connect Status Change bit (Bit 1) to be set. 1367215976Sjmallett This field is zero if Port Power is zero. */ 1368215976Sjmallett#else 1369215976Sjmallett uint32_t ccs : 1; 1370215976Sjmallett uint32_t csc : 1; 1371215976Sjmallett uint32_t ped : 1; 1372215976Sjmallett uint32_t pedc : 1; 1373215976Sjmallett uint32_t oca : 1; 1374215976Sjmallett uint32_t occ : 1; 1375215976Sjmallett uint32_t fpr : 1; 1376215976Sjmallett uint32_t spd : 1; 1377215976Sjmallett uint32_t prst : 1; 1378215976Sjmallett uint32_t reserved_9_9 : 1; 1379215976Sjmallett uint32_t lsts : 2; 1380215976Sjmallett uint32_t pp : 1; 1381215976Sjmallett uint32_t po : 1; 1382215976Sjmallett uint32_t pic : 2; 1383215976Sjmallett uint32_t ptc : 4; 1384215976Sjmallett uint32_t wkcnnt_e : 1; 1385215976Sjmallett uint32_t wkdscnnt_e : 1; 1386215976Sjmallett uint32_t wkoc_e : 1; 1387215976Sjmallett uint32_t reserved_23_31 : 9; 1388215976Sjmallett#endif 1389215976Sjmallett } s; 1390232812Sjmallett struct cvmx_uahcx_ehci_portscx_s cn61xx; 1391215976Sjmallett struct cvmx_uahcx_ehci_portscx_s cn63xx; 1392215976Sjmallett struct cvmx_uahcx_ehci_portscx_s cn63xxp1; 1393232812Sjmallett struct cvmx_uahcx_ehci_portscx_s cn66xx; 1394232812Sjmallett struct cvmx_uahcx_ehci_portscx_s cn68xx; 1395232812Sjmallett struct cvmx_uahcx_ehci_portscx_s cn68xxp1; 1396232812Sjmallett struct cvmx_uahcx_ehci_portscx_s cnf71xx; 1397215976Sjmallett}; 1398215976Sjmalletttypedef union cvmx_uahcx_ehci_portscx cvmx_uahcx_ehci_portscx_t; 1399215976Sjmallett 1400215976Sjmallett/** 1401215976Sjmallett * cvmx_uahc#_ehci_usbcmd 1402215976Sjmallett * 1403215976Sjmallett * USBCMD = USB Command Register 1404215976Sjmallett * The Command Register indicates the command to be executed by the serial bus host controller. Writing to the register causes a command to be executed. 1405215976Sjmallett */ 1406232812Sjmallettunion cvmx_uahcx_ehci_usbcmd { 1407215976Sjmallett uint32_t u32; 1408232812Sjmallett struct cvmx_uahcx_ehci_usbcmd_s { 1409232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1410215976Sjmallett uint32_t reserved_24_31 : 8; 1411215976Sjmallett uint32_t itc : 8; /**< Interrupt Threshold Control. This field is used by system software 1412215976Sjmallett to select the maximum rate at which the host controller will issue interrupts. The only 1413215976Sjmallett valid values are defined below. If software writes an invalid value to this register, the 1414215976Sjmallett results are undefined. Value Maximum Interrupt Interval 1415215976Sjmallett 00h Reserved 1416215976Sjmallett 01h 1 micro-frame 1417215976Sjmallett 02h 2 micro-frames 1418215976Sjmallett 04h 4 micro-frames 1419215976Sjmallett 08h 8 micro-frames (default, equates to 1 ms) 1420215976Sjmallett 10h 16 micro-frames (2 ms) 1421215976Sjmallett 20h 32 micro-frames (4 ms) 1422215976Sjmallett 40h 64 micro-frames (8 ms) */ 1423215976Sjmallett uint32_t reserved_12_15 : 4; 1424215976Sjmallett uint32_t aspm_en : 1; /**< Asynchronous Schedule Park Mode Enable. */ 1425215976Sjmallett uint32_t reserved_10_10 : 1; 1426215976Sjmallett uint32_t aspmc : 2; /**< Asynchronous Schedule Park Mode Count. */ 1427215976Sjmallett uint32_t lhcr : 1; /**< Light Host Controller Reset */ 1428215976Sjmallett uint32_t iaa_db : 1; /**< Interrupt on Async Advance Doorbell.This bit is used as a doorbell by 1429215976Sjmallett software to tell the host controller to issue an interrupt the next time it advances 1430215976Sjmallett asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. 1431215976Sjmallett When the host controller has evicted all appropriate cached schedule state, it sets the 1432215976Sjmallett Interrupt on Async Advance status bit in the USBSTS register. If the Interrupt on Async 1433215976Sjmallett Advance Enable bit in the USBINTR register is a one then the host controller will assert 1434215976Sjmallett an interrupt at the next interrupt threshold. */ 1435215976Sjmallett uint32_t as_en : 1; /**< Asynchronous Schedule Enable .This bit controls whether the host 1436215976Sjmallett controller skips processing the Asynchronous Schedule. Values mean: 1437215976Sjmallett - 0: Do not process the Asynchronous Schedule 1438215976Sjmallett - 1: Use the ASYNCLISTADDR register to access the Asynchronous Schedule. */ 1439215976Sjmallett uint32_t ps_en : 1; /**< Periodic Schedule Enable. This bit controls whether the host 1440215976Sjmallett controller skips processing the Periodic Schedule. Values mean: 1441215976Sjmallett - 0: Do not process the Periodic Schedule 1442215976Sjmallett - 1: Use the PERIODICLISTBASE register to access the Periodic Schedule. */ 1443215976Sjmallett uint32_t fls : 2; /**< Frame List Size. This field is R/W only if Programmable 1444215976Sjmallett Frame List Flag in the HCCPARAMS registers is set to a one. This field specifies the 1445215976Sjmallett size of the frame list. The size the frame list controls which bits in the Frame Index 1446215976Sjmallett Register should be used for the Frame List Current index. Values mean: 1447215976Sjmallett 00b: 1024 elements (4096 bytes) Default value 1448215976Sjmallett 01b: 512 elements (2048 bytes) 1449215976Sjmallett 10b: 256 elements (1024 bytes) - for resource-constrained environments 1450215976Sjmallett 11b: Reserved */ 1451215976Sjmallett uint32_t hcreset : 1; /**< Host Controller Reset (HCRESET). This control bit is used by software to reset 1452215976Sjmallett the host controller. The effects of this on Root Hub registers are similar to a Chip 1453215976Sjmallett Hardware Reset. When software writes a one to this bit, the Host Controller resets 1454215976Sjmallett its internal pipelines, timers, counters, state machines, etc. to their initial 1455215976Sjmallett value. Any transaction currently in progress on USB is immediately terminated. 1456215976Sjmallett A USB reset is not driven on downstream ports. 1457215976Sjmallett This bit is set to zero by the Host Controller when the reset process is complete. Software can not 1458215976Sjmallett terminate the reset process early by writing zero to this register. 1459215976Sjmallett Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero. 1460215976Sjmallett Attempting to reset an activtely running host controller will result in undefined behavior. */ 1461215976Sjmallett uint32_t rs : 1; /**< Run/Stop (RS). 1462215976Sjmallett 1=Run. 0=Stop. 1463215976Sjmallett When set to a 1, the Host Controller proceeds with execution of the schedule. 1464215976Sjmallett The Host Controller continues execution as long as this bit is set to a 1. 1465215976Sjmallett When this bit is set to 0, the Host Controller completes the current and any 1466215976Sjmallett actively pipelined transactions on the USB and then halts. The Host 1467215976Sjmallett Controller must halt within 16 micro-frames after software clears the Run bit. The HC 1468215976Sjmallett Halted bit in the status register indicates when the Host Controller has finished its 1469215976Sjmallett pending pipelined transactions and has entered the stopped state. Software must not 1470215976Sjmallett write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in 1471215976Sjmallett the USBSTS register is a one). Doing so will yield undefined results. */ 1472215976Sjmallett#else 1473215976Sjmallett uint32_t rs : 1; 1474215976Sjmallett uint32_t hcreset : 1; 1475215976Sjmallett uint32_t fls : 2; 1476215976Sjmallett uint32_t ps_en : 1; 1477215976Sjmallett uint32_t as_en : 1; 1478215976Sjmallett uint32_t iaa_db : 1; 1479215976Sjmallett uint32_t lhcr : 1; 1480215976Sjmallett uint32_t aspmc : 2; 1481215976Sjmallett uint32_t reserved_10_10 : 1; 1482215976Sjmallett uint32_t aspm_en : 1; 1483215976Sjmallett uint32_t reserved_12_15 : 4; 1484215976Sjmallett uint32_t itc : 8; 1485215976Sjmallett uint32_t reserved_24_31 : 8; 1486215976Sjmallett#endif 1487215976Sjmallett } s; 1488232812Sjmallett struct cvmx_uahcx_ehci_usbcmd_s cn61xx; 1489215976Sjmallett struct cvmx_uahcx_ehci_usbcmd_s cn63xx; 1490215976Sjmallett struct cvmx_uahcx_ehci_usbcmd_s cn63xxp1; 1491232812Sjmallett struct cvmx_uahcx_ehci_usbcmd_s cn66xx; 1492232812Sjmallett struct cvmx_uahcx_ehci_usbcmd_s cn68xx; 1493232812Sjmallett struct cvmx_uahcx_ehci_usbcmd_s cn68xxp1; 1494232812Sjmallett struct cvmx_uahcx_ehci_usbcmd_s cnf71xx; 1495215976Sjmallett}; 1496215976Sjmalletttypedef union cvmx_uahcx_ehci_usbcmd cvmx_uahcx_ehci_usbcmd_t; 1497215976Sjmallett 1498215976Sjmallett/** 1499215976Sjmallett * cvmx_uahc#_ehci_usbintr 1500215976Sjmallett * 1501215976Sjmallett * USBINTR = USB Interrupt Enable Register 1502215976Sjmallett * This register enables and disables reporting of the corresponding interrupt to the software. When a bit is set 1503215976Sjmallett * and the corresponding interrupt is active, an interrupt is generated to the host. Interrupt sources that are 1504215976Sjmallett * disabled in this register still appear in the USBSTS to allow the software to poll for events. 1505215976Sjmallett * Each interrupt enable bit description indicates whether it is dependent on the interrupt threshold mechanism. 1506215976Sjmallett * Note: for all enable register bits, 1= Enabled, 0= Disabled 1507215976Sjmallett */ 1508232812Sjmallettunion cvmx_uahcx_ehci_usbintr { 1509215976Sjmallett uint32_t u32; 1510232812Sjmallett struct cvmx_uahcx_ehci_usbintr_s { 1511232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1512215976Sjmallett uint32_t reserved_6_31 : 26; 1513215976Sjmallett uint32_t ioaa_en : 1; /**< Interrupt on Async Advance Enable When this bit is a one, and the Interrupt on 1514215976Sjmallett Async Advance bit in the USBSTS register is a one, the host controller will issue an 1515215976Sjmallett interrupt at the next interrupt threshold. The interrupt is acknowledged by software 1516215976Sjmallett clearing the Interrupt on Async Advance bit. */ 1517215976Sjmallett uint32_t hserr_en : 1; /**< Host System Error Enable When this bit is a one, and the Host System 1518215976Sjmallett Error Status bit in the USBSTS register is a one, the host controller will issue an 1519215976Sjmallett interrupt. The interrupt is acknowledged by software clearing the Host System Error bit. */ 1520215976Sjmallett uint32_t flro_en : 1; /**< Frame List Rollover Enable. When this bit is a one, and the Frame List 1521215976Sjmallett Rollover bit in the USBSTS register is a one, the host controller will issue an 1522215976Sjmallett interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit. */ 1523215976Sjmallett uint32_t pci_en : 1; /**< Port Change Interrupt Enable. When this bit is a one, and the Port Change Detect bit in 1524215976Sjmallett the USBSTS register is a one, the host controller will issue an interrupt. 1525215976Sjmallett The interrupt is acknowledged by software clearing the Port Change Detect bit. */ 1526215976Sjmallett uint32_t usberrint_en : 1; /**< USB Error Interrupt Enable. When this bit is a one, and the USBERRINT 1527215976Sjmallett bit in the USBSTS register is a one, the host controller will issue an interrupt at the next 1528215976Sjmallett interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit. */ 1529215976Sjmallett uint32_t usbint_en : 1; /**< USB Interrupt Enable. When this bit is a one, and the USBINT bit in the USBSTS register 1530215976Sjmallett is a one, the host controller will issue an interrupt at the next interrupt threshold. 1531215976Sjmallett The interrupt is acknowledged by software clearing the USBINT bit. */ 1532215976Sjmallett#else 1533215976Sjmallett uint32_t usbint_en : 1; 1534215976Sjmallett uint32_t usberrint_en : 1; 1535215976Sjmallett uint32_t pci_en : 1; 1536215976Sjmallett uint32_t flro_en : 1; 1537215976Sjmallett uint32_t hserr_en : 1; 1538215976Sjmallett uint32_t ioaa_en : 1; 1539215976Sjmallett uint32_t reserved_6_31 : 26; 1540215976Sjmallett#endif 1541215976Sjmallett } s; 1542232812Sjmallett struct cvmx_uahcx_ehci_usbintr_s cn61xx; 1543215976Sjmallett struct cvmx_uahcx_ehci_usbintr_s cn63xx; 1544215976Sjmallett struct cvmx_uahcx_ehci_usbintr_s cn63xxp1; 1545232812Sjmallett struct cvmx_uahcx_ehci_usbintr_s cn66xx; 1546232812Sjmallett struct cvmx_uahcx_ehci_usbintr_s cn68xx; 1547232812Sjmallett struct cvmx_uahcx_ehci_usbintr_s cn68xxp1; 1548232812Sjmallett struct cvmx_uahcx_ehci_usbintr_s cnf71xx; 1549215976Sjmallett}; 1550215976Sjmalletttypedef union cvmx_uahcx_ehci_usbintr cvmx_uahcx_ehci_usbintr_t; 1551215976Sjmallett 1552215976Sjmallett/** 1553215976Sjmallett * cvmx_uahc#_ehci_usbsts 1554215976Sjmallett * 1555215976Sjmallett * USBSTS = USB Status Register 1556215976Sjmallett * This register indicates pending interrupts and various states of the Host Controller. The status resulting from 1557215976Sjmallett * a transaction on the serial bus is not indicated in this register. Software sets a bit to 0 in this register by 1558215976Sjmallett * writing a 1 to it. 1559215976Sjmallett */ 1560232812Sjmallettunion cvmx_uahcx_ehci_usbsts { 1561215976Sjmallett uint32_t u32; 1562232812Sjmallett struct cvmx_uahcx_ehci_usbsts_s { 1563232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1564215976Sjmallett uint32_t reserved_16_31 : 16; 1565215976Sjmallett uint32_t ass : 1; /**< Asynchronous Schedule Status. The bit reports the current real 1566215976Sjmallett status of the Asynchronous Schedule. If this bit is a zero then the status of the 1567215976Sjmallett Asynchronous Schedule is disabled. If this bit is a one then the status of the 1568215976Sjmallett Asynchronous Schedule is enabled. The Host Controller is not required to immediately 1569215976Sjmallett disable or enable the Asynchronous Schedule when software transitions the 1570215976Sjmallett Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the 1571215976Sjmallett Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is 1572215976Sjmallett either enabled (1) or disabled (0). */ 1573215976Sjmallett uint32_t pss : 1; /**< Periodic Schedule Status. The bit reports the current real status of 1574215976Sjmallett the Periodic Schedule. If this bit is a zero then the status of the Periodic 1575215976Sjmallett Schedule is disabled. If this bit is a one then the status of the Periodic Schedule 1576215976Sjmallett is enabled. The Host Controller is not required to immediately disable or enable the 1577215976Sjmallett Periodic Schedule when software transitions the Periodic Schedule Enable bit in 1578215976Sjmallett the USBCMD register. When this bit and the Periodic Schedule Enable bit are the 1579215976Sjmallett same value, the Periodic Schedule is either enabled (1) or disabled (0). */ 1580215976Sjmallett uint32_t reclm : 1; /**< Reclamation.This is a read-only status bit, which is used to detect an 1581215976Sjmallett empty asynchronous schedule. */ 1582215976Sjmallett uint32_t hchtd : 1; /**< HCHalted. This bit is a zero whenever the Run/Stop bit is a one. The 1583215976Sjmallett Host Controller sets this bit to one after it has stopped executing as a result of the 1584215976Sjmallett Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. 1585215976Sjmallett internal error). */ 1586215976Sjmallett uint32_t reserved_6_11 : 6; 1587215976Sjmallett uint32_t ioaa : 1; /**< Interrupt on Async Advance. System software can force the host 1588215976Sjmallett controller to issue an interrupt the next time the host controller advances the 1589215976Sjmallett asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell bit 1590215976Sjmallett in the USBCMD register. This status bit indicates the assertion of that interrupt source. */ 1591215976Sjmallett uint32_t hsyserr : 1; /**< Host System Error. The Host Controller sets this bit to 1 when a serious error 1592215976Sjmallett occurs during a host system access involving the Host Controller module. */ 1593215976Sjmallett uint32_t flro : 1; /**< Frame List Rollover. The Host Controller sets this bit to a one when the 1594215976Sjmallett Frame List Index rolls over from its maximum value to zero. The exact value at 1595215976Sjmallett which the rollover occurs depends on the frame list size. For example, if 1596215976Sjmallett the frame list size (as programmed in the Frame List Size field of the USBCMD register) 1597215976Sjmallett is 1024, the Frame Index Register rolls over every time FRINDEX[13] toggles. Similarly, 1598215976Sjmallett if the size is 512, the Host Controller sets this bit to a one every time FRINDEX[12] 1599215976Sjmallett toggles. */ 1600215976Sjmallett uint32_t pcd : 1; /**< Port Change Detect. The Host Controller sets this bit to a one when any port 1601215976Sjmallett for which the Port Owner bit is set to zero (see Section 2.3.9) has a change bit transition 1602215976Sjmallett from a zero to a one or a Force Port Resume bit transition from a zero to a one as a 1603215976Sjmallett result of a J-K transition detected on a suspended port. This bit will also be set as a 1604215976Sjmallett result of the Connect Status Change being set to a one after system software has 1605215976Sjmallett relinquished ownership of a connected port by writing a one to a port's Port Owner bit. */ 1606215976Sjmallett uint32_t usberrint : 1; /**< USB Error Interrupt. The Host Controller sets this bit to 1 when completion of a USB 1607215976Sjmallett transaction results in an error condition (e.g., error counter underflow). If the TD on 1608215976Sjmallett which the error interrupt occurred also had its IOC bit set, both this bit and USBINT 1609215976Sjmallett bit are set. */ 1610215976Sjmallett uint32_t usbint : 1; /**< USB Interrupt. The Host Controller sets this bit to 1 on the completion of a USB 1611215976Sjmallett transaction, which results in the retirement of a Transfer Descriptor that had its 1612215976Sjmallett IOC bit set. The Host Controller also sets this bit to 1 when a short packet is 1613215976Sjmallett detected (actual number of bytes received was less than the expected number of bytes). */ 1614215976Sjmallett#else 1615215976Sjmallett uint32_t usbint : 1; 1616215976Sjmallett uint32_t usberrint : 1; 1617215976Sjmallett uint32_t pcd : 1; 1618215976Sjmallett uint32_t flro : 1; 1619215976Sjmallett uint32_t hsyserr : 1; 1620215976Sjmallett uint32_t ioaa : 1; 1621215976Sjmallett uint32_t reserved_6_11 : 6; 1622215976Sjmallett uint32_t hchtd : 1; 1623215976Sjmallett uint32_t reclm : 1; 1624215976Sjmallett uint32_t pss : 1; 1625215976Sjmallett uint32_t ass : 1; 1626215976Sjmallett uint32_t reserved_16_31 : 16; 1627215976Sjmallett#endif 1628215976Sjmallett } s; 1629232812Sjmallett struct cvmx_uahcx_ehci_usbsts_s cn61xx; 1630215976Sjmallett struct cvmx_uahcx_ehci_usbsts_s cn63xx; 1631215976Sjmallett struct cvmx_uahcx_ehci_usbsts_s cn63xxp1; 1632232812Sjmallett struct cvmx_uahcx_ehci_usbsts_s cn66xx; 1633232812Sjmallett struct cvmx_uahcx_ehci_usbsts_s cn68xx; 1634232812Sjmallett struct cvmx_uahcx_ehci_usbsts_s cn68xxp1; 1635232812Sjmallett struct cvmx_uahcx_ehci_usbsts_s cnf71xx; 1636215976Sjmallett}; 1637215976Sjmalletttypedef union cvmx_uahcx_ehci_usbsts cvmx_uahcx_ehci_usbsts_t; 1638215976Sjmallett 1639215976Sjmallett/** 1640215976Sjmallett * cvmx_uahc#_ohci0_hcbulkcurrented 1641215976Sjmallett * 1642215976Sjmallett * HCBULKCURRENTED = Host Controller Bulk Current ED Register 1643215976Sjmallett * 1644215976Sjmallett * The HcBulkCurrentED register contains the physical address of the current endpoint of the Bulk list. As the Bulk list will be served in a round-robin 1645215976Sjmallett * fashion, the endpoints will be ordered according to their insertion to the list. 1646215976Sjmallett */ 1647232812Sjmallettunion cvmx_uahcx_ohci0_hcbulkcurrented { 1648215976Sjmallett uint32_t u32; 1649232812Sjmallett struct cvmx_uahcx_ohci0_hcbulkcurrented_s { 1650232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1651215976Sjmallett uint32_t bced : 28; /**< BulkCurrentED. This is advanced to the next ED after the HC has served the 1652215976Sjmallett present one. HC continues processing the list from where it left off in the 1653215976Sjmallett last Frame. When it reaches the end of the Bulk list, HC checks the 1654215976Sjmallett ControlListFilled of HcControl. If set, it copies the content of HcBulkHeadED 1655215976Sjmallett to HcBulkCurrentED and clears the bit. If it is not set, it does nothing. 1656215976Sjmallett HCD is only allowed to modify this register when the BulkListEnable of 1657215976Sjmallett HcControl is cleared. When set, the HCD only reads the instantaneous value of 1658215976Sjmallett this register. This is initially set to zero to indicate the end of the Bulk 1659215976Sjmallett list. */ 1660215976Sjmallett uint32_t reserved_0_3 : 4; 1661215976Sjmallett#else 1662215976Sjmallett uint32_t reserved_0_3 : 4; 1663215976Sjmallett uint32_t bced : 28; 1664215976Sjmallett#endif 1665215976Sjmallett } s; 1666232812Sjmallett struct cvmx_uahcx_ohci0_hcbulkcurrented_s cn61xx; 1667215976Sjmallett struct cvmx_uahcx_ohci0_hcbulkcurrented_s cn63xx; 1668215976Sjmallett struct cvmx_uahcx_ohci0_hcbulkcurrented_s cn63xxp1; 1669232812Sjmallett struct cvmx_uahcx_ohci0_hcbulkcurrented_s cn66xx; 1670232812Sjmallett struct cvmx_uahcx_ohci0_hcbulkcurrented_s cn68xx; 1671232812Sjmallett struct cvmx_uahcx_ohci0_hcbulkcurrented_s cn68xxp1; 1672232812Sjmallett struct cvmx_uahcx_ohci0_hcbulkcurrented_s cnf71xx; 1673215976Sjmallett}; 1674215976Sjmalletttypedef union cvmx_uahcx_ohci0_hcbulkcurrented cvmx_uahcx_ohci0_hcbulkcurrented_t; 1675215976Sjmallett 1676215976Sjmallett/** 1677215976Sjmallett * cvmx_uahc#_ohci0_hcbulkheaded 1678215976Sjmallett * 1679215976Sjmallett * HCBULKHEADED = Host Controller Bulk Head ED Register 1680215976Sjmallett * 1681215976Sjmallett * The HcBulkHeadED register contains the physical address of the first Endpoint Descriptor of the Bulk list. 1682215976Sjmallett */ 1683232812Sjmallettunion cvmx_uahcx_ohci0_hcbulkheaded { 1684215976Sjmallett uint32_t u32; 1685232812Sjmallett struct cvmx_uahcx_ohci0_hcbulkheaded_s { 1686232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1687215976Sjmallett uint32_t bhed : 28; /**< BulkHeadED. HC traverses the Bulk list starting with the HcBulkHeadED 1688215976Sjmallett pointer. The content is loaded from HCCA during the initialization of HC. */ 1689215976Sjmallett uint32_t reserved_0_3 : 4; 1690215976Sjmallett#else 1691215976Sjmallett uint32_t reserved_0_3 : 4; 1692215976Sjmallett uint32_t bhed : 28; 1693215976Sjmallett#endif 1694215976Sjmallett } s; 1695232812Sjmallett struct cvmx_uahcx_ohci0_hcbulkheaded_s cn61xx; 1696215976Sjmallett struct cvmx_uahcx_ohci0_hcbulkheaded_s cn63xx; 1697215976Sjmallett struct cvmx_uahcx_ohci0_hcbulkheaded_s cn63xxp1; 1698232812Sjmallett struct cvmx_uahcx_ohci0_hcbulkheaded_s cn66xx; 1699232812Sjmallett struct cvmx_uahcx_ohci0_hcbulkheaded_s cn68xx; 1700232812Sjmallett struct cvmx_uahcx_ohci0_hcbulkheaded_s cn68xxp1; 1701232812Sjmallett struct cvmx_uahcx_ohci0_hcbulkheaded_s cnf71xx; 1702215976Sjmallett}; 1703215976Sjmalletttypedef union cvmx_uahcx_ohci0_hcbulkheaded cvmx_uahcx_ohci0_hcbulkheaded_t; 1704215976Sjmallett 1705215976Sjmallett/** 1706215976Sjmallett * cvmx_uahc#_ohci0_hccommandstatus 1707215976Sjmallett * 1708215976Sjmallett * HCCOMMANDSTATUS = Host Controller Command Status Register 1709215976Sjmallett * 1710215976Sjmallett * The HcCommandStatus register is used by the Host Controller to receive commands issued by the Host Controller Driver, as well as reflecting the 1711215976Sjmallett * current status of the Host Controller. To the Host Controller Driver, it appears to be a "write to set" register. The Host Controller must ensure 1712215976Sjmallett * that bits written as '1' become set in the register while bits written as '0' remain unchanged in the register. The Host Controller Driver 1713215976Sjmallett * may issue multiple distinct commands to the Host Controller without concern for corrupting previously issued commands. The Host Controller Driver 1714215976Sjmallett * has normal read access to all bits. 1715215976Sjmallett * The SchedulingOverrunCount field indicates the number of frames with which the Host Controller has detected the scheduling overrun error. This 1716215976Sjmallett * occurs when the Periodic list does not complete before EOF. When a scheduling overrun error is detected, the Host Controller increments the counter 1717215976Sjmallett * and sets the SchedulingOverrun field in the HcInterruptStatus register. 1718215976Sjmallett */ 1719232812Sjmallettunion cvmx_uahcx_ohci0_hccommandstatus { 1720215976Sjmallett uint32_t u32; 1721232812Sjmallett struct cvmx_uahcx_ohci0_hccommandstatus_s { 1722232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1723215976Sjmallett uint32_t reserved_18_31 : 14; 1724215976Sjmallett uint32_t soc : 2; /**< SchedulingOverrunCount. These bits are incremented on each scheduling overrun 1725215976Sjmallett error. It is initialized to 00b and wraps around at 11b. This will be 1726215976Sjmallett incremented when a scheduling overrun is detected even if SchedulingOverrun 1727215976Sjmallett in HcInterruptStatus has already been set. This is used by HCD to monitor 1728215976Sjmallett any persistent scheduling problems. */ 1729215976Sjmallett uint32_t reserved_4_15 : 12; 1730215976Sjmallett uint32_t ocr : 1; /**< OwnershipChangeRequest. This bit is set by an OS HCD to request a change of 1731215976Sjmallett control of the HC. When set HC will set the OwnershipChange field in 1732215976Sjmallett HcInterruptStatus. After the changeover, this bit is cleared and remains so 1733215976Sjmallett until the next request from OS HCD. */ 1734215976Sjmallett uint32_t blf : 1; /**< BulkListFilled This bit is used to indicate whether there are any TDs on the 1735215976Sjmallett Bulk list. It is set by HCD whenever it adds a TD to an ED in the Bulk list. 1736215976Sjmallett When HC begins to process the head of the Bulk list, it checks BF. As long 1737215976Sjmallett as BulkListFilled is 0, HC will not start processing the Bulk list. If 1738215976Sjmallett BulkListFilled is 1, HC will start processing the Bulk list and will set BF 1739215976Sjmallett to 0. If HC finds a TD on the list, then HC will set BulkListFilled to 1 1740215976Sjmallett causing the Bulk list processing to continue. If no TD is found on the Bulk 1741215976Sjmallett list,and if HCD does not set BulkListFilled, then BulkListFilled will still 1742215976Sjmallett be 0 when HC completes processing the Bulk list and Bulk list processing will 1743215976Sjmallett stop. */ 1744215976Sjmallett uint32_t clf : 1; /**< ControlListFilled. This bit is used to indicate whether there are any TDs 1745215976Sjmallett on the Control list. It is set by HCD whenever it adds a TD to an ED in the 1746215976Sjmallett Control list. When HC begins to process the head of the Control list, it 1747215976Sjmallett checks CLF. As long as ControlListFilled is 0, HC will not start processing 1748215976Sjmallett the Control list. If CF is 1, HC will start processing the Control list and 1749215976Sjmallett will set ControlListFilled to 0. If HC finds a TD on the list, then HC will 1750215976Sjmallett set ControlListFilled to 1 causing the Control list processing to continue. 1751215976Sjmallett If no TD is found on the Control list, and if the HCD does not set 1752215976Sjmallett ControlListFilled, then ControlListFilled will still be 0 when HC completes 1753215976Sjmallett processing the Control list and Control list processing will stop. */ 1754215976Sjmallett uint32_t hcr : 1; /**< HostControllerReset. This bit is set by HCD to initiate a software reset of 1755215976Sjmallett HC. Regardless of the functional state of HC, it moves to the USBSUSPEND 1756215976Sjmallett state in which most of the operational registers are reset except those 1757215976Sjmallett stated otherwise; e.g., the InterruptRouting field of HcControl, and no 1758215976Sjmallett Host bus accesses are allowed. This bit is cleared by HC upon the 1759215976Sjmallett completion of the reset operation. The reset operation must be completed 1760215976Sjmallett within 10 ms. This bit, when set, should not cause a reset to the Root Hub 1761215976Sjmallett and no subsequent reset signaling should be asserted to its downstream ports. */ 1762215976Sjmallett#else 1763215976Sjmallett uint32_t hcr : 1; 1764215976Sjmallett uint32_t clf : 1; 1765215976Sjmallett uint32_t blf : 1; 1766215976Sjmallett uint32_t ocr : 1; 1767215976Sjmallett uint32_t reserved_4_15 : 12; 1768215976Sjmallett uint32_t soc : 2; 1769215976Sjmallett uint32_t reserved_18_31 : 14; 1770215976Sjmallett#endif 1771215976Sjmallett } s; 1772232812Sjmallett struct cvmx_uahcx_ohci0_hccommandstatus_s cn61xx; 1773215976Sjmallett struct cvmx_uahcx_ohci0_hccommandstatus_s cn63xx; 1774215976Sjmallett struct cvmx_uahcx_ohci0_hccommandstatus_s cn63xxp1; 1775232812Sjmallett struct cvmx_uahcx_ohci0_hccommandstatus_s cn66xx; 1776232812Sjmallett struct cvmx_uahcx_ohci0_hccommandstatus_s cn68xx; 1777232812Sjmallett struct cvmx_uahcx_ohci0_hccommandstatus_s cn68xxp1; 1778232812Sjmallett struct cvmx_uahcx_ohci0_hccommandstatus_s cnf71xx; 1779215976Sjmallett}; 1780215976Sjmalletttypedef union cvmx_uahcx_ohci0_hccommandstatus cvmx_uahcx_ohci0_hccommandstatus_t; 1781215976Sjmallett 1782215976Sjmallett/** 1783215976Sjmallett * cvmx_uahc#_ohci0_hccontrol 1784215976Sjmallett * 1785215976Sjmallett * HCCONTROL = Host Controller Control Register 1786215976Sjmallett * 1787215976Sjmallett * The HcControl register defines the operating modes for the Host Controller. Most of the fields in this register are modified only by the Host Controller 1788215976Sjmallett * Driver, except HostControllerFunctionalState and RemoteWakeupConnected. 1789215976Sjmallett */ 1790232812Sjmallettunion cvmx_uahcx_ohci0_hccontrol { 1791215976Sjmallett uint32_t u32; 1792232812Sjmallett struct cvmx_uahcx_ohci0_hccontrol_s { 1793232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1794215976Sjmallett uint32_t reserved_11_31 : 21; 1795215976Sjmallett uint32_t rwe : 1; /**< RemoteWakeupEnable. This bit is used by HCD to enable or disable the remote wakeup 1796215976Sjmallett feature upon the detection of upstream resume signaling. When this bit is set and 1797215976Sjmallett the ResumeDetected bit in HcInterruptStatus is set, a remote wakeup is signaled 1798215976Sjmallett to the host system. Setting this bit has no impact on the generation of hardware 1799215976Sjmallett interrupt. */ 1800215976Sjmallett uint32_t rwc : 1; /**< RemoteWakeupConnected.This bit indicates whether HC supports remote wakeup signaling. 1801215976Sjmallett If remote wakeup is supported and used by the system it is the responsibility of 1802215976Sjmallett system firmware to set this bit during POST. HC clears the bit upon a hardware reset 1803215976Sjmallett but does not alter it upon a software reset. Remote wakeup signaling of the host 1804215976Sjmallett system is host-bus-specific and is not described in this specification. */ 1805215976Sjmallett uint32_t ir : 1; /**< InterruptRouting 1806215976Sjmallett This bit determines the routing of interrupts generated by events registered in 1807215976Sjmallett HcInterruptStatus. If clear, all interrupts are routed to the normal host bus 1808215976Sjmallett interrupt mechanism. If set, interrupts are routed to the System Management 1809215976Sjmallett Interrupt. HCD clears this bit upon a hardware reset, but it does not alter 1810215976Sjmallett this bit upon a software reset. HCD uses this bit as a tag to indicate the 1811215976Sjmallett ownership of HC. */ 1812215976Sjmallett uint32_t hcfs : 2; /**< HostControllerFunctionalState for USB 1813215976Sjmallett 00b: USBRESET 1814215976Sjmallett 01b: USBRESUME 1815215976Sjmallett 10b: USBOPERATIONAL 1816215976Sjmallett 11b: USBSUSPEND 1817215976Sjmallett A transition to USBOPERATIONAL from another state causes SOF generation to begin 1818215976Sjmallett 1 ms later. HCD may determine whether HC has begun sending SOFs by reading the 1819215976Sjmallett StartofFrame field of HcInterruptStatus. 1820215976Sjmallett This field may be changed by HC only when in the USBSUSPEND state. HC may move from 1821215976Sjmallett the USBSUSPEND state to the USBRESUME state after detecting the resume signaling 1822215976Sjmallett from a downstream port. 1823215976Sjmallett HC enters USBSUSPEND after a software reset, whereas it enters USBRESET after a 1824215976Sjmallett hardware reset. The latter also resets the Root Hub and asserts subsequent reset 1825215976Sjmallett signaling to downstream ports. */ 1826215976Sjmallett uint32_t ble : 1; /**< BulkListEnable. This bit is set to enable the processing of the Bulk list in the 1827215976Sjmallett next Frame. If cleared by HCD, processing of the Bulk list does not occur after 1828215976Sjmallett the next SOF. HC checks this bit whenever it determines to process the list. When 1829215976Sjmallett disabled, HCD may modify the list. If HcBulkCurrentED is pointing to an ED to be 1830215976Sjmallett removed, HCD must advance the pointer by updating HcBulkCurrentED before re-enabling 1831215976Sjmallett processing of the list. */ 1832215976Sjmallett uint32_t cle : 1; /**< ControlListEnable. This bit is set to enable the processing of the Control list in 1833215976Sjmallett the next Frame. If cleared by HCD, processing of the Control list does not occur 1834215976Sjmallett after the next SOF. HC must check this bit whenever it determines to process the 1835215976Sjmallett list. When disabled, HCD may modify the list. If HcControlCurrentED is pointing to 1836215976Sjmallett an ED to be removed, HCD must advance the pointer by updating HcControlCurrentED 1837215976Sjmallett before re-enabling processing of the list. */ 1838215976Sjmallett uint32_t ie : 1; /**< IsochronousEnable This bit is used by HCD to enable/disable processing of 1839215976Sjmallett isochronous EDs. While processing the periodic list in a Frame, HC checks the 1840215976Sjmallett status of this bit when it finds an Isochronous ED (F=1). If set (enabled), HC 1841215976Sjmallett continues processing the EDs. If cleared (disabled), HC halts processing of the 1842215976Sjmallett periodic list (which now contains only isochronous EDs) and begins processing the 1843215976Sjmallett Bulk/Control lists. Setting this bit is guaranteed to take effect in the next 1844215976Sjmallett Frame (not the current Frame). */ 1845215976Sjmallett uint32_t ple : 1; /**< PeriodicListEnable. This bit is set to enable the processing of the periodic list 1846215976Sjmallett in the next Frame. If cleared by HCD, processing of the periodic list does not 1847215976Sjmallett occur after the next SOF. HC must check this bit before it starts processing 1848215976Sjmallett the list. */ 1849215976Sjmallett uint32_t cbsr : 2; /**< ControlBulkServiceRatio. This specifies the service ratio between Control and 1850215976Sjmallett Bulk EDs. Before processing any of the nonperiodic lists, HC must compare the 1851215976Sjmallett ratio specified with its internal count on how many nonempty Control EDs have 1852215976Sjmallett been processed, in determining whether to continue serving another Control ED 1853215976Sjmallett or switching to Bulk EDs. The internal count will be retained when crossing 1854215976Sjmallett the frame boundary. In case of reset, HCD is responsible for restoring this 1855215976Sjmallett value. 1856215976Sjmallett 1857215976Sjmallett CBSR No. of Control EDs Over Bulk EDs Served 1858215976Sjmallett 0 1:1 1859215976Sjmallett 1 2:1 1860215976Sjmallett 2 3:1 1861215976Sjmallett 3 4:1 */ 1862215976Sjmallett#else 1863215976Sjmallett uint32_t cbsr : 2; 1864215976Sjmallett uint32_t ple : 1; 1865215976Sjmallett uint32_t ie : 1; 1866215976Sjmallett uint32_t cle : 1; 1867215976Sjmallett uint32_t ble : 1; 1868215976Sjmallett uint32_t hcfs : 2; 1869215976Sjmallett uint32_t ir : 1; 1870215976Sjmallett uint32_t rwc : 1; 1871215976Sjmallett uint32_t rwe : 1; 1872215976Sjmallett uint32_t reserved_11_31 : 21; 1873215976Sjmallett#endif 1874215976Sjmallett } s; 1875232812Sjmallett struct cvmx_uahcx_ohci0_hccontrol_s cn61xx; 1876215976Sjmallett struct cvmx_uahcx_ohci0_hccontrol_s cn63xx; 1877215976Sjmallett struct cvmx_uahcx_ohci0_hccontrol_s cn63xxp1; 1878232812Sjmallett struct cvmx_uahcx_ohci0_hccontrol_s cn66xx; 1879232812Sjmallett struct cvmx_uahcx_ohci0_hccontrol_s cn68xx; 1880232812Sjmallett struct cvmx_uahcx_ohci0_hccontrol_s cn68xxp1; 1881232812Sjmallett struct cvmx_uahcx_ohci0_hccontrol_s cnf71xx; 1882215976Sjmallett}; 1883215976Sjmalletttypedef union cvmx_uahcx_ohci0_hccontrol cvmx_uahcx_ohci0_hccontrol_t; 1884215976Sjmallett 1885215976Sjmallett/** 1886215976Sjmallett * cvmx_uahc#_ohci0_hccontrolcurrented 1887215976Sjmallett * 1888215976Sjmallett * HCCONTROLCURRENTED = Host Controller Control Current ED Register 1889215976Sjmallett * 1890215976Sjmallett * The HcControlCurrentED register contains the physical address of the current Endpoint Descriptor of the Control list. 1891215976Sjmallett */ 1892232812Sjmallettunion cvmx_uahcx_ohci0_hccontrolcurrented { 1893215976Sjmallett uint32_t u32; 1894232812Sjmallett struct cvmx_uahcx_ohci0_hccontrolcurrented_s { 1895232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1896215976Sjmallett uint32_t cced : 28; /**< ControlCurrentED. This pointer is advanced to the next ED after serving the 1897215976Sjmallett present one. HC will continue processing the list from where it left off in 1898215976Sjmallett the last Frame. When it reaches the end of the Control list, HC checks the 1899215976Sjmallett ControlListFilled of in HcCommandStatus. If set, it copies the content of 1900215976Sjmallett HcControlHeadED to HcControlCurrentED and clears the bit. If not set, it 1901215976Sjmallett does nothing. HCD is allowed to modify this register only when the 1902215976Sjmallett ControlListEnable of HcControl is cleared. When set, HCD only reads the 1903215976Sjmallett instantaneous value of this register. Initially, this is set to zero to 1904215976Sjmallett indicate the end of the Control list. */ 1905215976Sjmallett uint32_t reserved_0_3 : 4; 1906215976Sjmallett#else 1907215976Sjmallett uint32_t reserved_0_3 : 4; 1908215976Sjmallett uint32_t cced : 28; 1909215976Sjmallett#endif 1910215976Sjmallett } s; 1911232812Sjmallett struct cvmx_uahcx_ohci0_hccontrolcurrented_s cn61xx; 1912215976Sjmallett struct cvmx_uahcx_ohci0_hccontrolcurrented_s cn63xx; 1913215976Sjmallett struct cvmx_uahcx_ohci0_hccontrolcurrented_s cn63xxp1; 1914232812Sjmallett struct cvmx_uahcx_ohci0_hccontrolcurrented_s cn66xx; 1915232812Sjmallett struct cvmx_uahcx_ohci0_hccontrolcurrented_s cn68xx; 1916232812Sjmallett struct cvmx_uahcx_ohci0_hccontrolcurrented_s cn68xxp1; 1917232812Sjmallett struct cvmx_uahcx_ohci0_hccontrolcurrented_s cnf71xx; 1918215976Sjmallett}; 1919215976Sjmalletttypedef union cvmx_uahcx_ohci0_hccontrolcurrented cvmx_uahcx_ohci0_hccontrolcurrented_t; 1920215976Sjmallett 1921215976Sjmallett/** 1922215976Sjmallett * cvmx_uahc#_ohci0_hccontrolheaded 1923215976Sjmallett * 1924215976Sjmallett * HCCONTROLHEADED = Host Controller Control Head ED Register 1925215976Sjmallett * 1926215976Sjmallett * The HcControlHeadED register contains the physical address of the first Endpoint Descriptor of the Control list. 1927215976Sjmallett */ 1928232812Sjmallettunion cvmx_uahcx_ohci0_hccontrolheaded { 1929215976Sjmallett uint32_t u32; 1930232812Sjmallett struct cvmx_uahcx_ohci0_hccontrolheaded_s { 1931232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1932215976Sjmallett uint32_t ched : 28; /**< ControlHeadED. HC traverses the Control list starting with the HcControlHeadED 1933215976Sjmallett pointer. The content is loaded from HCCA during the initialization of HC. */ 1934215976Sjmallett uint32_t reserved_0_3 : 4; 1935215976Sjmallett#else 1936215976Sjmallett uint32_t reserved_0_3 : 4; 1937215976Sjmallett uint32_t ched : 28; 1938215976Sjmallett#endif 1939215976Sjmallett } s; 1940232812Sjmallett struct cvmx_uahcx_ohci0_hccontrolheaded_s cn61xx; 1941215976Sjmallett struct cvmx_uahcx_ohci0_hccontrolheaded_s cn63xx; 1942215976Sjmallett struct cvmx_uahcx_ohci0_hccontrolheaded_s cn63xxp1; 1943232812Sjmallett struct cvmx_uahcx_ohci0_hccontrolheaded_s cn66xx; 1944232812Sjmallett struct cvmx_uahcx_ohci0_hccontrolheaded_s cn68xx; 1945232812Sjmallett struct cvmx_uahcx_ohci0_hccontrolheaded_s cn68xxp1; 1946232812Sjmallett struct cvmx_uahcx_ohci0_hccontrolheaded_s cnf71xx; 1947215976Sjmallett}; 1948215976Sjmalletttypedef union cvmx_uahcx_ohci0_hccontrolheaded cvmx_uahcx_ohci0_hccontrolheaded_t; 1949215976Sjmallett 1950215976Sjmallett/** 1951215976Sjmallett * cvmx_uahc#_ohci0_hcdonehead 1952215976Sjmallett * 1953215976Sjmallett * HCDONEHEAD = Host Controller Done Head Register 1954215976Sjmallett * 1955215976Sjmallett * The HcDoneHead register contains the physical address of the last completed Transfer Descriptor that was added to the Done queue. In normal operation, 1956215976Sjmallett * the Host Controller Driver should not need to read this register as its content is periodically written to the HCCA. 1957215976Sjmallett */ 1958232812Sjmallettunion cvmx_uahcx_ohci0_hcdonehead { 1959215976Sjmallett uint32_t u32; 1960232812Sjmallett struct cvmx_uahcx_ohci0_hcdonehead_s { 1961232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1962215976Sjmallett uint32_t dh : 28; /**< DoneHead. When a TD is completed, HC writes the content of HcDoneHead to the 1963215976Sjmallett NextTD field of the TD. HC then overwrites the content of HcDoneHead with the 1964215976Sjmallett address of this TD. This is set to zero whenever HC writes the content of 1965215976Sjmallett this register to HCCA. It also sets the WritebackDoneHead of HcInterruptStatus. */ 1966215976Sjmallett uint32_t reserved_0_3 : 4; 1967215976Sjmallett#else 1968215976Sjmallett uint32_t reserved_0_3 : 4; 1969215976Sjmallett uint32_t dh : 28; 1970215976Sjmallett#endif 1971215976Sjmallett } s; 1972232812Sjmallett struct cvmx_uahcx_ohci0_hcdonehead_s cn61xx; 1973215976Sjmallett struct cvmx_uahcx_ohci0_hcdonehead_s cn63xx; 1974215976Sjmallett struct cvmx_uahcx_ohci0_hcdonehead_s cn63xxp1; 1975232812Sjmallett struct cvmx_uahcx_ohci0_hcdonehead_s cn66xx; 1976232812Sjmallett struct cvmx_uahcx_ohci0_hcdonehead_s cn68xx; 1977232812Sjmallett struct cvmx_uahcx_ohci0_hcdonehead_s cn68xxp1; 1978232812Sjmallett struct cvmx_uahcx_ohci0_hcdonehead_s cnf71xx; 1979215976Sjmallett}; 1980215976Sjmalletttypedef union cvmx_uahcx_ohci0_hcdonehead cvmx_uahcx_ohci0_hcdonehead_t; 1981215976Sjmallett 1982215976Sjmallett/** 1983215976Sjmallett * cvmx_uahc#_ohci0_hcfminterval 1984215976Sjmallett * 1985215976Sjmallett * HCFMINTERVAL = Host Controller Frame Interval Register 1986215976Sjmallett * 1987215976Sjmallett * The HcFmInterval register contains a 14-bit value which indicates the bit time interval in a Frame, (i.e., between two consecutive SOFs), and a 15-bit value 1988215976Sjmallett * indicating the Full Speed maximum packet size that the Host Controller may transmit or receive without causing scheduling overrun. The Host Controller Driver 1989215976Sjmallett * may carry out minor adjustment on the FrameInterval by writing a new value over the present one at each SOF. This provides the programmability necessary for 1990215976Sjmallett * the Host Controller to synchronize with an external clocking resource and to adjust any unknown local clock offset. 1991215976Sjmallett */ 1992232812Sjmallettunion cvmx_uahcx_ohci0_hcfminterval { 1993215976Sjmallett uint32_t u32; 1994232812Sjmallett struct cvmx_uahcx_ohci0_hcfminterval_s { 1995232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1996215976Sjmallett uint32_t fit : 1; /**< FrameIntervalToggle. HCD toggles this bit whenever it loads a new value to 1997215976Sjmallett FrameInterval. */ 1998215976Sjmallett uint32_t fsmps : 15; /**< FSLargestDataPacket. This field specifies a value which is loaded into the 1999215976Sjmallett Largest Data Packet Counter at the beginning of each frame. The counter value 2000215976Sjmallett represents the largest amount of data in bits which can be sent or received by 2001215976Sjmallett the HC in a single transaction at any given time without causing scheduling 2002215976Sjmallett overrun. The field value is calculated by the HCD. */ 2003215976Sjmallett uint32_t reserved_14_15 : 2; 2004215976Sjmallett uint32_t fi : 14; /**< FrameInterval. This specifies the interval between two consecutive SOFs in bit 2005215976Sjmallett times. The nominal value is set to be 11,999. HCD should store the current 2006215976Sjmallett value of this field before resetting HC. By setting the HostControllerReset 2007215976Sjmallett field of HcCommandStatus as this will cause the HC to reset this field to its 2008215976Sjmallett nominal value. HCD may choose to restore the stored value upon the completion 2009215976Sjmallett of the Reset sequence. */ 2010215976Sjmallett#else 2011215976Sjmallett uint32_t fi : 14; 2012215976Sjmallett uint32_t reserved_14_15 : 2; 2013215976Sjmallett uint32_t fsmps : 15; 2014215976Sjmallett uint32_t fit : 1; 2015215976Sjmallett#endif 2016215976Sjmallett } s; 2017232812Sjmallett struct cvmx_uahcx_ohci0_hcfminterval_s cn61xx; 2018215976Sjmallett struct cvmx_uahcx_ohci0_hcfminterval_s cn63xx; 2019215976Sjmallett struct cvmx_uahcx_ohci0_hcfminterval_s cn63xxp1; 2020232812Sjmallett struct cvmx_uahcx_ohci0_hcfminterval_s cn66xx; 2021232812Sjmallett struct cvmx_uahcx_ohci0_hcfminterval_s cn68xx; 2022232812Sjmallett struct cvmx_uahcx_ohci0_hcfminterval_s cn68xxp1; 2023232812Sjmallett struct cvmx_uahcx_ohci0_hcfminterval_s cnf71xx; 2024215976Sjmallett}; 2025215976Sjmalletttypedef union cvmx_uahcx_ohci0_hcfminterval cvmx_uahcx_ohci0_hcfminterval_t; 2026215976Sjmallett 2027215976Sjmallett/** 2028215976Sjmallett * cvmx_uahc#_ohci0_hcfmnumber 2029215976Sjmallett * 2030215976Sjmallett * HCFMNUMBER = Host Cotroller Frame Number Register 2031215976Sjmallett * 2032215976Sjmallett * The HcFmNumber register is a 16-bit counter. It provides a timing reference among events happening in the Host Controller and the Host Controller Driver. 2033215976Sjmallett * The Host Controller Driver may use the 16-bit value specified in this register and generate a 32-bit frame number without requiring frequent access to 2034215976Sjmallett * the register. 2035215976Sjmallett */ 2036232812Sjmallettunion cvmx_uahcx_ohci0_hcfmnumber { 2037215976Sjmallett uint32_t u32; 2038232812Sjmallett struct cvmx_uahcx_ohci0_hcfmnumber_s { 2039232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2040215976Sjmallett uint32_t reserved_16_31 : 16; 2041215976Sjmallett uint32_t fn : 16; /**< FrameNumber. This is incremented when HcFmRemaining is re-loaded. It will be 2042215976Sjmallett rolled over to 0h after ffffh. When entering the USBOPERATIONAL state, 2043215976Sjmallett this will be incremented automatically. The content will be written to HCCA 2044215976Sjmallett after HC has incremented the FrameNumber at each frame boundary and sent a 2045215976Sjmallett SOF but before HC reads the first ED in that Frame. After writing to HCCA, 2046215976Sjmallett HC will set the StartofFrame in HcInterruptStatus. */ 2047215976Sjmallett#else 2048215976Sjmallett uint32_t fn : 16; 2049215976Sjmallett uint32_t reserved_16_31 : 16; 2050215976Sjmallett#endif 2051215976Sjmallett } s; 2052232812Sjmallett struct cvmx_uahcx_ohci0_hcfmnumber_s cn61xx; 2053215976Sjmallett struct cvmx_uahcx_ohci0_hcfmnumber_s cn63xx; 2054215976Sjmallett struct cvmx_uahcx_ohci0_hcfmnumber_s cn63xxp1; 2055232812Sjmallett struct cvmx_uahcx_ohci0_hcfmnumber_s cn66xx; 2056232812Sjmallett struct cvmx_uahcx_ohci0_hcfmnumber_s cn68xx; 2057232812Sjmallett struct cvmx_uahcx_ohci0_hcfmnumber_s cn68xxp1; 2058232812Sjmallett struct cvmx_uahcx_ohci0_hcfmnumber_s cnf71xx; 2059215976Sjmallett}; 2060215976Sjmalletttypedef union cvmx_uahcx_ohci0_hcfmnumber cvmx_uahcx_ohci0_hcfmnumber_t; 2061215976Sjmallett 2062215976Sjmallett/** 2063215976Sjmallett * cvmx_uahc#_ohci0_hcfmremaining 2064215976Sjmallett * 2065215976Sjmallett * HCFMREMAINING = Host Controller Frame Remaining Register 2066215976Sjmallett * The HcFmRemaining register is a 14-bit down counter showing the bit time remaining in the current Frame. 2067215976Sjmallett */ 2068232812Sjmallettunion cvmx_uahcx_ohci0_hcfmremaining { 2069215976Sjmallett uint32_t u32; 2070232812Sjmallett struct cvmx_uahcx_ohci0_hcfmremaining_s { 2071232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2072215976Sjmallett uint32_t frt : 1; /**< FrameRemainingToggle. This bit is loaded from the FrameIntervalToggle field 2073215976Sjmallett of HcFmInterval whenever FrameRemaining reaches 0. This bit is used by HCD 2074215976Sjmallett for the synchronization between FrameInterval and FrameRemaining. */ 2075215976Sjmallett uint32_t reserved_14_30 : 17; 2076215976Sjmallett uint32_t fr : 14; /**< FrameRemaining. This counter is decremented at each bit time. When it 2077215976Sjmallett reaches zero, it is reset by loading the FrameInterval value specified in 2078215976Sjmallett HcFmInterval at the next bit time boundary. When entering the USBOPERATIONAL 2079215976Sjmallett state, HC re-loads the content with the FrameInterval of HcFmInterval and uses 2080215976Sjmallett the updated value from the next SOF. */ 2081215976Sjmallett#else 2082215976Sjmallett uint32_t fr : 14; 2083215976Sjmallett uint32_t reserved_14_30 : 17; 2084215976Sjmallett uint32_t frt : 1; 2085215976Sjmallett#endif 2086215976Sjmallett } s; 2087232812Sjmallett struct cvmx_uahcx_ohci0_hcfmremaining_s cn61xx; 2088215976Sjmallett struct cvmx_uahcx_ohci0_hcfmremaining_s cn63xx; 2089215976Sjmallett struct cvmx_uahcx_ohci0_hcfmremaining_s cn63xxp1; 2090232812Sjmallett struct cvmx_uahcx_ohci0_hcfmremaining_s cn66xx; 2091232812Sjmallett struct cvmx_uahcx_ohci0_hcfmremaining_s cn68xx; 2092232812Sjmallett struct cvmx_uahcx_ohci0_hcfmremaining_s cn68xxp1; 2093232812Sjmallett struct cvmx_uahcx_ohci0_hcfmremaining_s cnf71xx; 2094215976Sjmallett}; 2095215976Sjmalletttypedef union cvmx_uahcx_ohci0_hcfmremaining cvmx_uahcx_ohci0_hcfmremaining_t; 2096215976Sjmallett 2097215976Sjmallett/** 2098215976Sjmallett * cvmx_uahc#_ohci0_hchcca 2099215976Sjmallett * 2100215976Sjmallett * HCHCCA = Host Controller Host Controller Communication Area Register 2101215976Sjmallett * 2102215976Sjmallett * The HcHCCA register contains the physical address of the Host Controller Communication Area. The Host Controller Driver determines the alignment restrictions 2103215976Sjmallett * by writing all 1s to HcHCCA and reading the content of HcHCCA. The alignment is evaluated by examining the number of zeroes in the lower order bits. The 2104215976Sjmallett * minimum alignment is 256 bytes; therefore, bits 0 through 7 must always return '0' when read. Detailed description can be found in Chapter 4. This area 2105215976Sjmallett * is used to hold the control structures and the Interrupt table that are accessed by both the Host Controller and the Host Controller Driver. 2106215976Sjmallett */ 2107232812Sjmallettunion cvmx_uahcx_ohci0_hchcca { 2108215976Sjmallett uint32_t u32; 2109232812Sjmallett struct cvmx_uahcx_ohci0_hchcca_s { 2110232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2111215976Sjmallett uint32_t hcca : 24; /**< This is the base address (bits [31:8]) of the Host Controller Communication Area. */ 2112215976Sjmallett uint32_t reserved_0_7 : 8; 2113215976Sjmallett#else 2114215976Sjmallett uint32_t reserved_0_7 : 8; 2115215976Sjmallett uint32_t hcca : 24; 2116215976Sjmallett#endif 2117215976Sjmallett } s; 2118232812Sjmallett struct cvmx_uahcx_ohci0_hchcca_s cn61xx; 2119215976Sjmallett struct cvmx_uahcx_ohci0_hchcca_s cn63xx; 2120215976Sjmallett struct cvmx_uahcx_ohci0_hchcca_s cn63xxp1; 2121232812Sjmallett struct cvmx_uahcx_ohci0_hchcca_s cn66xx; 2122232812Sjmallett struct cvmx_uahcx_ohci0_hchcca_s cn68xx; 2123232812Sjmallett struct cvmx_uahcx_ohci0_hchcca_s cn68xxp1; 2124232812Sjmallett struct cvmx_uahcx_ohci0_hchcca_s cnf71xx; 2125215976Sjmallett}; 2126215976Sjmalletttypedef union cvmx_uahcx_ohci0_hchcca cvmx_uahcx_ohci0_hchcca_t; 2127215976Sjmallett 2128215976Sjmallett/** 2129215976Sjmallett * cvmx_uahc#_ohci0_hcinterruptdisable 2130215976Sjmallett * 2131215976Sjmallett * HCINTERRUPTDISABLE = Host Controller InterruptDisable Register 2132215976Sjmallett * 2133215976Sjmallett * Each disable bit in the HcInterruptDisable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptDisable 2134215976Sjmallett * register is coupled with the HcInterruptEnable register. Thus, writing a '1' to a bit in this register clears the corresponding bit in the HcInterruptEnable 2135215976Sjmallett * register, whereas writing a '0' to a bit in this register leaves the corresponding bit in the HcInterruptEnable register unchanged. On read, the current 2136215976Sjmallett * value of the HcInterruptEnable register is returned. 2137215976Sjmallett */ 2138232812Sjmallettunion cvmx_uahcx_ohci0_hcinterruptdisable { 2139215976Sjmallett uint32_t u32; 2140232812Sjmallett struct cvmx_uahcx_ohci0_hcinterruptdisable_s { 2141232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2142215976Sjmallett uint32_t mie : 1; /**< A '0' written to this field is ignored by HC. 2143215976Sjmallett A '1' written to this field disables interrupt generation due to events 2144215976Sjmallett specified in the other bits of this register. This field is set after a 2145215976Sjmallett hardware or software reset. */ 2146215976Sjmallett uint32_t oc : 1; /**< 0 - Ignore; 1 - Disable interrupt generation due to Ownership Change. */ 2147215976Sjmallett uint32_t reserved_7_29 : 23; 2148215976Sjmallett uint32_t rhsc : 1; /**< 0 - Ignore; 1 - Disable interrupt generation due to Root Hub Status Change. */ 2149215976Sjmallett uint32_t fno : 1; /**< 0 - Ignore; 1 - Disable interrupt generation due to Frame Number Overflow. */ 2150215976Sjmallett uint32_t ue : 1; /**< 0 - Ignore; 1 - Disable interrupt generation due to Unrecoverable Error. */ 2151215976Sjmallett uint32_t rd : 1; /**< 0 - Ignore; 1 - Disable interrupt generation due to Resume Detect. */ 2152215976Sjmallett uint32_t sf : 1; /**< 0 - Ignore; 1 - Disable interrupt generation due to Start of Frame. */ 2153215976Sjmallett uint32_t wdh : 1; /**< 0 - Ignore; 1 - Disable interrupt generation due to HcDoneHead Writeback. */ 2154215976Sjmallett uint32_t so : 1; /**< 0 - Ignore; 1 - Disable interrupt generation due to Scheduling Overrun. */ 2155215976Sjmallett#else 2156215976Sjmallett uint32_t so : 1; 2157215976Sjmallett uint32_t wdh : 1; 2158215976Sjmallett uint32_t sf : 1; 2159215976Sjmallett uint32_t rd : 1; 2160215976Sjmallett uint32_t ue : 1; 2161215976Sjmallett uint32_t fno : 1; 2162215976Sjmallett uint32_t rhsc : 1; 2163215976Sjmallett uint32_t reserved_7_29 : 23; 2164215976Sjmallett uint32_t oc : 1; 2165215976Sjmallett uint32_t mie : 1; 2166215976Sjmallett#endif 2167215976Sjmallett } s; 2168232812Sjmallett struct cvmx_uahcx_ohci0_hcinterruptdisable_s cn61xx; 2169215976Sjmallett struct cvmx_uahcx_ohci0_hcinterruptdisable_s cn63xx; 2170215976Sjmallett struct cvmx_uahcx_ohci0_hcinterruptdisable_s cn63xxp1; 2171232812Sjmallett struct cvmx_uahcx_ohci0_hcinterruptdisable_s cn66xx; 2172232812Sjmallett struct cvmx_uahcx_ohci0_hcinterruptdisable_s cn68xx; 2173232812Sjmallett struct cvmx_uahcx_ohci0_hcinterruptdisable_s cn68xxp1; 2174232812Sjmallett struct cvmx_uahcx_ohci0_hcinterruptdisable_s cnf71xx; 2175215976Sjmallett}; 2176215976Sjmalletttypedef union cvmx_uahcx_ohci0_hcinterruptdisable cvmx_uahcx_ohci0_hcinterruptdisable_t; 2177215976Sjmallett 2178215976Sjmallett/** 2179215976Sjmallett * cvmx_uahc#_ohci0_hcinterruptenable 2180215976Sjmallett * 2181215976Sjmallett * HCINTERRUPTENABLE = Host Controller InterruptEnable Register 2182215976Sjmallett * 2183215976Sjmallett * Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptEnable 2184215976Sjmallett * register is used to control which events generate a hardware interrupt. When a bit is set in the HcInterruptStatus register AND the corresponding bit 2185215976Sjmallett * in the HcInterruptEnable register is set AND the MasterInterruptEnable bit is set, then a hardware interrupt is requested on the host bus. 2186215976Sjmallett * Writing a '1' to a bit in this register sets the corresponding bit, whereas writing a '0' to a bit in this register leaves the corresponding bit 2187215976Sjmallett * unchanged. On read, the current value of this register is returned. 2188215976Sjmallett */ 2189232812Sjmallettunion cvmx_uahcx_ohci0_hcinterruptenable { 2190215976Sjmallett uint32_t u32; 2191232812Sjmallett struct cvmx_uahcx_ohci0_hcinterruptenable_s { 2192232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2193215976Sjmallett uint32_t mie : 1; /**< A '0' written to this field is ignored by HC. 2194215976Sjmallett A '1' written to this field enables interrupt generation due to events 2195215976Sjmallett specified in the other bits of this register. This is used by HCD as a Master 2196215976Sjmallett Interrupt Enable. */ 2197215976Sjmallett uint32_t oc : 1; /**< 0 - Ignore; 1 - Enable interrupt generation due to Ownership Change. */ 2198215976Sjmallett uint32_t reserved_7_29 : 23; 2199215976Sjmallett uint32_t rhsc : 1; /**< 0 - Ignore; 1 - Enable interrupt generation due to Root Hub Status Change. */ 2200215976Sjmallett uint32_t fno : 1; /**< 0 - Ignore; 1 - Enable interrupt generation due to Frame Number Overflow. */ 2201215976Sjmallett uint32_t ue : 1; /**< 0 - Ignore; 1 - Enable interrupt generation due to Unrecoverable Error. */ 2202215976Sjmallett uint32_t rd : 1; /**< 0 - Ignore; 1 - Enable interrupt generation due to Resume Detect. */ 2203215976Sjmallett uint32_t sf : 1; /**< 0 - Ignore; 1 - Enable interrupt generation due to Start of Frame. */ 2204215976Sjmallett uint32_t wdh : 1; /**< 0 - Ignore; 1 - Enable interrupt generation due to HcDoneHead Writeback. */ 2205215976Sjmallett uint32_t so : 1; /**< 0 - Ignore; 1 - Enable interrupt generation due to Scheduling Overrun. */ 2206215976Sjmallett#else 2207215976Sjmallett uint32_t so : 1; 2208215976Sjmallett uint32_t wdh : 1; 2209215976Sjmallett uint32_t sf : 1; 2210215976Sjmallett uint32_t rd : 1; 2211215976Sjmallett uint32_t ue : 1; 2212215976Sjmallett uint32_t fno : 1; 2213215976Sjmallett uint32_t rhsc : 1; 2214215976Sjmallett uint32_t reserved_7_29 : 23; 2215215976Sjmallett uint32_t oc : 1; 2216215976Sjmallett uint32_t mie : 1; 2217215976Sjmallett#endif 2218215976Sjmallett } s; 2219232812Sjmallett struct cvmx_uahcx_ohci0_hcinterruptenable_s cn61xx; 2220215976Sjmallett struct cvmx_uahcx_ohci0_hcinterruptenable_s cn63xx; 2221215976Sjmallett struct cvmx_uahcx_ohci0_hcinterruptenable_s cn63xxp1; 2222232812Sjmallett struct cvmx_uahcx_ohci0_hcinterruptenable_s cn66xx; 2223232812Sjmallett struct cvmx_uahcx_ohci0_hcinterruptenable_s cn68xx; 2224232812Sjmallett struct cvmx_uahcx_ohci0_hcinterruptenable_s cn68xxp1; 2225232812Sjmallett struct cvmx_uahcx_ohci0_hcinterruptenable_s cnf71xx; 2226215976Sjmallett}; 2227215976Sjmalletttypedef union cvmx_uahcx_ohci0_hcinterruptenable cvmx_uahcx_ohci0_hcinterruptenable_t; 2228215976Sjmallett 2229215976Sjmallett/** 2230215976Sjmallett * cvmx_uahc#_ohci0_hcinterruptstatus 2231215976Sjmallett * 2232215976Sjmallett * HCINTERRUPTSTATUS = Host Controller InterruptStatus Register 2233215976Sjmallett * 2234215976Sjmallett * This register provides status on various events that cause hardware interrupts. When an event occurs, Host Controller sets the corresponding bit 2235215976Sjmallett * in this register. When a bit becomes set, a hardware interrupt is generated if the interrupt is enabled in the HcInterruptEnable register 2236215976Sjmallett * and the MasterInterruptEnable bit is set. The Host Controller Driver may clear specific bits in this register by writing '1' to bit positions 2237215976Sjmallett * to be cleared. The Host Controller Driver may not set any of these bits. The Host Controller will never clear the bit. 2238215976Sjmallett */ 2239232812Sjmallettunion cvmx_uahcx_ohci0_hcinterruptstatus { 2240215976Sjmallett uint32_t u32; 2241232812Sjmallett struct cvmx_uahcx_ohci0_hcinterruptstatus_s { 2242232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2243215976Sjmallett uint32_t reserved_31_31 : 1; 2244215976Sjmallett uint32_t oc : 1; /**< OwnershipChange. This bit is set by HC when HCD sets the OwnershipChangeRequest 2245215976Sjmallett field in HcCommandStatus. This event, when unmasked, will always generate an 2246215976Sjmallett System Management Interrupt (SMI) immediately. This bit is tied to 0b when the 2247215976Sjmallett SMI pin is not implemented. */ 2248215976Sjmallett uint32_t reserved_7_29 : 23; 2249215976Sjmallett uint32_t rhsc : 1; /**< RootHubStatusChange. This bit is set when the content of HcRhStatus or the 2250215976Sjmallett content of any of HcRhPortStatus[NumberofDownstreamPort] has changed. */ 2251215976Sjmallett uint32_t fno : 1; /**< FrameNumberOverflow. This bit is set when the MSb of HcFmNumber (bit 15) 2252215976Sjmallett changes value, from 0 to 1 or from 1 to 0, and after HccaFrameNumber has been 2253215976Sjmallett updated. */ 2254215976Sjmallett uint32_t ue : 1; /**< UnrecoverableError. This bit is set when HC detects a system error not related 2255215976Sjmallett to USB. HC should not proceed with any processing nor signaling before the 2256215976Sjmallett system error has been corrected. HCD clears this bit after HC has been reset. */ 2257215976Sjmallett uint32_t rd : 1; /**< ResumeDetected. This bit is set when HC detects that a device on the USB is 2258215976Sjmallett asserting resume signaling. It is the transition from no resume signaling to 2259215976Sjmallett resume signaling causing this bit to be set. This bit is not set when HCD 2260215976Sjmallett sets the USBRESUME state. */ 2261215976Sjmallett uint32_t sf : 1; /**< StartofFrame. This bit is set by HC at each start of a frame and after the 2262215976Sjmallett update of HccaFrameNumber. HC also generates a SOF token at the same time. */ 2263215976Sjmallett uint32_t wdh : 1; /**< WritebackDoneHead. This bit is set immediately after HC has written 2264215976Sjmallett HcDoneHead to HccaDoneHead. Further updates of the HccaDoneHead will not 2265215976Sjmallett occur until this bit has been cleared. HCD should only clear this bit after 2266215976Sjmallett it has saved the content of HccaDoneHead. */ 2267215976Sjmallett uint32_t so : 1; /**< SchedulingOverrun. This bit is set when the USB schedule for the current 2268215976Sjmallett Frame overruns and after the update of HccaFrameNumber. A scheduling overrun 2269215976Sjmallett will also cause the SchedulingOverrunCount of HcCommandStatus to be 2270215976Sjmallett incremented. */ 2271215976Sjmallett#else 2272215976Sjmallett uint32_t so : 1; 2273215976Sjmallett uint32_t wdh : 1; 2274215976Sjmallett uint32_t sf : 1; 2275215976Sjmallett uint32_t rd : 1; 2276215976Sjmallett uint32_t ue : 1; 2277215976Sjmallett uint32_t fno : 1; 2278215976Sjmallett uint32_t rhsc : 1; 2279215976Sjmallett uint32_t reserved_7_29 : 23; 2280215976Sjmallett uint32_t oc : 1; 2281215976Sjmallett uint32_t reserved_31_31 : 1; 2282215976Sjmallett#endif 2283215976Sjmallett } s; 2284232812Sjmallett struct cvmx_uahcx_ohci0_hcinterruptstatus_s cn61xx; 2285215976Sjmallett struct cvmx_uahcx_ohci0_hcinterruptstatus_s cn63xx; 2286215976Sjmallett struct cvmx_uahcx_ohci0_hcinterruptstatus_s cn63xxp1; 2287232812Sjmallett struct cvmx_uahcx_ohci0_hcinterruptstatus_s cn66xx; 2288232812Sjmallett struct cvmx_uahcx_ohci0_hcinterruptstatus_s cn68xx; 2289232812Sjmallett struct cvmx_uahcx_ohci0_hcinterruptstatus_s cn68xxp1; 2290232812Sjmallett struct cvmx_uahcx_ohci0_hcinterruptstatus_s cnf71xx; 2291215976Sjmallett}; 2292215976Sjmalletttypedef union cvmx_uahcx_ohci0_hcinterruptstatus cvmx_uahcx_ohci0_hcinterruptstatus_t; 2293215976Sjmallett 2294215976Sjmallett/** 2295215976Sjmallett * cvmx_uahc#_ohci0_hclsthreshold 2296215976Sjmallett * 2297215976Sjmallett * HCLSTHRESHOLD = Host Controller LS Threshold Register 2298215976Sjmallett * 2299215976Sjmallett * The HcLSThreshold register contains an 11-bit value used by the Host Controller to determine whether to commit to the transfer of a maximum of 8-byte 2300215976Sjmallett * LS packet before EOF. Neither the Host Controller nor the Host Controller Driver are allowed to change this value. 2301215976Sjmallett */ 2302232812Sjmallettunion cvmx_uahcx_ohci0_hclsthreshold { 2303215976Sjmallett uint32_t u32; 2304232812Sjmallett struct cvmx_uahcx_ohci0_hclsthreshold_s { 2305232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2306215976Sjmallett uint32_t reserved_12_31 : 20; 2307215976Sjmallett uint32_t lst : 12; /**< LSThreshold 2308215976Sjmallett This field contains a value which is compared to the FrameRemaining field 2309215976Sjmallett prior to initiating a Low Speed transaction. The transaction is started only 2310215976Sjmallett if FrameRemaining >= this field. The value is calculated by HCD 2311215976Sjmallett with the consideration of transmission and setup overhead. */ 2312215976Sjmallett#else 2313215976Sjmallett uint32_t lst : 12; 2314215976Sjmallett uint32_t reserved_12_31 : 20; 2315215976Sjmallett#endif 2316215976Sjmallett } s; 2317232812Sjmallett struct cvmx_uahcx_ohci0_hclsthreshold_s cn61xx; 2318215976Sjmallett struct cvmx_uahcx_ohci0_hclsthreshold_s cn63xx; 2319215976Sjmallett struct cvmx_uahcx_ohci0_hclsthreshold_s cn63xxp1; 2320232812Sjmallett struct cvmx_uahcx_ohci0_hclsthreshold_s cn66xx; 2321232812Sjmallett struct cvmx_uahcx_ohci0_hclsthreshold_s cn68xx; 2322232812Sjmallett struct cvmx_uahcx_ohci0_hclsthreshold_s cn68xxp1; 2323232812Sjmallett struct cvmx_uahcx_ohci0_hclsthreshold_s cnf71xx; 2324215976Sjmallett}; 2325215976Sjmalletttypedef union cvmx_uahcx_ohci0_hclsthreshold cvmx_uahcx_ohci0_hclsthreshold_t; 2326215976Sjmallett 2327215976Sjmallett/** 2328215976Sjmallett * cvmx_uahc#_ohci0_hcperiodcurrented 2329215976Sjmallett * 2330215976Sjmallett * HCPERIODCURRENTED = Host Controller Period Current ED Register 2331215976Sjmallett * 2332215976Sjmallett * The HcPeriodCurrentED register contains the physical address of the current Isochronous or Interrupt Endpoint Descriptor. 2333215976Sjmallett */ 2334232812Sjmallettunion cvmx_uahcx_ohci0_hcperiodcurrented { 2335215976Sjmallett uint32_t u32; 2336232812Sjmallett struct cvmx_uahcx_ohci0_hcperiodcurrented_s { 2337232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2338215976Sjmallett uint32_t pced : 28; /**< PeriodCurrentED. This is used by HC to point to the head of one of the 2339215976Sjmallett Periodic lists which will be processed in the current Frame. The content of 2340215976Sjmallett this register is updated by HC after a periodic ED has been processed. HCD 2341215976Sjmallett may read the content in determining which ED is currently being processed 2342215976Sjmallett at the time of reading. */ 2343215976Sjmallett uint32_t reserved_0_3 : 4; 2344215976Sjmallett#else 2345215976Sjmallett uint32_t reserved_0_3 : 4; 2346215976Sjmallett uint32_t pced : 28; 2347215976Sjmallett#endif 2348215976Sjmallett } s; 2349232812Sjmallett struct cvmx_uahcx_ohci0_hcperiodcurrented_s cn61xx; 2350215976Sjmallett struct cvmx_uahcx_ohci0_hcperiodcurrented_s cn63xx; 2351215976Sjmallett struct cvmx_uahcx_ohci0_hcperiodcurrented_s cn63xxp1; 2352232812Sjmallett struct cvmx_uahcx_ohci0_hcperiodcurrented_s cn66xx; 2353232812Sjmallett struct cvmx_uahcx_ohci0_hcperiodcurrented_s cn68xx; 2354232812Sjmallett struct cvmx_uahcx_ohci0_hcperiodcurrented_s cn68xxp1; 2355232812Sjmallett struct cvmx_uahcx_ohci0_hcperiodcurrented_s cnf71xx; 2356215976Sjmallett}; 2357215976Sjmalletttypedef union cvmx_uahcx_ohci0_hcperiodcurrented cvmx_uahcx_ohci0_hcperiodcurrented_t; 2358215976Sjmallett 2359215976Sjmallett/** 2360215976Sjmallett * cvmx_uahc#_ohci0_hcperiodicstart 2361215976Sjmallett * 2362215976Sjmallett * HCPERIODICSTART = Host Controller Periodic Start Register 2363215976Sjmallett * 2364215976Sjmallett * The HcPeriodicStart register has a 14-bit programmable value which determines when is the earliest time HC should start processing the periodic list. 2365215976Sjmallett */ 2366232812Sjmallettunion cvmx_uahcx_ohci0_hcperiodicstart { 2367215976Sjmallett uint32_t u32; 2368232812Sjmallett struct cvmx_uahcx_ohci0_hcperiodicstart_s { 2369232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2370215976Sjmallett uint32_t reserved_14_31 : 18; 2371215976Sjmallett uint32_t ps : 14; /**< PeriodicStart After a hardware reset, this field is cleared. This is then set 2372215976Sjmallett by HCD during the HC initialization. The value is calculated roughly as 10% 2373215976Sjmallett off from HcFmInterval.. A typical value will be 3E67h. When HcFmRemaining 2374215976Sjmallett reaches the value specified, processing of the periodic lists will have 2375215976Sjmallett priority over Control/Bulk processing. HC will therefore start processing 2376215976Sjmallett the Interrupt list after completing the current Control or Bulk transaction 2377215976Sjmallett that is in progress. */ 2378215976Sjmallett#else 2379215976Sjmallett uint32_t ps : 14; 2380215976Sjmallett uint32_t reserved_14_31 : 18; 2381215976Sjmallett#endif 2382215976Sjmallett } s; 2383232812Sjmallett struct cvmx_uahcx_ohci0_hcperiodicstart_s cn61xx; 2384215976Sjmallett struct cvmx_uahcx_ohci0_hcperiodicstart_s cn63xx; 2385215976Sjmallett struct cvmx_uahcx_ohci0_hcperiodicstart_s cn63xxp1; 2386232812Sjmallett struct cvmx_uahcx_ohci0_hcperiodicstart_s cn66xx; 2387232812Sjmallett struct cvmx_uahcx_ohci0_hcperiodicstart_s cn68xx; 2388232812Sjmallett struct cvmx_uahcx_ohci0_hcperiodicstart_s cn68xxp1; 2389232812Sjmallett struct cvmx_uahcx_ohci0_hcperiodicstart_s cnf71xx; 2390215976Sjmallett}; 2391215976Sjmalletttypedef union cvmx_uahcx_ohci0_hcperiodicstart cvmx_uahcx_ohci0_hcperiodicstart_t; 2392215976Sjmallett 2393215976Sjmallett/** 2394215976Sjmallett * cvmx_uahc#_ohci0_hcrevision 2395215976Sjmallett * 2396215976Sjmallett * HCREVISION = Host Controller Revision Register 2397215976Sjmallett * 2398215976Sjmallett */ 2399232812Sjmallettunion cvmx_uahcx_ohci0_hcrevision { 2400215976Sjmallett uint32_t u32; 2401232812Sjmallett struct cvmx_uahcx_ohci0_hcrevision_s { 2402232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2403215976Sjmallett uint32_t reserved_8_31 : 24; 2404215976Sjmallett uint32_t rev : 8; /**< Revision This read-only field contains the BCD representation of the version 2405215976Sjmallett of the HCI specification that is implemented by this HC. For example, a value 2406215976Sjmallett of 11h corresponds to version 1.1. All of the HC implementations that are 2407215976Sjmallett compliant with this specification will have a value of 10h. */ 2408215976Sjmallett#else 2409215976Sjmallett uint32_t rev : 8; 2410215976Sjmallett uint32_t reserved_8_31 : 24; 2411215976Sjmallett#endif 2412215976Sjmallett } s; 2413232812Sjmallett struct cvmx_uahcx_ohci0_hcrevision_s cn61xx; 2414215976Sjmallett struct cvmx_uahcx_ohci0_hcrevision_s cn63xx; 2415215976Sjmallett struct cvmx_uahcx_ohci0_hcrevision_s cn63xxp1; 2416232812Sjmallett struct cvmx_uahcx_ohci0_hcrevision_s cn66xx; 2417232812Sjmallett struct cvmx_uahcx_ohci0_hcrevision_s cn68xx; 2418232812Sjmallett struct cvmx_uahcx_ohci0_hcrevision_s cn68xxp1; 2419232812Sjmallett struct cvmx_uahcx_ohci0_hcrevision_s cnf71xx; 2420215976Sjmallett}; 2421215976Sjmalletttypedef union cvmx_uahcx_ohci0_hcrevision cvmx_uahcx_ohci0_hcrevision_t; 2422215976Sjmallett 2423215976Sjmallett/** 2424215976Sjmallett * cvmx_uahc#_ohci0_hcrhdescriptora 2425215976Sjmallett * 2426215976Sjmallett * HCRHDESCRIPTORA = Host Controller Root Hub DescriptorA Register 2427215976Sjmallett * 2428215976Sjmallett * The HcRhDescriptorA register is the first register of two describing the characteristics of the Root Hub. Reset values are implementation-specific. 2429232812Sjmallett * The descriptor length (11), descriptor type (0x29), and hub controller current (0) fields of the hub Class Descriptor are emulated by the HCD. All 2430215976Sjmallett * other fields are located in the HcRhDescriptorA and HcRhDescriptorB registers. 2431215976Sjmallett */ 2432232812Sjmallettunion cvmx_uahcx_ohci0_hcrhdescriptora { 2433215976Sjmallett uint32_t u32; 2434232812Sjmallett struct cvmx_uahcx_ohci0_hcrhdescriptora_s { 2435232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2436215976Sjmallett uint32_t potpgt : 8; /**< PowerOnToPowerGoodTime. This byte specifies the duration HCD has to wait before 2437215976Sjmallett accessing a powered-on port of the Root Hub. It is implementation-specific. The 2438215976Sjmallett unit of time is 2 ms. The duration is calculated as POTPGT * 2 ms. */ 2439215976Sjmallett uint32_t reserved_13_23 : 11; 2440215976Sjmallett uint32_t nocp : 1; /**< NoOverCurrentProtection. This bit describes how the overcurrent status for the 2441215976Sjmallett Root Hub ports are reported. When this bit is cleared, the 2442215976Sjmallett OverCurrentProtectionMode field specifies global or per-port reporting. 2443215976Sjmallett - 0: Over-current status is reported collectively for all downstream ports 2444215976Sjmallett - 1: No overcurrent protection supported */ 2445215976Sjmallett uint32_t ocpm : 1; /**< OverCurrentProtectionMode. This bit describes how the overcurrent status for 2446215976Sjmallett the Root Hub ports are reported. At reset, this fields should reflect the same 2447215976Sjmallett mode as PowerSwitchingMode. This field is valid only if the 2448215976Sjmallett NoOverCurrentProtection field is cleared. 0: over-current status is reported 2449215976Sjmallett collectively for all downstream ports 1: over-current status is reported on a 2450215976Sjmallett per-port basis */ 2451215976Sjmallett uint32_t dt : 1; /**< DeviceType. This bit specifies that the Root Hub is not a compound device. The 2452215976Sjmallett Root Hub is not permitted to be a compound device. This field should always 2453215976Sjmallett read/write 0. */ 2454215976Sjmallett uint32_t psm : 1; /**< PowerSwitchingMode. This bit is used to specify how the power switching of 2455215976Sjmallett the Root Hub ports is controlled. It is implementation-specific. This field 2456215976Sjmallett is only valid if the NoPowerSwitching field is cleared. 0: all ports are 2457215976Sjmallett powered at the same time. 1: each port is powered individually. This mode 2458215976Sjmallett allows port power to be controlled by either the global switch or per-port 2459215976Sjmallett switching. If the PortPowerControlMask bit is set, the port responds only 2460215976Sjmallett to port power commands (Set/ClearPortPower). If the port mask is cleared, 2461215976Sjmallett then the port is controlled only by the global power switch 2462215976Sjmallett (Set/ClearGlobalPower). */ 2463215976Sjmallett uint32_t nps : 1; /**< NoPowerSwitching These bits are used to specify whether power switching is 2464215976Sjmallett supported or port are always powered. It is implementation-specific. When 2465215976Sjmallett this bit is cleared, the PowerSwitchingMode specifies global or per-port 2466215976Sjmallett switching. 2467215976Sjmallett - 0: Ports are power switched 2468215976Sjmallett - 1: Ports are always powered on when the HC is powered on */ 2469215976Sjmallett uint32_t ndp : 8; /**< NumberDownstreamPorts. These bits specify the number of downstream ports 2470215976Sjmallett supported by the Root Hub. It is implementation-specific. The minimum number 2471215976Sjmallett of ports is 1. The maximum number of ports supported by OpenHCI is 15. */ 2472215976Sjmallett#else 2473215976Sjmallett uint32_t ndp : 8; 2474215976Sjmallett uint32_t nps : 1; 2475215976Sjmallett uint32_t psm : 1; 2476215976Sjmallett uint32_t dt : 1; 2477215976Sjmallett uint32_t ocpm : 1; 2478215976Sjmallett uint32_t nocp : 1; 2479215976Sjmallett uint32_t reserved_13_23 : 11; 2480215976Sjmallett uint32_t potpgt : 8; 2481215976Sjmallett#endif 2482215976Sjmallett } s; 2483232812Sjmallett struct cvmx_uahcx_ohci0_hcrhdescriptora_s cn61xx; 2484215976Sjmallett struct cvmx_uahcx_ohci0_hcrhdescriptora_s cn63xx; 2485215976Sjmallett struct cvmx_uahcx_ohci0_hcrhdescriptora_s cn63xxp1; 2486232812Sjmallett struct cvmx_uahcx_ohci0_hcrhdescriptora_s cn66xx; 2487232812Sjmallett struct cvmx_uahcx_ohci0_hcrhdescriptora_s cn68xx; 2488232812Sjmallett struct cvmx_uahcx_ohci0_hcrhdescriptora_s cn68xxp1; 2489232812Sjmallett struct cvmx_uahcx_ohci0_hcrhdescriptora_s cnf71xx; 2490215976Sjmallett}; 2491215976Sjmalletttypedef union cvmx_uahcx_ohci0_hcrhdescriptora cvmx_uahcx_ohci0_hcrhdescriptora_t; 2492215976Sjmallett 2493215976Sjmallett/** 2494215976Sjmallett * cvmx_uahc#_ohci0_hcrhdescriptorb 2495215976Sjmallett * 2496215976Sjmallett * HCRHDESCRIPTORB = Host Controller Root Hub DescriptorB Register 2497215976Sjmallett * 2498215976Sjmallett * The HcRhDescriptorB register is the second register of two describing the characteristics of the Root Hub. These fields are written during 2499215976Sjmallett * initialization to correspond with the system implementation. Reset values are implementation-specific. 2500215976Sjmallett */ 2501232812Sjmallettunion cvmx_uahcx_ohci0_hcrhdescriptorb { 2502215976Sjmallett uint32_t u32; 2503232812Sjmallett struct cvmx_uahcx_ohci0_hcrhdescriptorb_s { 2504232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2505215976Sjmallett uint32_t ppcm : 16; /**< PortPowerControlMask. 2506215976Sjmallett Each bit indicates if a port is affected by a global power control command 2507215976Sjmallett when PowerSwitchingMode is set. When set, the port's power state is only 2508215976Sjmallett affected by per-port power control (Set/ClearPortPower). When cleared, the 2509215976Sjmallett port is controlled by the global power switch (Set/ClearGlobalPower). If 2510215976Sjmallett the device is configured to global switching mode (PowerSwitchingMode=0), 2511215976Sjmallett this field is not valid. 2512215976Sjmallett bit 0: Reserved 2513215976Sjmallett bit 1: Ganged-power mask on Port \#1 2514215976Sjmallett bit 2: Ganged-power mask on Port \#2 2515215976Sjmallett - ... 2516215976Sjmallett bit15: Ganged-power mask on Port \#15 */ 2517215976Sjmallett uint32_t dr : 16; /**< DeviceRemovable. 2518215976Sjmallett Each bit is dedicated to a port of the Root Hub. When cleared,the attached 2519215976Sjmallett device is removable. When set, the attached device is not removable. 2520215976Sjmallett bit 0: Reserved 2521215976Sjmallett bit 1: Device attached to Port \#1 2522215976Sjmallett bit 2: Device attached to Port \#2 2523215976Sjmallett - ... 2524215976Sjmallett bit15: Device attached to Port \#15 */ 2525215976Sjmallett#else 2526215976Sjmallett uint32_t dr : 16; 2527215976Sjmallett uint32_t ppcm : 16; 2528215976Sjmallett#endif 2529215976Sjmallett } s; 2530232812Sjmallett struct cvmx_uahcx_ohci0_hcrhdescriptorb_s cn61xx; 2531215976Sjmallett struct cvmx_uahcx_ohci0_hcrhdescriptorb_s cn63xx; 2532215976Sjmallett struct cvmx_uahcx_ohci0_hcrhdescriptorb_s cn63xxp1; 2533232812Sjmallett struct cvmx_uahcx_ohci0_hcrhdescriptorb_s cn66xx; 2534232812Sjmallett struct cvmx_uahcx_ohci0_hcrhdescriptorb_s cn68xx; 2535232812Sjmallett struct cvmx_uahcx_ohci0_hcrhdescriptorb_s cn68xxp1; 2536232812Sjmallett struct cvmx_uahcx_ohci0_hcrhdescriptorb_s cnf71xx; 2537215976Sjmallett}; 2538215976Sjmalletttypedef union cvmx_uahcx_ohci0_hcrhdescriptorb cvmx_uahcx_ohci0_hcrhdescriptorb_t; 2539215976Sjmallett 2540215976Sjmallett/** 2541215976Sjmallett * cvmx_uahc#_ohci0_hcrhportstatus# 2542215976Sjmallett * 2543215976Sjmallett * HCRHPORTSTATUSX = Host Controller Root Hub Port X Status Registers 2544215976Sjmallett * 2545215976Sjmallett * The HcRhPortStatus[1:NDP] register is used to control and report port events on a per-port basis. NumberDownstreamPorts represents the number 2546215976Sjmallett * of HcRhPortStatus registers that are implemented in hardware. The lower word is used to reflect the port status, whereas the upper word reflects 2547215976Sjmallett * the status change bits. Some status bits are implemented with special write behavior (see below). If a transaction (token through handshake) is 2548215976Sjmallett * in progress when a write to change port status occurs, the resulting port status change must be postponed until the transaction completes. 2549215976Sjmallett * Reserved bits should always be written '0'. 2550215976Sjmallett */ 2551232812Sjmallettunion cvmx_uahcx_ohci0_hcrhportstatusx { 2552215976Sjmallett uint32_t u32; 2553232812Sjmallett struct cvmx_uahcx_ohci0_hcrhportstatusx_s { 2554232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2555215976Sjmallett uint32_t reserved_21_31 : 11; 2556215976Sjmallett uint32_t prsc : 1; /**< PortResetStatusChange. This bit is set at the end of the 10-ms port reset 2557215976Sjmallett signal. The HCD writes a '1' to clear this bit. Writing a '0' has no effect. 2558215976Sjmallett 0 = port reset is not complete 2559215976Sjmallett 1 = port reset is complete */ 2560215976Sjmallett uint32_t ocic : 1; /**< PortOverCurrentIndicatorChange. This bit is valid only if overcurrent 2561215976Sjmallett conditions are reported on a per-port basis. This bit is set when Root Hub 2562215976Sjmallett changes the PortOverCurrentIndicator bit. The HCD writes a '1' to clear this 2563215976Sjmallett bit. Writing a '0' has no effect. 2564215976Sjmallett 0 = no change in PortOverCurrentIndicator 2565215976Sjmallett 1 = PortOverCurrentIndicator has changed */ 2566215976Sjmallett uint32_t pssc : 1; /**< PortSuspendStatusChange. This bit is set when the full resume sequence has 2567215976Sjmallett been completed. This sequence includes the 20-s resume pulse, LS EOP, and 2568215976Sjmallett 3-ms resychronization delay. 2569215976Sjmallett The HCD writes a '1' to clear this bit. Writing a '0' has no effect. This 2570215976Sjmallett bit is also cleared when ResetStatusChange is set. 2571215976Sjmallett 0 = resume is not completed 2572215976Sjmallett 1 = resume completed */ 2573215976Sjmallett uint32_t pesc : 1; /**< PortEnableStatusChange. This bit is set when hardware events cause the 2574215976Sjmallett PortEnableStatus bit to be cleared. Changes from HCD writes do not set this 2575215976Sjmallett bit. The HCD writes a '1' to clear this bit. Writing a '0' has no effect. 2576215976Sjmallett 0 = no change in PortEnableStatus 2577215976Sjmallett 1 = change in PortEnableStatus */ 2578215976Sjmallett uint32_t csc : 1; /**< ConnectStatusChange. This bit is set whenever a connect or disconnect event 2579215976Sjmallett occurs. The HCD writes a '1' to clear this bit. Writing a '0' has no 2580215976Sjmallett effect. If CurrentConnectStatus is cleared when a SetPortReset,SetPortEnable, 2581215976Sjmallett or SetPortSuspend write occurs, this bit is set to force the driver to 2582215976Sjmallett re-evaluate the connection status since these writes should not occur if the 2583215976Sjmallett port is disconnected. 2584215976Sjmallett 0 = no change in CurrentConnectStatus 2585215976Sjmallett 1 = change in CurrentConnectStatus 2586215976Sjmallett Note: If the DeviceRemovable[NDP] bit is set, this bit is set only after a 2587215976Sjmallett Root Hub reset to inform the system that the device is attached. Description */ 2588215976Sjmallett uint32_t reserved_10_15 : 6; 2589215976Sjmallett uint32_t lsda : 1; /**< (read) LowSpeedDeviceAttached. This bit indicates the speed of the device 2590215976Sjmallett attached to this port. When set, a Low Speed device is attached to this 2591215976Sjmallett port. When clear, a Full Speed device is attached to this port. This 2592215976Sjmallett field is valid only when the CurrentConnectStatus is set. 2593215976Sjmallett 0 = full speed device attached 2594215976Sjmallett 1 = low speed device attached 2595215976Sjmallett (write) ClearPortPower. The HCD clears the PortPowerStatus bit by writing a 2596215976Sjmallett '1' to this bit. Writing a '0' has no effect. */ 2597215976Sjmallett uint32_t pps : 1; /**< (read) PortPowerStatus. This bit reflects the port's power status, regardless 2598215976Sjmallett of the type of power switching implemented. This bit is cleared if an 2599215976Sjmallett overcurrent condition is detected. HCD sets this bit by writing 2600215976Sjmallett SetPortPower or SetGlobalPower. HCD clears this bit by writing 2601215976Sjmallett ClearPortPower or ClearGlobalPower. Which power control switches are 2602215976Sjmallett enabled is determined by PowerSwitchingMode and PortPortControlMask[NDP]. 2603215976Sjmallett In global switching mode (PowerSwitchingMode=0), only Set/ClearGlobalPower 2604215976Sjmallett controls this bit. In per-port power switching (PowerSwitchingMode=1), 2605215976Sjmallett if the PortPowerControlMask[NDP] bit for the port is set, only 2606215976Sjmallett Set/ClearPortPower commands are enabled. If the mask is not set, only 2607215976Sjmallett Set/ClearGlobalPower commands are enabled. When port power is disabled, 2608215976Sjmallett CurrentConnectStatus, PortEnableStatus, PortSuspendStatus, and 2609215976Sjmallett PortResetStatus should be reset. 2610215976Sjmallett 0 = port power is off 2611215976Sjmallett 1 = port power is on 2612215976Sjmallett (write) SetPortPower. The HCD writes a '1' to set the PortPowerStatus bit. 2613215976Sjmallett Writing a '0' has no effect. Note: This bit is always reads '1' 2614215976Sjmallett if power switching is not supported. */ 2615215976Sjmallett uint32_t reserved_5_7 : 3; 2616215976Sjmallett uint32_t prs : 1; /**< (read) PortResetStatus. When this bit is set by a write to SetPortReset, port 2617215976Sjmallett reset signaling is asserted. When reset is completed, this bit is 2618215976Sjmallett cleared when PortResetStatusChange is set. This bit cannot be set if 2619215976Sjmallett CurrentConnectStatus is cleared. 2620215976Sjmallett 0 = port reset signal is not active 2621215976Sjmallett 1 = port reset signal is active 2622215976Sjmallett (write) SetPortReset. The HCD sets the port reset signaling by writing a '1' 2623215976Sjmallett to this bit. Writing a '0'has no effect. If CurrentConnectStatus is 2624215976Sjmallett cleared, this write does not set PortResetStatus, but instead sets 2625215976Sjmallett ConnectStatusChange. This informs the driver that it attempted to reset 2626215976Sjmallett a disconnected port. Description */ 2627215976Sjmallett uint32_t poci : 1; /**< (read) PortOverCurrentIndicator. This bit is only valid when the Root Hub is 2628215976Sjmallett configured in such a way that overcurrent conditions are reported on a 2629215976Sjmallett per-port basis. If per-port overcurrent reporting is not supported, this 2630215976Sjmallett bit is set to 0. If cleared, all power operations are normal for this 2631215976Sjmallett port. If set, an overcurrent condition exists on this port. This bit 2632215976Sjmallett always reflects the overcurrent input signal 2633215976Sjmallett 0 = no overcurrent condition. 2634215976Sjmallett 1 = overcurrent condition detected. 2635215976Sjmallett (write) ClearSuspendStatus. The HCD writes a '1' to initiate a resume. 2636215976Sjmallett Writing a '0' has no effect. A resume is initiated only if 2637215976Sjmallett PortSuspendStatus is set. */ 2638215976Sjmallett uint32_t pss : 1; /**< (read) PortSuspendStatus. This bit indicates the port is suspended or in the 2639215976Sjmallett resume sequence. It is set by a SetSuspendState write and cleared when 2640215976Sjmallett PortSuspendStatusChange is set at the end of the resume interval. This 2641215976Sjmallett bit cannot be set if CurrentConnectStatus is cleared. This bit is also 2642215976Sjmallett cleared when PortResetStatusChange is set at the end of the port reset 2643215976Sjmallett or when the HC is placed in the USBRESUME state. If an upstream resume is 2644215976Sjmallett in progress, it should propagate to the HC. 2645215976Sjmallett 0 = port is not suspended 2646215976Sjmallett 1 = port is suspended 2647215976Sjmallett (write) SetPortSuspend. The HCD sets the PortSuspendStatus bit by writing a 2648215976Sjmallett '1' to this bit. Writing a '0' has no effect. If CurrentConnectStatus 2649215976Sjmallett is cleared, this write does not set PortSuspendStatus; instead it sets 2650215976Sjmallett ConnectStatusChange.This informs the driver that it attempted to suspend 2651215976Sjmallett a disconnected port. */ 2652215976Sjmallett uint32_t pes : 1; /**< (read) PortEnableStatus. This bit indicates whether the port is enabled or 2653215976Sjmallett disabled. The Root Hub may clear this bit when an overcurrent condition, 2654215976Sjmallett disconnect event, switched-off power, or operational bus error such 2655215976Sjmallett as babble is detected. This change also causes PortEnabledStatusChange 2656215976Sjmallett to be set. HCD sets this bit by writing SetPortEnable and clears it by 2657215976Sjmallett writing ClearPortEnable. This bit cannot be set when CurrentConnectStatus 2658215976Sjmallett is cleared. This bit is also set, if not already, at the completion of a 2659215976Sjmallett port reset when ResetStatusChange is set or port suspend when 2660215976Sjmallett SuspendStatusChange is set. 2661215976Sjmallett 0 = port is disabled 2662215976Sjmallett 1 = port is enabled 2663215976Sjmallett (write) SetPortEnable. The HCD sets PortEnableStatus by writing a '1'. 2664215976Sjmallett Writing a '0' has no effect. If CurrentConnectStatus is cleared, this 2665215976Sjmallett write does not set PortEnableStatus, but instead sets ConnectStatusChange. 2666215976Sjmallett This informs the driver that it attempted to enable a disconnected port. */ 2667215976Sjmallett uint32_t ccs : 1; /**< (read) CurrentConnectStatus. This bit reflects the current state of the 2668215976Sjmallett downstream port. 2669215976Sjmallett 0 = no device connected 2670215976Sjmallett 1 = device connected 2671215976Sjmallett (write) ClearPortEnable. 2672215976Sjmallett The HCD writes a '1' to this bit to clear the PortEnableStatus bit. 2673215976Sjmallett Writing a '0' has no effect. The CurrentConnectStatus is not 2674215976Sjmallett affected by any write. 2675215976Sjmallett Note: This bit is always read '1b' when the attached device is 2676215976Sjmallett nonremovable (DeviceRemoveable[NDP]). */ 2677215976Sjmallett#else 2678215976Sjmallett uint32_t ccs : 1; 2679215976Sjmallett uint32_t pes : 1; 2680215976Sjmallett uint32_t pss : 1; 2681215976Sjmallett uint32_t poci : 1; 2682215976Sjmallett uint32_t prs : 1; 2683215976Sjmallett uint32_t reserved_5_7 : 3; 2684215976Sjmallett uint32_t pps : 1; 2685215976Sjmallett uint32_t lsda : 1; 2686215976Sjmallett uint32_t reserved_10_15 : 6; 2687215976Sjmallett uint32_t csc : 1; 2688215976Sjmallett uint32_t pesc : 1; 2689215976Sjmallett uint32_t pssc : 1; 2690215976Sjmallett uint32_t ocic : 1; 2691215976Sjmallett uint32_t prsc : 1; 2692215976Sjmallett uint32_t reserved_21_31 : 11; 2693215976Sjmallett#endif 2694215976Sjmallett } s; 2695232812Sjmallett struct cvmx_uahcx_ohci0_hcrhportstatusx_s cn61xx; 2696215976Sjmallett struct cvmx_uahcx_ohci0_hcrhportstatusx_s cn63xx; 2697215976Sjmallett struct cvmx_uahcx_ohci0_hcrhportstatusx_s cn63xxp1; 2698232812Sjmallett struct cvmx_uahcx_ohci0_hcrhportstatusx_s cn66xx; 2699232812Sjmallett struct cvmx_uahcx_ohci0_hcrhportstatusx_s cn68xx; 2700232812Sjmallett struct cvmx_uahcx_ohci0_hcrhportstatusx_s cn68xxp1; 2701232812Sjmallett struct cvmx_uahcx_ohci0_hcrhportstatusx_s cnf71xx; 2702215976Sjmallett}; 2703215976Sjmalletttypedef union cvmx_uahcx_ohci0_hcrhportstatusx cvmx_uahcx_ohci0_hcrhportstatusx_t; 2704215976Sjmallett 2705215976Sjmallett/** 2706215976Sjmallett * cvmx_uahc#_ohci0_hcrhstatus 2707215976Sjmallett * 2708215976Sjmallett * HCRHSTATUS = Host Controller Root Hub Status Register 2709215976Sjmallett * 2710215976Sjmallett * The HcRhStatus register is divided into two parts. The lower word of a Dword represents the Hub Status field and the upper word represents the Hub 2711215976Sjmallett * Status Change field. Reserved bits should always be written '0'. 2712215976Sjmallett */ 2713232812Sjmallettunion cvmx_uahcx_ohci0_hcrhstatus { 2714215976Sjmallett uint32_t u32; 2715232812Sjmallett struct cvmx_uahcx_ohci0_hcrhstatus_s { 2716232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2717215976Sjmallett uint32_t crwe : 1; /**< (write) ClearRemoteWakeupEnable Writing a '1' clears DeviceRemoveWakeupEnable. 2718215976Sjmallett Writing a '0' has no effect. */ 2719215976Sjmallett uint32_t reserved_18_30 : 13; 2720215976Sjmallett uint32_t ccic : 1; /**< OverCurrentIndicatorChange. This bit is set by hardware when a change has 2721215976Sjmallett occurred to the OCI field of this register. The HCD clears this bit by 2722215976Sjmallett writing a '1'. Writing a '0' has no effect. */ 2723215976Sjmallett uint32_t lpsc : 1; /**< (read) LocalPowerStatusChange. The Root Hub does not support the local power 2724215976Sjmallett status feature; thus, this bit is always read as '0'. 2725215976Sjmallett (write) SetGlobalPower In global power mode (PowerSwitchingMode=0), This bit 2726215976Sjmallett is written to '1' to turn on power to all ports (clear PortPowerStatus). 2727215976Sjmallett In per-port power mode, it sets PortPowerStatus only on ports whose 2728215976Sjmallett PortPowerControlMask bit is not set. Writing a '0' has no effect. */ 2729215976Sjmallett uint32_t drwe : 1; /**< (read) DeviceRemoteWakeupEnable. This bit enables a ConnectStatusChange bit as 2730215976Sjmallett a resume event, causing a USBSUSPEND to USBRESUME state transition and 2731215976Sjmallett setting the ResumeDetected interrupt. 0 = ConnectStatusChange is not a 2732215976Sjmallett remote wakeup event. 1 = ConnectStatusChange is a remote wakeup event. 2733215976Sjmallett (write) SetRemoteWakeupEnable Writing a '1' sets DeviceRemoveWakeupEnable. 2734215976Sjmallett Writing a '0' has no effect. */ 2735215976Sjmallett uint32_t reserved_2_14 : 13; 2736215976Sjmallett uint32_t oci : 1; /**< OverCurrentIndicator. This bit reports overcurrent conditions when the global 2737215976Sjmallett reporting is implemented. When set, an overcurrent condition exists. When 2738215976Sjmallett cleared, all power operations are normal. If per-port overcurrent protection 2739215976Sjmallett is implemented this bit is always '0' */ 2740215976Sjmallett uint32_t lps : 1; /**< (read) LocalPowerStatus. The Root Hub does not support the local power status 2741215976Sjmallett feature; thus, this bit is always read as '0. 2742215976Sjmallett (write) ClearGlobalPower. In global power mode (PowerSwitchingMode=0), This 2743215976Sjmallett bit is written to '1' to turn off power to all ports 2744215976Sjmallett (clear PortPowerStatus). In per-port power mode, it clears 2745215976Sjmallett PortPowerStatus only on ports whose PortPowerControlMask bit is not 2746215976Sjmallett set. Writing a '0' has no effect. Description */ 2747215976Sjmallett#else 2748215976Sjmallett uint32_t lps : 1; 2749215976Sjmallett uint32_t oci : 1; 2750215976Sjmallett uint32_t reserved_2_14 : 13; 2751215976Sjmallett uint32_t drwe : 1; 2752215976Sjmallett uint32_t lpsc : 1; 2753215976Sjmallett uint32_t ccic : 1; 2754215976Sjmallett uint32_t reserved_18_30 : 13; 2755215976Sjmallett uint32_t crwe : 1; 2756215976Sjmallett#endif 2757215976Sjmallett } s; 2758232812Sjmallett struct cvmx_uahcx_ohci0_hcrhstatus_s cn61xx; 2759215976Sjmallett struct cvmx_uahcx_ohci0_hcrhstatus_s cn63xx; 2760215976Sjmallett struct cvmx_uahcx_ohci0_hcrhstatus_s cn63xxp1; 2761232812Sjmallett struct cvmx_uahcx_ohci0_hcrhstatus_s cn66xx; 2762232812Sjmallett struct cvmx_uahcx_ohci0_hcrhstatus_s cn68xx; 2763232812Sjmallett struct cvmx_uahcx_ohci0_hcrhstatus_s cn68xxp1; 2764232812Sjmallett struct cvmx_uahcx_ohci0_hcrhstatus_s cnf71xx; 2765215976Sjmallett}; 2766215976Sjmalletttypedef union cvmx_uahcx_ohci0_hcrhstatus cvmx_uahcx_ohci0_hcrhstatus_t; 2767215976Sjmallett 2768215976Sjmallett/** 2769215976Sjmallett * cvmx_uahc#_ohci0_insnreg06 2770215976Sjmallett * 2771215976Sjmallett * OHCI0_INSNREG06 = OHCI AHB Error Status Register (Synopsys Speicific) 2772215976Sjmallett * 2773215976Sjmallett * This register contains AHB Error Status. 2774215976Sjmallett */ 2775232812Sjmallettunion cvmx_uahcx_ohci0_insnreg06 { 2776215976Sjmallett uint32_t u32; 2777232812Sjmallett struct cvmx_uahcx_ohci0_insnreg06_s { 2778232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2779215976Sjmallett uint32_t vld : 1; /**< AHB Error Captured. Indicator that an AHB error was encountered and values were captured. 2780215976Sjmallett To clear this field the application must write a 0 to it. */ 2781215976Sjmallett uint32_t reserved_0_30 : 31; 2782215976Sjmallett#else 2783215976Sjmallett uint32_t reserved_0_30 : 31; 2784215976Sjmallett uint32_t vld : 1; 2785215976Sjmallett#endif 2786215976Sjmallett } s; 2787232812Sjmallett struct cvmx_uahcx_ohci0_insnreg06_s cn61xx; 2788215976Sjmallett struct cvmx_uahcx_ohci0_insnreg06_s cn63xx; 2789215976Sjmallett struct cvmx_uahcx_ohci0_insnreg06_s cn63xxp1; 2790232812Sjmallett struct cvmx_uahcx_ohci0_insnreg06_s cn66xx; 2791232812Sjmallett struct cvmx_uahcx_ohci0_insnreg06_s cn68xx; 2792232812Sjmallett struct cvmx_uahcx_ohci0_insnreg06_s cn68xxp1; 2793232812Sjmallett struct cvmx_uahcx_ohci0_insnreg06_s cnf71xx; 2794215976Sjmallett}; 2795215976Sjmalletttypedef union cvmx_uahcx_ohci0_insnreg06 cvmx_uahcx_ohci0_insnreg06_t; 2796215976Sjmallett 2797215976Sjmallett/** 2798215976Sjmallett * cvmx_uahc#_ohci0_insnreg07 2799215976Sjmallett * 2800215976Sjmallett * OHCI0_INSNREG07 = OHCI AHB Error Address Register (Synopsys Speicific) 2801215976Sjmallett * 2802215976Sjmallett * This register contains AHB Error Status. 2803215976Sjmallett */ 2804232812Sjmallettunion cvmx_uahcx_ohci0_insnreg07 { 2805215976Sjmallett uint32_t u32; 2806232812Sjmallett struct cvmx_uahcx_ohci0_insnreg07_s { 2807232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2808215976Sjmallett uint32_t err_addr : 32; /**< AHB Master Error Address. AHB address of the control phase at which the AHB error occurred */ 2809215976Sjmallett#else 2810215976Sjmallett uint32_t err_addr : 32; 2811215976Sjmallett#endif 2812215976Sjmallett } s; 2813232812Sjmallett struct cvmx_uahcx_ohci0_insnreg07_s cn61xx; 2814215976Sjmallett struct cvmx_uahcx_ohci0_insnreg07_s cn63xx; 2815215976Sjmallett struct cvmx_uahcx_ohci0_insnreg07_s cn63xxp1; 2816232812Sjmallett struct cvmx_uahcx_ohci0_insnreg07_s cn66xx; 2817232812Sjmallett struct cvmx_uahcx_ohci0_insnreg07_s cn68xx; 2818232812Sjmallett struct cvmx_uahcx_ohci0_insnreg07_s cn68xxp1; 2819232812Sjmallett struct cvmx_uahcx_ohci0_insnreg07_s cnf71xx; 2820215976Sjmallett}; 2821215976Sjmalletttypedef union cvmx_uahcx_ohci0_insnreg07 cvmx_uahcx_ohci0_insnreg07_t; 2822215976Sjmallett 2823215976Sjmallett#endif 2824