1210284Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights 3215990Sjmallett * reserved. 4210284Sjmallett * 5210284Sjmallett * 6215990Sjmallett * Redistribution and use in source and binary forms, with or without 7215990Sjmallett * modification, are permitted provided that the following conditions are 8215990Sjmallett * met: 9210284Sjmallett * 10215990Sjmallett * * Redistributions of source code must retain the above copyright 11215990Sjmallett * notice, this list of conditions and the following disclaimer. 12210284Sjmallett * 13215990Sjmallett * * Redistributions in binary form must reproduce the above 14215990Sjmallett * copyright notice, this list of conditions and the following 15215990Sjmallett * disclaimer in the documentation and/or other materials provided 16215990Sjmallett * with the distribution. 17215990Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215990Sjmallett * its contributors may be used to endorse or promote products 20215990Sjmallett * derived from this software without specific prior written 21215990Sjmallett * permission. 22215990Sjmallett 23215990Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215990Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215990Sjmallett * regulations, and may be subject to export or import regulations in other 26215990Sjmallett * countries. 27215990Sjmallett 28215990Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215990Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215990Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215990Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215990Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215990Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215990Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215990Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215990Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38210284Sjmallett ***********************license end**************************************/ 39210284Sjmallett 40210284Sjmallett 41210284Sjmallett 42210284Sjmallett 43210284Sjmallett 44215990Sjmallett 45210284Sjmallett/** 46210284Sjmallett * @file 47210284Sjmallett * 48210284Sjmallett * Interface to the Trace buffer hardware. 49210284Sjmallett * 50210284Sjmallett * <hr>$Revision: 30644 $<hr> 51210284Sjmallett */ 52215990Sjmallett#ifdef CVMX_BUILD_FOR_LINUX_KERNEL 53215990Sjmallett#include <linux/module.h> 54215990Sjmallett#include <asm/octeon/cvmx.h> 55215990Sjmallett#include <asm/octeon/cvmx-tra.h> 56232812Sjmallett#include <asm/octeon/cvmx-l2c.h> 57215990Sjmallett#else 58210284Sjmallett#include "cvmx.h" 59210284Sjmallett#include "cvmx-tra.h" 60232812Sjmallett#include "cvmx-l2c.h" 61215990Sjmallett#endif 62210284Sjmallett 63210284Sjmallettstatic const char *TYPE_ARRAY[] = { 64210284Sjmallett "DWB - Don't write back", 65210284Sjmallett "PL2 - Prefetch into L2", 66210284Sjmallett "PSL1 - Dcache fill, skip L2", 67210284Sjmallett "LDD - Dcache fill", 68210284Sjmallett "LDI - Icache/IO fill", 69210284Sjmallett "LDT - Icache/IO fill, skip L2", 70210284Sjmallett "STF - Store full", 71210284Sjmallett "STC - Store conditional", 72210284Sjmallett "STP - Store partial", 73210284Sjmallett "STT - Store full, skip L2", 74210284Sjmallett "IOBLD8 - IOB 8bit load", 75210284Sjmallett "IOBLD16 - IOB 16bit load", 76210284Sjmallett "IOBLD32 - IOB 32bit load", 77210284Sjmallett "IOBLD64 - IOB 64bit load", 78210284Sjmallett "IOBST - IOB store", 79210284Sjmallett "IOBDMA - Async IOB", 80210284Sjmallett "SAA - Store atomic add", 81210284Sjmallett "RSVD17", 82210284Sjmallett "RSVD18", 83210284Sjmallett "RSVD19", 84210284Sjmallett "RSVD20", 85210284Sjmallett "RSVD21", 86210284Sjmallett "RSVD22", 87210284Sjmallett "RSVD23", 88210284Sjmallett "RSVD24", 89210284Sjmallett "RSVD25", 90210284Sjmallett "RSVD26", 91210284Sjmallett "RSVD27", 92210284Sjmallett "RSVD28", 93210284Sjmallett "RSVD29", 94210284Sjmallett "RSVD30", 95210284Sjmallett "RSVD31" 96210284Sjmallett}; 97210284Sjmallett 98215990Sjmallettstatic const char *TYPE_ARRAY2[] = { 99215990Sjmallett "NOP - None", 100215990Sjmallett "LDT - Icache/IO fill, skip L2", 101215990Sjmallett "LDI - Icache/IO fill", 102215990Sjmallett "PL2 - Prefetch into L2", 103215990Sjmallett "RPL2 - Mark for replacement in L2", 104215990Sjmallett "DWB - Don't write back", 105215990Sjmallett "RSVD6", 106215990Sjmallett "RSVD7", 107215990Sjmallett "LDD - Dcache fill", 108215990Sjmallett "PSL1 - Prefetch L1, skip L2", 109215990Sjmallett "RSVD10", 110215990Sjmallett "RSVD11", 111215990Sjmallett "RSVD12", 112215990Sjmallett "RSVD13", 113215990Sjmallett "RSVD14", 114215990Sjmallett "IOBDMA - Async IOB", 115215990Sjmallett "STF - Store full", 116215990Sjmallett "STT - Store full, skip L2", 117215990Sjmallett "STP - Store partial", 118215990Sjmallett "STC - Store conditional", 119215990Sjmallett "STFIL1 - Store full, invalidate L1", 120215990Sjmallett "STTIL1 - Store full, skip L2, invalidate L1", 121215990Sjmallett "FAS32 - Atomic 32bit swap", 122215990Sjmallett "FAS64 - Atomic 64bit swap", 123215990Sjmallett "WBIL2i - Writeback, invalidate, by index/way", 124215990Sjmallett "LTGL2i - Read tag@index/way", 125215990Sjmallett "STGL2i - Write tag@index/way", 126215990Sjmallett "RSVD27", 127215990Sjmallett "INVL2 - Invalidate, by address", 128215990Sjmallett "WBIL2 - Writeback, invalidate, by address", 129215990Sjmallett "WBL2 - Writeback, by address", 130215990Sjmallett "LCKL2 - Allocate, lock, by address", 131215990Sjmallett "IOBLD8 - IOB 8bit load", 132215990Sjmallett "IOBLD16 - IOB 16bit load", 133215990Sjmallett "IOBLD32 - IOB 32bit load", 134215990Sjmallett "IOBLD64 - IOB 64bit load", 135215990Sjmallett "IOBST8 - IOB 8bit store", 136215990Sjmallett "IOBST16 - IOB 16bit store", 137215990Sjmallett "IOBST32 - IOB 32bit store", 138215990Sjmallett "IOBST64 - IOB 64bit store", 139215990Sjmallett "SET8 - 8bit Atomic swap with 1's", 140215990Sjmallett "SET16 - 16bit Atomic swap with 1's", 141215990Sjmallett "SET32 - 32bit Atomic swap with 1's", 142215990Sjmallett "SET64 - 64bit Atomic swap with 1's", 143215990Sjmallett "CLR8 - 8bit Atomic swap with 0's", 144215990Sjmallett "CLR16 - 16bit Atomic swap with 0's", 145215990Sjmallett "CLR32 - 32bit Atomic swap with 0's", 146215990Sjmallett "CLR64 - 64bit Atomic swap with 0's", 147215990Sjmallett "INCR8 - 8bit Atomic fetch & add by 1", 148215990Sjmallett "INCR16 - 16bit Atomic fetch & add by 1", 149215990Sjmallett "INCR32 - 32bit Atomic fetch & add by 1", 150215990Sjmallett "INCR64 - 64bit Atomic fetch & add by 1", 151215990Sjmallett "DECR8 - 8bit Atomic fetch & add by -1", 152215990Sjmallett "DECR16 - 16bit Atomic fetch & add by -1", 153215990Sjmallett "DECR32 - 32bit Atomic fetch & add by -1", 154215990Sjmallett "DECR64 - 64bit Atomic fetch & add by -1", 155215990Sjmallett "RSVD56", 156215990Sjmallett "RSVD57", 157215990Sjmallett "FAA32 - 32bit Atomic fetch and add", 158215990Sjmallett "FAA64 - 64bit Atomic fetch and add", 159215990Sjmallett "RSVD60", 160215990Sjmallett "RSVD61", 161215990Sjmallett "SAA32 - 32bit Atomic add", 162215990Sjmallett "SAA64 - 64bit Atomic add" 163215990Sjmallett}; 164215990Sjmallett 165210284Sjmallettstatic const char *SOURCE_ARRAY[] = { 166210284Sjmallett "PP0", 167210284Sjmallett "PP1", 168210284Sjmallett "PP2", 169210284Sjmallett "PP3", 170210284Sjmallett "PP4", 171210284Sjmallett "PP5", 172210284Sjmallett "PP6", 173210284Sjmallett "PP7", 174210284Sjmallett "PP8", 175210284Sjmallett "PP9", 176210284Sjmallett "PP10", 177210284Sjmallett "PP11", 178210284Sjmallett "PP12", 179210284Sjmallett "PP13", 180210284Sjmallett "PP14", 181210284Sjmallett "PP15", 182210284Sjmallett "PIP/IPD", 183210284Sjmallett "PKO-R", 184210284Sjmallett "FPA/TIM/DFA/PCI/ZIP/POW/PKO-W", 185210284Sjmallett "DWB", 186210284Sjmallett "RSVD20", 187210284Sjmallett "RSVD21", 188210284Sjmallett "RSVD22", 189210284Sjmallett "RSVD23", 190210284Sjmallett "RSVD24", 191210284Sjmallett "RSVD25", 192210284Sjmallett "RSVD26", 193210284Sjmallett "RSVD27", 194210284Sjmallett "RSVD28", 195210284Sjmallett "RSVD29", 196210284Sjmallett "RSVD30", 197232812Sjmallett "RSVD31", 198232812Sjmallett "PP16", 199232812Sjmallett "PP17", 200232812Sjmallett "PP18", 201232812Sjmallett "PP19", 202232812Sjmallett "PP20", 203232812Sjmallett "PP21", 204232812Sjmallett "PP22", 205232812Sjmallett "PP23", 206232812Sjmallett "PP24", 207232812Sjmallett "PP25", 208232812Sjmallett "PP26", 209232812Sjmallett "PP27", 210232812Sjmallett "PP28", 211232812Sjmallett "PP29", 212232812Sjmallett "PP30", 213232812Sjmallett "PP31" 214210284Sjmallett}; 215210284Sjmallett 216210284Sjmallettstatic const char *DEST_ARRAY[] = { 217210284Sjmallett "CIU/GPIO", 218210284Sjmallett "RSVD1", 219210284Sjmallett "RSVD2", 220215990Sjmallett "PCI/PCIe/SLI", 221210284Sjmallett "KEY", 222210284Sjmallett "FPA", 223210284Sjmallett "DFA", 224210284Sjmallett "ZIP", 225210284Sjmallett "RNG", 226210284Sjmallett "IPD", 227210284Sjmallett "PKO", 228210284Sjmallett "RSVD11", 229210284Sjmallett "POW", 230215990Sjmallett "USB0", 231215990Sjmallett "RAD", 232210284Sjmallett "RSVD15", 233210284Sjmallett "RSVD16", 234210284Sjmallett "RSVD17", 235210284Sjmallett "RSVD18", 236210284Sjmallett "RSVD19", 237210284Sjmallett "RSVD20", 238210284Sjmallett "RSVD21", 239210284Sjmallett "RSVD22", 240210284Sjmallett "RSVD23", 241210284Sjmallett "RSVD24", 242210284Sjmallett "RSVD25", 243210284Sjmallett "RSVD26", 244215990Sjmallett "DPI", 245210284Sjmallett "RSVD28", 246210284Sjmallett "RSVD29", 247215990Sjmallett "FAU", 248210284Sjmallett "RSVD31" 249210284Sjmallett}; 250210284Sjmallett 251232812Sjmallettint _cvmx_tra_unit = 0; 252232812Sjmallett 253215990Sjmallett#define CVMX_TRA_SOURCE_MASK (OCTEON_IS_MODEL(OCTEON_CN63XX) ? 0xf00ff : 0xfffff) 254215990Sjmallett#define CVMX_TRA_DESTINATION_MASK 0xfffffffful 255215990Sjmallett 256210284Sjmallett/** 257215990Sjmallett * @INTERNAL 258215990Sjmallett * Setup the trace buffer filter command mask. The bit position of filter commands 259215990Sjmallett * are different for each Octeon model. 260215990Sjmallett * 261215990Sjmallett * @param filter Which event to log 262215990Sjmallett * @return Bitmask of filter command based on the event. 263215990Sjmallett */ 264215990Sjmallettstatic uint64_t __cvmx_tra_set_filter_cmd_mask(cvmx_tra_filt_t filter) 265215990Sjmallett{ 266215990Sjmallett cvmx_tra_filt_cmd_t filter_command; 267215990Sjmallett 268215990Sjmallett if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)) 269215990Sjmallett { 270215990Sjmallett /* Bit positions of filter commands are different, map it accordingly */ 271215990Sjmallett uint64_t cmd = 0; 272215990Sjmallett if ((filter & CVMX_TRA_FILT_ALL) == -1ull) 273215990Sjmallett { 274215990Sjmallett if (OCTEON_IS_MODEL(OCTEON_CN5XXX)) 275215990Sjmallett cmd = 0x1ffff; 276215990Sjmallett else 277215990Sjmallett cmd = 0xffff; 278215990Sjmallett } 279215990Sjmallett if (filter & CVMX_TRA_FILT_DWB) 280215990Sjmallett cmd |= 1ull<<0; 281215990Sjmallett if (filter & CVMX_TRA_FILT_PL2) 282215990Sjmallett cmd |= 1ull<<1; 283215990Sjmallett if (filter & CVMX_TRA_FILT_PSL1) 284215990Sjmallett cmd |= 1ull<<2; 285215990Sjmallett if (filter & CVMX_TRA_FILT_LDD) 286215990Sjmallett cmd |= 1ull<<3; 287215990Sjmallett if (filter & CVMX_TRA_FILT_LDI) 288215990Sjmallett cmd |= 1ull<<4; 289215990Sjmallett if (filter & CVMX_TRA_FILT_LDT) 290215990Sjmallett cmd |= 1ull<<5; 291215990Sjmallett if (filter & CVMX_TRA_FILT_STF) 292215990Sjmallett cmd |= 1ull<<6; 293215990Sjmallett if (filter & CVMX_TRA_FILT_STC) 294215990Sjmallett cmd |= 1ull<<7; 295215990Sjmallett if (filter & CVMX_TRA_FILT_STP) 296215990Sjmallett cmd |= 1ull<<8; 297215990Sjmallett if (filter & CVMX_TRA_FILT_STT) 298215990Sjmallett cmd |= 1ull<<9; 299215990Sjmallett if (filter & CVMX_TRA_FILT_IOBLD8) 300215990Sjmallett cmd |= 1ull<<10; 301215990Sjmallett if (filter & CVMX_TRA_FILT_IOBLD16) 302215990Sjmallett cmd |= 1ull<<11; 303215990Sjmallett if (filter & CVMX_TRA_FILT_IOBLD32) 304215990Sjmallett cmd |= 1ull<<12; 305215990Sjmallett if (filter & CVMX_TRA_FILT_IOBLD64) 306215990Sjmallett cmd |= 1ull<<13; 307215990Sjmallett if (filter & CVMX_TRA_FILT_IOBST) 308215990Sjmallett cmd |= 1ull<<14; 309215990Sjmallett if (filter & CVMX_TRA_FILT_IOBDMA) 310215990Sjmallett cmd |= 1ull<<15; 311215990Sjmallett if (OCTEON_IS_MODEL(OCTEON_CN5XXX) && (filter & CVMX_TRA_FILT_SAA)) 312215990Sjmallett cmd |= 1ull<<16; 313215990Sjmallett 314215990Sjmallett filter_command.u64 = cmd; 315215990Sjmallett } 316215990Sjmallett else 317215990Sjmallett { 318215990Sjmallett if ((filter & CVMX_TRA_FILT_ALL) == -1ull) 319215990Sjmallett filter_command.u64 = CVMX_TRA_FILT_ALL; 320215990Sjmallett else 321215990Sjmallett filter_command.u64 = filter; 322215990Sjmallett 323215990Sjmallett filter_command.cn63xx.reserved_60_61 = 0; 324215990Sjmallett filter_command.cn63xx.reserved_56_57 = 0; 325232812Sjmallett filter_command.cn63xx.reserved_27_27 = 0; 326215990Sjmallett filter_command.cn63xx.reserved_10_14 = 0; 327215990Sjmallett filter_command.cn63xx.reserved_6_7 = 0; 328215990Sjmallett } 329215990Sjmallett return filter_command.u64; 330215990Sjmallett} 331215990Sjmallett 332215990Sjmallett 333215990Sjmallett/** 334210284Sjmallett * Setup the TRA buffer for use 335210284Sjmallett * 336210284Sjmallett * @param control TRA control setup 337210284Sjmallett * @param filter Which events to log 338210284Sjmallett * @param source_filter 339210284Sjmallett * Source match 340210284Sjmallett * @param dest_filter 341210284Sjmallett * Destination match 342210284Sjmallett * @param address Address compare 343210284Sjmallett * @param address_mask 344210284Sjmallett * Address mask 345210284Sjmallett */ 346215990Sjmallettvoid cvmx_tra_setup(cvmx_tra_ctl_t control, cvmx_tra_filt_t filter, 347215990Sjmallett cvmx_tra_sid_t source_filter, cvmx_tra_did_t dest_filter, 348210284Sjmallett uint64_t address, uint64_t address_mask) 349210284Sjmallett{ 350215990Sjmallett cvmx_tra_filt_cmd_t filt_cmd; 351215990Sjmallett cvmx_tra_filt_sid_t filt_sid; 352215990Sjmallett cvmx_tra_filt_did_t filt_did; 353232812Sjmallett int tad; 354215990Sjmallett 355215990Sjmallett filt_cmd.u64 = __cvmx_tra_set_filter_cmd_mask(filter); 356215990Sjmallett filt_sid.u64 = source_filter & CVMX_TRA_SOURCE_MASK; 357215990Sjmallett filt_did.u64 = dest_filter & CVMX_TRA_DESTINATION_MASK; 358215990Sjmallett 359232812Sjmallett /* Address filtering does not work when IOBDMA filter command is enabled 360232812Sjmallett because of some caveats. Disable the IOBDMA filter command. */ 361232812Sjmallett if ((OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) 362232812Sjmallett && ((filt_cmd.u64 & CVMX_TRA_FILT_IOBDMA) == CVMX_TRA_FILT_IOBDMA) 363232812Sjmallett && address_mask != 0) 364232812Sjmallett { 365232812Sjmallett cvmx_dprintf("The address-based filtering does not work with IOBDMAs, disabling the filter command.\n"); 366232812Sjmallett filt_cmd.u64 &= ~(CVMX_TRA_FILT_IOBDMA); 367232812Sjmallett } 368232812Sjmallett 369232812Sjmallett /* In OcteonII pass2, the mode bit is added to enable reading the trace 370232812Sjmallett buffer data from different registers for lower and upper 64-bit value. 371232812Sjmallett This bit is reserved in other Octeon models. */ 372232812Sjmallett control.s.rdat_md = 1; 373232812Sjmallett 374232812Sjmallett for (tad = 0; tad < CVMX_L2C_TADS; tad++) 375232812Sjmallett { 376232812Sjmallett cvmx_write_csr(CVMX_TRAX_CTL(tad), control.u64); 377232812Sjmallett cvmx_write_csr(CVMX_TRAX_FILT_CMD(tad), filt_cmd.u64); 378232812Sjmallett cvmx_write_csr(CVMX_TRAX_FILT_SID(tad), filt_sid.u64); 379232812Sjmallett cvmx_write_csr(CVMX_TRAX_FILT_DID(tad), filt_did.u64); 380232812Sjmallett cvmx_write_csr(CVMX_TRAX_FILT_ADR_ADR(tad), address); 381232812Sjmallett cvmx_write_csr(CVMX_TRAX_FILT_ADR_MSK(tad), address_mask); 382232812Sjmallett } 383210284Sjmallett} 384215990Sjmallett#ifdef CVMX_BUILD_FOR_LINUX_KERNEL 385215990SjmallettEXPORT_SYMBOL(cvmx_tra_setup); 386215990Sjmallett#endif 387210284Sjmallett 388232812Sjmallett/** 389232812Sjmallett * Setup each TRA buffer for use 390232812Sjmallett * 391232812Sjmallett * @param tra Which TRA buffer to use (0-3) 392232812Sjmallett * @param control TRA control setup 393232812Sjmallett * @param filter Which events to log 394232812Sjmallett * @param source_filter 395232812Sjmallett * Source match 396232812Sjmallett * @param dest_filter 397232812Sjmallett * Destination match 398232812Sjmallett * @param address Address compare 399232812Sjmallett * @param address_mask 400232812Sjmallett * Address mask 401232812Sjmallett */ 402232812Sjmallettvoid cvmx_tra_setup_v2(int tra, cvmx_tra_ctl_t control, cvmx_tra_filt_t filter, 403232812Sjmallett cvmx_tra_sid_t source_filter, cvmx_tra_did_t dest_filter, 404232812Sjmallett uint64_t address, uint64_t address_mask) 405232812Sjmallett{ 406232812Sjmallett cvmx_tra_filt_cmd_t filt_cmd; 407232812Sjmallett cvmx_tra_filt_sid_t filt_sid; 408232812Sjmallett cvmx_tra_filt_did_t filt_did; 409210284Sjmallett 410232812Sjmallett if ((tra + 1) > CVMX_L2C_TADS) 411232812Sjmallett { 412232812Sjmallett cvmx_dprintf("cvmx_tra_setup_per_tra: Invalid tra(%d), max allowed (%d)\n", tra, CVMX_L2C_TADS - 1); 413232812Sjmallett tra = 0; 414232812Sjmallett } 415232812Sjmallett 416232812Sjmallett filt_cmd.u64 = __cvmx_tra_set_filter_cmd_mask(filter); 417232812Sjmallett filt_sid.u64 = source_filter & CVMX_TRA_SOURCE_MASK; 418232812Sjmallett filt_did.u64 = dest_filter & CVMX_TRA_DESTINATION_MASK; 419232812Sjmallett 420232812Sjmallett /* Address filtering does not work when IOBDMA filter command is enabled 421232812Sjmallett because of some caveats. Disable the IOBDMA filter command. */ 422232812Sjmallett if ((OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) 423232812Sjmallett && ((filt_cmd.u64 & CVMX_TRA_FILT_IOBDMA) == CVMX_TRA_FILT_IOBDMA) 424232812Sjmallett && address_mask != 0) 425232812Sjmallett { 426232812Sjmallett cvmx_dprintf("The address-based filtering does not work with IOBDMAs, disabling the filter command.\n"); 427232812Sjmallett filt_cmd.u64 &= ~(CVMX_TRA_FILT_IOBDMA); 428232812Sjmallett } 429232812Sjmallett 430232812Sjmallett /* In OcteonII pass2, the mode bit is added to enable reading the trace 431232812Sjmallett buffer data from different registers for lower and upper 64-bit value. 432232812Sjmallett This bit is reserved in other Octeon models. */ 433232812Sjmallett control.s.rdat_md = 1; 434232812Sjmallett 435232812Sjmallett cvmx_write_csr(CVMX_TRAX_CTL(tra), control.u64); 436232812Sjmallett cvmx_write_csr(CVMX_TRAX_FILT_CMD(tra), filt_cmd.u64); 437232812Sjmallett cvmx_write_csr(CVMX_TRAX_FILT_SID(tra), filt_sid.u64); 438232812Sjmallett cvmx_write_csr(CVMX_TRAX_FILT_DID(tra), filt_did.u64); 439232812Sjmallett cvmx_write_csr(CVMX_TRAX_FILT_ADR_ADR(tra), address); 440232812Sjmallett cvmx_write_csr(CVMX_TRAX_FILT_ADR_MSK(tra), address_mask); 441232812Sjmallett} 442232812Sjmallett#ifdef CVMX_BUILD_FOR_LINUX_KERNEL 443232812SjmallettEXPORT_SYMBOL(cvmx_tra_setup_v2); 444232812Sjmallett#endif 445232812Sjmallett 446210284Sjmallett/** 447210284Sjmallett * Setup a TRA trigger. How the triggers are used should be 448210284Sjmallett * setup using cvmx_tra_setup. 449210284Sjmallett * 450210284Sjmallett * @param trigger Trigger to setup (0 or 1) 451210284Sjmallett * @param filter Which types of events to trigger on 452210284Sjmallett * @param source_filter 453210284Sjmallett * Source trigger match 454210284Sjmallett * @param dest_filter 455210284Sjmallett * Destination trigger match 456210284Sjmallett * @param address Trigger address compare 457210284Sjmallett * @param address_mask 458210284Sjmallett * Trigger address mask 459210284Sjmallett */ 460215990Sjmallettvoid cvmx_tra_trig_setup(uint64_t trigger, cvmx_tra_filt_t filter, 461215990Sjmallett cvmx_tra_sid_t source_filter, cvmx_tra_did_t dest_filter, 462210284Sjmallett uint64_t address, uint64_t address_mask) 463210284Sjmallett{ 464215990Sjmallett cvmx_tra_filt_cmd_t tra_filt_cmd; 465215990Sjmallett cvmx_tra_filt_sid_t tra_filt_sid; 466215990Sjmallett cvmx_tra_filt_did_t tra_filt_did; 467232812Sjmallett int tad; 468215990Sjmallett 469215990Sjmallett tra_filt_cmd.u64 = __cvmx_tra_set_filter_cmd_mask(filter); 470215990Sjmallett tra_filt_sid.u64 = source_filter & CVMX_TRA_SOURCE_MASK; 471215990Sjmallett tra_filt_did.u64 = dest_filter & CVMX_TRA_DESTINATION_MASK; 472215990Sjmallett 473232812Sjmallett /* Address filtering does not work when IOBDMA filter command is enabled 474232812Sjmallett because of some caveats. Disable the IOBDMA filter command. */ 475232812Sjmallett if ((OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) 476232812Sjmallett && ((tra_filt_cmd.u64 & CVMX_TRA_FILT_IOBDMA) == CVMX_TRA_FILT_IOBDMA) 477232812Sjmallett && address_mask != 0) 478232812Sjmallett { 479232812Sjmallett cvmx_dprintf("The address-based filtering does not work with IOBDMAs, disabling the filter command.\n"); 480232812Sjmallett tra_filt_cmd.u64 &= ~(CVMX_TRA_FILT_IOBDMA); 481232812Sjmallett } 482232812Sjmallett 483232812Sjmallett for (tad = 0; tad < CVMX_L2C_TADS; tad++) 484232812Sjmallett { 485232812Sjmallett cvmx_write_csr(CVMX_TRAX_TRIG0_CMD(tad) + trigger * 64, tra_filt_cmd.u64); 486232812Sjmallett cvmx_write_csr(CVMX_TRAX_TRIG0_SID(tad) + trigger * 64, tra_filt_sid.u64); 487232812Sjmallett cvmx_write_csr(CVMX_TRAX_TRIG0_DID(tad) + trigger * 64, tra_filt_did.u64); 488232812Sjmallett cvmx_write_csr(CVMX_TRAX_TRIG0_ADR_ADR(tad) + trigger * 64, address); 489232812Sjmallett cvmx_write_csr(CVMX_TRAX_TRIG0_ADR_MSK(tad) + trigger * 64, address_mask); 490232812Sjmallett } 491210284Sjmallett} 492215990Sjmallett#ifdef CVMX_BUILD_FOR_LINUX_KERNEL 493215990SjmallettEXPORT_SYMBOL(cvmx_tra_trig_setup); 494215990Sjmallett#endif 495210284Sjmallett 496232812Sjmallett/** 497232812Sjmallett * Setup each TRA trigger. How the triggers are used should be 498232812Sjmallett * setup using cvmx_tra_setup. 499232812Sjmallett * 500232812Sjmallett * @param tra Which TRA buffer to use (0-3) 501232812Sjmallett * @param trigger Trigger to setup (0 or 1) 502232812Sjmallett * @param filter Which types of events to trigger on 503232812Sjmallett * @param source_filter 504232812Sjmallett * Source trigger match 505232812Sjmallett * @param dest_filter 506232812Sjmallett * Destination trigger match 507232812Sjmallett * @param address Trigger address compare 508232812Sjmallett * @param address_mask 509232812Sjmallett * Trigger address mask 510232812Sjmallett */ 511232812Sjmallettvoid cvmx_tra_trig_setup_v2(int tra, uint64_t trigger, cvmx_tra_filt_t filter, 512232812Sjmallett cvmx_tra_sid_t source_filter, cvmx_tra_did_t dest_filter, 513232812Sjmallett uint64_t address, uint64_t address_mask) 514232812Sjmallett{ 515232812Sjmallett cvmx_tra_filt_cmd_t tra_filt_cmd; 516232812Sjmallett cvmx_tra_filt_sid_t tra_filt_sid; 517232812Sjmallett cvmx_tra_filt_did_t tra_filt_did; 518210284Sjmallett 519232812Sjmallett tra_filt_cmd.u64 = __cvmx_tra_set_filter_cmd_mask(filter); 520232812Sjmallett tra_filt_sid.u64 = source_filter & CVMX_TRA_SOURCE_MASK; 521232812Sjmallett tra_filt_did.u64 = dest_filter & CVMX_TRA_DESTINATION_MASK; 522232812Sjmallett 523232812Sjmallett /* Address filtering does not work when IOBDMA filter command is enabled 524232812Sjmallett because of some caveats. Disable the IOBDMA filter command. */ 525232812Sjmallett if ((OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF7XXX)) 526232812Sjmallett && ((tra_filt_cmd.u64 & CVMX_TRA_FILT_IOBDMA) == CVMX_TRA_FILT_IOBDMA) 527232812Sjmallett && address_mask != 0) 528232812Sjmallett { 529232812Sjmallett cvmx_dprintf("The address-based filtering does not work with IOBDMAs, disabling the filter command.\n"); 530232812Sjmallett tra_filt_cmd.u64 &= ~(CVMX_TRA_FILT_IOBDMA); 531232812Sjmallett } 532232812Sjmallett 533232812Sjmallett cvmx_write_csr(CVMX_TRAX_TRIG0_CMD(tra) + trigger * 64, tra_filt_cmd.u64); 534232812Sjmallett cvmx_write_csr(CVMX_TRAX_TRIG0_SID(tra) + trigger * 64, tra_filt_sid.u64); 535232812Sjmallett cvmx_write_csr(CVMX_TRAX_TRIG0_DID(tra) + trigger * 64, tra_filt_did.u64); 536232812Sjmallett cvmx_write_csr(CVMX_TRAX_TRIG0_ADR_ADR(tra) + trigger * 64, address); 537232812Sjmallett cvmx_write_csr(CVMX_TRAX_TRIG0_ADR_MSK(tra) + trigger * 64, address_mask); 538232812Sjmallett} 539232812Sjmallett#ifdef CVMX_BUILD_FOR_LINUX_KERNEL 540232812SjmallettEXPORT_SYMBOL(cvmx_tra_trig_setup_v2); 541232812Sjmallett#endif 542232812Sjmallett 543210284Sjmallett/** 544210284Sjmallett * Read an entry from the TRA buffer 545210284Sjmallett * 546210284Sjmallett * @return Value return. High bit will be zero if there wasn't any data 547210284Sjmallett */ 548210284Sjmallettcvmx_tra_data_t cvmx_tra_read(void) 549210284Sjmallett{ 550215990Sjmallett uint64_t address = CVMX_TRA_READ_DAT; 551210284Sjmallett cvmx_tra_data_t result; 552215990Sjmallett 553232812Sjmallett /* The trace buffer format is wider than 64-bits in OcteonII model, 554215990Sjmallett read the register again to get the second part of the data. */ 555232812Sjmallett if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) 556215990Sjmallett { 557215990Sjmallett /* These reads need to be as close as possible to each other */ 558215990Sjmallett result.u128.data = cvmx_read_csr(address); 559215990Sjmallett result.u128.datahi = cvmx_read_csr(address); 560215990Sjmallett } 561232812Sjmallett else if (!OCTEON_IS_MODEL(OCTEON_CN3XXX) && !OCTEON_IS_MODEL(OCTEON_CN5XXX)) 562232812Sjmallett { 563232812Sjmallett /* OcteonII pass2 uses different trace buffer data register for reading 564232812Sjmallett lower and upper 64-bit values */ 565232812Sjmallett result.u128.data = cvmx_read_csr(address); 566232812Sjmallett result.u128.datahi = cvmx_read_csr(CVMX_TRA_READ_DAT_HI); 567232812Sjmallett } 568215990Sjmallett else 569215990Sjmallett { 570215990Sjmallett result.u128.data = cvmx_read_csr(address); 571215990Sjmallett result.u128.datahi = 0; 572215990Sjmallett } 573215990Sjmallett 574210284Sjmallett return result; 575210284Sjmallett} 576210284Sjmallett 577210284Sjmallett/** 578232812Sjmallett * Read an entry from the TRA buffer from a given TRA unit. 579232812Sjmallett * 580232812Sjmallett * @param tra_unit Trace buffer unit to read 581232812Sjmallett * 582232812Sjmallett * @return Value return. High bit will be zero if there wasn't any data 583232812Sjmallett */ 584232812Sjmallettcvmx_tra_data_t cvmx_tra_read_v2(int tra_unit) 585232812Sjmallett{ 586232812Sjmallett cvmx_tra_data_t result; 587232812Sjmallett 588232812Sjmallett result.u128.data = cvmx_read_csr(CVMX_TRAX_READ_DAT(tra_unit)); 589232812Sjmallett result.u128.datahi = cvmx_read_csr(CVMX_TRAX_READ_DAT_HI(tra_unit)); 590232812Sjmallett 591232812Sjmallett return result; 592232812Sjmallett} 593232812Sjmallett 594232812Sjmallett/** 595210284Sjmallett * Decode a TRA entry into human readable output 596210284Sjmallett * 597210284Sjmallett * @param tra_ctl Trace control setup 598210284Sjmallett * @param data Data to decode 599210284Sjmallett */ 600210284Sjmallettvoid cvmx_tra_decode_text(cvmx_tra_ctl_t tra_ctl, cvmx_tra_data_t data) 601210284Sjmallett{ 602215990Sjmallett if (OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)) 603210284Sjmallett { 604215990Sjmallett /* The type is a five bit field for some entries and 4 for other. The four 605215990Sjmallett bit entries can be mis-typed if the top is set */ 606215990Sjmallett int type = data.cmn.type; 607215990Sjmallett 608215990Sjmallett if (type >= 0x1a) 609215990Sjmallett type &= 0xf; 610215990Sjmallett 611215990Sjmallett switch (type) 612215990Sjmallett { 613215990Sjmallett case 0: /* DWB */ 614215990Sjmallett case 1: /* PL2 */ 615215990Sjmallett case 2: /* PSL1 */ 616215990Sjmallett case 3: /* LDD */ 617215990Sjmallett case 4: /* LDI */ 618215990Sjmallett case 5: /* LDT */ 619215990Sjmallett cvmx_dprintf("0x%016llx %c%+10d %s %s 0x%016llx\n", 620215990Sjmallett (unsigned long long)data.u128.data, 621215990Sjmallett (data.cmn.discontinuity) ? 'D' : ' ', 622215990Sjmallett data.cmn.timestamp << (tra_ctl.s.time_grn*3), 623215990Sjmallett TYPE_ARRAY[type], 624215990Sjmallett SOURCE_ARRAY[data.cmn.source], 625215990Sjmallett (unsigned long long)data.cmn.address); 626215990Sjmallett break; 627215990Sjmallett case 6: /* STF */ 628215990Sjmallett case 7: /* STC */ 629215990Sjmallett case 8: /* STP */ 630215990Sjmallett case 9: /* STT */ 631215990Sjmallett case 16: /* SAA */ 632215990Sjmallett cvmx_dprintf("0x%016llx %c%+10d %s %s mask=0x%02x 0x%016llx\n", 633215990Sjmallett (unsigned long long)data.u128.data, 634210284Sjmallett (data.cmn.discontinuity) ? 'D' : ' ', 635210284Sjmallett data.cmn.timestamp << (tra_ctl.s.time_grn*3), 636210284Sjmallett TYPE_ARRAY[type], 637210284Sjmallett SOURCE_ARRAY[data.store.source], 638210284Sjmallett (unsigned int)data.store.mask, 639210284Sjmallett (unsigned long long)data.store.address << 3); 640215990Sjmallett break; 641215990Sjmallett case 10: /* IOBLD8 */ 642215990Sjmallett case 11: /* IOBLD16 */ 643215990Sjmallett case 12: /* IOBLD32 */ 644215990Sjmallett case 13: /* IOBLD64 */ 645215990Sjmallett case 14: /* IOBST */ 646215990Sjmallett cvmx_dprintf("0x%016llx %c%+10d %s %s->%s subdid=0x%x 0x%016llx\n", 647215990Sjmallett (unsigned long long)data.u128.data, 648210284Sjmallett (data.cmn.discontinuity) ? 'D' : ' ', 649210284Sjmallett data.cmn.timestamp << (tra_ctl.s.time_grn*3), 650210284Sjmallett TYPE_ARRAY[type], 651210284Sjmallett SOURCE_ARRAY[data.iobld.source], 652210284Sjmallett DEST_ARRAY[data.iobld.dest], 653210284Sjmallett (unsigned int)data.iobld.subid, 654210284Sjmallett (unsigned long long)data.iobld.address); 655215990Sjmallett break; 656215990Sjmallett case 15: /* IOBDMA */ 657215990Sjmallett cvmx_dprintf("0x%016llx %c%+10d %s %s->%s len=0x%x 0x%016llx\n", 658215990Sjmallett (unsigned long long)data.u128.data, 659210284Sjmallett (data.cmn.discontinuity) ? 'D' : ' ', 660210284Sjmallett data.cmn.timestamp << (tra_ctl.s.time_grn*3), 661210284Sjmallett TYPE_ARRAY[type], 662210284Sjmallett SOURCE_ARRAY[data.iob.source], 663210284Sjmallett DEST_ARRAY[data.iob.dest], 664210284Sjmallett (unsigned int)data.iob.mask, 665210284Sjmallett (unsigned long long)data.iob.address << 3); 666215990Sjmallett break; 667215990Sjmallett default: 668215990Sjmallett cvmx_dprintf("0x%016llx %c%+10d Unknown format\n", 669215990Sjmallett (unsigned long long)data.u128.data, 670210284Sjmallett (data.cmn.discontinuity) ? 'D' : ' ', 671210284Sjmallett data.cmn.timestamp << (tra_ctl.s.time_grn*3)); 672215990Sjmallett break; 673215990Sjmallett } 674210284Sjmallett } 675215990Sjmallett else 676215990Sjmallett { 677215990Sjmallett int type; 678232812Sjmallett int srcId; 679215990Sjmallett 680215990Sjmallett type = data.cmn2.type; 681215990Sjmallett 682215990Sjmallett switch (1ull<<type) 683215990Sjmallett { 684215990Sjmallett case CVMX_TRA_FILT_DECR64: 685215990Sjmallett case CVMX_TRA_FILT_DECR32: 686215990Sjmallett case CVMX_TRA_FILT_DECR16: 687215990Sjmallett case CVMX_TRA_FILT_DECR8: 688215990Sjmallett case CVMX_TRA_FILT_INCR64: 689215990Sjmallett case CVMX_TRA_FILT_INCR32: 690215990Sjmallett case CVMX_TRA_FILT_INCR16: 691215990Sjmallett case CVMX_TRA_FILT_INCR8: 692215990Sjmallett case CVMX_TRA_FILT_CLR64: 693215990Sjmallett case CVMX_TRA_FILT_CLR32: 694215990Sjmallett case CVMX_TRA_FILT_CLR16: 695215990Sjmallett case CVMX_TRA_FILT_CLR8: 696215990Sjmallett case CVMX_TRA_FILT_SET64: 697215990Sjmallett case CVMX_TRA_FILT_SET32: 698215990Sjmallett case CVMX_TRA_FILT_SET16: 699215990Sjmallett case CVMX_TRA_FILT_SET8: 700232812Sjmallett case CVMX_TRA_FILT_LCKL2: 701232812Sjmallett case CVMX_TRA_FILT_WBIL2: 702232812Sjmallett case CVMX_TRA_FILT_INVL2: 703232812Sjmallett case CVMX_TRA_FILT_STGL2I: 704232812Sjmallett case CVMX_TRA_FILT_LTGL2I: 705232812Sjmallett case CVMX_TRA_FILT_WBIL2I: 706215990Sjmallett case CVMX_TRA_FILT_WBL2: 707215990Sjmallett case CVMX_TRA_FILT_DWB: 708215990Sjmallett case CVMX_TRA_FILT_RPL2: 709215990Sjmallett case CVMX_TRA_FILT_PL2: 710215990Sjmallett case CVMX_TRA_FILT_LDI: 711215990Sjmallett case CVMX_TRA_FILT_LDT: 712232812Sjmallett /* CN68XX has 32 cores which are distributed to use different 713232812Sjmallett trace buffers, decode the core that has data */ 714232812Sjmallett if (OCTEON_IS_MODEL(OCTEON_CN68XX)) 715232812Sjmallett { 716232812Sjmallett if (data.cmn2.source <= 7) 717232812Sjmallett { 718232812Sjmallett srcId = _cvmx_tra_unit + (data.cmn2.source * 4); 719232812Sjmallett if (srcId >= 16) 720232812Sjmallett srcId += 16; 721232812Sjmallett } 722232812Sjmallett else 723232812Sjmallett srcId = (data.cmn2.source); 724232812Sjmallett } 725232812Sjmallett else 726232812Sjmallett srcId = (data.cmn2.source); 727232812Sjmallett 728215990Sjmallett cvmx_dprintf("0x%016llx%016llx %c%+10d %s %s 0x%016llx%llx\n", 729215990Sjmallett (unsigned long long)data.u128.datahi, (unsigned long long)data.u128.data, 730215990Sjmallett (data.cmn2.discontinuity) ? 'D' : ' ', 731215990Sjmallett data.cmn2.timestamp << (tra_ctl.s.time_grn*3), 732215990Sjmallett TYPE_ARRAY2[type], 733232812Sjmallett SOURCE_ARRAY[srcId], 734215990Sjmallett (unsigned long long)data.cmn2.addresshi, 735215990Sjmallett (unsigned long long)data.cmn2.addresslo); 736215990Sjmallett break; 737215990Sjmallett case CVMX_TRA_FILT_PSL1: 738215990Sjmallett case CVMX_TRA_FILT_LDD: 739215990Sjmallett case CVMX_TRA_FILT_FAS64: 740215990Sjmallett case CVMX_TRA_FILT_FAS32: 741215990Sjmallett case CVMX_TRA_FILT_FAA64: 742215990Sjmallett case CVMX_TRA_FILT_FAA32: 743215990Sjmallett case CVMX_TRA_FILT_SAA64: 744215990Sjmallett case CVMX_TRA_FILT_SAA32: 745215990Sjmallett case CVMX_TRA_FILT_STC: 746215990Sjmallett case CVMX_TRA_FILT_STF: 747215990Sjmallett case CVMX_TRA_FILT_STP: 748215990Sjmallett case CVMX_TRA_FILT_STT: 749232812Sjmallett case CVMX_TRA_FILT_STTIL1: 750232812Sjmallett case CVMX_TRA_FILT_STFIL1: 751232812Sjmallett /* CN68XX has 32 cores which are distributed to use different 752232812Sjmallett trace buffers, decode the core that has data */ 753232812Sjmallett if (OCTEON_IS_MODEL(OCTEON_CN68XX)) 754232812Sjmallett { 755232812Sjmallett if (data.store2.source <= 7) 756232812Sjmallett { 757232812Sjmallett srcId = _cvmx_tra_unit + (data.store2.source * 4); 758232812Sjmallett if (srcId >= 16) 759232812Sjmallett srcId += 16; 760232812Sjmallett } 761232812Sjmallett else 762232812Sjmallett srcId = data.store2.source; 763232812Sjmallett } 764232812Sjmallett else 765232812Sjmallett srcId = data.store2.source; 766232812Sjmallett 767215990Sjmallett cvmx_dprintf("0x%016llx%016llx %c%+10d %s %s mask=0x%02x 0x%016llx%llx\n", 768215990Sjmallett (unsigned long long)data.u128.datahi, (unsigned long long)data.u128.data, 769215990Sjmallett (data.cmn2.discontinuity) ? 'D' : ' ', 770215990Sjmallett data.cmn2.timestamp << (tra_ctl.s.time_grn*3), 771215990Sjmallett TYPE_ARRAY2[type], 772232812Sjmallett SOURCE_ARRAY[srcId], 773215990Sjmallett (unsigned int)data.store2.mask, 774215990Sjmallett (unsigned long long)data.store2.addresshi, 775215990Sjmallett (unsigned long long)data.store2.addresslo); 776215990Sjmallett break; 777215990Sjmallett case CVMX_TRA_FILT_IOBST64: 778215990Sjmallett case CVMX_TRA_FILT_IOBST32: 779215990Sjmallett case CVMX_TRA_FILT_IOBST16: 780215990Sjmallett case CVMX_TRA_FILT_IOBST8: 781215990Sjmallett case CVMX_TRA_FILT_IOBLD64: 782215990Sjmallett case CVMX_TRA_FILT_IOBLD32: 783215990Sjmallett case CVMX_TRA_FILT_IOBLD16: 784215990Sjmallett case CVMX_TRA_FILT_IOBLD8: 785232812Sjmallett /* CN68XX has 32 cores which are distributed to use different 786232812Sjmallett trace buffers, decode the core that has data */ 787232812Sjmallett if (OCTEON_IS_MODEL(OCTEON_CN68XX)) 788232812Sjmallett { 789232812Sjmallett if (data.iobld2.source <= 7) 790232812Sjmallett { 791232812Sjmallett srcId = _cvmx_tra_unit + (data.iobld2.source * 4); 792232812Sjmallett if (srcId >= 16) 793232812Sjmallett srcId += 16; 794232812Sjmallett } 795232812Sjmallett else 796232812Sjmallett srcId = data.iobld2.source; 797232812Sjmallett } 798232812Sjmallett else 799232812Sjmallett srcId = data.iobld2.source; 800232812Sjmallett 801215990Sjmallett cvmx_dprintf("0x%016llx%016llx %c%+10d %s %s->%s subdid=0x%x 0x%016llx%llx\n", 802215990Sjmallett (unsigned long long)data.u128.datahi, (unsigned long long)data.u128.data, 803215990Sjmallett (data.cmn2.discontinuity) ? 'D' : ' ', 804215990Sjmallett data.cmn2.timestamp << (tra_ctl.s.time_grn*3), 805215990Sjmallett TYPE_ARRAY2[type], 806232812Sjmallett SOURCE_ARRAY[srcId], 807215990Sjmallett DEST_ARRAY[data.iobld2.dest], 808215990Sjmallett (unsigned int)data.iobld2.subid, 809215990Sjmallett (unsigned long long)data.iobld2.addresshi, 810215990Sjmallett (unsigned long long)data.iobld2.addresslo); 811215990Sjmallett break; 812215990Sjmallett case CVMX_TRA_FILT_IOBDMA: 813232812Sjmallett /* CN68XX has 32 cores which are distributed to use different 814232812Sjmallett trace buffers, decode the core that has data */ 815232812Sjmallett if (OCTEON_IS_MODEL(OCTEON_CN68XX)) 816232812Sjmallett { 817232812Sjmallett if (data.iob2.source <= 7) 818232812Sjmallett { 819232812Sjmallett srcId = _cvmx_tra_unit + (data.iob2.source * 4); 820232812Sjmallett if (srcId >= 16) 821232812Sjmallett srcId += 16; 822232812Sjmallett } 823232812Sjmallett else 824232812Sjmallett srcId = data.iob2.source; 825232812Sjmallett } 826232812Sjmallett else 827232812Sjmallett srcId = data.iob2.source; 828232812Sjmallett 829215990Sjmallett cvmx_dprintf("0x%016llx%016llx %c%+10d %s %s->%s len=0x%x 0x%016llx%llx\n", 830215990Sjmallett (unsigned long long)data.u128.datahi, (unsigned long long)data.u128.data, 831215990Sjmallett (data.iob2.discontinuity) ? 'D' : ' ', 832215990Sjmallett data.iob2.timestamp << (tra_ctl.s.time_grn*3), 833215990Sjmallett TYPE_ARRAY2[type], 834232812Sjmallett SOURCE_ARRAY[srcId], 835215990Sjmallett DEST_ARRAY[data.iob2.dest], 836215990Sjmallett (unsigned int)data.iob2.mask, 837215990Sjmallett (unsigned long long)data.iob2.addresshi << 3, 838215990Sjmallett (unsigned long long)data.iob2.addresslo << 3); 839215990Sjmallett break; 840215990Sjmallett default: 841215990Sjmallett cvmx_dprintf("0x%016llx%016llx %c%+10d Unknown format\n", 842215990Sjmallett (unsigned long long)data.u128.datahi, (unsigned long long)data.u128.data, 843215990Sjmallett (data.cmn2.discontinuity) ? 'D' : ' ', 844215990Sjmallett data.cmn2.timestamp << (tra_ctl.s.time_grn*3)); 845215990Sjmallett break; 846215990Sjmallett } 847215990Sjmallett } 848210284Sjmallett} 849210284Sjmallett 850210284Sjmallett/** 851210284Sjmallett * Display the entire trace buffer. It is advised that you 852210284Sjmallett * disable the trace buffer before calling this routine 853210284Sjmallett * otherwise it could infinitely loop displaying trace data 854210284Sjmallett * that it created. 855210284Sjmallett */ 856210284Sjmallettvoid cvmx_tra_display(void) 857210284Sjmallett{ 858215990Sjmallett int valid = 0; 859210284Sjmallett 860232812Sjmallett /* Collect data from each TRA unit for decoding */ 861232812Sjmallett if (CVMX_L2C_TADS > 1) 862210284Sjmallett { 863232812Sjmallett cvmx_trax_ctl_t tra_ctl; 864232812Sjmallett cvmx_tra_data_t data[4]; 865232812Sjmallett int tad; 866232812Sjmallett do 867232812Sjmallett { 868215990Sjmallett valid = 0; 869232812Sjmallett for (tad = 0; tad < CVMX_L2C_TADS; tad++) 870232812Sjmallett data[tad] = cvmx_tra_read_v2(tad); 871215990Sjmallett 872232812Sjmallett for (tad = 0; tad < CVMX_L2C_TADS; tad++) 873232812Sjmallett { 874232812Sjmallett tra_ctl.u64 = cvmx_read_csr(CVMX_TRAX_CTL(tad)); 875215990Sjmallett 876232812Sjmallett if (data[tad].cmn2.valid) 877232812Sjmallett { 878232812Sjmallett _cvmx_tra_unit = tad; 879232812Sjmallett cvmx_tra_decode_text(tra_ctl, data[tad]); 880232812Sjmallett valid = 1; 881232812Sjmallett } 882232812Sjmallett } 883232812Sjmallett } while (valid); 884232812Sjmallett } 885232812Sjmallett else 886232812Sjmallett { 887232812Sjmallett cvmx_tra_ctl_t tra_ctl; 888232812Sjmallett cvmx_tra_data_t data; 889232812Sjmallett 890232812Sjmallett tra_ctl.u64 = cvmx_read_csr(CVMX_TRA_CTL); 891232812Sjmallett 892232812Sjmallett do 893232812Sjmallett { 894232812Sjmallett data = cvmx_tra_read(); 895232812Sjmallett if ((OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX)) && data.cmn.valid) 896232812Sjmallett valid = 1; 897232812Sjmallett else if (data.cmn2.valid) 898232812Sjmallett valid = 1; 899232812Sjmallett else 900232812Sjmallett valid = 0; 901232812Sjmallett 902232812Sjmallett if (valid) 903232812Sjmallett cvmx_tra_decode_text(tra_ctl, data); 904232812Sjmallett 905232812Sjmallett } while (valid); 906232812Sjmallett } 907210284Sjmallett} 908215990Sjmallett#ifdef CVMX_BUILD_FOR_LINUX_KERNEL 909215990SjmallettEXPORT_SYMBOL(cvmx_tra_display); 910215990Sjmallett#endif 911232812Sjmallett 912232812Sjmallett/** 913232812Sjmallett * Display the entire trace buffer. It is advised that you 914232812Sjmallett * disable the trace buffer before calling this routine 915232812Sjmallett * otherwise it could infinitely loop displaying trace data 916232812Sjmallett * that it created. 917232812Sjmallett * 918232812Sjmallett * @param tra_unit Which TRA buffer to use. 919232812Sjmallett */ 920232812Sjmallettvoid cvmx_tra_display_v2(int tra_unit) 921232812Sjmallett{ 922232812Sjmallett int valid = 0; 923232812Sjmallett 924232812Sjmallett cvmx_trax_ctl_t tra_ctl; 925232812Sjmallett cvmx_tra_data_t data; 926232812Sjmallett 927232812Sjmallett valid = 0; 928232812Sjmallett tra_ctl.u64 = cvmx_read_csr(CVMX_TRAX_CTL(tra_unit)); 929232812Sjmallett 930232812Sjmallett do 931232812Sjmallett { 932232812Sjmallett data = cvmx_tra_read_v2(tra_unit); 933232812Sjmallett if (data.cmn2.valid) 934232812Sjmallett { 935232812Sjmallett _cvmx_tra_unit = tra_unit; 936232812Sjmallett cvmx_tra_decode_text(tra_ctl, data); 937232812Sjmallett valid = 1; 938232812Sjmallett } 939232812Sjmallett } while (valid); 940232812Sjmallett} 941232812Sjmallett#ifdef CVMX_BUILD_FOR_LINUX_KERNEL 942232812SjmallettEXPORT_SYMBOL(cvmx_tra_display_v2); 943232812Sjmallett#endif 944