1228072Sbapt/***********************license start*************** 2228072Sbapt * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3228072Sbapt * reserved. 4228072Sbapt * 5228072Sbapt * 6228072Sbapt * Redistribution and use in source and binary forms, with or without 7228072Sbapt * modification, are permitted provided that the following conditions are 8228072Sbapt * met: 9228072Sbapt * 10228072Sbapt * * Redistributions of source code must retain the above copyright 11228072Sbapt * notice, this list of conditions and the following disclaimer. 12228072Sbapt * 13228072Sbapt * * Redistributions in binary form must reproduce the above 14228072Sbapt * copyright notice, this list of conditions and the following 15228072Sbapt * disclaimer in the documentation and/or other materials provided 16228072Sbapt * with the distribution. 17228072Sbapt 18228072Sbapt * * Neither the name of Cavium Inc. nor the names of 19228072Sbapt * its contributors may be used to endorse or promote products 20228072Sbapt * derived from this software without specific prior written 21228072Sbapt * permission. 22228072Sbapt 23228072Sbapt * This Software, including technical data, may be subject to U.S. export control 24228072Sbapt * laws, including the U.S. Export Administration Act and its associated 25228072Sbapt * regulations, and may be subject to export or import regulations in other 26228072Sbapt * countries. 27228072Sbapt 28228072Sbapt * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29228072Sbapt * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30228072Sbapt * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31228072Sbapt * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32228072Sbapt * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33228072Sbapt * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34228072Sbapt * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35228072Sbapt * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36228072Sbapt * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37228072Sbapt * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38228072Sbapt ***********************license end**************************************/ 39228072Sbapt 40228072Sbapt 41228072Sbapt/** 42228072Sbapt * cvmx-smix-defs.h 43228072Sbapt * 44228072Sbapt * Configuration and status register (CSR) type definitions for 45228072Sbapt * Octeon smix. 46228072Sbapt * 47228072Sbapt * This file is auto generated. Do not edit. 48228072Sbapt * 49228072Sbapt * <hr>$Revision$<hr> 50228072Sbapt * 51228072Sbapt */ 52228072Sbapt#ifndef __CVMX_SMIX_DEFS_H__ 53228072Sbapt#define __CVMX_SMIX_DEFS_H__ 54228072Sbapt 55228072Sbaptstatic inline uint64_t CVMX_SMIX_CLK(unsigned long offset) 56228072Sbapt{ 57228072Sbapt switch(cvmx_get_octeon_family()) { 58228072Sbapt case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 59228072Sbapt case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 60228072Sbapt case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 61228072Sbapt case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 62228072Sbapt case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 63228072Sbapt if ((offset == 0)) 64228072Sbapt return CVMX_ADD_IO_SEG(0x0001180000001818ull) + ((offset) & 0) * 256; 65228072Sbapt break; 66228072Sbapt case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 67228072Sbapt case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 68228072Sbapt case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 69228072Sbapt case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 70228072Sbapt case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 71228072Sbapt case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 72228072Sbapt if ((offset <= 1)) 73228072Sbapt return CVMX_ADD_IO_SEG(0x0001180000001818ull) + ((offset) & 1) * 256; 74228072Sbapt break; 75228072Sbapt case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 76228072Sbapt if ((offset <= 3)) 77228072Sbapt return CVMX_ADD_IO_SEG(0x0001180000003818ull) + ((offset) & 3) * 128; 78228072Sbapt break; 79228072Sbapt } 80228072Sbapt cvmx_warn("CVMX_SMIX_CLK (offset = %lu) not supported on this chip\n", offset); 81228072Sbapt return CVMX_ADD_IO_SEG(0x0001180000001818ull) + ((offset) & 1) * 256; 82228072Sbapt} 83228072Sbaptstatic inline uint64_t CVMX_SMIX_CMD(unsigned long offset) 84228072Sbapt{ 85228072Sbapt switch(cvmx_get_octeon_family()) { 86228072Sbapt case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 87228072Sbapt case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 88228072Sbapt case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 89228072Sbapt case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 90228072Sbapt case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 91228072Sbapt if ((offset == 0)) 92228072Sbapt return CVMX_ADD_IO_SEG(0x0001180000001800ull) + ((offset) & 0) * 256; 93228072Sbapt break; 94228072Sbapt case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 95228072Sbapt case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 96228072Sbapt case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 97228072Sbapt case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 98228072Sbapt case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 99228072Sbapt case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 100228072Sbapt if ((offset <= 1)) 101228072Sbapt return CVMX_ADD_IO_SEG(0x0001180000001800ull) + ((offset) & 1) * 256; 102228072Sbapt break; 103228072Sbapt case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 104228072Sbapt if ((offset <= 3)) 105228072Sbapt return CVMX_ADD_IO_SEG(0x0001180000003800ull) + ((offset) & 3) * 128; 106228072Sbapt break; 107228072Sbapt } 108228072Sbapt cvmx_warn("CVMX_SMIX_CMD (offset = %lu) not supported on this chip\n", offset); 109228072Sbapt return CVMX_ADD_IO_SEG(0x0001180000001800ull) + ((offset) & 1) * 256; 110228072Sbapt} 111228072Sbaptstatic inline uint64_t CVMX_SMIX_EN(unsigned long offset) 112228072Sbapt{ 113228072Sbapt switch(cvmx_get_octeon_family()) { 114228072Sbapt case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 115228072Sbapt case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 116228072Sbapt case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 117228072Sbapt case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 118228072Sbapt case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 119228072Sbapt if ((offset == 0)) 120228072Sbapt return CVMX_ADD_IO_SEG(0x0001180000001820ull) + ((offset) & 0) * 256; 121228072Sbapt break; 122228072Sbapt case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 123228072Sbapt case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 124228072Sbapt case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 125228072Sbapt case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 126228072Sbapt case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 127228072Sbapt case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 128228072Sbapt if ((offset <= 1)) 129228072Sbapt return CVMX_ADD_IO_SEG(0x0001180000001820ull) + ((offset) & 1) * 256; 130228072Sbapt break; 131228072Sbapt case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 132228072Sbapt if ((offset <= 3)) 133228072Sbapt return CVMX_ADD_IO_SEG(0x0001180000003820ull) + ((offset) & 3) * 128; 134228072Sbapt break; 135228072Sbapt } 136228072Sbapt cvmx_warn("CVMX_SMIX_EN (offset = %lu) not supported on this chip\n", offset); 137228072Sbapt return CVMX_ADD_IO_SEG(0x0001180000001820ull) + ((offset) & 1) * 256; 138228072Sbapt} 139228072Sbaptstatic inline uint64_t CVMX_SMIX_RD_DAT(unsigned long offset) 140228072Sbapt{ 141228072Sbapt switch(cvmx_get_octeon_family()) { 142228072Sbapt case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 143228072Sbapt case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 144228072Sbapt case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 145228072Sbapt case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 146228072Sbapt case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 147228072Sbapt if ((offset == 0)) 148228072Sbapt return CVMX_ADD_IO_SEG(0x0001180000001810ull) + ((offset) & 0) * 256; 149228072Sbapt break; 150228072Sbapt case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 151228072Sbapt case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 152228072Sbapt case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 153228072Sbapt case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 154228072Sbapt case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 155228072Sbapt case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 156228072Sbapt if ((offset <= 1)) 157228072Sbapt return CVMX_ADD_IO_SEG(0x0001180000001810ull) + ((offset) & 1) * 256; 158228072Sbapt break; 159228072Sbapt case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 160228072Sbapt if ((offset <= 3)) 161228072Sbapt return CVMX_ADD_IO_SEG(0x0001180000003810ull) + ((offset) & 3) * 128; 162228072Sbapt break; 163228072Sbapt } 164228072Sbapt cvmx_warn("CVMX_SMIX_RD_DAT (offset = %lu) not supported on this chip\n", offset); 165228072Sbapt return CVMX_ADD_IO_SEG(0x0001180000001810ull) + ((offset) & 1) * 256; 166228072Sbapt} 167228072Sbaptstatic inline uint64_t CVMX_SMIX_WR_DAT(unsigned long offset) 168228072Sbapt{ 169228072Sbapt switch(cvmx_get_octeon_family()) { 170228072Sbapt case OCTEON_CN30XX & OCTEON_FAMILY_MASK: 171228072Sbapt case OCTEON_CN50XX & OCTEON_FAMILY_MASK: 172228072Sbapt case OCTEON_CN38XX & OCTEON_FAMILY_MASK: 173228072Sbapt case OCTEON_CN31XX & OCTEON_FAMILY_MASK: 174228072Sbapt case OCTEON_CN58XX & OCTEON_FAMILY_MASK: 175228072Sbapt if ((offset == 0)) 176228072Sbapt return CVMX_ADD_IO_SEG(0x0001180000001808ull) + ((offset) & 0) * 256; 177228072Sbapt break; 178228072Sbapt case OCTEON_CNF71XX & OCTEON_FAMILY_MASK: 179228072Sbapt case OCTEON_CN61XX & OCTEON_FAMILY_MASK: 180228072Sbapt case OCTEON_CN56XX & OCTEON_FAMILY_MASK: 181228072Sbapt case OCTEON_CN66XX & OCTEON_FAMILY_MASK: 182228072Sbapt case OCTEON_CN52XX & OCTEON_FAMILY_MASK: 183228072Sbapt case OCTEON_CN63XX & OCTEON_FAMILY_MASK: 184228072Sbapt if ((offset <= 1)) 185228072Sbapt return CVMX_ADD_IO_SEG(0x0001180000001808ull) + ((offset) & 1) * 256; 186228072Sbapt break; 187228072Sbapt case OCTEON_CN68XX & OCTEON_FAMILY_MASK: 188228072Sbapt if ((offset <= 3)) 189228072Sbapt return CVMX_ADD_IO_SEG(0x0001180000003808ull) + ((offset) & 3) * 128; 190228072Sbapt break; 191228072Sbapt } 192228072Sbapt cvmx_warn("CVMX_SMIX_WR_DAT (offset = %lu) not supported on this chip\n", offset); 193228072Sbapt return CVMX_ADD_IO_SEG(0x0001180000001808ull) + ((offset) & 1) * 256; 194228072Sbapt} 195228072Sbapt 196228072Sbapt/** 197228072Sbapt * cvmx_smi#_clk 198228072Sbapt * 199228072Sbapt * SMI_CLK = Clock Control Register 200228072Sbapt * 201228072Sbapt */ 202228072Sbaptunion cvmx_smix_clk { 203228072Sbapt uint64_t u64; 204228072Sbapt struct cvmx_smix_clk_s { 205228072Sbapt#ifdef __BIG_ENDIAN_BITFIELD 206228072Sbapt uint64_t reserved_25_63 : 39; 207228072Sbapt uint64_t mode : 1; /**< IEEE operating mode 208228072Sbapt 0=Clause 22 complient 209228072Sbapt 1=Clause 45 complient */ 210228072Sbapt uint64_t reserved_21_23 : 3; 211228072Sbapt uint64_t sample_hi : 5; /**< When to sample read data (extended bits) */ 212228072Sbapt uint64_t sample_mode : 1; /**< Read Data sampling mode 213228072Sbapt According to the 802.3 spec, on reads, the STA 214228072Sbapt transitions MDC and the PHY drives MDIO with 215228072Sbapt some delay relative to that edge. This is edge1. 216228072Sbapt The STA then samples MDIO on the next rising edge 217228072Sbapt of MDC. This is edge2. Octeon can sample the 218228072Sbapt read data relative to either edge. 219228072Sbapt 0=[SAMPLE_HI,SAMPLE] specify the sample time 220228072Sbapt relative to edge2 221228072Sbapt 1=[SAMPLE_HI,SAMPLE] specify the sample time 222228072Sbapt relative to edge1 */ 223228072Sbapt uint64_t reserved_14_14 : 1; 224228072Sbapt uint64_t clk_idle : 1; /**< Do not toggle MDC on idle cycles */ 225228072Sbapt uint64_t preamble : 1; /**< Send PREAMBLE on SMI transacton 226228072Sbapt PREAMBLE must be set 1 when MODE=1 in order 227228072Sbapt for the receiving PHY to correctly frame the 228228072Sbapt transaction. */ 229228072Sbapt uint64_t sample : 4; /**< When to sample read data 230228072Sbapt (number of eclks after the rising edge of mdc) 231228072Sbapt ( [SAMPLE_HI,SAMPLE] > 1 ) 232228072Sbapt ( [SAMPLE_HI, SAMPLE] + 3 <= 2*PHASE ) */ 233228072Sbapt uint64_t phase : 8; /**< MDC Clock Phase 234228072Sbapt (number of eclks that make up an mdc phase) 235228072Sbapt (PHASE > 2) */ 236228072Sbapt#else 237228072Sbapt uint64_t phase : 8; 238228072Sbapt uint64_t sample : 4; 239228072Sbapt uint64_t preamble : 1; 240228072Sbapt uint64_t clk_idle : 1; 241228072Sbapt uint64_t reserved_14_14 : 1; 242228072Sbapt uint64_t sample_mode : 1; 243228072Sbapt uint64_t sample_hi : 5; 244228072Sbapt uint64_t reserved_21_23 : 3; 245228072Sbapt uint64_t mode : 1; 246228072Sbapt uint64_t reserved_25_63 : 39; 247228072Sbapt#endif 248228072Sbapt } s; 249228072Sbapt struct cvmx_smix_clk_cn30xx { 250228072Sbapt#ifdef __BIG_ENDIAN_BITFIELD 251228072Sbapt uint64_t reserved_21_63 : 43; 252228072Sbapt uint64_t sample_hi : 5; /**< When to sample read data (extended bits) */ 253228072Sbapt uint64_t sample_mode : 1; /**< Read Data sampling mode 254228072Sbapt According to the 802.3 spec, on reads, the STA 255228072Sbapt transitions MDC and the PHY drives MDIO with 256228072Sbapt some delay relative to that edge. This is edge1. 257228072Sbapt The STA then samples MDIO on the next rising edge 258228072Sbapt of MDC. This is edge2. Octeon can sample the 259228072Sbapt read data relative to either edge. 260228072Sbapt 0=[SAMPLE_HI,SAMPLE] specify the sample time 261228072Sbapt relative to edge2 262228072Sbapt 1=[SAMPLE_HI,SAMPLE] specify the sample time 263228072Sbapt relative to edge1 */ 264228072Sbapt uint64_t reserved_14_14 : 1; 265228072Sbapt uint64_t clk_idle : 1; /**< Do not toggle MDC on idle cycles */ 266228072Sbapt uint64_t preamble : 1; /**< Send PREAMBLE on SMI transacton */ 267228072Sbapt uint64_t sample : 4; /**< When to sample read data 268228072Sbapt (number of eclks after the rising edge of mdc) 269228072Sbapt ( [SAMPLE_HI,SAMPLE] > 1 ) 270228072Sbapt ( [SAMPLE_HI, SAMPLE] + 3 <= 2*PHASE ) */ 271228072Sbapt uint64_t phase : 8; /**< MDC Clock Phase 272228072Sbapt (number of eclks that make up an mdc phase) 273228072Sbapt (PHASE > 2) */ 274228072Sbapt#else 275228072Sbapt uint64_t phase : 8; 276228072Sbapt uint64_t sample : 4; 277228072Sbapt uint64_t preamble : 1; 278228072Sbapt uint64_t clk_idle : 1; 279228072Sbapt uint64_t reserved_14_14 : 1; 280228072Sbapt uint64_t sample_mode : 1; 281228072Sbapt uint64_t sample_hi : 5; 282228072Sbapt uint64_t reserved_21_63 : 43; 283228072Sbapt#endif 284228072Sbapt } cn30xx; 285228072Sbapt struct cvmx_smix_clk_cn30xx cn31xx; 286228072Sbapt struct cvmx_smix_clk_cn30xx cn38xx; 287228072Sbapt struct cvmx_smix_clk_cn30xx cn38xxp2; 288228072Sbapt struct cvmx_smix_clk_s cn50xx; 289228072Sbapt struct cvmx_smix_clk_s cn52xx; 290228072Sbapt struct cvmx_smix_clk_s cn52xxp1; 291228072Sbapt struct cvmx_smix_clk_s cn56xx; 292228072Sbapt struct cvmx_smix_clk_s cn56xxp1; 293228072Sbapt struct cvmx_smix_clk_cn30xx cn58xx; 294228072Sbapt struct cvmx_smix_clk_cn30xx cn58xxp1; 295228072Sbapt struct cvmx_smix_clk_s cn61xx; 296228072Sbapt struct cvmx_smix_clk_s cn63xx; 297228072Sbapt struct cvmx_smix_clk_s cn63xxp1; 298228072Sbapt struct cvmx_smix_clk_s cn66xx; 299228072Sbapt struct cvmx_smix_clk_s cn68xx; 300228072Sbapt struct cvmx_smix_clk_s cn68xxp1; 301228072Sbapt struct cvmx_smix_clk_s cnf71xx; 302228072Sbapt}; 303228072Sbapttypedef union cvmx_smix_clk cvmx_smix_clk_t; 304228072Sbapt 305228072Sbapt/** 306228072Sbapt * cvmx_smi#_cmd 307228072Sbapt * 308228072Sbapt * SMI_CMD = Force a Read/Write command to the PHY 309228072Sbapt * 310228072Sbapt * 311228072Sbapt * Notes: 312228072Sbapt * Writes to this register will create SMI xactions. Software will poll on (depending on the xaction type). 313228072Sbapt * 314228072Sbapt */ 315228072Sbaptunion cvmx_smix_cmd { 316228072Sbapt uint64_t u64; 317228072Sbapt struct cvmx_smix_cmd_s { 318228072Sbapt#ifdef __BIG_ENDIAN_BITFIELD 319228072Sbapt uint64_t reserved_18_63 : 46; 320228072Sbapt uint64_t phy_op : 2; /**< PHY Opcode depending on SMI_CLK[MODE] 321228072Sbapt SMI_CLK[MODE] == 0 (<=1Gbs / Clause 22) 322228072Sbapt x0=write 323228072Sbapt x1=read 324228072Sbapt SMI_CLK[MODE] == 1 (>1Gbs / Clause 45) 325228072Sbapt 00=address 326228072Sbapt 01=write 327228072Sbapt 11=read 328228072Sbapt 10=post-read-increment-address */ 329228072Sbapt uint64_t reserved_13_15 : 3; 330228072Sbapt uint64_t phy_adr : 5; /**< PHY Address */ 331228072Sbapt uint64_t reserved_5_7 : 3; 332228072Sbapt uint64_t reg_adr : 5; /**< PHY Register Offset */ 333228072Sbapt#else 334228072Sbapt uint64_t reg_adr : 5; 335228072Sbapt uint64_t reserved_5_7 : 3; 336228072Sbapt uint64_t phy_adr : 5; 337228072Sbapt uint64_t reserved_13_15 : 3; 338228072Sbapt uint64_t phy_op : 2; 339228072Sbapt uint64_t reserved_18_63 : 46; 340228072Sbapt#endif 341228072Sbapt } s; 342228072Sbapt struct cvmx_smix_cmd_cn30xx { 343228072Sbapt#ifdef __BIG_ENDIAN_BITFIELD 344228072Sbapt uint64_t reserved_17_63 : 47; 345228072Sbapt uint64_t phy_op : 1; /**< PHY Opcode 346228072Sbapt 0=write 347228072Sbapt 1=read */ 348228072Sbapt uint64_t reserved_13_15 : 3; 349228072Sbapt uint64_t phy_adr : 5; /**< PHY Address */ 350228072Sbapt uint64_t reserved_5_7 : 3; 351228072Sbapt uint64_t reg_adr : 5; /**< PHY Register Offset */ 352228072Sbapt#else 353228072Sbapt uint64_t reg_adr : 5; 354228072Sbapt uint64_t reserved_5_7 : 3; 355228072Sbapt uint64_t phy_adr : 5; 356228072Sbapt uint64_t reserved_13_15 : 3; 357228072Sbapt uint64_t phy_op : 1; 358228072Sbapt uint64_t reserved_17_63 : 47; 359228072Sbapt#endif 360228072Sbapt } cn30xx; 361228072Sbapt struct cvmx_smix_cmd_cn30xx cn31xx; 362228072Sbapt struct cvmx_smix_cmd_cn30xx cn38xx; 363228072Sbapt struct cvmx_smix_cmd_cn30xx cn38xxp2; 364228072Sbapt struct cvmx_smix_cmd_s cn50xx; 365228072Sbapt struct cvmx_smix_cmd_s cn52xx; 366228072Sbapt struct cvmx_smix_cmd_s cn52xxp1; 367228072Sbapt struct cvmx_smix_cmd_s cn56xx; 368228072Sbapt struct cvmx_smix_cmd_s cn56xxp1; 369228072Sbapt struct cvmx_smix_cmd_cn30xx cn58xx; 370228072Sbapt struct cvmx_smix_cmd_cn30xx cn58xxp1; 371228072Sbapt struct cvmx_smix_cmd_s cn61xx; 372228072Sbapt struct cvmx_smix_cmd_s cn63xx; 373228072Sbapt struct cvmx_smix_cmd_s cn63xxp1; 374228072Sbapt struct cvmx_smix_cmd_s cn66xx; 375228072Sbapt struct cvmx_smix_cmd_s cn68xx; 376228072Sbapt struct cvmx_smix_cmd_s cn68xxp1; 377228072Sbapt struct cvmx_smix_cmd_s cnf71xx; 378228072Sbapt}; 379228072Sbapttypedef union cvmx_smix_cmd cvmx_smix_cmd_t; 380228072Sbapt 381228072Sbapt/** 382228072Sbapt * cvmx_smi#_en 383228072Sbapt * 384228072Sbapt * SMI_EN = Enable the SMI interface 385228072Sbapt * 386228072Sbapt */ 387228072Sbaptunion cvmx_smix_en { 388228072Sbapt uint64_t u64; 389228072Sbapt struct cvmx_smix_en_s { 390228072Sbapt#ifdef __BIG_ENDIAN_BITFIELD 391228072Sbapt uint64_t reserved_1_63 : 63; 392228072Sbapt uint64_t en : 1; /**< Interface enable 393228072Sbapt 0=SMI Interface is down / no transactions, no MDC 394228072Sbapt 1=SMI Interface is up */ 395228072Sbapt#else 396228072Sbapt uint64_t en : 1; 397228072Sbapt uint64_t reserved_1_63 : 63; 398228072Sbapt#endif 399228072Sbapt } s; 400228072Sbapt struct cvmx_smix_en_s cn30xx; 401228072Sbapt struct cvmx_smix_en_s cn31xx; 402228072Sbapt struct cvmx_smix_en_s cn38xx; 403228072Sbapt struct cvmx_smix_en_s cn38xxp2; 404228072Sbapt struct cvmx_smix_en_s cn50xx; 405228072Sbapt struct cvmx_smix_en_s cn52xx; 406228072Sbapt struct cvmx_smix_en_s cn52xxp1; 407228072Sbapt struct cvmx_smix_en_s cn56xx; 408228072Sbapt struct cvmx_smix_en_s cn56xxp1; 409228072Sbapt struct cvmx_smix_en_s cn58xx; 410228072Sbapt struct cvmx_smix_en_s cn58xxp1; 411228072Sbapt struct cvmx_smix_en_s cn61xx; 412228072Sbapt struct cvmx_smix_en_s cn63xx; 413228072Sbapt struct cvmx_smix_en_s cn63xxp1; 414228072Sbapt struct cvmx_smix_en_s cn66xx; 415228072Sbapt struct cvmx_smix_en_s cn68xx; 416228072Sbapt struct cvmx_smix_en_s cn68xxp1; 417228072Sbapt struct cvmx_smix_en_s cnf71xx; 418228072Sbapt}; 419228072Sbapttypedef union cvmx_smix_en cvmx_smix_en_t; 420228072Sbapt 421228072Sbapt/** 422228072Sbapt * cvmx_smi#_rd_dat 423228072Sbapt * 424228072Sbapt * SMI_RD_DAT = SMI Read Data 425228072Sbapt * 426228072Sbapt * 427228072Sbapt * Notes: 428228072Sbapt * VAL will assert when the read xaction completes. A read to this register 429228072Sbapt * will clear VAL. PENDING indicates that an SMI RD transaction is in flight. 430228072Sbapt */ 431228072Sbaptunion cvmx_smix_rd_dat { 432228072Sbapt uint64_t u64; 433228072Sbapt struct cvmx_smix_rd_dat_s { 434228072Sbapt#ifdef __BIG_ENDIAN_BITFIELD 435228072Sbapt uint64_t reserved_18_63 : 46; 436228072Sbapt uint64_t pending : 1; /**< Read Xaction Pending */ 437228072Sbapt uint64_t val : 1; /**< Read Data Valid */ 438228072Sbapt uint64_t dat : 16; /**< Read Data */ 439228072Sbapt#else 440228072Sbapt uint64_t dat : 16; 441228072Sbapt uint64_t val : 1; 442228072Sbapt uint64_t pending : 1; 443228072Sbapt uint64_t reserved_18_63 : 46; 444228072Sbapt#endif 445228072Sbapt } s; 446228072Sbapt struct cvmx_smix_rd_dat_s cn30xx; 447228072Sbapt struct cvmx_smix_rd_dat_s cn31xx; 448228072Sbapt struct cvmx_smix_rd_dat_s cn38xx; 449228072Sbapt struct cvmx_smix_rd_dat_s cn38xxp2; 450228072Sbapt struct cvmx_smix_rd_dat_s cn50xx; 451228072Sbapt struct cvmx_smix_rd_dat_s cn52xx; 452228072Sbapt struct cvmx_smix_rd_dat_s cn52xxp1; 453228072Sbapt struct cvmx_smix_rd_dat_s cn56xx; 454228072Sbapt struct cvmx_smix_rd_dat_s cn56xxp1; 455228072Sbapt struct cvmx_smix_rd_dat_s cn58xx; 456228072Sbapt struct cvmx_smix_rd_dat_s cn58xxp1; 457228072Sbapt struct cvmx_smix_rd_dat_s cn61xx; 458228072Sbapt struct cvmx_smix_rd_dat_s cn63xx; 459228072Sbapt struct cvmx_smix_rd_dat_s cn63xxp1; 460228072Sbapt struct cvmx_smix_rd_dat_s cn66xx; 461228072Sbapt struct cvmx_smix_rd_dat_s cn68xx; 462228072Sbapt struct cvmx_smix_rd_dat_s cn68xxp1; 463228072Sbapt struct cvmx_smix_rd_dat_s cnf71xx; 464228072Sbapt}; 465228072Sbapttypedef union cvmx_smix_rd_dat cvmx_smix_rd_dat_t; 466228072Sbapt 467228072Sbapt/** 468228072Sbapt * cvmx_smi#_wr_dat 469228072Sbapt * 470228072Sbapt * SMI_WR_DAT = SMI Write Data 471228072Sbapt * 472228072Sbapt * 473228072Sbapt * Notes: 474228072Sbapt * VAL will assert when the write xaction completes. A read to this register 475228072Sbapt * will clear VAL. PENDING indicates that an SMI WR transaction is in flight. 476228072Sbapt */ 477228072Sbaptunion cvmx_smix_wr_dat { 478228072Sbapt uint64_t u64; 479228072Sbapt struct cvmx_smix_wr_dat_s { 480228072Sbapt#ifdef __BIG_ENDIAN_BITFIELD 481228072Sbapt uint64_t reserved_18_63 : 46; 482228072Sbapt uint64_t pending : 1; /**< Write Xaction Pending */ 483228072Sbapt uint64_t val : 1; /**< Write Data Valid */ 484228072Sbapt uint64_t dat : 16; /**< Write Data */ 485228072Sbapt#else 486228072Sbapt uint64_t dat : 16; 487228072Sbapt uint64_t val : 1; 488228072Sbapt uint64_t pending : 1; 489228072Sbapt uint64_t reserved_18_63 : 46; 490228072Sbapt#endif 491228072Sbapt } s; 492228072Sbapt struct cvmx_smix_wr_dat_s cn30xx; 493228072Sbapt struct cvmx_smix_wr_dat_s cn31xx; 494228072Sbapt struct cvmx_smix_wr_dat_s cn38xx; 495228072Sbapt struct cvmx_smix_wr_dat_s cn38xxp2; 496228072Sbapt struct cvmx_smix_wr_dat_s cn50xx; 497228072Sbapt struct cvmx_smix_wr_dat_s cn52xx; 498228072Sbapt struct cvmx_smix_wr_dat_s cn52xxp1; 499228072Sbapt struct cvmx_smix_wr_dat_s cn56xx; 500228072Sbapt struct cvmx_smix_wr_dat_s cn56xxp1; 501228072Sbapt struct cvmx_smix_wr_dat_s cn58xx; 502228072Sbapt struct cvmx_smix_wr_dat_s cn58xxp1; 503228072Sbapt struct cvmx_smix_wr_dat_s cn61xx; 504228072Sbapt struct cvmx_smix_wr_dat_s cn63xx; 505228072Sbapt struct cvmx_smix_wr_dat_s cn63xxp1; 506228072Sbapt struct cvmx_smix_wr_dat_s cn66xx; 507228072Sbapt struct cvmx_smix_wr_dat_s cn68xx; 508228072Sbapt struct cvmx_smix_wr_dat_s cn68xxp1; 509228072Sbapt struct cvmx_smix_wr_dat_s cnf71xx; 510228072Sbapt}; 511228072Sbapttypedef union cvmx_smix_wr_dat cvmx_smix_wr_dat_t; 512228072Sbapt 513228072Sbapt#endif 514228072Sbapt