1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-pciercx-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon pciercx. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_PCIERCX_DEFS_H__ 53232812Sjmallett#define __CVMX_PCIERCX_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 56215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG000(unsigned long block_id) 57215976Sjmallett{ 58215976Sjmallett if (!( 59215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 60215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 61232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 62232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 63232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 64232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 65232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 66215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG000(%lu) is invalid on this chip\n", block_id); 67215976Sjmallett return 0x0000000000000000ull; 68215976Sjmallett} 69215976Sjmallett#else 70215976Sjmallett#define CVMX_PCIERCX_CFG000(block_id) (0x0000000000000000ull) 71215976Sjmallett#endif 72215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 73215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG001(unsigned long block_id) 74215976Sjmallett{ 75215976Sjmallett if (!( 76215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 77215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 78232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 79232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 80232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 81232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 82232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 83215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG001(%lu) is invalid on this chip\n", block_id); 84215976Sjmallett return 0x0000000000000004ull; 85215976Sjmallett} 86215976Sjmallett#else 87215976Sjmallett#define CVMX_PCIERCX_CFG001(block_id) (0x0000000000000004ull) 88215976Sjmallett#endif 89215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 90215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG002(unsigned long block_id) 91215976Sjmallett{ 92215976Sjmallett if (!( 93215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 94215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 95232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 96232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 97232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 98232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 99232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 100215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG002(%lu) is invalid on this chip\n", block_id); 101215976Sjmallett return 0x0000000000000008ull; 102215976Sjmallett} 103215976Sjmallett#else 104215976Sjmallett#define CVMX_PCIERCX_CFG002(block_id) (0x0000000000000008ull) 105215976Sjmallett#endif 106215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 107215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG003(unsigned long block_id) 108215976Sjmallett{ 109215976Sjmallett if (!( 110215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 111215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 112232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 113232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 114232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 115232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 116232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 117215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG003(%lu) is invalid on this chip\n", block_id); 118215976Sjmallett return 0x000000000000000Cull; 119215976Sjmallett} 120215976Sjmallett#else 121215976Sjmallett#define CVMX_PCIERCX_CFG003(block_id) (0x000000000000000Cull) 122215976Sjmallett#endif 123215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 124215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG004(unsigned long block_id) 125215976Sjmallett{ 126215976Sjmallett if (!( 127215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 128215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 129232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 130232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 131232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 132232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 133232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 134215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG004(%lu) is invalid on this chip\n", block_id); 135215976Sjmallett return 0x0000000000000010ull; 136215976Sjmallett} 137215976Sjmallett#else 138215976Sjmallett#define CVMX_PCIERCX_CFG004(block_id) (0x0000000000000010ull) 139215976Sjmallett#endif 140215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 141215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG005(unsigned long block_id) 142215976Sjmallett{ 143215976Sjmallett if (!( 144215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 145215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 146232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 147232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 148232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 149232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 150232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 151215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG005(%lu) is invalid on this chip\n", block_id); 152215976Sjmallett return 0x0000000000000014ull; 153215976Sjmallett} 154215976Sjmallett#else 155215976Sjmallett#define CVMX_PCIERCX_CFG005(block_id) (0x0000000000000014ull) 156215976Sjmallett#endif 157215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 158215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG006(unsigned long block_id) 159215976Sjmallett{ 160215976Sjmallett if (!( 161215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 162215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 163232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 164232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 165232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 166232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 167232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 168215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG006(%lu) is invalid on this chip\n", block_id); 169215976Sjmallett return 0x0000000000000018ull; 170215976Sjmallett} 171215976Sjmallett#else 172215976Sjmallett#define CVMX_PCIERCX_CFG006(block_id) (0x0000000000000018ull) 173215976Sjmallett#endif 174215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 175215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG007(unsigned long block_id) 176215976Sjmallett{ 177215976Sjmallett if (!( 178215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 179215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 180232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 181232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 182232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 183232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 184232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 185215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG007(%lu) is invalid on this chip\n", block_id); 186215976Sjmallett return 0x000000000000001Cull; 187215976Sjmallett} 188215976Sjmallett#else 189215976Sjmallett#define CVMX_PCIERCX_CFG007(block_id) (0x000000000000001Cull) 190215976Sjmallett#endif 191215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 192215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG008(unsigned long block_id) 193215976Sjmallett{ 194215976Sjmallett if (!( 195215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 196215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 197232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 198232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 199232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 200232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 201232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 202215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG008(%lu) is invalid on this chip\n", block_id); 203215976Sjmallett return 0x0000000000000020ull; 204215976Sjmallett} 205215976Sjmallett#else 206215976Sjmallett#define CVMX_PCIERCX_CFG008(block_id) (0x0000000000000020ull) 207215976Sjmallett#endif 208215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 209215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG009(unsigned long block_id) 210215976Sjmallett{ 211215976Sjmallett if (!( 212215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 213215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 214232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 215232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 216232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 217232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 218232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 219215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG009(%lu) is invalid on this chip\n", block_id); 220215976Sjmallett return 0x0000000000000024ull; 221215976Sjmallett} 222215976Sjmallett#else 223215976Sjmallett#define CVMX_PCIERCX_CFG009(block_id) (0x0000000000000024ull) 224215976Sjmallett#endif 225215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 226215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG010(unsigned long block_id) 227215976Sjmallett{ 228215976Sjmallett if (!( 229215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 230215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 231232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 232232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 233232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 234232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 235232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 236215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG010(%lu) is invalid on this chip\n", block_id); 237215976Sjmallett return 0x0000000000000028ull; 238215976Sjmallett} 239215976Sjmallett#else 240215976Sjmallett#define CVMX_PCIERCX_CFG010(block_id) (0x0000000000000028ull) 241215976Sjmallett#endif 242215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 243215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG011(unsigned long block_id) 244215976Sjmallett{ 245215976Sjmallett if (!( 246215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 247215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 248232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 249232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 250232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 251232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 252232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 253215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG011(%lu) is invalid on this chip\n", block_id); 254215976Sjmallett return 0x000000000000002Cull; 255215976Sjmallett} 256215976Sjmallett#else 257215976Sjmallett#define CVMX_PCIERCX_CFG011(block_id) (0x000000000000002Cull) 258215976Sjmallett#endif 259215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 260215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG012(unsigned long block_id) 261215976Sjmallett{ 262215976Sjmallett if (!( 263215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 264215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 265232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 266232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 267232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 268232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 269232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 270215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG012(%lu) is invalid on this chip\n", block_id); 271215976Sjmallett return 0x0000000000000030ull; 272215976Sjmallett} 273215976Sjmallett#else 274215976Sjmallett#define CVMX_PCIERCX_CFG012(block_id) (0x0000000000000030ull) 275215976Sjmallett#endif 276215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 277215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG013(unsigned long block_id) 278215976Sjmallett{ 279215976Sjmallett if (!( 280215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 281215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 282232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 283232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 284232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 285232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 286232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 287215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG013(%lu) is invalid on this chip\n", block_id); 288215976Sjmallett return 0x0000000000000034ull; 289215976Sjmallett} 290215976Sjmallett#else 291215976Sjmallett#define CVMX_PCIERCX_CFG013(block_id) (0x0000000000000034ull) 292215976Sjmallett#endif 293215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 294215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG014(unsigned long block_id) 295215976Sjmallett{ 296215976Sjmallett if (!( 297215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 298215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 299232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 300232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 301232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 302232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 303232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 304215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG014(%lu) is invalid on this chip\n", block_id); 305215976Sjmallett return 0x0000000000000038ull; 306215976Sjmallett} 307215976Sjmallett#else 308215976Sjmallett#define CVMX_PCIERCX_CFG014(block_id) (0x0000000000000038ull) 309215976Sjmallett#endif 310215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 311215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG015(unsigned long block_id) 312215976Sjmallett{ 313215976Sjmallett if (!( 314215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 315215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 316232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 317232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 318232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 319232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 320232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 321215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG015(%lu) is invalid on this chip\n", block_id); 322215976Sjmallett return 0x000000000000003Cull; 323215976Sjmallett} 324215976Sjmallett#else 325215976Sjmallett#define CVMX_PCIERCX_CFG015(block_id) (0x000000000000003Cull) 326215976Sjmallett#endif 327215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 328215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG016(unsigned long block_id) 329215976Sjmallett{ 330215976Sjmallett if (!( 331215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 332215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 333232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 334232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 335232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 336232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 337232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 338215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG016(%lu) is invalid on this chip\n", block_id); 339215976Sjmallett return 0x0000000000000040ull; 340215976Sjmallett} 341215976Sjmallett#else 342215976Sjmallett#define CVMX_PCIERCX_CFG016(block_id) (0x0000000000000040ull) 343215976Sjmallett#endif 344215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 345215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG017(unsigned long block_id) 346215976Sjmallett{ 347215976Sjmallett if (!( 348215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 349215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 350232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 351232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 352232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 353232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 354232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 355215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG017(%lu) is invalid on this chip\n", block_id); 356215976Sjmallett return 0x0000000000000044ull; 357215976Sjmallett} 358215976Sjmallett#else 359215976Sjmallett#define CVMX_PCIERCX_CFG017(block_id) (0x0000000000000044ull) 360215976Sjmallett#endif 361215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 362215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG020(unsigned long block_id) 363215976Sjmallett{ 364215976Sjmallett if (!( 365215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 366215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 367232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 368232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 369232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 370232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 371232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 372215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG020(%lu) is invalid on this chip\n", block_id); 373215976Sjmallett return 0x0000000000000050ull; 374215976Sjmallett} 375215976Sjmallett#else 376215976Sjmallett#define CVMX_PCIERCX_CFG020(block_id) (0x0000000000000050ull) 377215976Sjmallett#endif 378215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 379215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG021(unsigned long block_id) 380215976Sjmallett{ 381215976Sjmallett if (!( 382215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 383215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 384232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 385232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 386232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 387232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 388232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 389215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG021(%lu) is invalid on this chip\n", block_id); 390215976Sjmallett return 0x0000000000000054ull; 391215976Sjmallett} 392215976Sjmallett#else 393215976Sjmallett#define CVMX_PCIERCX_CFG021(block_id) (0x0000000000000054ull) 394215976Sjmallett#endif 395215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 396215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG022(unsigned long block_id) 397215976Sjmallett{ 398215976Sjmallett if (!( 399215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 400215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 401232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 402232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 403232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 404232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 405232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 406215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG022(%lu) is invalid on this chip\n", block_id); 407215976Sjmallett return 0x0000000000000058ull; 408215976Sjmallett} 409215976Sjmallett#else 410215976Sjmallett#define CVMX_PCIERCX_CFG022(block_id) (0x0000000000000058ull) 411215976Sjmallett#endif 412215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 413215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG023(unsigned long block_id) 414215976Sjmallett{ 415215976Sjmallett if (!( 416215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 417215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 418232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 419232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 420232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 421232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 422232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 423215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG023(%lu) is invalid on this chip\n", block_id); 424215976Sjmallett return 0x000000000000005Cull; 425215976Sjmallett} 426215976Sjmallett#else 427215976Sjmallett#define CVMX_PCIERCX_CFG023(block_id) (0x000000000000005Cull) 428215976Sjmallett#endif 429215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 430215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG028(unsigned long block_id) 431215976Sjmallett{ 432215976Sjmallett if (!( 433215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 434215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 435232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 436232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 437232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 438232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 439232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 440215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG028(%lu) is invalid on this chip\n", block_id); 441215976Sjmallett return 0x0000000000000070ull; 442215976Sjmallett} 443215976Sjmallett#else 444215976Sjmallett#define CVMX_PCIERCX_CFG028(block_id) (0x0000000000000070ull) 445215976Sjmallett#endif 446215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 447215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG029(unsigned long block_id) 448215976Sjmallett{ 449215976Sjmallett if (!( 450215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 451215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 452232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 453232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 454232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 455232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 456232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 457215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG029(%lu) is invalid on this chip\n", block_id); 458215976Sjmallett return 0x0000000000000074ull; 459215976Sjmallett} 460215976Sjmallett#else 461215976Sjmallett#define CVMX_PCIERCX_CFG029(block_id) (0x0000000000000074ull) 462215976Sjmallett#endif 463215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 464215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG030(unsigned long block_id) 465215976Sjmallett{ 466215976Sjmallett if (!( 467215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 468215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 469232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 470232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 471232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 472232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 473232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 474215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG030(%lu) is invalid on this chip\n", block_id); 475215976Sjmallett return 0x0000000000000078ull; 476215976Sjmallett} 477215976Sjmallett#else 478215976Sjmallett#define CVMX_PCIERCX_CFG030(block_id) (0x0000000000000078ull) 479215976Sjmallett#endif 480215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 481215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG031(unsigned long block_id) 482215976Sjmallett{ 483215976Sjmallett if (!( 484215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 485215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 486232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 487232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 488232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 489232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 490232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 491215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG031(%lu) is invalid on this chip\n", block_id); 492215976Sjmallett return 0x000000000000007Cull; 493215976Sjmallett} 494215976Sjmallett#else 495215976Sjmallett#define CVMX_PCIERCX_CFG031(block_id) (0x000000000000007Cull) 496215976Sjmallett#endif 497215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 498215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG032(unsigned long block_id) 499215976Sjmallett{ 500215976Sjmallett if (!( 501215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 502215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 503232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 504232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 505232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 506232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 507232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 508215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG032(%lu) is invalid on this chip\n", block_id); 509215976Sjmallett return 0x0000000000000080ull; 510215976Sjmallett} 511215976Sjmallett#else 512215976Sjmallett#define CVMX_PCIERCX_CFG032(block_id) (0x0000000000000080ull) 513215976Sjmallett#endif 514215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 515215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG033(unsigned long block_id) 516215976Sjmallett{ 517215976Sjmallett if (!( 518215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 519215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 520232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 521232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 522232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 523232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 524232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 525215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG033(%lu) is invalid on this chip\n", block_id); 526215976Sjmallett return 0x0000000000000084ull; 527215976Sjmallett} 528215976Sjmallett#else 529215976Sjmallett#define CVMX_PCIERCX_CFG033(block_id) (0x0000000000000084ull) 530215976Sjmallett#endif 531215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 532215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG034(unsigned long block_id) 533215976Sjmallett{ 534215976Sjmallett if (!( 535215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 536215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 537232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 538232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 539232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 540232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 541232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 542215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG034(%lu) is invalid on this chip\n", block_id); 543215976Sjmallett return 0x0000000000000088ull; 544215976Sjmallett} 545215976Sjmallett#else 546215976Sjmallett#define CVMX_PCIERCX_CFG034(block_id) (0x0000000000000088ull) 547215976Sjmallett#endif 548215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 549215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG035(unsigned long block_id) 550215976Sjmallett{ 551215976Sjmallett if (!( 552215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 553215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 554232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 555232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 556232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 557232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 558232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 559215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG035(%lu) is invalid on this chip\n", block_id); 560215976Sjmallett return 0x000000000000008Cull; 561215976Sjmallett} 562215976Sjmallett#else 563215976Sjmallett#define CVMX_PCIERCX_CFG035(block_id) (0x000000000000008Cull) 564215976Sjmallett#endif 565215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 566215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG036(unsigned long block_id) 567215976Sjmallett{ 568215976Sjmallett if (!( 569215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 570215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 571232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 572232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 573232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 574232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 575232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 576215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG036(%lu) is invalid on this chip\n", block_id); 577215976Sjmallett return 0x0000000000000090ull; 578215976Sjmallett} 579215976Sjmallett#else 580215976Sjmallett#define CVMX_PCIERCX_CFG036(block_id) (0x0000000000000090ull) 581215976Sjmallett#endif 582215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 583215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG037(unsigned long block_id) 584215976Sjmallett{ 585215976Sjmallett if (!( 586215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 587215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 588232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 589232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 590232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 591232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 592232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 593215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG037(%lu) is invalid on this chip\n", block_id); 594215976Sjmallett return 0x0000000000000094ull; 595215976Sjmallett} 596215976Sjmallett#else 597215976Sjmallett#define CVMX_PCIERCX_CFG037(block_id) (0x0000000000000094ull) 598215976Sjmallett#endif 599215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 600215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG038(unsigned long block_id) 601215976Sjmallett{ 602215976Sjmallett if (!( 603215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 604215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 605232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 606232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 607232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 608232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 609232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 610215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG038(%lu) is invalid on this chip\n", block_id); 611215976Sjmallett return 0x0000000000000098ull; 612215976Sjmallett} 613215976Sjmallett#else 614215976Sjmallett#define CVMX_PCIERCX_CFG038(block_id) (0x0000000000000098ull) 615215976Sjmallett#endif 616215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 617215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG039(unsigned long block_id) 618215976Sjmallett{ 619215976Sjmallett if (!( 620215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 621215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 622232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 623232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 624232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 625232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 626232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 627215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG039(%lu) is invalid on this chip\n", block_id); 628215976Sjmallett return 0x000000000000009Cull; 629215976Sjmallett} 630215976Sjmallett#else 631215976Sjmallett#define CVMX_PCIERCX_CFG039(block_id) (0x000000000000009Cull) 632215976Sjmallett#endif 633215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 634215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG040(unsigned long block_id) 635215976Sjmallett{ 636215976Sjmallett if (!( 637215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 638215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 639232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 640232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 641232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 642232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 643232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 644215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG040(%lu) is invalid on this chip\n", block_id); 645215976Sjmallett return 0x00000000000000A0ull; 646215976Sjmallett} 647215976Sjmallett#else 648215976Sjmallett#define CVMX_PCIERCX_CFG040(block_id) (0x00000000000000A0ull) 649215976Sjmallett#endif 650215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 651215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG041(unsigned long block_id) 652215976Sjmallett{ 653215976Sjmallett if (!( 654215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 655215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 656232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 657232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 658232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 659232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 660232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 661215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG041(%lu) is invalid on this chip\n", block_id); 662215976Sjmallett return 0x00000000000000A4ull; 663215976Sjmallett} 664215976Sjmallett#else 665215976Sjmallett#define CVMX_PCIERCX_CFG041(block_id) (0x00000000000000A4ull) 666215976Sjmallett#endif 667215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 668215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG042(unsigned long block_id) 669215976Sjmallett{ 670215976Sjmallett if (!( 671215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 672215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 673232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 674232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 675232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 676232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 677232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 678215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG042(%lu) is invalid on this chip\n", block_id); 679215976Sjmallett return 0x00000000000000A8ull; 680215976Sjmallett} 681215976Sjmallett#else 682215976Sjmallett#define CVMX_PCIERCX_CFG042(block_id) (0x00000000000000A8ull) 683215976Sjmallett#endif 684215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 685215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG064(unsigned long block_id) 686215976Sjmallett{ 687215976Sjmallett if (!( 688215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 689215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 690232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 691232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 692232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 693232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 694232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 695215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG064(%lu) is invalid on this chip\n", block_id); 696215976Sjmallett return 0x0000000000000100ull; 697215976Sjmallett} 698215976Sjmallett#else 699215976Sjmallett#define CVMX_PCIERCX_CFG064(block_id) (0x0000000000000100ull) 700215976Sjmallett#endif 701215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 702215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG065(unsigned long block_id) 703215976Sjmallett{ 704215976Sjmallett if (!( 705215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 706215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 707232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 708232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 709232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 710232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 711232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 712215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG065(%lu) is invalid on this chip\n", block_id); 713215976Sjmallett return 0x0000000000000104ull; 714215976Sjmallett} 715215976Sjmallett#else 716215976Sjmallett#define CVMX_PCIERCX_CFG065(block_id) (0x0000000000000104ull) 717215976Sjmallett#endif 718215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 719215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG066(unsigned long block_id) 720215976Sjmallett{ 721215976Sjmallett if (!( 722215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 723215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 724232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 725232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 726232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 727232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 728232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 729215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG066(%lu) is invalid on this chip\n", block_id); 730215976Sjmallett return 0x0000000000000108ull; 731215976Sjmallett} 732215976Sjmallett#else 733215976Sjmallett#define CVMX_PCIERCX_CFG066(block_id) (0x0000000000000108ull) 734215976Sjmallett#endif 735215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 736215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG067(unsigned long block_id) 737215976Sjmallett{ 738215976Sjmallett if (!( 739215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 740215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 741232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 742232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 743232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 744232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 745232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 746215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG067(%lu) is invalid on this chip\n", block_id); 747215976Sjmallett return 0x000000000000010Cull; 748215976Sjmallett} 749215976Sjmallett#else 750215976Sjmallett#define CVMX_PCIERCX_CFG067(block_id) (0x000000000000010Cull) 751215976Sjmallett#endif 752215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 753215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG068(unsigned long block_id) 754215976Sjmallett{ 755215976Sjmallett if (!( 756215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 757215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 758232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 759232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 760232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 761232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 762232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 763215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG068(%lu) is invalid on this chip\n", block_id); 764215976Sjmallett return 0x0000000000000110ull; 765215976Sjmallett} 766215976Sjmallett#else 767215976Sjmallett#define CVMX_PCIERCX_CFG068(block_id) (0x0000000000000110ull) 768215976Sjmallett#endif 769215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 770215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG069(unsigned long block_id) 771215976Sjmallett{ 772215976Sjmallett if (!( 773215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 774215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 775232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 776232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 777232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 778232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 779232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 780215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG069(%lu) is invalid on this chip\n", block_id); 781215976Sjmallett return 0x0000000000000114ull; 782215976Sjmallett} 783215976Sjmallett#else 784215976Sjmallett#define CVMX_PCIERCX_CFG069(block_id) (0x0000000000000114ull) 785215976Sjmallett#endif 786215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 787215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG070(unsigned long block_id) 788215976Sjmallett{ 789215976Sjmallett if (!( 790215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 791215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 792232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 793232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 794232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 795232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 796232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 797215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG070(%lu) is invalid on this chip\n", block_id); 798215976Sjmallett return 0x0000000000000118ull; 799215976Sjmallett} 800215976Sjmallett#else 801215976Sjmallett#define CVMX_PCIERCX_CFG070(block_id) (0x0000000000000118ull) 802215976Sjmallett#endif 803215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 804215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG071(unsigned long block_id) 805215976Sjmallett{ 806215976Sjmallett if (!( 807215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 808215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 809232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 810232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 811232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 812232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 813232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 814215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG071(%lu) is invalid on this chip\n", block_id); 815215976Sjmallett return 0x000000000000011Cull; 816215976Sjmallett} 817215976Sjmallett#else 818215976Sjmallett#define CVMX_PCIERCX_CFG071(block_id) (0x000000000000011Cull) 819215976Sjmallett#endif 820215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 821215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG072(unsigned long block_id) 822215976Sjmallett{ 823215976Sjmallett if (!( 824215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 825215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 826232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 827232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 828232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 829232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 830232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 831215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG072(%lu) is invalid on this chip\n", block_id); 832215976Sjmallett return 0x0000000000000120ull; 833215976Sjmallett} 834215976Sjmallett#else 835215976Sjmallett#define CVMX_PCIERCX_CFG072(block_id) (0x0000000000000120ull) 836215976Sjmallett#endif 837215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 838215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG073(unsigned long block_id) 839215976Sjmallett{ 840215976Sjmallett if (!( 841215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 842215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 843232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 844232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 845232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 846232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 847232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 848215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG073(%lu) is invalid on this chip\n", block_id); 849215976Sjmallett return 0x0000000000000124ull; 850215976Sjmallett} 851215976Sjmallett#else 852215976Sjmallett#define CVMX_PCIERCX_CFG073(block_id) (0x0000000000000124ull) 853215976Sjmallett#endif 854215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 855215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG074(unsigned long block_id) 856215976Sjmallett{ 857215976Sjmallett if (!( 858215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 859215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 860232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 861232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 862232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 863232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 864232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 865215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG074(%lu) is invalid on this chip\n", block_id); 866215976Sjmallett return 0x0000000000000128ull; 867215976Sjmallett} 868215976Sjmallett#else 869215976Sjmallett#define CVMX_PCIERCX_CFG074(block_id) (0x0000000000000128ull) 870215976Sjmallett#endif 871215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 872215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG075(unsigned long block_id) 873215976Sjmallett{ 874215976Sjmallett if (!( 875215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 876215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 877232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 878232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 879232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 880232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 881232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 882215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG075(%lu) is invalid on this chip\n", block_id); 883215976Sjmallett return 0x000000000000012Cull; 884215976Sjmallett} 885215976Sjmallett#else 886215976Sjmallett#define CVMX_PCIERCX_CFG075(block_id) (0x000000000000012Cull) 887215976Sjmallett#endif 888215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 889215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG076(unsigned long block_id) 890215976Sjmallett{ 891215976Sjmallett if (!( 892215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 893215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 894232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 895232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 896232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 897232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 898232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 899215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG076(%lu) is invalid on this chip\n", block_id); 900215976Sjmallett return 0x0000000000000130ull; 901215976Sjmallett} 902215976Sjmallett#else 903215976Sjmallett#define CVMX_PCIERCX_CFG076(block_id) (0x0000000000000130ull) 904215976Sjmallett#endif 905215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 906215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG077(unsigned long block_id) 907215976Sjmallett{ 908215976Sjmallett if (!( 909215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 910215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 911232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 912232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 913232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 914232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 915232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 916215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG077(%lu) is invalid on this chip\n", block_id); 917215976Sjmallett return 0x0000000000000134ull; 918215976Sjmallett} 919215976Sjmallett#else 920215976Sjmallett#define CVMX_PCIERCX_CFG077(block_id) (0x0000000000000134ull) 921215976Sjmallett#endif 922215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 923215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG448(unsigned long block_id) 924215976Sjmallett{ 925215976Sjmallett if (!( 926215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 927215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 928232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 929232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 930232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 931232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 932232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 933215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG448(%lu) is invalid on this chip\n", block_id); 934215976Sjmallett return 0x0000000000000700ull; 935215976Sjmallett} 936215976Sjmallett#else 937215976Sjmallett#define CVMX_PCIERCX_CFG448(block_id) (0x0000000000000700ull) 938215976Sjmallett#endif 939215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 940215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG449(unsigned long block_id) 941215976Sjmallett{ 942215976Sjmallett if (!( 943215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 944215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 945232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 946232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 947232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 948232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 949232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 950215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG449(%lu) is invalid on this chip\n", block_id); 951215976Sjmallett return 0x0000000000000704ull; 952215976Sjmallett} 953215976Sjmallett#else 954215976Sjmallett#define CVMX_PCIERCX_CFG449(block_id) (0x0000000000000704ull) 955215976Sjmallett#endif 956215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 957215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG450(unsigned long block_id) 958215976Sjmallett{ 959215976Sjmallett if (!( 960215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 961215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 962232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 963232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 964232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 965232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 966232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 967215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG450(%lu) is invalid on this chip\n", block_id); 968215976Sjmallett return 0x0000000000000708ull; 969215976Sjmallett} 970215976Sjmallett#else 971215976Sjmallett#define CVMX_PCIERCX_CFG450(block_id) (0x0000000000000708ull) 972215976Sjmallett#endif 973215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 974215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG451(unsigned long block_id) 975215976Sjmallett{ 976215976Sjmallett if (!( 977215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 978215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 979232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 980232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 981232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 982232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 983232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 984215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG451(%lu) is invalid on this chip\n", block_id); 985215976Sjmallett return 0x000000000000070Cull; 986215976Sjmallett} 987215976Sjmallett#else 988215976Sjmallett#define CVMX_PCIERCX_CFG451(block_id) (0x000000000000070Cull) 989215976Sjmallett#endif 990215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 991215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG452(unsigned long block_id) 992215976Sjmallett{ 993215976Sjmallett if (!( 994215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 995215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 996232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 997232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 998232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 999232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1000232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1001215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG452(%lu) is invalid on this chip\n", block_id); 1002215976Sjmallett return 0x0000000000000710ull; 1003215976Sjmallett} 1004215976Sjmallett#else 1005215976Sjmallett#define CVMX_PCIERCX_CFG452(block_id) (0x0000000000000710ull) 1006215976Sjmallett#endif 1007215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1008215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG453(unsigned long block_id) 1009215976Sjmallett{ 1010215976Sjmallett if (!( 1011215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1012215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1013232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1014232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1015232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1016232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1017232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1018215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG453(%lu) is invalid on this chip\n", block_id); 1019215976Sjmallett return 0x0000000000000714ull; 1020215976Sjmallett} 1021215976Sjmallett#else 1022215976Sjmallett#define CVMX_PCIERCX_CFG453(block_id) (0x0000000000000714ull) 1023215976Sjmallett#endif 1024215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1025215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG454(unsigned long block_id) 1026215976Sjmallett{ 1027215976Sjmallett if (!( 1028215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1029215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1030232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1031232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1032232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1033232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1034232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1035215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG454(%lu) is invalid on this chip\n", block_id); 1036215976Sjmallett return 0x0000000000000718ull; 1037215976Sjmallett} 1038215976Sjmallett#else 1039215976Sjmallett#define CVMX_PCIERCX_CFG454(block_id) (0x0000000000000718ull) 1040215976Sjmallett#endif 1041215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1042215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG455(unsigned long block_id) 1043215976Sjmallett{ 1044215976Sjmallett if (!( 1045215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1046215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1047232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1048232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1049232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1050232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1051232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1052215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG455(%lu) is invalid on this chip\n", block_id); 1053215976Sjmallett return 0x000000000000071Cull; 1054215976Sjmallett} 1055215976Sjmallett#else 1056215976Sjmallett#define CVMX_PCIERCX_CFG455(block_id) (0x000000000000071Cull) 1057215976Sjmallett#endif 1058215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1059215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG456(unsigned long block_id) 1060215976Sjmallett{ 1061215976Sjmallett if (!( 1062215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1063215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1064232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1065232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1066232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1067232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1068232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1069215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG456(%lu) is invalid on this chip\n", block_id); 1070215976Sjmallett return 0x0000000000000720ull; 1071215976Sjmallett} 1072215976Sjmallett#else 1073215976Sjmallett#define CVMX_PCIERCX_CFG456(block_id) (0x0000000000000720ull) 1074215976Sjmallett#endif 1075215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1076215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG458(unsigned long block_id) 1077215976Sjmallett{ 1078215976Sjmallett if (!( 1079215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1080215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1081232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1082232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1083232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1084232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1085232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1086215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG458(%lu) is invalid on this chip\n", block_id); 1087215976Sjmallett return 0x0000000000000728ull; 1088215976Sjmallett} 1089215976Sjmallett#else 1090215976Sjmallett#define CVMX_PCIERCX_CFG458(block_id) (0x0000000000000728ull) 1091215976Sjmallett#endif 1092215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1093215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG459(unsigned long block_id) 1094215976Sjmallett{ 1095215976Sjmallett if (!( 1096215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1097215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1098232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1099232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1100232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1101232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1102232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1103215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG459(%lu) is invalid on this chip\n", block_id); 1104215976Sjmallett return 0x000000000000072Cull; 1105215976Sjmallett} 1106215976Sjmallett#else 1107215976Sjmallett#define CVMX_PCIERCX_CFG459(block_id) (0x000000000000072Cull) 1108215976Sjmallett#endif 1109215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1110215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG460(unsigned long block_id) 1111215976Sjmallett{ 1112215976Sjmallett if (!( 1113215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1114215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1115232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1116232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1117232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1118232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1119232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1120215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG460(%lu) is invalid on this chip\n", block_id); 1121215976Sjmallett return 0x0000000000000730ull; 1122215976Sjmallett} 1123215976Sjmallett#else 1124215976Sjmallett#define CVMX_PCIERCX_CFG460(block_id) (0x0000000000000730ull) 1125215976Sjmallett#endif 1126215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1127215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG461(unsigned long block_id) 1128215976Sjmallett{ 1129215976Sjmallett if (!( 1130215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1131215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1132232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1133232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1134232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1135232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1136232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1137215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG461(%lu) is invalid on this chip\n", block_id); 1138215976Sjmallett return 0x0000000000000734ull; 1139215976Sjmallett} 1140215976Sjmallett#else 1141215976Sjmallett#define CVMX_PCIERCX_CFG461(block_id) (0x0000000000000734ull) 1142215976Sjmallett#endif 1143215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1144215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG462(unsigned long block_id) 1145215976Sjmallett{ 1146215976Sjmallett if (!( 1147215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1148215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1149232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1150232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1151232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1152232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1153232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1154215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG462(%lu) is invalid on this chip\n", block_id); 1155215976Sjmallett return 0x0000000000000738ull; 1156215976Sjmallett} 1157215976Sjmallett#else 1158215976Sjmallett#define CVMX_PCIERCX_CFG462(block_id) (0x0000000000000738ull) 1159215976Sjmallett#endif 1160215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1161215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG463(unsigned long block_id) 1162215976Sjmallett{ 1163215976Sjmallett if (!( 1164215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1165215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1166232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1167232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1168232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1169232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1170232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1171215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG463(%lu) is invalid on this chip\n", block_id); 1172215976Sjmallett return 0x000000000000073Cull; 1173215976Sjmallett} 1174215976Sjmallett#else 1175215976Sjmallett#define CVMX_PCIERCX_CFG463(block_id) (0x000000000000073Cull) 1176215976Sjmallett#endif 1177215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1178215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG464(unsigned long block_id) 1179215976Sjmallett{ 1180215976Sjmallett if (!( 1181215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1182215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1183232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1184232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1185232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1186232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1187232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1188215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG464(%lu) is invalid on this chip\n", block_id); 1189215976Sjmallett return 0x0000000000000740ull; 1190215976Sjmallett} 1191215976Sjmallett#else 1192215976Sjmallett#define CVMX_PCIERCX_CFG464(block_id) (0x0000000000000740ull) 1193215976Sjmallett#endif 1194215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1195215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG465(unsigned long block_id) 1196215976Sjmallett{ 1197215976Sjmallett if (!( 1198215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1199215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1200232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1201232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1202232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1203232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1204232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1205215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG465(%lu) is invalid on this chip\n", block_id); 1206215976Sjmallett return 0x0000000000000744ull; 1207215976Sjmallett} 1208215976Sjmallett#else 1209215976Sjmallett#define CVMX_PCIERCX_CFG465(block_id) (0x0000000000000744ull) 1210215976Sjmallett#endif 1211215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1212215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG466(unsigned long block_id) 1213215976Sjmallett{ 1214215976Sjmallett if (!( 1215215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1216215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1217232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1218232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1219232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1220232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1221232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1222215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG466(%lu) is invalid on this chip\n", block_id); 1223215976Sjmallett return 0x0000000000000748ull; 1224215976Sjmallett} 1225215976Sjmallett#else 1226215976Sjmallett#define CVMX_PCIERCX_CFG466(block_id) (0x0000000000000748ull) 1227215976Sjmallett#endif 1228215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1229215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG467(unsigned long block_id) 1230215976Sjmallett{ 1231215976Sjmallett if (!( 1232215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1233215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1234232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1235232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1236232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1237232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1238232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1239215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG467(%lu) is invalid on this chip\n", block_id); 1240215976Sjmallett return 0x000000000000074Cull; 1241215976Sjmallett} 1242215976Sjmallett#else 1243215976Sjmallett#define CVMX_PCIERCX_CFG467(block_id) (0x000000000000074Cull) 1244215976Sjmallett#endif 1245215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1246215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG468(unsigned long block_id) 1247215976Sjmallett{ 1248215976Sjmallett if (!( 1249215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1250215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1251232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1252232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1253232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1254232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1255232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1256215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG468(%lu) is invalid on this chip\n", block_id); 1257215976Sjmallett return 0x0000000000000750ull; 1258215976Sjmallett} 1259215976Sjmallett#else 1260215976Sjmallett#define CVMX_PCIERCX_CFG468(block_id) (0x0000000000000750ull) 1261215976Sjmallett#endif 1262215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1263215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG490(unsigned long block_id) 1264215976Sjmallett{ 1265215976Sjmallett if (!( 1266215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1267215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1268232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1269232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1270232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1271232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1272232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1273215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG490(%lu) is invalid on this chip\n", block_id); 1274215976Sjmallett return 0x00000000000007A8ull; 1275215976Sjmallett} 1276215976Sjmallett#else 1277215976Sjmallett#define CVMX_PCIERCX_CFG490(block_id) (0x00000000000007A8ull) 1278215976Sjmallett#endif 1279215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1280215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG491(unsigned long block_id) 1281215976Sjmallett{ 1282215976Sjmallett if (!( 1283215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1284215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1285232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1286232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1287232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1288232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1289232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1290215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG491(%lu) is invalid on this chip\n", block_id); 1291215976Sjmallett return 0x00000000000007ACull; 1292215976Sjmallett} 1293215976Sjmallett#else 1294215976Sjmallett#define CVMX_PCIERCX_CFG491(block_id) (0x00000000000007ACull) 1295215976Sjmallett#endif 1296215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1297215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG492(unsigned long block_id) 1298215976Sjmallett{ 1299215976Sjmallett if (!( 1300215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1301215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1302232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1303232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1304232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1305232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1306232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1307215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG492(%lu) is invalid on this chip\n", block_id); 1308215976Sjmallett return 0x00000000000007B0ull; 1309215976Sjmallett} 1310215976Sjmallett#else 1311215976Sjmallett#define CVMX_PCIERCX_CFG492(block_id) (0x00000000000007B0ull) 1312215976Sjmallett#endif 1313215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1314215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG515(unsigned long block_id) 1315215976Sjmallett{ 1316215976Sjmallett if (!( 1317232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1318232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1319232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1320232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1321232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1322215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG515(%lu) is invalid on this chip\n", block_id); 1323215976Sjmallett return 0x000000000000080Cull; 1324215976Sjmallett} 1325215976Sjmallett#else 1326215976Sjmallett#define CVMX_PCIERCX_CFG515(block_id) (0x000000000000080Cull) 1327215976Sjmallett#endif 1328215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1329215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG516(unsigned long block_id) 1330215976Sjmallett{ 1331215976Sjmallett if (!( 1332215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1333215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1334232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1335232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1336232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1337232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1338232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1339215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG516(%lu) is invalid on this chip\n", block_id); 1340215976Sjmallett return 0x0000000000000810ull; 1341215976Sjmallett} 1342215976Sjmallett#else 1343215976Sjmallett#define CVMX_PCIERCX_CFG516(block_id) (0x0000000000000810ull) 1344215976Sjmallett#endif 1345215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1346215976Sjmallettstatic inline uint64_t CVMX_PCIERCX_CFG517(unsigned long block_id) 1347215976Sjmallett{ 1348215976Sjmallett if (!( 1349215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((block_id <= 1))) || 1350215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((block_id <= 1))) || 1351232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((block_id <= 1))) || 1352232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((block_id <= 1))) || 1353232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((block_id <= 1))) || 1354232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CN68XX) && ((block_id <= 1))) || 1355232812Sjmallett (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((block_id <= 1))))) 1356215976Sjmallett cvmx_warn("CVMX_PCIERCX_CFG517(%lu) is invalid on this chip\n", block_id); 1357215976Sjmallett return 0x0000000000000814ull; 1358215976Sjmallett} 1359215976Sjmallett#else 1360215976Sjmallett#define CVMX_PCIERCX_CFG517(block_id) (0x0000000000000814ull) 1361215976Sjmallett#endif 1362215976Sjmallett 1363215976Sjmallett/** 1364215976Sjmallett * cvmx_pcierc#_cfg000 1365215976Sjmallett * 1366215976Sjmallett * PCIE_CFG000 = First 32-bits of PCIE type 1 config space (Device ID and Vendor ID Register) 1367215976Sjmallett * 1368215976Sjmallett */ 1369232812Sjmallettunion cvmx_pciercx_cfg000 { 1370215976Sjmallett uint32_t u32; 1371232812Sjmallett struct cvmx_pciercx_cfg000_s { 1372232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1373215976Sjmallett uint32_t devid : 16; /**< Device ID, writable through PEM(0..1)_CFG_WR 1374215976Sjmallett However, the application must not change this field. */ 1375215976Sjmallett uint32_t vendid : 16; /**< Vendor ID, writable through PEM(0..1)_CFG_WR 1376215976Sjmallett However, the application must not change this field. */ 1377215976Sjmallett#else 1378215976Sjmallett uint32_t vendid : 16; 1379215976Sjmallett uint32_t devid : 16; 1380215976Sjmallett#endif 1381215976Sjmallett } s; 1382215976Sjmallett struct cvmx_pciercx_cfg000_s cn52xx; 1383215976Sjmallett struct cvmx_pciercx_cfg000_s cn52xxp1; 1384215976Sjmallett struct cvmx_pciercx_cfg000_s cn56xx; 1385215976Sjmallett struct cvmx_pciercx_cfg000_s cn56xxp1; 1386232812Sjmallett struct cvmx_pciercx_cfg000_s cn61xx; 1387215976Sjmallett struct cvmx_pciercx_cfg000_s cn63xx; 1388215976Sjmallett struct cvmx_pciercx_cfg000_s cn63xxp1; 1389232812Sjmallett struct cvmx_pciercx_cfg000_s cn66xx; 1390232812Sjmallett struct cvmx_pciercx_cfg000_s cn68xx; 1391232812Sjmallett struct cvmx_pciercx_cfg000_s cn68xxp1; 1392232812Sjmallett struct cvmx_pciercx_cfg000_s cnf71xx; 1393215976Sjmallett}; 1394215976Sjmalletttypedef union cvmx_pciercx_cfg000 cvmx_pciercx_cfg000_t; 1395215976Sjmallett 1396215976Sjmallett/** 1397215976Sjmallett * cvmx_pcierc#_cfg001 1398215976Sjmallett * 1399215976Sjmallett * PCIE_CFG001 = Second 32-bits of PCIE type 1 config space (Command/Status Register) 1400215976Sjmallett * 1401215976Sjmallett */ 1402232812Sjmallettunion cvmx_pciercx_cfg001 { 1403215976Sjmallett uint32_t u32; 1404232812Sjmallett struct cvmx_pciercx_cfg001_s { 1405232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1406215976Sjmallett uint32_t dpe : 1; /**< Detected Parity Error */ 1407215976Sjmallett uint32_t sse : 1; /**< Signaled System Error */ 1408215976Sjmallett uint32_t rma : 1; /**< Received Master Abort */ 1409215976Sjmallett uint32_t rta : 1; /**< Received Target Abort */ 1410215976Sjmallett uint32_t sta : 1; /**< Signaled Target Abort */ 1411215976Sjmallett uint32_t devt : 2; /**< DEVSEL Timing 1412215976Sjmallett Not applicable for PCI Express. Hardwired to 0. */ 1413215976Sjmallett uint32_t mdpe : 1; /**< Master Data Parity Error */ 1414215976Sjmallett uint32_t fbb : 1; /**< Fast Back-to-Back Capable 1415215976Sjmallett Not applicable for PCI Express. Hardwired to 0. */ 1416215976Sjmallett uint32_t reserved_22_22 : 1; 1417215976Sjmallett uint32_t m66 : 1; /**< 66 MHz Capable 1418215976Sjmallett Not applicable for PCI Express. Hardwired to 0. */ 1419215976Sjmallett uint32_t cl : 1; /**< Capabilities List 1420215976Sjmallett Indicates presence of an extended capability item. 1421215976Sjmallett Hardwired to 1. */ 1422215976Sjmallett uint32_t i_stat : 1; /**< INTx Status */ 1423215976Sjmallett uint32_t reserved_11_18 : 8; 1424215976Sjmallett uint32_t i_dis : 1; /**< INTx Assertion Disable */ 1425215976Sjmallett uint32_t fbbe : 1; /**< Fast Back-to-Back Enable 1426215976Sjmallett Not applicable for PCI Express. Must be hardwired to 0. */ 1427215976Sjmallett uint32_t see : 1; /**< SERR# Enable */ 1428215976Sjmallett uint32_t ids_wcc : 1; /**< IDSEL Stepping/Wait Cycle Control 1429215976Sjmallett Not applicable for PCI Express. Must be hardwired to 0 */ 1430215976Sjmallett uint32_t per : 1; /**< Parity Error Response */ 1431215976Sjmallett uint32_t vps : 1; /**< VGA Palette Snoop 1432215976Sjmallett Not applicable for PCI Express. Must be hardwired to 0. */ 1433215976Sjmallett uint32_t mwice : 1; /**< Memory Write and Invalidate 1434215976Sjmallett Not applicable for PCI Express. Must be hardwired to 0. */ 1435215976Sjmallett uint32_t scse : 1; /**< Special Cycle Enable 1436215976Sjmallett Not applicable for PCI Express. Must be hardwired to 0. */ 1437215976Sjmallett uint32_t me : 1; /**< Bus Master Enable */ 1438215976Sjmallett uint32_t msae : 1; /**< Memory Space Enable */ 1439215976Sjmallett uint32_t isae : 1; /**< I/O Space Enable */ 1440215976Sjmallett#else 1441215976Sjmallett uint32_t isae : 1; 1442215976Sjmallett uint32_t msae : 1; 1443215976Sjmallett uint32_t me : 1; 1444215976Sjmallett uint32_t scse : 1; 1445215976Sjmallett uint32_t mwice : 1; 1446215976Sjmallett uint32_t vps : 1; 1447215976Sjmallett uint32_t per : 1; 1448215976Sjmallett uint32_t ids_wcc : 1; 1449215976Sjmallett uint32_t see : 1; 1450215976Sjmallett uint32_t fbbe : 1; 1451215976Sjmallett uint32_t i_dis : 1; 1452215976Sjmallett uint32_t reserved_11_18 : 8; 1453215976Sjmallett uint32_t i_stat : 1; 1454215976Sjmallett uint32_t cl : 1; 1455215976Sjmallett uint32_t m66 : 1; 1456215976Sjmallett uint32_t reserved_22_22 : 1; 1457215976Sjmallett uint32_t fbb : 1; 1458215976Sjmallett uint32_t mdpe : 1; 1459215976Sjmallett uint32_t devt : 2; 1460215976Sjmallett uint32_t sta : 1; 1461215976Sjmallett uint32_t rta : 1; 1462215976Sjmallett uint32_t rma : 1; 1463215976Sjmallett uint32_t sse : 1; 1464215976Sjmallett uint32_t dpe : 1; 1465215976Sjmallett#endif 1466215976Sjmallett } s; 1467215976Sjmallett struct cvmx_pciercx_cfg001_s cn52xx; 1468215976Sjmallett struct cvmx_pciercx_cfg001_s cn52xxp1; 1469215976Sjmallett struct cvmx_pciercx_cfg001_s cn56xx; 1470215976Sjmallett struct cvmx_pciercx_cfg001_s cn56xxp1; 1471232812Sjmallett struct cvmx_pciercx_cfg001_s cn61xx; 1472215976Sjmallett struct cvmx_pciercx_cfg001_s cn63xx; 1473215976Sjmallett struct cvmx_pciercx_cfg001_s cn63xxp1; 1474232812Sjmallett struct cvmx_pciercx_cfg001_s cn66xx; 1475232812Sjmallett struct cvmx_pciercx_cfg001_s cn68xx; 1476232812Sjmallett struct cvmx_pciercx_cfg001_s cn68xxp1; 1477232812Sjmallett struct cvmx_pciercx_cfg001_s cnf71xx; 1478215976Sjmallett}; 1479215976Sjmalletttypedef union cvmx_pciercx_cfg001 cvmx_pciercx_cfg001_t; 1480215976Sjmallett 1481215976Sjmallett/** 1482215976Sjmallett * cvmx_pcierc#_cfg002 1483215976Sjmallett * 1484215976Sjmallett * PCIE_CFG002 = Third 32-bits of PCIE type 1 config space (Revision ID/Class Code Register) 1485215976Sjmallett * 1486215976Sjmallett */ 1487232812Sjmallettunion cvmx_pciercx_cfg002 { 1488215976Sjmallett uint32_t u32; 1489232812Sjmallett struct cvmx_pciercx_cfg002_s { 1490232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1491215976Sjmallett uint32_t bcc : 8; /**< Base Class Code, writable through PEM(0..1)_CFG_WR 1492215976Sjmallett However, the application must not change this field. */ 1493215976Sjmallett uint32_t sc : 8; /**< Subclass Code, writable through PEM(0..1)_CFG_WR 1494215976Sjmallett However, the application must not change this field. */ 1495215976Sjmallett uint32_t pi : 8; /**< Programming Interface, writable through PEM(0..1)_CFG_WR 1496215976Sjmallett However, the application must not change this field. */ 1497215976Sjmallett uint32_t rid : 8; /**< Revision ID, writable through PEM(0..1)_CFG_WR 1498215976Sjmallett However, the application must not change this field. */ 1499215976Sjmallett#else 1500215976Sjmallett uint32_t rid : 8; 1501215976Sjmallett uint32_t pi : 8; 1502215976Sjmallett uint32_t sc : 8; 1503215976Sjmallett uint32_t bcc : 8; 1504215976Sjmallett#endif 1505215976Sjmallett } s; 1506215976Sjmallett struct cvmx_pciercx_cfg002_s cn52xx; 1507215976Sjmallett struct cvmx_pciercx_cfg002_s cn52xxp1; 1508215976Sjmallett struct cvmx_pciercx_cfg002_s cn56xx; 1509215976Sjmallett struct cvmx_pciercx_cfg002_s cn56xxp1; 1510232812Sjmallett struct cvmx_pciercx_cfg002_s cn61xx; 1511215976Sjmallett struct cvmx_pciercx_cfg002_s cn63xx; 1512215976Sjmallett struct cvmx_pciercx_cfg002_s cn63xxp1; 1513232812Sjmallett struct cvmx_pciercx_cfg002_s cn66xx; 1514232812Sjmallett struct cvmx_pciercx_cfg002_s cn68xx; 1515232812Sjmallett struct cvmx_pciercx_cfg002_s cn68xxp1; 1516232812Sjmallett struct cvmx_pciercx_cfg002_s cnf71xx; 1517215976Sjmallett}; 1518215976Sjmalletttypedef union cvmx_pciercx_cfg002 cvmx_pciercx_cfg002_t; 1519215976Sjmallett 1520215976Sjmallett/** 1521215976Sjmallett * cvmx_pcierc#_cfg003 1522215976Sjmallett * 1523215976Sjmallett * PCIE_CFG003 = Fourth 32-bits of PCIE type 1 config space (Cache Line Size/Master Latency Timer/Header Type Register/BIST Register) 1524215976Sjmallett * 1525215976Sjmallett */ 1526232812Sjmallettunion cvmx_pciercx_cfg003 { 1527215976Sjmallett uint32_t u32; 1528232812Sjmallett struct cvmx_pciercx_cfg003_s { 1529232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1530215976Sjmallett uint32_t bist : 8; /**< The BIST register functions are not supported. 1531215976Sjmallett All 8 bits of the BIST register are hardwired to 0. */ 1532215976Sjmallett uint32_t mfd : 1; /**< Multi Function Device 1533215976Sjmallett The Multi Function Device bit is writable through PEM(0..1)_CFG_WR. 1534215976Sjmallett However, this is a single function device. Therefore, the 1535215976Sjmallett application must not write a 1 to this bit. */ 1536215976Sjmallett uint32_t chf : 7; /**< Configuration Header Format 1537215976Sjmallett Hardwired to 1. */ 1538215976Sjmallett uint32_t lt : 8; /**< Master Latency Timer 1539215976Sjmallett Not applicable for PCI Express, hardwired to 0. */ 1540215976Sjmallett uint32_t cls : 8; /**< Cache Line Size 1541215976Sjmallett The Cache Line Size register is RW for legacy compatibility 1542215976Sjmallett purposes and is not applicable to PCI Express device 1543215976Sjmallett functionality. */ 1544215976Sjmallett#else 1545215976Sjmallett uint32_t cls : 8; 1546215976Sjmallett uint32_t lt : 8; 1547215976Sjmallett uint32_t chf : 7; 1548215976Sjmallett uint32_t mfd : 1; 1549215976Sjmallett uint32_t bist : 8; 1550215976Sjmallett#endif 1551215976Sjmallett } s; 1552215976Sjmallett struct cvmx_pciercx_cfg003_s cn52xx; 1553215976Sjmallett struct cvmx_pciercx_cfg003_s cn52xxp1; 1554215976Sjmallett struct cvmx_pciercx_cfg003_s cn56xx; 1555215976Sjmallett struct cvmx_pciercx_cfg003_s cn56xxp1; 1556232812Sjmallett struct cvmx_pciercx_cfg003_s cn61xx; 1557215976Sjmallett struct cvmx_pciercx_cfg003_s cn63xx; 1558215976Sjmallett struct cvmx_pciercx_cfg003_s cn63xxp1; 1559232812Sjmallett struct cvmx_pciercx_cfg003_s cn66xx; 1560232812Sjmallett struct cvmx_pciercx_cfg003_s cn68xx; 1561232812Sjmallett struct cvmx_pciercx_cfg003_s cn68xxp1; 1562232812Sjmallett struct cvmx_pciercx_cfg003_s cnf71xx; 1563215976Sjmallett}; 1564215976Sjmalletttypedef union cvmx_pciercx_cfg003 cvmx_pciercx_cfg003_t; 1565215976Sjmallett 1566215976Sjmallett/** 1567215976Sjmallett * cvmx_pcierc#_cfg004 1568215976Sjmallett * 1569215976Sjmallett * PCIE_CFG004 = Fifth 32-bits of PCIE type 1 config space (Base Address Register 0 - Low) 1570215976Sjmallett * 1571215976Sjmallett */ 1572232812Sjmallettunion cvmx_pciercx_cfg004 { 1573215976Sjmallett uint32_t u32; 1574232812Sjmallett struct cvmx_pciercx_cfg004_s { 1575232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1576215976Sjmallett uint32_t reserved_0_31 : 32; 1577215976Sjmallett#else 1578215976Sjmallett uint32_t reserved_0_31 : 32; 1579215976Sjmallett#endif 1580215976Sjmallett } s; 1581215976Sjmallett struct cvmx_pciercx_cfg004_s cn52xx; 1582215976Sjmallett struct cvmx_pciercx_cfg004_s cn52xxp1; 1583215976Sjmallett struct cvmx_pciercx_cfg004_s cn56xx; 1584215976Sjmallett struct cvmx_pciercx_cfg004_s cn56xxp1; 1585232812Sjmallett struct cvmx_pciercx_cfg004_s cn61xx; 1586215976Sjmallett struct cvmx_pciercx_cfg004_s cn63xx; 1587215976Sjmallett struct cvmx_pciercx_cfg004_s cn63xxp1; 1588232812Sjmallett struct cvmx_pciercx_cfg004_s cn66xx; 1589232812Sjmallett struct cvmx_pciercx_cfg004_s cn68xx; 1590232812Sjmallett struct cvmx_pciercx_cfg004_s cn68xxp1; 1591232812Sjmallett struct cvmx_pciercx_cfg004_s cnf71xx; 1592215976Sjmallett}; 1593215976Sjmalletttypedef union cvmx_pciercx_cfg004 cvmx_pciercx_cfg004_t; 1594215976Sjmallett 1595215976Sjmallett/** 1596215976Sjmallett * cvmx_pcierc#_cfg005 1597215976Sjmallett * 1598215976Sjmallett * PCIE_CFG005 = Sixth 32-bits of PCIE type 1 config space (Base Address Register 0 - High) 1599215976Sjmallett * 1600215976Sjmallett */ 1601232812Sjmallettunion cvmx_pciercx_cfg005 { 1602215976Sjmallett uint32_t u32; 1603232812Sjmallett struct cvmx_pciercx_cfg005_s { 1604232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1605215976Sjmallett uint32_t reserved_0_31 : 32; 1606215976Sjmallett#else 1607215976Sjmallett uint32_t reserved_0_31 : 32; 1608215976Sjmallett#endif 1609215976Sjmallett } s; 1610215976Sjmallett struct cvmx_pciercx_cfg005_s cn52xx; 1611215976Sjmallett struct cvmx_pciercx_cfg005_s cn52xxp1; 1612215976Sjmallett struct cvmx_pciercx_cfg005_s cn56xx; 1613215976Sjmallett struct cvmx_pciercx_cfg005_s cn56xxp1; 1614232812Sjmallett struct cvmx_pciercx_cfg005_s cn61xx; 1615215976Sjmallett struct cvmx_pciercx_cfg005_s cn63xx; 1616215976Sjmallett struct cvmx_pciercx_cfg005_s cn63xxp1; 1617232812Sjmallett struct cvmx_pciercx_cfg005_s cn66xx; 1618232812Sjmallett struct cvmx_pciercx_cfg005_s cn68xx; 1619232812Sjmallett struct cvmx_pciercx_cfg005_s cn68xxp1; 1620232812Sjmallett struct cvmx_pciercx_cfg005_s cnf71xx; 1621215976Sjmallett}; 1622215976Sjmalletttypedef union cvmx_pciercx_cfg005 cvmx_pciercx_cfg005_t; 1623215976Sjmallett 1624215976Sjmallett/** 1625215976Sjmallett * cvmx_pcierc#_cfg006 1626215976Sjmallett * 1627215976Sjmallett * PCIE_CFG006 = Seventh 32-bits of PCIE type 1 config space (Bus Number Registers) 1628215976Sjmallett * 1629215976Sjmallett */ 1630232812Sjmallettunion cvmx_pciercx_cfg006 { 1631215976Sjmallett uint32_t u32; 1632232812Sjmallett struct cvmx_pciercx_cfg006_s { 1633232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1634215976Sjmallett uint32_t slt : 8; /**< Secondary Latency Timer 1635215976Sjmallett Not applicable to PCI Express, hardwired to 0x00. */ 1636215976Sjmallett uint32_t subbnum : 8; /**< Subordinate Bus Number */ 1637215976Sjmallett uint32_t sbnum : 8; /**< Secondary Bus Number */ 1638215976Sjmallett uint32_t pbnum : 8; /**< Primary Bus Number */ 1639215976Sjmallett#else 1640215976Sjmallett uint32_t pbnum : 8; 1641215976Sjmallett uint32_t sbnum : 8; 1642215976Sjmallett uint32_t subbnum : 8; 1643215976Sjmallett uint32_t slt : 8; 1644215976Sjmallett#endif 1645215976Sjmallett } s; 1646215976Sjmallett struct cvmx_pciercx_cfg006_s cn52xx; 1647215976Sjmallett struct cvmx_pciercx_cfg006_s cn52xxp1; 1648215976Sjmallett struct cvmx_pciercx_cfg006_s cn56xx; 1649215976Sjmallett struct cvmx_pciercx_cfg006_s cn56xxp1; 1650232812Sjmallett struct cvmx_pciercx_cfg006_s cn61xx; 1651215976Sjmallett struct cvmx_pciercx_cfg006_s cn63xx; 1652215976Sjmallett struct cvmx_pciercx_cfg006_s cn63xxp1; 1653232812Sjmallett struct cvmx_pciercx_cfg006_s cn66xx; 1654232812Sjmallett struct cvmx_pciercx_cfg006_s cn68xx; 1655232812Sjmallett struct cvmx_pciercx_cfg006_s cn68xxp1; 1656232812Sjmallett struct cvmx_pciercx_cfg006_s cnf71xx; 1657215976Sjmallett}; 1658215976Sjmalletttypedef union cvmx_pciercx_cfg006 cvmx_pciercx_cfg006_t; 1659215976Sjmallett 1660215976Sjmallett/** 1661215976Sjmallett * cvmx_pcierc#_cfg007 1662215976Sjmallett * 1663215976Sjmallett * PCIE_CFG007 = Eighth 32-bits of PCIE type 1 config space (IO Base and IO Limit/Secondary Status Register) 1664215976Sjmallett * 1665215976Sjmallett */ 1666232812Sjmallettunion cvmx_pciercx_cfg007 { 1667215976Sjmallett uint32_t u32; 1668232812Sjmallett struct cvmx_pciercx_cfg007_s { 1669232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1670215976Sjmallett uint32_t dpe : 1; /**< Detected Parity Error */ 1671215976Sjmallett uint32_t sse : 1; /**< Signaled System Error */ 1672215976Sjmallett uint32_t rma : 1; /**< Received Master Abort */ 1673215976Sjmallett uint32_t rta : 1; /**< Received Target Abort */ 1674215976Sjmallett uint32_t sta : 1; /**< Signaled Target Abort */ 1675215976Sjmallett uint32_t devt : 2; /**< DEVSEL Timing 1676215976Sjmallett Not applicable for PCI Express. Hardwired to 0. */ 1677215976Sjmallett uint32_t mdpe : 1; /**< Master Data Parity Error */ 1678215976Sjmallett uint32_t fbb : 1; /**< Fast Back-to-Back Capable 1679215976Sjmallett Not applicable for PCI Express. Hardwired to 0. */ 1680215976Sjmallett uint32_t reserved_22_22 : 1; 1681215976Sjmallett uint32_t m66 : 1; /**< 66 MHz Capable 1682215976Sjmallett Not applicable for PCI Express. Hardwired to 0. */ 1683215976Sjmallett uint32_t reserved_16_20 : 5; 1684215976Sjmallett uint32_t lio_limi : 4; /**< I/O Space Limit */ 1685215976Sjmallett uint32_t reserved_9_11 : 3; 1686215976Sjmallett uint32_t io32b : 1; /**< 32-Bit I/O Space */ 1687215976Sjmallett uint32_t lio_base : 4; /**< I/O Space Base */ 1688215976Sjmallett uint32_t reserved_1_3 : 3; 1689215976Sjmallett uint32_t io32a : 1; /**< 32-Bit I/O Space 1690215976Sjmallett o 0 = 16-bit I/O addressing 1691215976Sjmallett o 1 = 32-bit I/O addressing 1692215976Sjmallett This bit is writable through PEM(0..1)_CFG_WR. 1693215976Sjmallett When the application 1694215976Sjmallett writes to this bit through PEM(0..1)_CFG_WR, 1695215976Sjmallett the same value is written 1696215976Sjmallett to bit 8 of this register. */ 1697215976Sjmallett#else 1698215976Sjmallett uint32_t io32a : 1; 1699215976Sjmallett uint32_t reserved_1_3 : 3; 1700215976Sjmallett uint32_t lio_base : 4; 1701215976Sjmallett uint32_t io32b : 1; 1702215976Sjmallett uint32_t reserved_9_11 : 3; 1703215976Sjmallett uint32_t lio_limi : 4; 1704215976Sjmallett uint32_t reserved_16_20 : 5; 1705215976Sjmallett uint32_t m66 : 1; 1706215976Sjmallett uint32_t reserved_22_22 : 1; 1707215976Sjmallett uint32_t fbb : 1; 1708215976Sjmallett uint32_t mdpe : 1; 1709215976Sjmallett uint32_t devt : 2; 1710215976Sjmallett uint32_t sta : 1; 1711215976Sjmallett uint32_t rta : 1; 1712215976Sjmallett uint32_t rma : 1; 1713215976Sjmallett uint32_t sse : 1; 1714215976Sjmallett uint32_t dpe : 1; 1715215976Sjmallett#endif 1716215976Sjmallett } s; 1717215976Sjmallett struct cvmx_pciercx_cfg007_s cn52xx; 1718215976Sjmallett struct cvmx_pciercx_cfg007_s cn52xxp1; 1719215976Sjmallett struct cvmx_pciercx_cfg007_s cn56xx; 1720215976Sjmallett struct cvmx_pciercx_cfg007_s cn56xxp1; 1721232812Sjmallett struct cvmx_pciercx_cfg007_s cn61xx; 1722215976Sjmallett struct cvmx_pciercx_cfg007_s cn63xx; 1723215976Sjmallett struct cvmx_pciercx_cfg007_s cn63xxp1; 1724232812Sjmallett struct cvmx_pciercx_cfg007_s cn66xx; 1725232812Sjmallett struct cvmx_pciercx_cfg007_s cn68xx; 1726232812Sjmallett struct cvmx_pciercx_cfg007_s cn68xxp1; 1727232812Sjmallett struct cvmx_pciercx_cfg007_s cnf71xx; 1728215976Sjmallett}; 1729215976Sjmalletttypedef union cvmx_pciercx_cfg007 cvmx_pciercx_cfg007_t; 1730215976Sjmallett 1731215976Sjmallett/** 1732215976Sjmallett * cvmx_pcierc#_cfg008 1733215976Sjmallett * 1734215976Sjmallett * PCIE_CFG008 = Ninth 32-bits of PCIE type 1 config space (Memory Base and Memory Limit Register) 1735215976Sjmallett * 1736215976Sjmallett */ 1737232812Sjmallettunion cvmx_pciercx_cfg008 { 1738215976Sjmallett uint32_t u32; 1739232812Sjmallett struct cvmx_pciercx_cfg008_s { 1740232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1741215976Sjmallett uint32_t ml_addr : 12; /**< Memory Limit Address */ 1742215976Sjmallett uint32_t reserved_16_19 : 4; 1743215976Sjmallett uint32_t mb_addr : 12; /**< Memory Base Address */ 1744215976Sjmallett uint32_t reserved_0_3 : 4; 1745215976Sjmallett#else 1746215976Sjmallett uint32_t reserved_0_3 : 4; 1747215976Sjmallett uint32_t mb_addr : 12; 1748215976Sjmallett uint32_t reserved_16_19 : 4; 1749215976Sjmallett uint32_t ml_addr : 12; 1750215976Sjmallett#endif 1751215976Sjmallett } s; 1752215976Sjmallett struct cvmx_pciercx_cfg008_s cn52xx; 1753215976Sjmallett struct cvmx_pciercx_cfg008_s cn52xxp1; 1754215976Sjmallett struct cvmx_pciercx_cfg008_s cn56xx; 1755215976Sjmallett struct cvmx_pciercx_cfg008_s cn56xxp1; 1756232812Sjmallett struct cvmx_pciercx_cfg008_s cn61xx; 1757215976Sjmallett struct cvmx_pciercx_cfg008_s cn63xx; 1758215976Sjmallett struct cvmx_pciercx_cfg008_s cn63xxp1; 1759232812Sjmallett struct cvmx_pciercx_cfg008_s cn66xx; 1760232812Sjmallett struct cvmx_pciercx_cfg008_s cn68xx; 1761232812Sjmallett struct cvmx_pciercx_cfg008_s cn68xxp1; 1762232812Sjmallett struct cvmx_pciercx_cfg008_s cnf71xx; 1763215976Sjmallett}; 1764215976Sjmalletttypedef union cvmx_pciercx_cfg008 cvmx_pciercx_cfg008_t; 1765215976Sjmallett 1766215976Sjmallett/** 1767215976Sjmallett * cvmx_pcierc#_cfg009 1768215976Sjmallett * 1769215976Sjmallett * PCIE_CFG009 = Tenth 32-bits of PCIE type 1 config space (Prefetchable Memory Base and Limit Register) 1770215976Sjmallett * 1771215976Sjmallett */ 1772232812Sjmallettunion cvmx_pciercx_cfg009 { 1773215976Sjmallett uint32_t u32; 1774232812Sjmallett struct cvmx_pciercx_cfg009_s { 1775232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1776215976Sjmallett uint32_t lmem_limit : 12; /**< Upper 12 bits of 32-bit Prefetchable Memory End Address */ 1777215976Sjmallett uint32_t reserved_17_19 : 3; 1778215976Sjmallett uint32_t mem64b : 1; /**< 64-Bit Memory Addressing 1779215976Sjmallett o 0 = 32-bit memory addressing 1780215976Sjmallett o 1 = 64-bit memory addressing */ 1781215976Sjmallett uint32_t lmem_base : 12; /**< Upper 12 bits of 32-bit Prefetchable Memory Start Address */ 1782215976Sjmallett uint32_t reserved_1_3 : 3; 1783215976Sjmallett uint32_t mem64a : 1; /**< 64-Bit Memory Addressing 1784215976Sjmallett o 0 = 32-bit memory addressing 1785215976Sjmallett o 1 = 64-bit memory addressing 1786215976Sjmallett This bit is writable through PEM(0..1)_CFG_WR. 1787215976Sjmallett When the application 1788215976Sjmallett writes to this bit through PEM(0..1)_CFG_WR, 1789215976Sjmallett the same value is written 1790215976Sjmallett to bit 16 of this register. */ 1791215976Sjmallett#else 1792215976Sjmallett uint32_t mem64a : 1; 1793215976Sjmallett uint32_t reserved_1_3 : 3; 1794215976Sjmallett uint32_t lmem_base : 12; 1795215976Sjmallett uint32_t mem64b : 1; 1796215976Sjmallett uint32_t reserved_17_19 : 3; 1797215976Sjmallett uint32_t lmem_limit : 12; 1798215976Sjmallett#endif 1799215976Sjmallett } s; 1800215976Sjmallett struct cvmx_pciercx_cfg009_s cn52xx; 1801215976Sjmallett struct cvmx_pciercx_cfg009_s cn52xxp1; 1802215976Sjmallett struct cvmx_pciercx_cfg009_s cn56xx; 1803215976Sjmallett struct cvmx_pciercx_cfg009_s cn56xxp1; 1804232812Sjmallett struct cvmx_pciercx_cfg009_s cn61xx; 1805215976Sjmallett struct cvmx_pciercx_cfg009_s cn63xx; 1806215976Sjmallett struct cvmx_pciercx_cfg009_s cn63xxp1; 1807232812Sjmallett struct cvmx_pciercx_cfg009_s cn66xx; 1808232812Sjmallett struct cvmx_pciercx_cfg009_s cn68xx; 1809232812Sjmallett struct cvmx_pciercx_cfg009_s cn68xxp1; 1810232812Sjmallett struct cvmx_pciercx_cfg009_s cnf71xx; 1811215976Sjmallett}; 1812215976Sjmalletttypedef union cvmx_pciercx_cfg009 cvmx_pciercx_cfg009_t; 1813215976Sjmallett 1814215976Sjmallett/** 1815215976Sjmallett * cvmx_pcierc#_cfg010 1816215976Sjmallett * 1817215976Sjmallett * PCIE_CFG010 = Eleventh 32-bits of PCIE type 1 config space (Prefetchable Base Upper 32 Bits Register) 1818215976Sjmallett * 1819215976Sjmallett */ 1820232812Sjmallettunion cvmx_pciercx_cfg010 { 1821215976Sjmallett uint32_t u32; 1822232812Sjmallett struct cvmx_pciercx_cfg010_s { 1823232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1824215976Sjmallett uint32_t umem_base : 32; /**< Upper 32 Bits of Base Address of Prefetchable Memory Space 1825215976Sjmallett Used only when 64-bit prefetchable memory addressing is 1826215976Sjmallett enabled. */ 1827215976Sjmallett#else 1828215976Sjmallett uint32_t umem_base : 32; 1829215976Sjmallett#endif 1830215976Sjmallett } s; 1831215976Sjmallett struct cvmx_pciercx_cfg010_s cn52xx; 1832215976Sjmallett struct cvmx_pciercx_cfg010_s cn52xxp1; 1833215976Sjmallett struct cvmx_pciercx_cfg010_s cn56xx; 1834215976Sjmallett struct cvmx_pciercx_cfg010_s cn56xxp1; 1835232812Sjmallett struct cvmx_pciercx_cfg010_s cn61xx; 1836215976Sjmallett struct cvmx_pciercx_cfg010_s cn63xx; 1837215976Sjmallett struct cvmx_pciercx_cfg010_s cn63xxp1; 1838232812Sjmallett struct cvmx_pciercx_cfg010_s cn66xx; 1839232812Sjmallett struct cvmx_pciercx_cfg010_s cn68xx; 1840232812Sjmallett struct cvmx_pciercx_cfg010_s cn68xxp1; 1841232812Sjmallett struct cvmx_pciercx_cfg010_s cnf71xx; 1842215976Sjmallett}; 1843215976Sjmalletttypedef union cvmx_pciercx_cfg010 cvmx_pciercx_cfg010_t; 1844215976Sjmallett 1845215976Sjmallett/** 1846215976Sjmallett * cvmx_pcierc#_cfg011 1847215976Sjmallett * 1848215976Sjmallett * PCIE_CFG011 = Twelfth 32-bits of PCIE type 1 config space (Prefetchable Limit Upper 32 Bits Register) 1849215976Sjmallett * 1850215976Sjmallett */ 1851232812Sjmallettunion cvmx_pciercx_cfg011 { 1852215976Sjmallett uint32_t u32; 1853232812Sjmallett struct cvmx_pciercx_cfg011_s { 1854232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1855215976Sjmallett uint32_t umem_limit : 32; /**< Upper 32 Bits of Limit Address of Prefetchable Memory Space 1856215976Sjmallett Used only when 64-bit prefetchable memory addressing is 1857215976Sjmallett enabled. */ 1858215976Sjmallett#else 1859215976Sjmallett uint32_t umem_limit : 32; 1860215976Sjmallett#endif 1861215976Sjmallett } s; 1862215976Sjmallett struct cvmx_pciercx_cfg011_s cn52xx; 1863215976Sjmallett struct cvmx_pciercx_cfg011_s cn52xxp1; 1864215976Sjmallett struct cvmx_pciercx_cfg011_s cn56xx; 1865215976Sjmallett struct cvmx_pciercx_cfg011_s cn56xxp1; 1866232812Sjmallett struct cvmx_pciercx_cfg011_s cn61xx; 1867215976Sjmallett struct cvmx_pciercx_cfg011_s cn63xx; 1868215976Sjmallett struct cvmx_pciercx_cfg011_s cn63xxp1; 1869232812Sjmallett struct cvmx_pciercx_cfg011_s cn66xx; 1870232812Sjmallett struct cvmx_pciercx_cfg011_s cn68xx; 1871232812Sjmallett struct cvmx_pciercx_cfg011_s cn68xxp1; 1872232812Sjmallett struct cvmx_pciercx_cfg011_s cnf71xx; 1873215976Sjmallett}; 1874215976Sjmalletttypedef union cvmx_pciercx_cfg011 cvmx_pciercx_cfg011_t; 1875215976Sjmallett 1876215976Sjmallett/** 1877215976Sjmallett * cvmx_pcierc#_cfg012 1878215976Sjmallett * 1879215976Sjmallett * PCIE_CFG012 = Thirteenth 32-bits of PCIE type 1 config space (IO Base and Limit Upper 16 Bits Register) 1880215976Sjmallett * 1881215976Sjmallett */ 1882232812Sjmallettunion cvmx_pciercx_cfg012 { 1883215976Sjmallett uint32_t u32; 1884232812Sjmallett struct cvmx_pciercx_cfg012_s { 1885232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1886215976Sjmallett uint32_t uio_limit : 16; /**< Upper 16 Bits of I/O Limit (if 32-bit I/O decoding is supported 1887215976Sjmallett for devices on the secondary side) */ 1888215976Sjmallett uint32_t uio_base : 16; /**< Upper 16 Bits of I/O Base (if 32-bit I/O decoding is supported 1889215976Sjmallett for devices on the secondary side) */ 1890215976Sjmallett#else 1891215976Sjmallett uint32_t uio_base : 16; 1892215976Sjmallett uint32_t uio_limit : 16; 1893215976Sjmallett#endif 1894215976Sjmallett } s; 1895215976Sjmallett struct cvmx_pciercx_cfg012_s cn52xx; 1896215976Sjmallett struct cvmx_pciercx_cfg012_s cn52xxp1; 1897215976Sjmallett struct cvmx_pciercx_cfg012_s cn56xx; 1898215976Sjmallett struct cvmx_pciercx_cfg012_s cn56xxp1; 1899232812Sjmallett struct cvmx_pciercx_cfg012_s cn61xx; 1900215976Sjmallett struct cvmx_pciercx_cfg012_s cn63xx; 1901215976Sjmallett struct cvmx_pciercx_cfg012_s cn63xxp1; 1902232812Sjmallett struct cvmx_pciercx_cfg012_s cn66xx; 1903232812Sjmallett struct cvmx_pciercx_cfg012_s cn68xx; 1904232812Sjmallett struct cvmx_pciercx_cfg012_s cn68xxp1; 1905232812Sjmallett struct cvmx_pciercx_cfg012_s cnf71xx; 1906215976Sjmallett}; 1907215976Sjmalletttypedef union cvmx_pciercx_cfg012 cvmx_pciercx_cfg012_t; 1908215976Sjmallett 1909215976Sjmallett/** 1910215976Sjmallett * cvmx_pcierc#_cfg013 1911215976Sjmallett * 1912215976Sjmallett * PCIE_CFG013 = Fourteenth 32-bits of PCIE type 1 config space (Capability Pointer Register) 1913215976Sjmallett * 1914215976Sjmallett */ 1915232812Sjmallettunion cvmx_pciercx_cfg013 { 1916215976Sjmallett uint32_t u32; 1917232812Sjmallett struct cvmx_pciercx_cfg013_s { 1918232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1919215976Sjmallett uint32_t reserved_8_31 : 24; 1920215976Sjmallett uint32_t cp : 8; /**< First Capability Pointer. 1921215976Sjmallett Points to Power Management Capability structure by 1922215976Sjmallett default, writable through PEM(0..1)_CFG_WR 1923215976Sjmallett However, the application must not change this field. */ 1924215976Sjmallett#else 1925215976Sjmallett uint32_t cp : 8; 1926215976Sjmallett uint32_t reserved_8_31 : 24; 1927215976Sjmallett#endif 1928215976Sjmallett } s; 1929215976Sjmallett struct cvmx_pciercx_cfg013_s cn52xx; 1930215976Sjmallett struct cvmx_pciercx_cfg013_s cn52xxp1; 1931215976Sjmallett struct cvmx_pciercx_cfg013_s cn56xx; 1932215976Sjmallett struct cvmx_pciercx_cfg013_s cn56xxp1; 1933232812Sjmallett struct cvmx_pciercx_cfg013_s cn61xx; 1934215976Sjmallett struct cvmx_pciercx_cfg013_s cn63xx; 1935215976Sjmallett struct cvmx_pciercx_cfg013_s cn63xxp1; 1936232812Sjmallett struct cvmx_pciercx_cfg013_s cn66xx; 1937232812Sjmallett struct cvmx_pciercx_cfg013_s cn68xx; 1938232812Sjmallett struct cvmx_pciercx_cfg013_s cn68xxp1; 1939232812Sjmallett struct cvmx_pciercx_cfg013_s cnf71xx; 1940215976Sjmallett}; 1941215976Sjmalletttypedef union cvmx_pciercx_cfg013 cvmx_pciercx_cfg013_t; 1942215976Sjmallett 1943215976Sjmallett/** 1944215976Sjmallett * cvmx_pcierc#_cfg014 1945215976Sjmallett * 1946215976Sjmallett * PCIE_CFG014 = Fifteenth 32-bits of PCIE type 1 config space (Expansion ROM Base Address Register) 1947215976Sjmallett * 1948215976Sjmallett */ 1949232812Sjmallettunion cvmx_pciercx_cfg014 { 1950215976Sjmallett uint32_t u32; 1951232812Sjmallett struct cvmx_pciercx_cfg014_s { 1952232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1953215976Sjmallett uint32_t reserved_0_31 : 32; 1954215976Sjmallett#else 1955215976Sjmallett uint32_t reserved_0_31 : 32; 1956215976Sjmallett#endif 1957215976Sjmallett } s; 1958215976Sjmallett struct cvmx_pciercx_cfg014_s cn52xx; 1959215976Sjmallett struct cvmx_pciercx_cfg014_s cn52xxp1; 1960215976Sjmallett struct cvmx_pciercx_cfg014_s cn56xx; 1961215976Sjmallett struct cvmx_pciercx_cfg014_s cn56xxp1; 1962232812Sjmallett struct cvmx_pciercx_cfg014_s cn61xx; 1963215976Sjmallett struct cvmx_pciercx_cfg014_s cn63xx; 1964215976Sjmallett struct cvmx_pciercx_cfg014_s cn63xxp1; 1965232812Sjmallett struct cvmx_pciercx_cfg014_s cn66xx; 1966232812Sjmallett struct cvmx_pciercx_cfg014_s cn68xx; 1967232812Sjmallett struct cvmx_pciercx_cfg014_s cn68xxp1; 1968232812Sjmallett struct cvmx_pciercx_cfg014_s cnf71xx; 1969215976Sjmallett}; 1970215976Sjmalletttypedef union cvmx_pciercx_cfg014 cvmx_pciercx_cfg014_t; 1971215976Sjmallett 1972215976Sjmallett/** 1973215976Sjmallett * cvmx_pcierc#_cfg015 1974215976Sjmallett * 1975215976Sjmallett * PCIE_CFG015 = Sixteenth 32-bits of PCIE type 1 config space (Interrupt Line Register/Interrupt Pin/Bridge Control Register) 1976215976Sjmallett * 1977215976Sjmallett */ 1978232812Sjmallettunion cvmx_pciercx_cfg015 { 1979215976Sjmallett uint32_t u32; 1980232812Sjmallett struct cvmx_pciercx_cfg015_s { 1981232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1982215976Sjmallett uint32_t reserved_28_31 : 4; 1983215976Sjmallett uint32_t dtsees : 1; /**< Discard Timer SERR Enable Status 1984215976Sjmallett Not applicable to PCI Express, hardwired to 0. */ 1985215976Sjmallett uint32_t dts : 1; /**< Discard Timer Status 1986215976Sjmallett Not applicable to PCI Express, hardwired to 0. */ 1987215976Sjmallett uint32_t sdt : 1; /**< Secondary Discard Timer 1988215976Sjmallett Not applicable to PCI Express, hardwired to 0. */ 1989215976Sjmallett uint32_t pdt : 1; /**< Primary Discard Timer 1990215976Sjmallett Not applicable to PCI Express, hardwired to 0. */ 1991215976Sjmallett uint32_t fbbe : 1; /**< Fast Back-to-Back Transactions Enable 1992215976Sjmallett Not applicable to PCI Express, hardwired to 0. */ 1993215976Sjmallett uint32_t sbrst : 1; /**< Secondary Bus Reset 1994215976Sjmallett Hot reset. Causes TS1s with the hot reset bit to be sent to 1995215976Sjmallett the link partner. When set, SW should wait 2ms before 1996215976Sjmallett clearing. The link partner normally responds by sending TS1s 1997215976Sjmallett with the hot reset bit set, which will cause a link 1998215976Sjmallett down event - refer to "PCIe Link-Down Reset in RC Mode" 1999215976Sjmallett section. */ 2000215976Sjmallett uint32_t mam : 1; /**< Master Abort Mode 2001215976Sjmallett Not applicable to PCI Express, hardwired to 0. */ 2002215976Sjmallett uint32_t vga16d : 1; /**< VGA 16-Bit Decode */ 2003215976Sjmallett uint32_t vgae : 1; /**< VGA Enable */ 2004215976Sjmallett uint32_t isae : 1; /**< ISA Enable */ 2005215976Sjmallett uint32_t see : 1; /**< SERR Enable */ 2006215976Sjmallett uint32_t pere : 1; /**< Parity Error Response Enable */ 2007215976Sjmallett uint32_t inta : 8; /**< Interrupt Pin 2008215976Sjmallett Identifies the legacy interrupt Message that the device 2009215976Sjmallett (or device function) uses. 2010215976Sjmallett The Interrupt Pin register is writable through PEM(0..1)_CFG_WR. 2011215976Sjmallett In a single-function configuration, only INTA is used. 2012215976Sjmallett Therefore, the application must not change this field. */ 2013215976Sjmallett uint32_t il : 8; /**< Interrupt Line */ 2014215976Sjmallett#else 2015215976Sjmallett uint32_t il : 8; 2016215976Sjmallett uint32_t inta : 8; 2017215976Sjmallett uint32_t pere : 1; 2018215976Sjmallett uint32_t see : 1; 2019215976Sjmallett uint32_t isae : 1; 2020215976Sjmallett uint32_t vgae : 1; 2021215976Sjmallett uint32_t vga16d : 1; 2022215976Sjmallett uint32_t mam : 1; 2023215976Sjmallett uint32_t sbrst : 1; 2024215976Sjmallett uint32_t fbbe : 1; 2025215976Sjmallett uint32_t pdt : 1; 2026215976Sjmallett uint32_t sdt : 1; 2027215976Sjmallett uint32_t dts : 1; 2028215976Sjmallett uint32_t dtsees : 1; 2029215976Sjmallett uint32_t reserved_28_31 : 4; 2030215976Sjmallett#endif 2031215976Sjmallett } s; 2032215976Sjmallett struct cvmx_pciercx_cfg015_s cn52xx; 2033215976Sjmallett struct cvmx_pciercx_cfg015_s cn52xxp1; 2034215976Sjmallett struct cvmx_pciercx_cfg015_s cn56xx; 2035215976Sjmallett struct cvmx_pciercx_cfg015_s cn56xxp1; 2036232812Sjmallett struct cvmx_pciercx_cfg015_s cn61xx; 2037215976Sjmallett struct cvmx_pciercx_cfg015_s cn63xx; 2038215976Sjmallett struct cvmx_pciercx_cfg015_s cn63xxp1; 2039232812Sjmallett struct cvmx_pciercx_cfg015_s cn66xx; 2040232812Sjmallett struct cvmx_pciercx_cfg015_s cn68xx; 2041232812Sjmallett struct cvmx_pciercx_cfg015_s cn68xxp1; 2042232812Sjmallett struct cvmx_pciercx_cfg015_s cnf71xx; 2043215976Sjmallett}; 2044215976Sjmalletttypedef union cvmx_pciercx_cfg015 cvmx_pciercx_cfg015_t; 2045215976Sjmallett 2046215976Sjmallett/** 2047215976Sjmallett * cvmx_pcierc#_cfg016 2048215976Sjmallett * 2049215976Sjmallett * PCIE_CFG016 = Seventeenth 32-bits of PCIE type 1 config space 2050215976Sjmallett * (Power Management Capability ID/ 2051215976Sjmallett * Power Management Next Item Pointer/ 2052215976Sjmallett * Power Management Capabilities Register) 2053215976Sjmallett */ 2054232812Sjmallettunion cvmx_pciercx_cfg016 { 2055215976Sjmallett uint32_t u32; 2056232812Sjmallett struct cvmx_pciercx_cfg016_s { 2057232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2058215976Sjmallett uint32_t pmes : 5; /**< PME_Support 2059215976Sjmallett A value of 0 for any bit indicates that the 2060215976Sjmallett device (or function) is not capable of generating PME Messages 2061215976Sjmallett while in that power state: 2062215976Sjmallett o Bit 11: If set, PME Messages can be generated from D0 2063215976Sjmallett o Bit 12: If set, PME Messages can be generated from D1 2064215976Sjmallett o Bit 13: If set, PME Messages can be generated from D2 2065215976Sjmallett o Bit 14: If set, PME Messages can be generated from D3hot 2066215976Sjmallett o Bit 15: If set, PME Messages can be generated from D3cold 2067215976Sjmallett The PME_Support field is writable through PEM(0..1)_CFG_WR. 2068215976Sjmallett However, the application must not change this field. */ 2069215976Sjmallett uint32_t d2s : 1; /**< D2 Support, writable through PEM(0..1)_CFG_WR 2070215976Sjmallett However, the application must not change this field. */ 2071215976Sjmallett uint32_t d1s : 1; /**< D1 Support, writable through PEM(0..1)_CFG_WR 2072215976Sjmallett However, the application must not change this field. */ 2073215976Sjmallett uint32_t auxc : 3; /**< AUX Current, writable through PEM(0..1)_CFG_WR 2074215976Sjmallett However, the application must not change this field. */ 2075215976Sjmallett uint32_t dsi : 1; /**< Device Specific Initialization (DSI), writable through PEM(0..1)_CFG_WR 2076215976Sjmallett However, the application must not change this field. */ 2077215976Sjmallett uint32_t reserved_20_20 : 1; 2078215976Sjmallett uint32_t pme_clock : 1; /**< PME Clock, hardwired to 0 */ 2079215976Sjmallett uint32_t pmsv : 3; /**< Power Management Specification Version, writable through PEM(0..1)_CFG_WR 2080215976Sjmallett However, the application must not change this field. */ 2081215976Sjmallett uint32_t ncp : 8; /**< Next Capability Pointer 2082215976Sjmallett Points to the MSI capabilities by default, writable 2083215976Sjmallett through PEM(0..1)_CFG_WR. */ 2084215976Sjmallett uint32_t pmcid : 8; /**< Power Management Capability ID */ 2085215976Sjmallett#else 2086215976Sjmallett uint32_t pmcid : 8; 2087215976Sjmallett uint32_t ncp : 8; 2088215976Sjmallett uint32_t pmsv : 3; 2089215976Sjmallett uint32_t pme_clock : 1; 2090215976Sjmallett uint32_t reserved_20_20 : 1; 2091215976Sjmallett uint32_t dsi : 1; 2092215976Sjmallett uint32_t auxc : 3; 2093215976Sjmallett uint32_t d1s : 1; 2094215976Sjmallett uint32_t d2s : 1; 2095215976Sjmallett uint32_t pmes : 5; 2096215976Sjmallett#endif 2097215976Sjmallett } s; 2098215976Sjmallett struct cvmx_pciercx_cfg016_s cn52xx; 2099215976Sjmallett struct cvmx_pciercx_cfg016_s cn52xxp1; 2100215976Sjmallett struct cvmx_pciercx_cfg016_s cn56xx; 2101215976Sjmallett struct cvmx_pciercx_cfg016_s cn56xxp1; 2102232812Sjmallett struct cvmx_pciercx_cfg016_s cn61xx; 2103215976Sjmallett struct cvmx_pciercx_cfg016_s cn63xx; 2104215976Sjmallett struct cvmx_pciercx_cfg016_s cn63xxp1; 2105232812Sjmallett struct cvmx_pciercx_cfg016_s cn66xx; 2106232812Sjmallett struct cvmx_pciercx_cfg016_s cn68xx; 2107232812Sjmallett struct cvmx_pciercx_cfg016_s cn68xxp1; 2108232812Sjmallett struct cvmx_pciercx_cfg016_s cnf71xx; 2109215976Sjmallett}; 2110215976Sjmalletttypedef union cvmx_pciercx_cfg016 cvmx_pciercx_cfg016_t; 2111215976Sjmallett 2112215976Sjmallett/** 2113215976Sjmallett * cvmx_pcierc#_cfg017 2114215976Sjmallett * 2115215976Sjmallett * PCIE_CFG017 = Eighteenth 32-bits of PCIE type 1 config space (Power Management Control and Status Register) 2116215976Sjmallett * 2117215976Sjmallett */ 2118232812Sjmallettunion cvmx_pciercx_cfg017 { 2119215976Sjmallett uint32_t u32; 2120232812Sjmallett struct cvmx_pciercx_cfg017_s { 2121232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2122215976Sjmallett uint32_t pmdia : 8; /**< Data register for additional information (not supported) */ 2123215976Sjmallett uint32_t bpccee : 1; /**< Bus Power/Clock Control Enable, hardwired to 0 */ 2124215976Sjmallett uint32_t bd3h : 1; /**< B2/B3 Support, hardwired to 0 */ 2125215976Sjmallett uint32_t reserved_16_21 : 6; 2126215976Sjmallett uint32_t pmess : 1; /**< PME Status 2127215976Sjmallett Indicates if a previously enabled PME event occurred or not. */ 2128215976Sjmallett uint32_t pmedsia : 2; /**< Data Scale (not supported) */ 2129215976Sjmallett uint32_t pmds : 4; /**< Data Select (not supported) */ 2130215976Sjmallett uint32_t pmeens : 1; /**< PME Enable 2131215976Sjmallett A value of 1 indicates that the device is enabled to 2132215976Sjmallett generate PME. */ 2133215976Sjmallett uint32_t reserved_4_7 : 4; 2134215976Sjmallett uint32_t nsr : 1; /**< No Soft Reset, writable through PEM(0..1)_CFG_WR 2135215976Sjmallett However, the application must not change this field. */ 2136215976Sjmallett uint32_t reserved_2_2 : 1; 2137215976Sjmallett uint32_t ps : 2; /**< Power State 2138215976Sjmallett Controls the device power state: 2139215976Sjmallett o 00b: D0 2140215976Sjmallett o 01b: D1 2141215976Sjmallett o 10b: D2 2142215976Sjmallett o 11b: D3 2143215976Sjmallett The written value is ignored if the specific state is 2144215976Sjmallett not supported. */ 2145215976Sjmallett#else 2146215976Sjmallett uint32_t ps : 2; 2147215976Sjmallett uint32_t reserved_2_2 : 1; 2148215976Sjmallett uint32_t nsr : 1; 2149215976Sjmallett uint32_t reserved_4_7 : 4; 2150215976Sjmallett uint32_t pmeens : 1; 2151215976Sjmallett uint32_t pmds : 4; 2152215976Sjmallett uint32_t pmedsia : 2; 2153215976Sjmallett uint32_t pmess : 1; 2154215976Sjmallett uint32_t reserved_16_21 : 6; 2155215976Sjmallett uint32_t bd3h : 1; 2156215976Sjmallett uint32_t bpccee : 1; 2157215976Sjmallett uint32_t pmdia : 8; 2158215976Sjmallett#endif 2159215976Sjmallett } s; 2160215976Sjmallett struct cvmx_pciercx_cfg017_s cn52xx; 2161215976Sjmallett struct cvmx_pciercx_cfg017_s cn52xxp1; 2162215976Sjmallett struct cvmx_pciercx_cfg017_s cn56xx; 2163215976Sjmallett struct cvmx_pciercx_cfg017_s cn56xxp1; 2164232812Sjmallett struct cvmx_pciercx_cfg017_s cn61xx; 2165215976Sjmallett struct cvmx_pciercx_cfg017_s cn63xx; 2166215976Sjmallett struct cvmx_pciercx_cfg017_s cn63xxp1; 2167232812Sjmallett struct cvmx_pciercx_cfg017_s cn66xx; 2168232812Sjmallett struct cvmx_pciercx_cfg017_s cn68xx; 2169232812Sjmallett struct cvmx_pciercx_cfg017_s cn68xxp1; 2170232812Sjmallett struct cvmx_pciercx_cfg017_s cnf71xx; 2171215976Sjmallett}; 2172215976Sjmalletttypedef union cvmx_pciercx_cfg017 cvmx_pciercx_cfg017_t; 2173215976Sjmallett 2174215976Sjmallett/** 2175215976Sjmallett * cvmx_pcierc#_cfg020 2176215976Sjmallett * 2177215976Sjmallett * PCIE_CFG020 = Twenty-first 32-bits of PCIE type 1 config space 2178215976Sjmallett * (MSI Capability ID/ 2179215976Sjmallett * MSI Next Item Pointer/ 2180215976Sjmallett * MSI Control Register) 2181215976Sjmallett */ 2182232812Sjmallettunion cvmx_pciercx_cfg020 { 2183215976Sjmallett uint32_t u32; 2184232812Sjmallett struct cvmx_pciercx_cfg020_s { 2185232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2186232812Sjmallett uint32_t reserved_25_31 : 7; 2187232812Sjmallett uint32_t pvm : 1; /**< Per-vector masking capable */ 2188215976Sjmallett uint32_t m64 : 1; /**< 64-bit Address Capable, writable through PEM(0..1)_CFG_WR 2189215976Sjmallett However, the application must not change this field. */ 2190215976Sjmallett uint32_t mme : 3; /**< Multiple Message Enabled 2191215976Sjmallett Indicates that multiple Message mode is enabled by system 2192215976Sjmallett software. The number of Messages enabled must be less than 2193215976Sjmallett or equal to the Multiple Message Capable value. */ 2194215976Sjmallett uint32_t mmc : 3; /**< Multiple Message Capable, writable through PEM(0..1)_CFG_WR 2195215976Sjmallett However, the application must not change this field. */ 2196215976Sjmallett uint32_t msien : 1; /**< MSI Enabled 2197215976Sjmallett When set, INTx must be disabled. 2198215976Sjmallett This bit must never be set, as internal-MSI is not supported in 2199215976Sjmallett RC mode. (Note that this has no effect on external MSI, which 2200215976Sjmallett will be commonly used in RC mode.) */ 2201215976Sjmallett uint32_t ncp : 8; /**< Next Capability Pointer 2202215976Sjmallett Points to PCI Express Capabilities by default, 2203215976Sjmallett writable through PEM(0..1)_CFG_WR. 2204215976Sjmallett However, the application must not change this field. */ 2205215976Sjmallett uint32_t msicid : 8; /**< MSI Capability ID */ 2206215976Sjmallett#else 2207215976Sjmallett uint32_t msicid : 8; 2208215976Sjmallett uint32_t ncp : 8; 2209215976Sjmallett uint32_t msien : 1; 2210215976Sjmallett uint32_t mmc : 3; 2211215976Sjmallett uint32_t mme : 3; 2212215976Sjmallett uint32_t m64 : 1; 2213232812Sjmallett uint32_t pvm : 1; 2214232812Sjmallett uint32_t reserved_25_31 : 7; 2215232812Sjmallett#endif 2216232812Sjmallett } s; 2217232812Sjmallett struct cvmx_pciercx_cfg020_cn52xx { 2218232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2219215976Sjmallett uint32_t reserved_24_31 : 8; 2220232812Sjmallett uint32_t m64 : 1; /**< 64-bit Address Capable, writable through PESC(0..1)_CFG_WR 2221232812Sjmallett However, the application must not change this field. */ 2222232812Sjmallett uint32_t mme : 3; /**< Multiple Message Enabled 2223232812Sjmallett Indicates that multiple Message mode is enabled by system 2224232812Sjmallett software. The number of Messages enabled must be less than 2225232812Sjmallett or equal to the Multiple Message Capable value. */ 2226232812Sjmallett uint32_t mmc : 3; /**< Multiple Message Capable, writable through PESC(0..1)_CFG_WR 2227232812Sjmallett However, the application must not change this field. */ 2228232812Sjmallett uint32_t msien : 1; /**< MSI Enabled 2229232812Sjmallett When set, INTx must be disabled. 2230232812Sjmallett This bit must never be set, as internal-MSI is not supported in 2231232812Sjmallett RC mode. (Note that this has no effect on external MSI, which 2232232812Sjmallett will be commonly used in RC mode.) */ 2233232812Sjmallett uint32_t ncp : 8; /**< Next Capability Pointer 2234232812Sjmallett Points to PCI Express Capabilities by default, 2235232812Sjmallett writable through PESC(0..1)_CFG_WR. 2236232812Sjmallett However, the application must not change this field. */ 2237232812Sjmallett uint32_t msicid : 8; /**< MSI Capability ID */ 2238232812Sjmallett#else 2239232812Sjmallett uint32_t msicid : 8; 2240232812Sjmallett uint32_t ncp : 8; 2241232812Sjmallett uint32_t msien : 1; 2242232812Sjmallett uint32_t mmc : 3; 2243232812Sjmallett uint32_t mme : 3; 2244232812Sjmallett uint32_t m64 : 1; 2245232812Sjmallett uint32_t reserved_24_31 : 8; 2246215976Sjmallett#endif 2247232812Sjmallett } cn52xx; 2248232812Sjmallett struct cvmx_pciercx_cfg020_cn52xx cn52xxp1; 2249232812Sjmallett struct cvmx_pciercx_cfg020_cn52xx cn56xx; 2250232812Sjmallett struct cvmx_pciercx_cfg020_cn52xx cn56xxp1; 2251232812Sjmallett struct cvmx_pciercx_cfg020_s cn61xx; 2252232812Sjmallett struct cvmx_pciercx_cfg020_cn52xx cn63xx; 2253232812Sjmallett struct cvmx_pciercx_cfg020_cn52xx cn63xxp1; 2254232812Sjmallett struct cvmx_pciercx_cfg020_cn52xx cn66xx; 2255232812Sjmallett struct cvmx_pciercx_cfg020_cn52xx cn68xx; 2256232812Sjmallett struct cvmx_pciercx_cfg020_cn52xx cn68xxp1; 2257232812Sjmallett struct cvmx_pciercx_cfg020_s cnf71xx; 2258215976Sjmallett}; 2259215976Sjmalletttypedef union cvmx_pciercx_cfg020 cvmx_pciercx_cfg020_t; 2260215976Sjmallett 2261215976Sjmallett/** 2262215976Sjmallett * cvmx_pcierc#_cfg021 2263215976Sjmallett * 2264215976Sjmallett * PCIE_CFG021 = Twenty-second 32-bits of PCIE type 1 config space (MSI Lower 32 Bits Address Register) 2265215976Sjmallett * 2266215976Sjmallett */ 2267232812Sjmallettunion cvmx_pciercx_cfg021 { 2268215976Sjmallett uint32_t u32; 2269232812Sjmallett struct cvmx_pciercx_cfg021_s { 2270232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2271215976Sjmallett uint32_t lmsi : 30; /**< Lower 32-bit Address */ 2272215976Sjmallett uint32_t reserved_0_1 : 2; 2273215976Sjmallett#else 2274215976Sjmallett uint32_t reserved_0_1 : 2; 2275215976Sjmallett uint32_t lmsi : 30; 2276215976Sjmallett#endif 2277215976Sjmallett } s; 2278215976Sjmallett struct cvmx_pciercx_cfg021_s cn52xx; 2279215976Sjmallett struct cvmx_pciercx_cfg021_s cn52xxp1; 2280215976Sjmallett struct cvmx_pciercx_cfg021_s cn56xx; 2281215976Sjmallett struct cvmx_pciercx_cfg021_s cn56xxp1; 2282232812Sjmallett struct cvmx_pciercx_cfg021_s cn61xx; 2283215976Sjmallett struct cvmx_pciercx_cfg021_s cn63xx; 2284215976Sjmallett struct cvmx_pciercx_cfg021_s cn63xxp1; 2285232812Sjmallett struct cvmx_pciercx_cfg021_s cn66xx; 2286232812Sjmallett struct cvmx_pciercx_cfg021_s cn68xx; 2287232812Sjmallett struct cvmx_pciercx_cfg021_s cn68xxp1; 2288232812Sjmallett struct cvmx_pciercx_cfg021_s cnf71xx; 2289215976Sjmallett}; 2290215976Sjmalletttypedef union cvmx_pciercx_cfg021 cvmx_pciercx_cfg021_t; 2291215976Sjmallett 2292215976Sjmallett/** 2293215976Sjmallett * cvmx_pcierc#_cfg022 2294215976Sjmallett * 2295215976Sjmallett * PCIE_CFG022 = Twenty-third 32-bits of PCIE type 1 config space (MSI Upper 32 bits Address Register) 2296215976Sjmallett * 2297215976Sjmallett */ 2298232812Sjmallettunion cvmx_pciercx_cfg022 { 2299215976Sjmallett uint32_t u32; 2300232812Sjmallett struct cvmx_pciercx_cfg022_s { 2301232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2302215976Sjmallett uint32_t umsi : 32; /**< Upper 32-bit Address */ 2303215976Sjmallett#else 2304215976Sjmallett uint32_t umsi : 32; 2305215976Sjmallett#endif 2306215976Sjmallett } s; 2307215976Sjmallett struct cvmx_pciercx_cfg022_s cn52xx; 2308215976Sjmallett struct cvmx_pciercx_cfg022_s cn52xxp1; 2309215976Sjmallett struct cvmx_pciercx_cfg022_s cn56xx; 2310215976Sjmallett struct cvmx_pciercx_cfg022_s cn56xxp1; 2311232812Sjmallett struct cvmx_pciercx_cfg022_s cn61xx; 2312215976Sjmallett struct cvmx_pciercx_cfg022_s cn63xx; 2313215976Sjmallett struct cvmx_pciercx_cfg022_s cn63xxp1; 2314232812Sjmallett struct cvmx_pciercx_cfg022_s cn66xx; 2315232812Sjmallett struct cvmx_pciercx_cfg022_s cn68xx; 2316232812Sjmallett struct cvmx_pciercx_cfg022_s cn68xxp1; 2317232812Sjmallett struct cvmx_pciercx_cfg022_s cnf71xx; 2318215976Sjmallett}; 2319215976Sjmalletttypedef union cvmx_pciercx_cfg022 cvmx_pciercx_cfg022_t; 2320215976Sjmallett 2321215976Sjmallett/** 2322215976Sjmallett * cvmx_pcierc#_cfg023 2323215976Sjmallett * 2324215976Sjmallett * PCIE_CFG023 = Twenty-fourth 32-bits of PCIE type 1 config space (MSI Data Register) 2325215976Sjmallett * 2326215976Sjmallett */ 2327232812Sjmallettunion cvmx_pciercx_cfg023 { 2328215976Sjmallett uint32_t u32; 2329232812Sjmallett struct cvmx_pciercx_cfg023_s { 2330232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2331215976Sjmallett uint32_t reserved_16_31 : 16; 2332215976Sjmallett uint32_t msimd : 16; /**< MSI Data 2333215976Sjmallett Pattern assigned by system software, bits [4:0] are Or-ed with 2334215976Sjmallett MSI_VECTOR to generate 32 MSI Messages per function. */ 2335215976Sjmallett#else 2336215976Sjmallett uint32_t msimd : 16; 2337215976Sjmallett uint32_t reserved_16_31 : 16; 2338215976Sjmallett#endif 2339215976Sjmallett } s; 2340215976Sjmallett struct cvmx_pciercx_cfg023_s cn52xx; 2341215976Sjmallett struct cvmx_pciercx_cfg023_s cn52xxp1; 2342215976Sjmallett struct cvmx_pciercx_cfg023_s cn56xx; 2343215976Sjmallett struct cvmx_pciercx_cfg023_s cn56xxp1; 2344232812Sjmallett struct cvmx_pciercx_cfg023_s cn61xx; 2345215976Sjmallett struct cvmx_pciercx_cfg023_s cn63xx; 2346215976Sjmallett struct cvmx_pciercx_cfg023_s cn63xxp1; 2347232812Sjmallett struct cvmx_pciercx_cfg023_s cn66xx; 2348232812Sjmallett struct cvmx_pciercx_cfg023_s cn68xx; 2349232812Sjmallett struct cvmx_pciercx_cfg023_s cn68xxp1; 2350232812Sjmallett struct cvmx_pciercx_cfg023_s cnf71xx; 2351215976Sjmallett}; 2352215976Sjmalletttypedef union cvmx_pciercx_cfg023 cvmx_pciercx_cfg023_t; 2353215976Sjmallett 2354215976Sjmallett/** 2355215976Sjmallett * cvmx_pcierc#_cfg028 2356215976Sjmallett * 2357215976Sjmallett * PCIE_CFG028 = Twenty-ninth 32-bits of PCIE type 1 config space 2358215976Sjmallett * (PCI Express Capabilities List Register/ 2359215976Sjmallett * PCI Express Capabilities Register) 2360215976Sjmallett */ 2361232812Sjmallettunion cvmx_pciercx_cfg028 { 2362215976Sjmallett uint32_t u32; 2363232812Sjmallett struct cvmx_pciercx_cfg028_s { 2364232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2365215976Sjmallett uint32_t reserved_30_31 : 2; 2366215976Sjmallett uint32_t imn : 5; /**< Interrupt Message Number 2367215976Sjmallett Updated by hardware, writable through PEM(0..1)_CFG_WR. 2368215976Sjmallett However, the application must not change this field. */ 2369215976Sjmallett uint32_t si : 1; /**< Slot Implemented 2370215976Sjmallett This bit is writable through PEM(0..1)_CFG_WR. 2371215976Sjmallett However, it must 0 for an 2372215976Sjmallett Endpoint device. Therefore, the application must not write a 2373215976Sjmallett 1 to this bit. */ 2374215976Sjmallett uint32_t dpt : 4; /**< Device Port Type */ 2375215976Sjmallett uint32_t pciecv : 4; /**< PCI Express Capability Version */ 2376215976Sjmallett uint32_t ncp : 8; /**< Next Capability Pointer 2377215976Sjmallett writable through PEM(0..1)_CFG_WR. 2378215976Sjmallett However, the application must not change this field. */ 2379215976Sjmallett uint32_t pcieid : 8; /**< PCIE Capability ID */ 2380215976Sjmallett#else 2381215976Sjmallett uint32_t pcieid : 8; 2382215976Sjmallett uint32_t ncp : 8; 2383215976Sjmallett uint32_t pciecv : 4; 2384215976Sjmallett uint32_t dpt : 4; 2385215976Sjmallett uint32_t si : 1; 2386215976Sjmallett uint32_t imn : 5; 2387215976Sjmallett uint32_t reserved_30_31 : 2; 2388215976Sjmallett#endif 2389215976Sjmallett } s; 2390215976Sjmallett struct cvmx_pciercx_cfg028_s cn52xx; 2391215976Sjmallett struct cvmx_pciercx_cfg028_s cn52xxp1; 2392215976Sjmallett struct cvmx_pciercx_cfg028_s cn56xx; 2393215976Sjmallett struct cvmx_pciercx_cfg028_s cn56xxp1; 2394232812Sjmallett struct cvmx_pciercx_cfg028_s cn61xx; 2395215976Sjmallett struct cvmx_pciercx_cfg028_s cn63xx; 2396215976Sjmallett struct cvmx_pciercx_cfg028_s cn63xxp1; 2397232812Sjmallett struct cvmx_pciercx_cfg028_s cn66xx; 2398232812Sjmallett struct cvmx_pciercx_cfg028_s cn68xx; 2399232812Sjmallett struct cvmx_pciercx_cfg028_s cn68xxp1; 2400232812Sjmallett struct cvmx_pciercx_cfg028_s cnf71xx; 2401215976Sjmallett}; 2402215976Sjmalletttypedef union cvmx_pciercx_cfg028 cvmx_pciercx_cfg028_t; 2403215976Sjmallett 2404215976Sjmallett/** 2405215976Sjmallett * cvmx_pcierc#_cfg029 2406215976Sjmallett * 2407215976Sjmallett * PCIE_CFG029 = Thirtieth 32-bits of PCIE type 1 config space (Device Capabilities Register) 2408215976Sjmallett * 2409215976Sjmallett */ 2410232812Sjmallettunion cvmx_pciercx_cfg029 { 2411215976Sjmallett uint32_t u32; 2412232812Sjmallett struct cvmx_pciercx_cfg029_s { 2413232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2414215976Sjmallett uint32_t reserved_28_31 : 4; 2415215976Sjmallett uint32_t cspls : 2; /**< Captured Slot Power Limit Scale 2416215976Sjmallett Not applicable for RC port, upstream port only. */ 2417215976Sjmallett uint32_t csplv : 8; /**< Captured Slot Power Limit Value 2418215976Sjmallett Not applicable for RC port, upstream port only. */ 2419215976Sjmallett uint32_t reserved_16_17 : 2; 2420215976Sjmallett uint32_t rber : 1; /**< Role-Based Error Reporting, writable through PEM(0..1)_CFG_WR 2421215976Sjmallett However, the application must not change this field. */ 2422215976Sjmallett uint32_t reserved_12_14 : 3; 2423215976Sjmallett uint32_t el1al : 3; /**< Endpoint L1 Acceptable Latency, writable through PEM(0..1)_CFG_WR 2424215976Sjmallett Must be 0x0 for non-endpoint devices. */ 2425215976Sjmallett uint32_t el0al : 3; /**< Endpoint L0s Acceptable Latency, writable through PEM(0..1)_CFG_WR 2426215976Sjmallett Must be 0x0 for non-endpoint devices. */ 2427215976Sjmallett uint32_t etfs : 1; /**< Extended Tag Field Supported 2428215976Sjmallett This bit is writable through PEM(0..1)_CFG_WR. 2429215976Sjmallett However, the application 2430215976Sjmallett must not write a 1 to this bit. */ 2431215976Sjmallett uint32_t pfs : 2; /**< Phantom Function Supported 2432215976Sjmallett This field is writable through PEM(0..1)_CFG_WR. 2433215976Sjmallett However, Phantom 2434215976Sjmallett Function is not supported. Therefore, the application must not 2435215976Sjmallett write any value other than 0x0 to this field. */ 2436215976Sjmallett uint32_t mpss : 3; /**< Max_Payload_Size Supported, writable through PEM(0..1)_CFG_WR 2437215976Sjmallett However, the application must not change this field. */ 2438215976Sjmallett#else 2439215976Sjmallett uint32_t mpss : 3; 2440215976Sjmallett uint32_t pfs : 2; 2441215976Sjmallett uint32_t etfs : 1; 2442215976Sjmallett uint32_t el0al : 3; 2443215976Sjmallett uint32_t el1al : 3; 2444215976Sjmallett uint32_t reserved_12_14 : 3; 2445215976Sjmallett uint32_t rber : 1; 2446215976Sjmallett uint32_t reserved_16_17 : 2; 2447215976Sjmallett uint32_t csplv : 8; 2448215976Sjmallett uint32_t cspls : 2; 2449215976Sjmallett uint32_t reserved_28_31 : 4; 2450215976Sjmallett#endif 2451215976Sjmallett } s; 2452215976Sjmallett struct cvmx_pciercx_cfg029_s cn52xx; 2453215976Sjmallett struct cvmx_pciercx_cfg029_s cn52xxp1; 2454215976Sjmallett struct cvmx_pciercx_cfg029_s cn56xx; 2455215976Sjmallett struct cvmx_pciercx_cfg029_s cn56xxp1; 2456232812Sjmallett struct cvmx_pciercx_cfg029_s cn61xx; 2457215976Sjmallett struct cvmx_pciercx_cfg029_s cn63xx; 2458215976Sjmallett struct cvmx_pciercx_cfg029_s cn63xxp1; 2459232812Sjmallett struct cvmx_pciercx_cfg029_s cn66xx; 2460232812Sjmallett struct cvmx_pciercx_cfg029_s cn68xx; 2461232812Sjmallett struct cvmx_pciercx_cfg029_s cn68xxp1; 2462232812Sjmallett struct cvmx_pciercx_cfg029_s cnf71xx; 2463215976Sjmallett}; 2464215976Sjmalletttypedef union cvmx_pciercx_cfg029 cvmx_pciercx_cfg029_t; 2465215976Sjmallett 2466215976Sjmallett/** 2467215976Sjmallett * cvmx_pcierc#_cfg030 2468215976Sjmallett * 2469215976Sjmallett * PCIE_CFG030 = Thirty-first 32-bits of PCIE type 1 config space 2470215976Sjmallett * (Device Control Register/Device Status Register) 2471215976Sjmallett */ 2472232812Sjmallettunion cvmx_pciercx_cfg030 { 2473215976Sjmallett uint32_t u32; 2474232812Sjmallett struct cvmx_pciercx_cfg030_s { 2475232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2476215976Sjmallett uint32_t reserved_22_31 : 10; 2477215976Sjmallett uint32_t tp : 1; /**< Transaction Pending 2478232812Sjmallett Hard-wired to 0. */ 2479215976Sjmallett uint32_t ap_d : 1; /**< Aux Power Detected 2480215976Sjmallett Set to 1 if Aux power detected. */ 2481215976Sjmallett uint32_t ur_d : 1; /**< Unsupported Request Detected 2482215976Sjmallett Errors are logged in this register regardless of whether 2483215976Sjmallett error reporting is enabled in the Device Control register. 2484215976Sjmallett UR_D occurs when we receive something we don't support. 2485215976Sjmallett Unsupported requests are Nonfatal errors, so UR_D should 2486215976Sjmallett cause NFE_D. Receiving a vendor defined message should 2487215976Sjmallett cause an unsupported request. */ 2488215976Sjmallett uint32_t fe_d : 1; /**< Fatal Error Detected 2489215976Sjmallett Errors are logged in this register regardless of whether 2490215976Sjmallett error reporting is enabled in the Device Control register. 2491215976Sjmallett FE_D is set if receive any of the errors in PCIE_CFG066 that 2492215976Sjmallett has a severity set to Fatal. Malformed TLP's generally fit 2493215976Sjmallett into this category. */ 2494215976Sjmallett uint32_t nfe_d : 1; /**< Non-Fatal Error detected 2495215976Sjmallett Errors are logged in this register regardless of whether 2496215976Sjmallett error reporting is enabled in the Device Control register. 2497215976Sjmallett NFE_D is set if we receive any of the errors in PCIE_CFG066 2498215976Sjmallett that has a severity set to Nonfatal and does NOT meet Advisory 2499215976Sjmallett Nonfatal criteria , which 2500215976Sjmallett most poisoned TLP's should be. */ 2501215976Sjmallett uint32_t ce_d : 1; /**< Correctable Error Detected 2502215976Sjmallett Errors are logged in this register regardless of whether 2503215976Sjmallett error reporting is enabled in the Device Control register. 2504215976Sjmallett CE_D is set if we receive any of the errors in PCIE_CFG068 2505215976Sjmallett for example a Replay Timer Timeout. Also, it can be set if 2506215976Sjmallett we get any of the errors in PCIE_CFG066 that has a severity 2507215976Sjmallett set to Nonfatal and meets the Advisory Nonfatal criteria, 2508215976Sjmallett which most ECRC errors should be. */ 2509215976Sjmallett uint32_t reserved_15_15 : 1; 2510215976Sjmallett uint32_t mrrs : 3; /**< Max Read Request Size 2511215976Sjmallett 0 = 128B 2512215976Sjmallett 1 = 256B 2513215976Sjmallett 2 = 512B 2514215976Sjmallett 3 = 1024B 2515215976Sjmallett 4 = 2048B 2516215976Sjmallett 5 = 4096B 2517215976Sjmallett Note: SLI_S2M_PORT#_CTL[MRRS] and DPI_SLI_PRT#_CFG[MRRS] and 2518215976Sjmallett also must be set properly. 2519215976Sjmallett SLI_S2M_PORT#_CTL[MRRS] and DPI_SLI_PRT#_CFG[MRRS] must 2520215976Sjmallett not exceed the desired max read request size. */ 2521215976Sjmallett uint32_t ns_en : 1; /**< Enable No Snoop */ 2522215976Sjmallett uint32_t ap_en : 1; /**< AUX Power PM Enable */ 2523215976Sjmallett uint32_t pf_en : 1; /**< Phantom Function Enable 2524215976Sjmallett This bit should never be set - OCTEON requests never use 2525215976Sjmallett phantom functions. */ 2526215976Sjmallett uint32_t etf_en : 1; /**< Extended Tag Field Enable 2527215976Sjmallett This bit should never be set - OCTEON requests never use 2528215976Sjmallett extended tags. */ 2529215976Sjmallett uint32_t mps : 3; /**< Max Payload Size 2530215976Sjmallett Legal values: 2531215976Sjmallett 0 = 128B 2532215976Sjmallett 1 = 256B 2533215976Sjmallett Larger sizes not supported. 2534215976Sjmallett Note: Both PCI Express Ports must be set to the same value 2535215976Sjmallett for Peer-to-Peer to function properly. 2536215976Sjmallett Note: DPI_SLI_PRT#_CFG[MPS] must also be set to the same 2537215976Sjmallett value for proper functionality. */ 2538232812Sjmallett uint32_t ro_en : 1; /**< Enable Relaxed Ordering 2539232812Sjmallett This bit is not used. */ 2540215976Sjmallett uint32_t ur_en : 1; /**< Unsupported Request Reporting Enable */ 2541215976Sjmallett uint32_t fe_en : 1; /**< Fatal Error Reporting Enable */ 2542215976Sjmallett uint32_t nfe_en : 1; /**< Non-Fatal Error Reporting Enable */ 2543215976Sjmallett uint32_t ce_en : 1; /**< Correctable Error Reporting Enable */ 2544215976Sjmallett#else 2545215976Sjmallett uint32_t ce_en : 1; 2546215976Sjmallett uint32_t nfe_en : 1; 2547215976Sjmallett uint32_t fe_en : 1; 2548215976Sjmallett uint32_t ur_en : 1; 2549215976Sjmallett uint32_t ro_en : 1; 2550215976Sjmallett uint32_t mps : 3; 2551215976Sjmallett uint32_t etf_en : 1; 2552215976Sjmallett uint32_t pf_en : 1; 2553215976Sjmallett uint32_t ap_en : 1; 2554215976Sjmallett uint32_t ns_en : 1; 2555215976Sjmallett uint32_t mrrs : 3; 2556215976Sjmallett uint32_t reserved_15_15 : 1; 2557215976Sjmallett uint32_t ce_d : 1; 2558215976Sjmallett uint32_t nfe_d : 1; 2559215976Sjmallett uint32_t fe_d : 1; 2560215976Sjmallett uint32_t ur_d : 1; 2561215976Sjmallett uint32_t ap_d : 1; 2562215976Sjmallett uint32_t tp : 1; 2563215976Sjmallett uint32_t reserved_22_31 : 10; 2564215976Sjmallett#endif 2565215976Sjmallett } s; 2566215976Sjmallett struct cvmx_pciercx_cfg030_s cn52xx; 2567215976Sjmallett struct cvmx_pciercx_cfg030_s cn52xxp1; 2568215976Sjmallett struct cvmx_pciercx_cfg030_s cn56xx; 2569215976Sjmallett struct cvmx_pciercx_cfg030_s cn56xxp1; 2570232812Sjmallett struct cvmx_pciercx_cfg030_s cn61xx; 2571215976Sjmallett struct cvmx_pciercx_cfg030_s cn63xx; 2572215976Sjmallett struct cvmx_pciercx_cfg030_s cn63xxp1; 2573232812Sjmallett struct cvmx_pciercx_cfg030_s cn66xx; 2574232812Sjmallett struct cvmx_pciercx_cfg030_s cn68xx; 2575232812Sjmallett struct cvmx_pciercx_cfg030_s cn68xxp1; 2576232812Sjmallett struct cvmx_pciercx_cfg030_s cnf71xx; 2577215976Sjmallett}; 2578215976Sjmalletttypedef union cvmx_pciercx_cfg030 cvmx_pciercx_cfg030_t; 2579215976Sjmallett 2580215976Sjmallett/** 2581215976Sjmallett * cvmx_pcierc#_cfg031 2582215976Sjmallett * 2583215976Sjmallett * PCIE_CFG031 = Thirty-second 32-bits of PCIE type 1 config space 2584215976Sjmallett * (Link Capabilities Register) 2585215976Sjmallett */ 2586232812Sjmallettunion cvmx_pciercx_cfg031 { 2587215976Sjmallett uint32_t u32; 2588232812Sjmallett struct cvmx_pciercx_cfg031_s { 2589232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2590232812Sjmallett uint32_t pnum : 8; /**< Port Number 2591232812Sjmallett writable through PEM(0..1)_CFG_WR, however the application 2592232812Sjmallett must not change this field. */ 2593232812Sjmallett uint32_t reserved_23_23 : 1; 2594232812Sjmallett uint32_t aspm : 1; /**< ASPM Optionality Compliance */ 2595232812Sjmallett uint32_t lbnc : 1; /**< Link Bandwidth Notification Capability 2596232812Sjmallett Set to 1 for Root Complex devices. writable through PEM(0..1)_CFG_WR. 2597215976Sjmallett However, the application must not change this field. */ 2598215976Sjmallett uint32_t dllarc : 1; /**< Data Link Layer Active Reporting Capable 2599215976Sjmallett Set to 1 for Root Complex devices and 0 for Endpoint devices. */ 2600215976Sjmallett uint32_t sderc : 1; /**< Surprise Down Error Reporting Capable 2601215976Sjmallett Not supported, hardwired to 0x0. */ 2602215976Sjmallett uint32_t cpm : 1; /**< Clock Power Management 2603215976Sjmallett The default value is the value you specify during hardware 2604215976Sjmallett configuration, writable through PEM(0..1)_CFG_WR. 2605215976Sjmallett However, the application must not change this field. */ 2606215976Sjmallett uint32_t l1el : 3; /**< L1 Exit Latency 2607215976Sjmallett The default value is the value you specify during hardware 2608215976Sjmallett configuration, writable through PEM(0..1)_CFG_WR. 2609215976Sjmallett However, the application must not change this field. */ 2610215976Sjmallett uint32_t l0el : 3; /**< L0s Exit Latency 2611215976Sjmallett The default value is the value you specify during hardware 2612215976Sjmallett configuration, writable through PEM(0..1)_CFG_WR. 2613215976Sjmallett However, the application must not change this field. */ 2614215976Sjmallett uint32_t aslpms : 2; /**< Active State Link PM Support 2615215976Sjmallett The default value is the value you specify during hardware 2616215976Sjmallett configuration, writable through PEM(0..1)_CFG_WR. 2617215976Sjmallett However, the application must not change this field. */ 2618215976Sjmallett uint32_t mlw : 6; /**< Maximum Link Width 2619215976Sjmallett The default value is the value you specify during hardware 2620232812Sjmallett configuration (x1 or x2) writable through PEM(0..1)_CFG_WR. */ 2621215976Sjmallett uint32_t mls : 4; /**< Maximum Link Speed 2622232812Sjmallett The reset value of this field is controlled by a value sent from 2623232812Sjmallett the lsb of the MIO_QLM#_SPD register. 2624232812Sjmallett qlm#_spd[0] RST_VALUE NOTE 2625232812Sjmallett 1 0001b 2.5 GHz supported 2626232812Sjmallett 0 0010b 5.0 GHz and 2.5 GHz supported 2627215976Sjmallett This field is writable through PEM(0..1)_CFG_WR. 2628215976Sjmallett However, the application must not change this field. */ 2629215976Sjmallett#else 2630215976Sjmallett uint32_t mls : 4; 2631215976Sjmallett uint32_t mlw : 6; 2632215976Sjmallett uint32_t aslpms : 2; 2633215976Sjmallett uint32_t l0el : 3; 2634215976Sjmallett uint32_t l1el : 3; 2635215976Sjmallett uint32_t cpm : 1; 2636215976Sjmallett uint32_t sderc : 1; 2637215976Sjmallett uint32_t dllarc : 1; 2638215976Sjmallett uint32_t lbnc : 1; 2639232812Sjmallett uint32_t aspm : 1; 2640232812Sjmallett uint32_t reserved_23_23 : 1; 2641232812Sjmallett uint32_t pnum : 8; 2642232812Sjmallett#endif 2643232812Sjmallett } s; 2644232812Sjmallett struct cvmx_pciercx_cfg031_cn52xx { 2645232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2646232812Sjmallett uint32_t pnum : 8; /**< Port Number, writable through PESC(0..1)_CFG_WR 2647232812Sjmallett However, the application must not change this field. */ 2648215976Sjmallett uint32_t reserved_22_23 : 2; 2649232812Sjmallett uint32_t lbnc : 1; /**< Link Bandwith Notification Capability */ 2650232812Sjmallett uint32_t dllarc : 1; /**< Data Link Layer Active Reporting Capable 2651232812Sjmallett Set to 1 for Root Complex devices and 0 for Endpoint devices. */ 2652232812Sjmallett uint32_t sderc : 1; /**< Surprise Down Error Reporting Capable 2653232812Sjmallett Not supported, hardwired to 0x0. */ 2654232812Sjmallett uint32_t cpm : 1; /**< Clock Power Management 2655232812Sjmallett The default value is the value you specify during hardware 2656232812Sjmallett configuration, writable through PESC(0..1)_CFG_WR. 2657232812Sjmallett However, the application must not change this field. */ 2658232812Sjmallett uint32_t l1el : 3; /**< L1 Exit Latency 2659232812Sjmallett The default value is the value you specify during hardware 2660232812Sjmallett configuration, writable through PESC(0..1)_CFG_WR. 2661232812Sjmallett However, the application must not change this field. */ 2662232812Sjmallett uint32_t l0el : 3; /**< L0s Exit Latency 2663232812Sjmallett The default value is the value you specify during hardware 2664232812Sjmallett configuration, writable through PESC(0..1)_CFG_WR. 2665232812Sjmallett However, the application must not change this field. */ 2666232812Sjmallett uint32_t aslpms : 2; /**< Active State Link PM Support 2667232812Sjmallett The default value is the value you specify during hardware 2668232812Sjmallett configuration, writable through PESC(0..1)_CFG_WR. 2669232812Sjmallett However, the application must not change this field. */ 2670232812Sjmallett uint32_t mlw : 6; /**< Maximum Link Width 2671232812Sjmallett The default value is the value you specify during hardware 2672232812Sjmallett configuration (x1, x4, x8, or x16), writable through PESC(0..1)_CFG_WR. 2673232812Sjmallett The SW needs to set this to 0x4 or 0x2 depending on the max 2674232812Sjmallett number of lanes (QLM_CFG == 1 set to 0x4 else 0x2). */ 2675232812Sjmallett uint32_t mls : 4; /**< Maximum Link Speed 2676232812Sjmallett Default value is 0x1 for 2.5 Gbps Link. 2677232812Sjmallett This field is writable through PESC(0..1)_CFG_WR. 2678232812Sjmallett However, 0x1 is the 2679232812Sjmallett only supported value. Therefore, the application must not write 2680232812Sjmallett any value other than 0x1 to this field. */ 2681232812Sjmallett#else 2682232812Sjmallett uint32_t mls : 4; 2683232812Sjmallett uint32_t mlw : 6; 2684232812Sjmallett uint32_t aslpms : 2; 2685232812Sjmallett uint32_t l0el : 3; 2686232812Sjmallett uint32_t l1el : 3; 2687232812Sjmallett uint32_t cpm : 1; 2688232812Sjmallett uint32_t sderc : 1; 2689232812Sjmallett uint32_t dllarc : 1; 2690232812Sjmallett uint32_t lbnc : 1; 2691232812Sjmallett uint32_t reserved_22_23 : 2; 2692215976Sjmallett uint32_t pnum : 8; 2693215976Sjmallett#endif 2694232812Sjmallett } cn52xx; 2695232812Sjmallett struct cvmx_pciercx_cfg031_cn52xx cn52xxp1; 2696232812Sjmallett struct cvmx_pciercx_cfg031_cn52xx cn56xx; 2697232812Sjmallett struct cvmx_pciercx_cfg031_cn52xx cn56xxp1; 2698232812Sjmallett struct cvmx_pciercx_cfg031_s cn61xx; 2699232812Sjmallett struct cvmx_pciercx_cfg031_cn52xx cn63xx; 2700232812Sjmallett struct cvmx_pciercx_cfg031_cn52xx cn63xxp1; 2701232812Sjmallett struct cvmx_pciercx_cfg031_s cn66xx; 2702232812Sjmallett struct cvmx_pciercx_cfg031_s cn68xx; 2703232812Sjmallett struct cvmx_pciercx_cfg031_cn52xx cn68xxp1; 2704232812Sjmallett struct cvmx_pciercx_cfg031_s cnf71xx; 2705215976Sjmallett}; 2706215976Sjmalletttypedef union cvmx_pciercx_cfg031 cvmx_pciercx_cfg031_t; 2707215976Sjmallett 2708215976Sjmallett/** 2709215976Sjmallett * cvmx_pcierc#_cfg032 2710215976Sjmallett * 2711215976Sjmallett * PCIE_CFG032 = Thirty-third 32-bits of PCIE type 1 config space 2712215976Sjmallett * (Link Control Register/Link Status Register) 2713215976Sjmallett */ 2714232812Sjmallettunion cvmx_pciercx_cfg032 { 2715215976Sjmallett uint32_t u32; 2716232812Sjmallett struct cvmx_pciercx_cfg032_s { 2717232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2718232812Sjmallett uint32_t lab : 1; /**< Link Autonomous Bandwidth Status 2719232812Sjmallett this bit is set to indicate that hardware has autonomously 2720232812Sjmallett changed Link speed or width, without the Port transitioning 2721232812Sjmallett through DL_Down status, for reasons other than to attempt 2722232812Sjmallett to correct unreliable Link operation. */ 2723232812Sjmallett uint32_t lbm : 1; /**< Link Bandwidth Management Status 2724232812Sjmallett This bit is set to indicate either of the following has 2725232812Sjmallett occurred without the Port transitioning through DL_DOWN status 2726232812Sjmallett o A link retraining has completed following a write of 1b to 2727232812Sjmallett the Retrain Link bit 2728232812Sjmallett o Hardware has changed the Link speed or width to attempt to 2729232812Sjmallett correct unreliable Link operation, either through a LTSSM 2730232812Sjmallett timeout of higher level process. This bit must be set if 2731232812Sjmallett the Physical Layer reports a speed or width change was 2732232812Sjmallett inititiated by the Downstream component tha was not 2733232812Sjmallett indicated as an autonomous change */ 2734215976Sjmallett uint32_t dlla : 1; /**< Data Link Layer Active */ 2735215976Sjmallett uint32_t scc : 1; /**< Slot Clock Configuration 2736215976Sjmallett Indicates that the component uses the same physical reference 2737215976Sjmallett clock that the platform provides on the connector. The default 2738215976Sjmallett value is the value you select during hardware configuration, 2739215976Sjmallett writable through PEM(0..1)_CFG_WR. 2740215976Sjmallett However, the application must not change this field. */ 2741215976Sjmallett uint32_t lt : 1; /**< Link Training */ 2742215976Sjmallett uint32_t reserved_26_26 : 1; 2743215976Sjmallett uint32_t nlw : 6; /**< Negotiated Link Width 2744232812Sjmallett Set automatically by hardware after Link initialization. 2745232812Sjmallett Value is undefined when link is not up. */ 2746215976Sjmallett uint32_t ls : 4; /**< Link Speed 2747232812Sjmallett 0001 == The negotiated Link speed: 2.5 Gbps 2748232812Sjmallett 0010 == The negotiated Link speed: 5.0 Gbps 2749232812Sjmallett 0100 == The negotiated Link speed: 8.0 Gbps (Not Supported) */ 2750215976Sjmallett uint32_t reserved_12_15 : 4; 2751215976Sjmallett uint32_t lab_int_enb : 1; /**< Link Autonomous Bandwidth Interrupt Enable 2752232812Sjmallett When set, enables the generation of an interrupt to indicate 2753232812Sjmallett that the Link Autonomous Bandwidth Status bit has been set. */ 2754215976Sjmallett uint32_t lbm_int_enb : 1; /**< Link Bandwidth Management Interrupt Enable 2755232812Sjmallett When set, enables the generation of an interrupt to indicate 2756232812Sjmallett that the Link Bandwidth Management Status bit has been set. */ 2757215976Sjmallett uint32_t hawd : 1; /**< Hardware Autonomous Width Disable 2758215976Sjmallett (Not Supported) */ 2759215976Sjmallett uint32_t ecpm : 1; /**< Enable Clock Power Management 2760215976Sjmallett Hardwired to 0 if Clock Power Management is disabled in 2761215976Sjmallett the Link Capabilities register. */ 2762215976Sjmallett uint32_t es : 1; /**< Extended Synch */ 2763215976Sjmallett uint32_t ccc : 1; /**< Common Clock Configuration */ 2764215976Sjmallett uint32_t rl : 1; /**< Retrain Link */ 2765215976Sjmallett uint32_t ld : 1; /**< Link Disable */ 2766215976Sjmallett uint32_t rcb : 1; /**< Read Completion Boundary (RCB), writable through PEM(0..1)_CFG_WR 2767215976Sjmallett However, the application must not change this field 2768215976Sjmallett because an RCB of 64 bytes is not supported. */ 2769215976Sjmallett uint32_t reserved_2_2 : 1; 2770215976Sjmallett uint32_t aslpc : 2; /**< Active State Link PM Control */ 2771215976Sjmallett#else 2772215976Sjmallett uint32_t aslpc : 2; 2773215976Sjmallett uint32_t reserved_2_2 : 1; 2774215976Sjmallett uint32_t rcb : 1; 2775215976Sjmallett uint32_t ld : 1; 2776215976Sjmallett uint32_t rl : 1; 2777215976Sjmallett uint32_t ccc : 1; 2778215976Sjmallett uint32_t es : 1; 2779215976Sjmallett uint32_t ecpm : 1; 2780215976Sjmallett uint32_t hawd : 1; 2781215976Sjmallett uint32_t lbm_int_enb : 1; 2782215976Sjmallett uint32_t lab_int_enb : 1; 2783215976Sjmallett uint32_t reserved_12_15 : 4; 2784215976Sjmallett uint32_t ls : 4; 2785215976Sjmallett uint32_t nlw : 6; 2786215976Sjmallett uint32_t reserved_26_26 : 1; 2787215976Sjmallett uint32_t lt : 1; 2788215976Sjmallett uint32_t scc : 1; 2789215976Sjmallett uint32_t dlla : 1; 2790215976Sjmallett uint32_t lbm : 1; 2791215976Sjmallett uint32_t lab : 1; 2792215976Sjmallett#endif 2793215976Sjmallett } s; 2794215976Sjmallett struct cvmx_pciercx_cfg032_s cn52xx; 2795215976Sjmallett struct cvmx_pciercx_cfg032_s cn52xxp1; 2796215976Sjmallett struct cvmx_pciercx_cfg032_s cn56xx; 2797215976Sjmallett struct cvmx_pciercx_cfg032_s cn56xxp1; 2798232812Sjmallett struct cvmx_pciercx_cfg032_s cn61xx; 2799215976Sjmallett struct cvmx_pciercx_cfg032_s cn63xx; 2800215976Sjmallett struct cvmx_pciercx_cfg032_s cn63xxp1; 2801232812Sjmallett struct cvmx_pciercx_cfg032_s cn66xx; 2802232812Sjmallett struct cvmx_pciercx_cfg032_s cn68xx; 2803232812Sjmallett struct cvmx_pciercx_cfg032_s cn68xxp1; 2804232812Sjmallett struct cvmx_pciercx_cfg032_s cnf71xx; 2805215976Sjmallett}; 2806215976Sjmalletttypedef union cvmx_pciercx_cfg032 cvmx_pciercx_cfg032_t; 2807215976Sjmallett 2808215976Sjmallett/** 2809215976Sjmallett * cvmx_pcierc#_cfg033 2810215976Sjmallett * 2811215976Sjmallett * PCIE_CFG033 = Thirty-fourth 32-bits of PCIE type 1 config space 2812215976Sjmallett * (Slot Capabilities Register) 2813215976Sjmallett */ 2814232812Sjmallettunion cvmx_pciercx_cfg033 { 2815215976Sjmallett uint32_t u32; 2816232812Sjmallett struct cvmx_pciercx_cfg033_s { 2817232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2818215976Sjmallett uint32_t ps_num : 13; /**< Physical Slot Number, writable through PEM(0..1)_CFG_WR 2819215976Sjmallett However, the application must not change this field. */ 2820215976Sjmallett uint32_t nccs : 1; /**< No Command Complete Support, writable through PEM(0..1)_CFG_WR 2821215976Sjmallett However, the application must not change this field. */ 2822215976Sjmallett uint32_t emip : 1; /**< Electromechanical Interlock Present, writable through PEM(0..1)_CFG_WR 2823215976Sjmallett However, the application must not change this field. */ 2824215976Sjmallett uint32_t sp_ls : 2; /**< Slot Power Limit Scale, writable through PEM(0..1)_CFG_WR. */ 2825215976Sjmallett uint32_t sp_lv : 8; /**< Slot Power Limit Value, writable through PEM(0..1)_CFG_WR. */ 2826215976Sjmallett uint32_t hp_c : 1; /**< Hot-Plug Capable, writable through PEM(0..1)_CFG_WR 2827215976Sjmallett However, the application must not change this field. */ 2828215976Sjmallett uint32_t hp_s : 1; /**< Hot-Plug Surprise, writable through PEM(0..1)_CFG_WR 2829215976Sjmallett However, the application must not change this field. */ 2830215976Sjmallett uint32_t pip : 1; /**< Power Indicator Present, writable through PEM(0..1)_CFG_WR 2831215976Sjmallett However, the application must not change this field. */ 2832215976Sjmallett uint32_t aip : 1; /**< Attention Indicator Present, writable through PEM(0..1)_CFG_WR 2833215976Sjmallett However, the application must not change this field. */ 2834215976Sjmallett uint32_t mrlsp : 1; /**< MRL Sensor Present, writable through PEM(0..1)_CFG_WR 2835215976Sjmallett However, the application must not change this field. */ 2836215976Sjmallett uint32_t pcp : 1; /**< Power Controller Present, writable through PEM(0..1)_CFG_WR 2837215976Sjmallett However, the application must not change this field. */ 2838215976Sjmallett uint32_t abp : 1; /**< Attention Button Present, writable through PEM(0..1)_CFG_WR 2839215976Sjmallett However, the application must not change this field. */ 2840215976Sjmallett#else 2841215976Sjmallett uint32_t abp : 1; 2842215976Sjmallett uint32_t pcp : 1; 2843215976Sjmallett uint32_t mrlsp : 1; 2844215976Sjmallett uint32_t aip : 1; 2845215976Sjmallett uint32_t pip : 1; 2846215976Sjmallett uint32_t hp_s : 1; 2847215976Sjmallett uint32_t hp_c : 1; 2848215976Sjmallett uint32_t sp_lv : 8; 2849215976Sjmallett uint32_t sp_ls : 2; 2850215976Sjmallett uint32_t emip : 1; 2851215976Sjmallett uint32_t nccs : 1; 2852215976Sjmallett uint32_t ps_num : 13; 2853215976Sjmallett#endif 2854215976Sjmallett } s; 2855215976Sjmallett struct cvmx_pciercx_cfg033_s cn52xx; 2856215976Sjmallett struct cvmx_pciercx_cfg033_s cn52xxp1; 2857215976Sjmallett struct cvmx_pciercx_cfg033_s cn56xx; 2858215976Sjmallett struct cvmx_pciercx_cfg033_s cn56xxp1; 2859232812Sjmallett struct cvmx_pciercx_cfg033_s cn61xx; 2860215976Sjmallett struct cvmx_pciercx_cfg033_s cn63xx; 2861215976Sjmallett struct cvmx_pciercx_cfg033_s cn63xxp1; 2862232812Sjmallett struct cvmx_pciercx_cfg033_s cn66xx; 2863232812Sjmallett struct cvmx_pciercx_cfg033_s cn68xx; 2864232812Sjmallett struct cvmx_pciercx_cfg033_s cn68xxp1; 2865232812Sjmallett struct cvmx_pciercx_cfg033_s cnf71xx; 2866215976Sjmallett}; 2867215976Sjmalletttypedef union cvmx_pciercx_cfg033 cvmx_pciercx_cfg033_t; 2868215976Sjmallett 2869215976Sjmallett/** 2870215976Sjmallett * cvmx_pcierc#_cfg034 2871215976Sjmallett * 2872215976Sjmallett * PCIE_CFG034 = Thirty-fifth 32-bits of PCIE type 1 config space 2873215976Sjmallett * (Slot Control Register/Slot Status Register) 2874215976Sjmallett */ 2875232812Sjmallettunion cvmx_pciercx_cfg034 { 2876215976Sjmallett uint32_t u32; 2877232812Sjmallett struct cvmx_pciercx_cfg034_s { 2878232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2879215976Sjmallett uint32_t reserved_25_31 : 7; 2880215976Sjmallett uint32_t dlls_c : 1; /**< Data Link Layer State Changed */ 2881215976Sjmallett uint32_t emis : 1; /**< Electromechanical Interlock Status */ 2882215976Sjmallett uint32_t pds : 1; /**< Presence Detect State */ 2883215976Sjmallett uint32_t mrlss : 1; /**< MRL Sensor State */ 2884215976Sjmallett uint32_t ccint_d : 1; /**< Command Completed */ 2885215976Sjmallett uint32_t pd_c : 1; /**< Presence Detect Changed */ 2886215976Sjmallett uint32_t mrls_c : 1; /**< MRL Sensor Changed */ 2887215976Sjmallett uint32_t pf_d : 1; /**< Power Fault Detected */ 2888215976Sjmallett uint32_t abp_d : 1; /**< Attention Button Pressed */ 2889215976Sjmallett uint32_t reserved_13_15 : 3; 2890215976Sjmallett uint32_t dlls_en : 1; /**< Data Link Layer State Changed Enable */ 2891215976Sjmallett uint32_t emic : 1; /**< Electromechanical Interlock Control */ 2892215976Sjmallett uint32_t pcc : 1; /**< Power Controller Control */ 2893215976Sjmallett uint32_t pic : 2; /**< Power Indicator Control */ 2894215976Sjmallett uint32_t aic : 2; /**< Attention Indicator Control */ 2895215976Sjmallett uint32_t hpint_en : 1; /**< Hot-Plug Interrupt Enable */ 2896215976Sjmallett uint32_t ccint_en : 1; /**< Command Completed Interrupt Enable */ 2897215976Sjmallett uint32_t pd_en : 1; /**< Presence Detect Changed Enable */ 2898215976Sjmallett uint32_t mrls_en : 1; /**< MRL Sensor Changed Enable */ 2899215976Sjmallett uint32_t pf_en : 1; /**< Power Fault Detected Enable */ 2900215976Sjmallett uint32_t abp_en : 1; /**< Attention Button Pressed Enable */ 2901215976Sjmallett#else 2902215976Sjmallett uint32_t abp_en : 1; 2903215976Sjmallett uint32_t pf_en : 1; 2904215976Sjmallett uint32_t mrls_en : 1; 2905215976Sjmallett uint32_t pd_en : 1; 2906215976Sjmallett uint32_t ccint_en : 1; 2907215976Sjmallett uint32_t hpint_en : 1; 2908215976Sjmallett uint32_t aic : 2; 2909215976Sjmallett uint32_t pic : 2; 2910215976Sjmallett uint32_t pcc : 1; 2911215976Sjmallett uint32_t emic : 1; 2912215976Sjmallett uint32_t dlls_en : 1; 2913215976Sjmallett uint32_t reserved_13_15 : 3; 2914215976Sjmallett uint32_t abp_d : 1; 2915215976Sjmallett uint32_t pf_d : 1; 2916215976Sjmallett uint32_t mrls_c : 1; 2917215976Sjmallett uint32_t pd_c : 1; 2918215976Sjmallett uint32_t ccint_d : 1; 2919215976Sjmallett uint32_t mrlss : 1; 2920215976Sjmallett uint32_t pds : 1; 2921215976Sjmallett uint32_t emis : 1; 2922215976Sjmallett uint32_t dlls_c : 1; 2923215976Sjmallett uint32_t reserved_25_31 : 7; 2924215976Sjmallett#endif 2925215976Sjmallett } s; 2926215976Sjmallett struct cvmx_pciercx_cfg034_s cn52xx; 2927215976Sjmallett struct cvmx_pciercx_cfg034_s cn52xxp1; 2928215976Sjmallett struct cvmx_pciercx_cfg034_s cn56xx; 2929215976Sjmallett struct cvmx_pciercx_cfg034_s cn56xxp1; 2930232812Sjmallett struct cvmx_pciercx_cfg034_s cn61xx; 2931215976Sjmallett struct cvmx_pciercx_cfg034_s cn63xx; 2932215976Sjmallett struct cvmx_pciercx_cfg034_s cn63xxp1; 2933232812Sjmallett struct cvmx_pciercx_cfg034_s cn66xx; 2934232812Sjmallett struct cvmx_pciercx_cfg034_s cn68xx; 2935232812Sjmallett struct cvmx_pciercx_cfg034_s cn68xxp1; 2936232812Sjmallett struct cvmx_pciercx_cfg034_s cnf71xx; 2937215976Sjmallett}; 2938215976Sjmalletttypedef union cvmx_pciercx_cfg034 cvmx_pciercx_cfg034_t; 2939215976Sjmallett 2940215976Sjmallett/** 2941215976Sjmallett * cvmx_pcierc#_cfg035 2942215976Sjmallett * 2943215976Sjmallett * PCIE_CFG035 = Thirty-sixth 32-bits of PCIE type 1 config space 2944215976Sjmallett * (Root Control Register/Root Capabilities Register) 2945215976Sjmallett */ 2946232812Sjmallettunion cvmx_pciercx_cfg035 { 2947215976Sjmallett uint32_t u32; 2948232812Sjmallett struct cvmx_pciercx_cfg035_s { 2949232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2950215976Sjmallett uint32_t reserved_17_31 : 15; 2951215976Sjmallett uint32_t crssv : 1; /**< CRS Software Visibility 2952215976Sjmallett Not supported, hardwired to 0x0. */ 2953215976Sjmallett uint32_t reserved_5_15 : 11; 2954215976Sjmallett uint32_t crssve : 1; /**< CRS Software Visibility Enable 2955215976Sjmallett Not supported, hardwired to 0x0. */ 2956215976Sjmallett uint32_t pmeie : 1; /**< PME Interrupt Enable */ 2957215976Sjmallett uint32_t sefee : 1; /**< System Error on Fatal Error Enable */ 2958215976Sjmallett uint32_t senfee : 1; /**< System Error on Non-fatal Error Enable */ 2959215976Sjmallett uint32_t secee : 1; /**< System Error on Correctable Error Enable */ 2960215976Sjmallett#else 2961215976Sjmallett uint32_t secee : 1; 2962215976Sjmallett uint32_t senfee : 1; 2963215976Sjmallett uint32_t sefee : 1; 2964215976Sjmallett uint32_t pmeie : 1; 2965215976Sjmallett uint32_t crssve : 1; 2966215976Sjmallett uint32_t reserved_5_15 : 11; 2967215976Sjmallett uint32_t crssv : 1; 2968215976Sjmallett uint32_t reserved_17_31 : 15; 2969215976Sjmallett#endif 2970215976Sjmallett } s; 2971215976Sjmallett struct cvmx_pciercx_cfg035_s cn52xx; 2972215976Sjmallett struct cvmx_pciercx_cfg035_s cn52xxp1; 2973215976Sjmallett struct cvmx_pciercx_cfg035_s cn56xx; 2974215976Sjmallett struct cvmx_pciercx_cfg035_s cn56xxp1; 2975232812Sjmallett struct cvmx_pciercx_cfg035_s cn61xx; 2976215976Sjmallett struct cvmx_pciercx_cfg035_s cn63xx; 2977215976Sjmallett struct cvmx_pciercx_cfg035_s cn63xxp1; 2978232812Sjmallett struct cvmx_pciercx_cfg035_s cn66xx; 2979232812Sjmallett struct cvmx_pciercx_cfg035_s cn68xx; 2980232812Sjmallett struct cvmx_pciercx_cfg035_s cn68xxp1; 2981232812Sjmallett struct cvmx_pciercx_cfg035_s cnf71xx; 2982215976Sjmallett}; 2983215976Sjmalletttypedef union cvmx_pciercx_cfg035 cvmx_pciercx_cfg035_t; 2984215976Sjmallett 2985215976Sjmallett/** 2986215976Sjmallett * cvmx_pcierc#_cfg036 2987215976Sjmallett * 2988215976Sjmallett * PCIE_CFG036 = Thirty-seventh 32-bits of PCIE type 1 config space 2989215976Sjmallett * (Root Status Register) 2990215976Sjmallett */ 2991232812Sjmallettunion cvmx_pciercx_cfg036 { 2992215976Sjmallett uint32_t u32; 2993232812Sjmallett struct cvmx_pciercx_cfg036_s { 2994232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2995215976Sjmallett uint32_t reserved_18_31 : 14; 2996215976Sjmallett uint32_t pme_pend : 1; /**< PME Pending */ 2997215976Sjmallett uint32_t pme_stat : 1; /**< PME Status */ 2998215976Sjmallett uint32_t pme_rid : 16; /**< PME Requester ID */ 2999215976Sjmallett#else 3000215976Sjmallett uint32_t pme_rid : 16; 3001215976Sjmallett uint32_t pme_stat : 1; 3002215976Sjmallett uint32_t pme_pend : 1; 3003215976Sjmallett uint32_t reserved_18_31 : 14; 3004215976Sjmallett#endif 3005215976Sjmallett } s; 3006215976Sjmallett struct cvmx_pciercx_cfg036_s cn52xx; 3007215976Sjmallett struct cvmx_pciercx_cfg036_s cn52xxp1; 3008215976Sjmallett struct cvmx_pciercx_cfg036_s cn56xx; 3009215976Sjmallett struct cvmx_pciercx_cfg036_s cn56xxp1; 3010232812Sjmallett struct cvmx_pciercx_cfg036_s cn61xx; 3011215976Sjmallett struct cvmx_pciercx_cfg036_s cn63xx; 3012215976Sjmallett struct cvmx_pciercx_cfg036_s cn63xxp1; 3013232812Sjmallett struct cvmx_pciercx_cfg036_s cn66xx; 3014232812Sjmallett struct cvmx_pciercx_cfg036_s cn68xx; 3015232812Sjmallett struct cvmx_pciercx_cfg036_s cn68xxp1; 3016232812Sjmallett struct cvmx_pciercx_cfg036_s cnf71xx; 3017215976Sjmallett}; 3018215976Sjmalletttypedef union cvmx_pciercx_cfg036 cvmx_pciercx_cfg036_t; 3019215976Sjmallett 3020215976Sjmallett/** 3021215976Sjmallett * cvmx_pcierc#_cfg037 3022215976Sjmallett * 3023215976Sjmallett * PCIE_CFG037 = Thirty-eighth 32-bits of PCIE type 1 config space 3024215976Sjmallett * (Device Capabilities 2 Register) 3025215976Sjmallett */ 3026232812Sjmallettunion cvmx_pciercx_cfg037 { 3027215976Sjmallett uint32_t u32; 3028232812Sjmallett struct cvmx_pciercx_cfg037_s { 3029232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3030232812Sjmallett uint32_t reserved_20_31 : 12; 3031232812Sjmallett uint32_t obffs : 2; /**< Optimized Buffer Flush Fill (OBFF) Supported 3032232812Sjmallett (Not Supported) */ 3033232812Sjmallett uint32_t reserved_12_17 : 6; 3034232812Sjmallett uint32_t ltrs : 1; /**< Latency Tolerance Reporting (LTR) Mechanism Supported 3035232812Sjmallett (Not Supported) */ 3036232812Sjmallett uint32_t noroprpr : 1; /**< No RO-enabled PR-PR Passing 3037232812Sjmallett When set, the routing element never carries out the passing 3038232812Sjmallett permitted in the Relaxed Ordering Model. */ 3039232812Sjmallett uint32_t atom128s : 1; /**< 128-bit AtomicOp Supported 3040232812Sjmallett (Not Supported) */ 3041232812Sjmallett uint32_t atom64s : 1; /**< 64-bit AtomicOp Supported 3042232812Sjmallett (Not Supported) */ 3043232812Sjmallett uint32_t atom32s : 1; /**< 32-bit AtomicOp Supported 3044232812Sjmallett (Not Supported) */ 3045232812Sjmallett uint32_t atom_ops : 1; /**< AtomicOp Routing Supported 3046232812Sjmallett (Not Supported) */ 3047232812Sjmallett uint32_t reserved_5_5 : 1; 3048232812Sjmallett uint32_t ctds : 1; /**< Completion Timeout Disable Supported */ 3049232812Sjmallett uint32_t ctrs : 4; /**< Completion Timeout Ranges Supported */ 3050232812Sjmallett#else 3051232812Sjmallett uint32_t ctrs : 4; 3052232812Sjmallett uint32_t ctds : 1; 3053232812Sjmallett uint32_t reserved_5_5 : 1; 3054232812Sjmallett uint32_t atom_ops : 1; 3055232812Sjmallett uint32_t atom32s : 1; 3056232812Sjmallett uint32_t atom64s : 1; 3057232812Sjmallett uint32_t atom128s : 1; 3058232812Sjmallett uint32_t noroprpr : 1; 3059232812Sjmallett uint32_t ltrs : 1; 3060232812Sjmallett uint32_t reserved_12_17 : 6; 3061232812Sjmallett uint32_t obffs : 2; 3062232812Sjmallett uint32_t reserved_20_31 : 12; 3063232812Sjmallett#endif 3064232812Sjmallett } s; 3065232812Sjmallett struct cvmx_pciercx_cfg037_cn52xx { 3066232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3067215976Sjmallett uint32_t reserved_5_31 : 27; 3068215976Sjmallett uint32_t ctds : 1; /**< Completion Timeout Disable Supported */ 3069215976Sjmallett uint32_t ctrs : 4; /**< Completion Timeout Ranges Supported 3070215976Sjmallett Value of 0 indicates that Completion Timeout Programming 3071215976Sjmallett is not supported 3072215976Sjmallett Completion timeout is 16.7ms. */ 3073215976Sjmallett#else 3074215976Sjmallett uint32_t ctrs : 4; 3075215976Sjmallett uint32_t ctds : 1; 3076215976Sjmallett uint32_t reserved_5_31 : 27; 3077215976Sjmallett#endif 3078232812Sjmallett } cn52xx; 3079232812Sjmallett struct cvmx_pciercx_cfg037_cn52xx cn52xxp1; 3080232812Sjmallett struct cvmx_pciercx_cfg037_cn52xx cn56xx; 3081232812Sjmallett struct cvmx_pciercx_cfg037_cn52xx cn56xxp1; 3082232812Sjmallett struct cvmx_pciercx_cfg037_cn61xx { 3083232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3084232812Sjmallett uint32_t reserved_14_31 : 18; 3085232812Sjmallett uint32_t tph : 2; /**< TPH Completer Supported 3086232812Sjmallett (Not Supported) */ 3087232812Sjmallett uint32_t reserved_11_11 : 1; 3088232812Sjmallett uint32_t noroprpr : 1; /**< No RO-enabled PR-PR Passing 3089232812Sjmallett When set, the routing element never carries out the passing 3090232812Sjmallett permitted in the Relaxed Ordering Model. */ 3091232812Sjmallett uint32_t atom128s : 1; /**< 128-bit AtomicOp Supported 3092232812Sjmallett (Not Supported) */ 3093232812Sjmallett uint32_t atom64s : 1; /**< 64-bit AtomicOp Supported 3094232812Sjmallett (Not Supported) */ 3095232812Sjmallett uint32_t atom32s : 1; /**< 32-bit AtomicOp Supported 3096232812Sjmallett (Not Supported) */ 3097232812Sjmallett uint32_t atom_ops : 1; /**< AtomicOp Routing Supported 3098232812Sjmallett (Not Supported) */ 3099232812Sjmallett uint32_t ari_fw : 1; /**< ARI Forwarding Supported 3100232812Sjmallett (Not Supported) */ 3101232812Sjmallett uint32_t ctds : 1; /**< Completion Timeout Disable Supported */ 3102232812Sjmallett uint32_t ctrs : 4; /**< Completion Timeout Ranges Supported */ 3103232812Sjmallett#else 3104232812Sjmallett uint32_t ctrs : 4; 3105232812Sjmallett uint32_t ctds : 1; 3106232812Sjmallett uint32_t ari_fw : 1; 3107232812Sjmallett uint32_t atom_ops : 1; 3108232812Sjmallett uint32_t atom32s : 1; 3109232812Sjmallett uint32_t atom64s : 1; 3110232812Sjmallett uint32_t atom128s : 1; 3111232812Sjmallett uint32_t noroprpr : 1; 3112232812Sjmallett uint32_t reserved_11_11 : 1; 3113232812Sjmallett uint32_t tph : 2; 3114232812Sjmallett uint32_t reserved_14_31 : 18; 3115232812Sjmallett#endif 3116232812Sjmallett } cn61xx; 3117232812Sjmallett struct cvmx_pciercx_cfg037_cn52xx cn63xx; 3118232812Sjmallett struct cvmx_pciercx_cfg037_cn52xx cn63xxp1; 3119232812Sjmallett struct cvmx_pciercx_cfg037_cn66xx { 3120232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3121232812Sjmallett uint32_t reserved_14_31 : 18; 3122232812Sjmallett uint32_t tph : 2; /**< TPH Completer Supported 3123232812Sjmallett (Not Supported) */ 3124232812Sjmallett uint32_t reserved_11_11 : 1; 3125232812Sjmallett uint32_t noroprpr : 1; /**< No RO-enabled PR-PR Passing 3126232812Sjmallett When set, the routing element never carries out the passing 3127232812Sjmallett permitted in the Relaxed Ordering Model. */ 3128232812Sjmallett uint32_t atom128s : 1; /**< 128-bit AtomicOp Supported 3129232812Sjmallett (Not Supported) */ 3130232812Sjmallett uint32_t atom64s : 1; /**< 64-bit AtomicOp Supported 3131232812Sjmallett (Not Supported) */ 3132232812Sjmallett uint32_t atom32s : 1; /**< 32-bit AtomicOp Supported 3133232812Sjmallett (Not Supported) */ 3134232812Sjmallett uint32_t atom_ops : 1; /**< AtomicOp Routing Supported 3135232812Sjmallett (Not Supported) */ 3136232812Sjmallett uint32_t ari : 1; /**< Alternate Routing ID Forwarding Supported 3137232812Sjmallett (Not Supported) */ 3138232812Sjmallett uint32_t ctds : 1; /**< Completion Timeout Disable Supported */ 3139232812Sjmallett uint32_t ctrs : 4; /**< Completion Timeout Ranges Supported */ 3140232812Sjmallett#else 3141232812Sjmallett uint32_t ctrs : 4; 3142232812Sjmallett uint32_t ctds : 1; 3143232812Sjmallett uint32_t ari : 1; 3144232812Sjmallett uint32_t atom_ops : 1; 3145232812Sjmallett uint32_t atom32s : 1; 3146232812Sjmallett uint32_t atom64s : 1; 3147232812Sjmallett uint32_t atom128s : 1; 3148232812Sjmallett uint32_t noroprpr : 1; 3149232812Sjmallett uint32_t reserved_11_11 : 1; 3150232812Sjmallett uint32_t tph : 2; 3151232812Sjmallett uint32_t reserved_14_31 : 18; 3152232812Sjmallett#endif 3153232812Sjmallett } cn66xx; 3154232812Sjmallett struct cvmx_pciercx_cfg037_cn66xx cn68xx; 3155232812Sjmallett struct cvmx_pciercx_cfg037_cn66xx cn68xxp1; 3156232812Sjmallett struct cvmx_pciercx_cfg037_cnf71xx { 3157232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3158232812Sjmallett uint32_t reserved_20_31 : 12; 3159232812Sjmallett uint32_t obffs : 2; /**< Optimized Buffer Flush Fill (OBFF) Supported 3160232812Sjmallett (Not Supported) */ 3161232812Sjmallett uint32_t reserved_14_17 : 4; 3162232812Sjmallett uint32_t tphs : 2; /**< TPH Completer Supported 3163232812Sjmallett (Not Supported) */ 3164232812Sjmallett uint32_t ltrs : 1; /**< Latency Tolerance Reporting (LTR) Mechanism Supported 3165232812Sjmallett (Not Supported) */ 3166232812Sjmallett uint32_t noroprpr : 1; /**< No RO-enabled PR-PR Passing 3167232812Sjmallett When set, the routing element never carries out the passing 3168232812Sjmallett permitted in the Relaxed Ordering Model. */ 3169232812Sjmallett uint32_t atom128s : 1; /**< 128-bit AtomicOp Supported 3170232812Sjmallett (Not Supported) */ 3171232812Sjmallett uint32_t atom64s : 1; /**< 64-bit AtomicOp Supported 3172232812Sjmallett (Not Supported) */ 3173232812Sjmallett uint32_t atom32s : 1; /**< 32-bit AtomicOp Supported 3174232812Sjmallett (Not Supported) */ 3175232812Sjmallett uint32_t atom_ops : 1; /**< AtomicOp Routing Supported 3176232812Sjmallett (Not Supported) */ 3177232812Sjmallett uint32_t ari_fw : 1; /**< ARI Forwarding Supported 3178232812Sjmallett (Not Supported) */ 3179232812Sjmallett uint32_t ctds : 1; /**< Completion Timeout Disable Supported */ 3180232812Sjmallett uint32_t ctrs : 4; /**< Completion Timeout Ranges Supported */ 3181232812Sjmallett#else 3182232812Sjmallett uint32_t ctrs : 4; 3183232812Sjmallett uint32_t ctds : 1; 3184232812Sjmallett uint32_t ari_fw : 1; 3185232812Sjmallett uint32_t atom_ops : 1; 3186232812Sjmallett uint32_t atom32s : 1; 3187232812Sjmallett uint32_t atom64s : 1; 3188232812Sjmallett uint32_t atom128s : 1; 3189232812Sjmallett uint32_t noroprpr : 1; 3190232812Sjmallett uint32_t ltrs : 1; 3191232812Sjmallett uint32_t tphs : 2; 3192232812Sjmallett uint32_t reserved_14_17 : 4; 3193232812Sjmallett uint32_t obffs : 2; 3194232812Sjmallett uint32_t reserved_20_31 : 12; 3195232812Sjmallett#endif 3196232812Sjmallett } cnf71xx; 3197215976Sjmallett}; 3198215976Sjmalletttypedef union cvmx_pciercx_cfg037 cvmx_pciercx_cfg037_t; 3199215976Sjmallett 3200215976Sjmallett/** 3201215976Sjmallett * cvmx_pcierc#_cfg038 3202215976Sjmallett * 3203215976Sjmallett * PCIE_CFG038 = Thirty-ninth 32-bits of PCIE type 1 config space 3204215976Sjmallett * (Device Control 2 Register) 3205215976Sjmallett */ 3206232812Sjmallettunion cvmx_pciercx_cfg038 { 3207215976Sjmallett uint32_t u32; 3208232812Sjmallett struct cvmx_pciercx_cfg038_s { 3209232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3210232812Sjmallett uint32_t reserved_15_31 : 17; 3211232812Sjmallett uint32_t obffe : 2; /**< Optimized Buffer Flush Fill (OBFF) Enable 3212232812Sjmallett (Not Supported) */ 3213232812Sjmallett uint32_t reserved_11_12 : 2; 3214232812Sjmallett uint32_t ltre : 1; /**< Latency Tolerance Reporting (LTR) Mechanism Enable 3215232812Sjmallett (Not Supported) */ 3216232812Sjmallett uint32_t id0_cp : 1; /**< ID Based Ordering Completion Enable 3217232812Sjmallett (Not Supported) */ 3218232812Sjmallett uint32_t id0_rq : 1; /**< ID Based Ordering Request Enable 3219232812Sjmallett (Not Supported) */ 3220232812Sjmallett uint32_t atom_op_eb : 1; /**< AtomicOp Egress Blocking 3221232812Sjmallett (Not Supported)m */ 3222232812Sjmallett uint32_t atom_op : 1; /**< AtomicOp Requester Enable 3223232812Sjmallett (Not Supported) */ 3224232812Sjmallett uint32_t ari : 1; /**< Alternate Routing ID Forwarding Supported 3225232812Sjmallett (Not Supported) */ 3226232812Sjmallett uint32_t ctd : 1; /**< Completion Timeout Disable */ 3227232812Sjmallett uint32_t ctv : 4; /**< Completion Timeout Value 3228232812Sjmallett o 0000b Default range: 16 ms to 55 ms 3229232812Sjmallett o 0001b 50 us to 100 us 3230232812Sjmallett o 0010b 1 ms to 10 ms 3231232812Sjmallett o 0101b 16 ms to 55 ms 3232232812Sjmallett o 0110b 65 ms to 210 ms 3233232812Sjmallett o 1001b 260 ms to 900 ms 3234232812Sjmallett o 1010b 1 s to 3.5 s 3235232812Sjmallett o 1101b 4 s to 13 s 3236232812Sjmallett o 1110b 17 s to 64 s 3237232812Sjmallett Values not defined are reserved */ 3238232812Sjmallett#else 3239232812Sjmallett uint32_t ctv : 4; 3240232812Sjmallett uint32_t ctd : 1; 3241232812Sjmallett uint32_t ari : 1; 3242232812Sjmallett uint32_t atom_op : 1; 3243232812Sjmallett uint32_t atom_op_eb : 1; 3244232812Sjmallett uint32_t id0_rq : 1; 3245232812Sjmallett uint32_t id0_cp : 1; 3246232812Sjmallett uint32_t ltre : 1; 3247232812Sjmallett uint32_t reserved_11_12 : 2; 3248232812Sjmallett uint32_t obffe : 2; 3249232812Sjmallett uint32_t reserved_15_31 : 17; 3250232812Sjmallett#endif 3251232812Sjmallett } s; 3252232812Sjmallett struct cvmx_pciercx_cfg038_cn52xx { 3253232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3254215976Sjmallett uint32_t reserved_5_31 : 27; 3255215976Sjmallett uint32_t ctd : 1; /**< Completion Timeout Disable */ 3256215976Sjmallett uint32_t ctv : 4; /**< Completion Timeout Value 3257215976Sjmallett Completion Timeout Programming is not supported 3258215976Sjmallett Completion timeout is 16.7ms. */ 3259215976Sjmallett#else 3260215976Sjmallett uint32_t ctv : 4; 3261215976Sjmallett uint32_t ctd : 1; 3262215976Sjmallett uint32_t reserved_5_31 : 27; 3263215976Sjmallett#endif 3264232812Sjmallett } cn52xx; 3265232812Sjmallett struct cvmx_pciercx_cfg038_cn52xx cn52xxp1; 3266232812Sjmallett struct cvmx_pciercx_cfg038_cn52xx cn56xx; 3267232812Sjmallett struct cvmx_pciercx_cfg038_cn52xx cn56xxp1; 3268232812Sjmallett struct cvmx_pciercx_cfg038_cn61xx { 3269232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3270232812Sjmallett uint32_t reserved_10_31 : 22; 3271232812Sjmallett uint32_t id0_cp : 1; /**< ID Based Ordering Completion Enable 3272232812Sjmallett (Not Supported) */ 3273232812Sjmallett uint32_t id0_rq : 1; /**< ID Based Ordering Request Enable 3274232812Sjmallett (Not Supported) */ 3275232812Sjmallett uint32_t atom_op_eb : 1; /**< AtomicOp Egress Blocking 3276232812Sjmallett (Not Supported)m */ 3277232812Sjmallett uint32_t atom_op : 1; /**< AtomicOp Requester Enable 3278232812Sjmallett (Not Supported) */ 3279232812Sjmallett uint32_t ari : 1; /**< Alternate Routing ID Forwarding Supported 3280232812Sjmallett (Not Supported) */ 3281232812Sjmallett uint32_t ctd : 1; /**< Completion Timeout Disable */ 3282232812Sjmallett uint32_t ctv : 4; /**< Completion Timeout Value 3283232812Sjmallett o 0000b Default range: 16 ms to 55 ms 3284232812Sjmallett o 0001b 50 us to 100 us 3285232812Sjmallett o 0010b 1 ms to 10 ms 3286232812Sjmallett o 0101b 16 ms to 55 ms 3287232812Sjmallett o 0110b 65 ms to 210 ms 3288232812Sjmallett o 1001b 260 ms to 900 ms 3289232812Sjmallett o 1010b 1 s to 3.5 s 3290232812Sjmallett o 1101b 4 s to 13 s 3291232812Sjmallett o 1110b 17 s to 64 s 3292232812Sjmallett Values not defined are reserved */ 3293232812Sjmallett#else 3294232812Sjmallett uint32_t ctv : 4; 3295232812Sjmallett uint32_t ctd : 1; 3296232812Sjmallett uint32_t ari : 1; 3297232812Sjmallett uint32_t atom_op : 1; 3298232812Sjmallett uint32_t atom_op_eb : 1; 3299232812Sjmallett uint32_t id0_rq : 1; 3300232812Sjmallett uint32_t id0_cp : 1; 3301232812Sjmallett uint32_t reserved_10_31 : 22; 3302232812Sjmallett#endif 3303232812Sjmallett } cn61xx; 3304232812Sjmallett struct cvmx_pciercx_cfg038_cn52xx cn63xx; 3305232812Sjmallett struct cvmx_pciercx_cfg038_cn52xx cn63xxp1; 3306232812Sjmallett struct cvmx_pciercx_cfg038_cn61xx cn66xx; 3307232812Sjmallett struct cvmx_pciercx_cfg038_cn61xx cn68xx; 3308232812Sjmallett struct cvmx_pciercx_cfg038_cn61xx cn68xxp1; 3309232812Sjmallett struct cvmx_pciercx_cfg038_s cnf71xx; 3310215976Sjmallett}; 3311215976Sjmalletttypedef union cvmx_pciercx_cfg038 cvmx_pciercx_cfg038_t; 3312215976Sjmallett 3313215976Sjmallett/** 3314215976Sjmallett * cvmx_pcierc#_cfg039 3315215976Sjmallett * 3316215976Sjmallett * PCIE_CFG039 = Fourtieth 32-bits of PCIE type 1 config space 3317215976Sjmallett * (Link Capabilities 2 Register) 3318215976Sjmallett */ 3319232812Sjmallettunion cvmx_pciercx_cfg039 { 3320215976Sjmallett uint32_t u32; 3321232812Sjmallett struct cvmx_pciercx_cfg039_s { 3322232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3323232812Sjmallett uint32_t reserved_9_31 : 23; 3324232812Sjmallett uint32_t cls : 1; /**< Crosslink Supported */ 3325232812Sjmallett uint32_t slsv : 7; /**< Supported Link Speeds Vector 3326232812Sjmallett Indicates the supported Link speeds of the associated Port. 3327232812Sjmallett For each bit, a value of 1b indicates that the cooresponding 3328232812Sjmallett Link speed is supported; otherwise, the Link speed is not 3329232812Sjmallett supported. 3330232812Sjmallett Bit definitions are: 3331232812Sjmallett Bit 1 2.5 GT/s 3332232812Sjmallett Bit 2 5.0 GT/s 3333232812Sjmallett Bit 3 8.0 GT/s (Not Supported) 3334232812Sjmallett Bits 7:4 reserved 3335232812Sjmallett The reset value of this field is controlled by a value sent from 3336232812Sjmallett the lsb of the MIO_QLM#_SPD register 3337232812Sjmallett qlm#_spd[0] RST_VALUE NOTE 3338232812Sjmallett 1 0001b 2.5 GHz supported 3339232812Sjmallett 0 0011b 5.0 GHz and 2.5 GHz supported */ 3340232812Sjmallett uint32_t reserved_0_0 : 1; 3341232812Sjmallett#else 3342232812Sjmallett uint32_t reserved_0_0 : 1; 3343232812Sjmallett uint32_t slsv : 7; 3344232812Sjmallett uint32_t cls : 1; 3345232812Sjmallett uint32_t reserved_9_31 : 23; 3346232812Sjmallett#endif 3347232812Sjmallett } s; 3348232812Sjmallett struct cvmx_pciercx_cfg039_cn52xx { 3349232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3350215976Sjmallett uint32_t reserved_0_31 : 32; 3351215976Sjmallett#else 3352215976Sjmallett uint32_t reserved_0_31 : 32; 3353215976Sjmallett#endif 3354232812Sjmallett } cn52xx; 3355232812Sjmallett struct cvmx_pciercx_cfg039_cn52xx cn52xxp1; 3356232812Sjmallett struct cvmx_pciercx_cfg039_cn52xx cn56xx; 3357232812Sjmallett struct cvmx_pciercx_cfg039_cn52xx cn56xxp1; 3358232812Sjmallett struct cvmx_pciercx_cfg039_s cn61xx; 3359215976Sjmallett struct cvmx_pciercx_cfg039_s cn63xx; 3360232812Sjmallett struct cvmx_pciercx_cfg039_cn52xx cn63xxp1; 3361232812Sjmallett struct cvmx_pciercx_cfg039_s cn66xx; 3362232812Sjmallett struct cvmx_pciercx_cfg039_s cn68xx; 3363232812Sjmallett struct cvmx_pciercx_cfg039_s cn68xxp1; 3364232812Sjmallett struct cvmx_pciercx_cfg039_s cnf71xx; 3365215976Sjmallett}; 3366215976Sjmalletttypedef union cvmx_pciercx_cfg039 cvmx_pciercx_cfg039_t; 3367215976Sjmallett 3368215976Sjmallett/** 3369215976Sjmallett * cvmx_pcierc#_cfg040 3370215976Sjmallett * 3371215976Sjmallett * PCIE_CFG040 = Fourty-first 32-bits of PCIE type 1 config space 3372215976Sjmallett * (Link Control 2 Register/Link Status 2 Register) 3373215976Sjmallett */ 3374232812Sjmallettunion cvmx_pciercx_cfg040 { 3375215976Sjmallett uint32_t u32; 3376232812Sjmallett struct cvmx_pciercx_cfg040_s { 3377232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3378215976Sjmallett uint32_t reserved_17_31 : 15; 3379215976Sjmallett uint32_t cdl : 1; /**< Current De-emphasis Level 3380215976Sjmallett When the Link is operating at 5 GT/s speed, this bit 3381215976Sjmallett reflects the level of de-emphasis. Encodings: 3382215976Sjmallett 1b: -3.5 dB 3383215976Sjmallett 0b: -6 dB 3384215976Sjmallett Note: The value in this bit is undefined when the Link is 3385215976Sjmallett operating at 2.5 GT/s speed */ 3386215976Sjmallett uint32_t reserved_13_15 : 3; 3387215976Sjmallett uint32_t cde : 1; /**< Compliance De-emphasis 3388215976Sjmallett This bit sets the de-emphasis level in Polling. Compliance 3389215976Sjmallett state if the entry occurred due to the Tx Compliance 3390215976Sjmallett Receive bit being 1b. Encodings: 3391215976Sjmallett 1b: -3.5 dB 3392215976Sjmallett 0b: -6 dB 3393215976Sjmallett Note: When the Link is operating at 2.5 GT/s, the setting 3394215976Sjmallett of this bit has no effect. */ 3395215976Sjmallett uint32_t csos : 1; /**< Compliance SOS 3396215976Sjmallett When set to 1b, the LTSSM is required to send SKP 3397215976Sjmallett Ordered Sets periodically in between the (modified) 3398215976Sjmallett compliance patterns. 3399215976Sjmallett Note: When the Link is operating at 2.5 GT/s, the setting 3400215976Sjmallett of this bit has no effect. */ 3401215976Sjmallett uint32_t emc : 1; /**< Enter Modified Compliance 3402215976Sjmallett When this bit is set to 1b, the device transmits a modified 3403215976Sjmallett compliance pattern if the LTSSM enters Polling. 3404215976Sjmallett Compliance state. */ 3405215976Sjmallett uint32_t tm : 3; /**< Transmit Margin 3406215976Sjmallett This field controls the value of the non-de-emphasized 3407232812Sjmallett voltage level at the Transmitter signals: 3408215976Sjmallett - 000: 800-1200 mV for full swing 400-600 mV for half-swing 3409215976Sjmallett - 001-010: values must be monotonic with a non-zero slope 3410215976Sjmallett - 011: 200-400 mV for full-swing and 100-200 mV for halfswing 3411215976Sjmallett - 100-111: reserved 3412215976Sjmallett This field is reset to 000b on entry to the LTSSM Polling. 3413215976Sjmallett Compliance substate. 3414215976Sjmallett When operating in 5.0 GT/s mode with full swing, the 3415215976Sjmallett de-emphasis ratio must be maintained within +/- 1 dB 3416215976Sjmallett from the specification-defined operational value 3417215976Sjmallett either -3.5 or -6 dB). */ 3418215976Sjmallett uint32_t sde : 1; /**< Selectable De-emphasis 3419215976Sjmallett When the Link is operating at 5.0 GT/s speed, selects the 3420215976Sjmallett level of de-emphasis: 3421215976Sjmallett - 1: -3.5 dB 3422215976Sjmallett - 0: -6 dB 3423215976Sjmallett When the Link is operating at 2.5 GT/s speed, the setting 3424215976Sjmallett of this bit has no effect. */ 3425215976Sjmallett uint32_t hasd : 1; /**< Hardware Autonomous Speed Disable 3426215976Sjmallett When asserted, the 3427215976Sjmallett application must disable hardware from changing the Link 3428215976Sjmallett speed for device-specific reasons other than attempting to 3429215976Sjmallett correct unreliable Link operation by reducing Link speed. 3430215976Sjmallett Initial transition to the highest supported common link 3431215976Sjmallett speed is not blocked by this signal. */ 3432215976Sjmallett uint32_t ec : 1; /**< Enter Compliance 3433215976Sjmallett Software is permitted to force a link to enter Compliance 3434215976Sjmallett mode at the speed indicated in the Target Link Speed 3435215976Sjmallett field by setting this bit to 1b in both components on a link 3436215976Sjmallett and then initiating a hot reset on the link. */ 3437215976Sjmallett uint32_t tls : 4; /**< Target Link Speed 3438215976Sjmallett For Downstream ports, this field sets an upper limit on link 3439215976Sjmallett operational speed by restricting the values advertised by 3440215976Sjmallett the upstream component in its training sequences: 3441215976Sjmallett - 0001: 2.5Gb/s Target Link Speed 3442215976Sjmallett - 0010: 5Gb/s Target Link Speed 3443232812Sjmallett - 0100: 8Gb/s Target Link Speed (Not Supported) 3444215976Sjmallett All other encodings are reserved. 3445215976Sjmallett If a value is written to this field that does not correspond to 3446215976Sjmallett a speed included in the Supported Link Speeds field, the 3447215976Sjmallett result is undefined. 3448215976Sjmallett For both Upstream and Downstream ports, this field is 3449215976Sjmallett used to set the target compliance mode speed when 3450215976Sjmallett software is using the Enter Compliance bit to force a link 3451215976Sjmallett into compliance mode. 3452232812Sjmallett The reset value of this field is controlled by a value sent from 3453232812Sjmallett the lsb of the MIO_QLM#_SPD register. 3454232812Sjmallett qlm#_spd[0] RST_VALUE NOTE 3455232812Sjmallett 1 0001b 2.5 GHz supported 3456232812Sjmallett 0 0010b 5.0 GHz and 2.5 GHz supported */ 3457215976Sjmallett#else 3458215976Sjmallett uint32_t tls : 4; 3459215976Sjmallett uint32_t ec : 1; 3460215976Sjmallett uint32_t hasd : 1; 3461215976Sjmallett uint32_t sde : 1; 3462215976Sjmallett uint32_t tm : 3; 3463215976Sjmallett uint32_t emc : 1; 3464215976Sjmallett uint32_t csos : 1; 3465215976Sjmallett uint32_t cde : 1; 3466215976Sjmallett uint32_t reserved_13_15 : 3; 3467215976Sjmallett uint32_t cdl : 1; 3468215976Sjmallett uint32_t reserved_17_31 : 15; 3469215976Sjmallett#endif 3470215976Sjmallett } s; 3471232812Sjmallett struct cvmx_pciercx_cfg040_cn52xx { 3472232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3473215976Sjmallett uint32_t reserved_0_31 : 32; 3474215976Sjmallett#else 3475215976Sjmallett uint32_t reserved_0_31 : 32; 3476215976Sjmallett#endif 3477215976Sjmallett } cn52xx; 3478215976Sjmallett struct cvmx_pciercx_cfg040_cn52xx cn52xxp1; 3479215976Sjmallett struct cvmx_pciercx_cfg040_cn52xx cn56xx; 3480215976Sjmallett struct cvmx_pciercx_cfg040_cn52xx cn56xxp1; 3481232812Sjmallett struct cvmx_pciercx_cfg040_s cn61xx; 3482215976Sjmallett struct cvmx_pciercx_cfg040_s cn63xx; 3483215976Sjmallett struct cvmx_pciercx_cfg040_s cn63xxp1; 3484232812Sjmallett struct cvmx_pciercx_cfg040_s cn66xx; 3485232812Sjmallett struct cvmx_pciercx_cfg040_s cn68xx; 3486232812Sjmallett struct cvmx_pciercx_cfg040_s cn68xxp1; 3487232812Sjmallett struct cvmx_pciercx_cfg040_s cnf71xx; 3488215976Sjmallett}; 3489215976Sjmalletttypedef union cvmx_pciercx_cfg040 cvmx_pciercx_cfg040_t; 3490215976Sjmallett 3491215976Sjmallett/** 3492215976Sjmallett * cvmx_pcierc#_cfg041 3493215976Sjmallett * 3494215976Sjmallett * PCIE_CFG041 = Fourty-second 32-bits of PCIE type 1 config space 3495215976Sjmallett * (Slot Capabilities 2 Register) 3496215976Sjmallett */ 3497232812Sjmallettunion cvmx_pciercx_cfg041 { 3498215976Sjmallett uint32_t u32; 3499232812Sjmallett struct cvmx_pciercx_cfg041_s { 3500232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3501215976Sjmallett uint32_t reserved_0_31 : 32; 3502215976Sjmallett#else 3503215976Sjmallett uint32_t reserved_0_31 : 32; 3504215976Sjmallett#endif 3505215976Sjmallett } s; 3506215976Sjmallett struct cvmx_pciercx_cfg041_s cn52xx; 3507215976Sjmallett struct cvmx_pciercx_cfg041_s cn52xxp1; 3508215976Sjmallett struct cvmx_pciercx_cfg041_s cn56xx; 3509215976Sjmallett struct cvmx_pciercx_cfg041_s cn56xxp1; 3510232812Sjmallett struct cvmx_pciercx_cfg041_s cn61xx; 3511215976Sjmallett struct cvmx_pciercx_cfg041_s cn63xx; 3512215976Sjmallett struct cvmx_pciercx_cfg041_s cn63xxp1; 3513232812Sjmallett struct cvmx_pciercx_cfg041_s cn66xx; 3514232812Sjmallett struct cvmx_pciercx_cfg041_s cn68xx; 3515232812Sjmallett struct cvmx_pciercx_cfg041_s cn68xxp1; 3516232812Sjmallett struct cvmx_pciercx_cfg041_s cnf71xx; 3517215976Sjmallett}; 3518215976Sjmalletttypedef union cvmx_pciercx_cfg041 cvmx_pciercx_cfg041_t; 3519215976Sjmallett 3520215976Sjmallett/** 3521215976Sjmallett * cvmx_pcierc#_cfg042 3522215976Sjmallett * 3523215976Sjmallett * PCIE_CFG042 = Fourty-third 32-bits of PCIE type 1 config space 3524215976Sjmallett * (Slot Control 2 Register/Slot Status 2 Register) 3525215976Sjmallett */ 3526232812Sjmallettunion cvmx_pciercx_cfg042 { 3527215976Sjmallett uint32_t u32; 3528232812Sjmallett struct cvmx_pciercx_cfg042_s { 3529232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3530215976Sjmallett uint32_t reserved_0_31 : 32; 3531215976Sjmallett#else 3532215976Sjmallett uint32_t reserved_0_31 : 32; 3533215976Sjmallett#endif 3534215976Sjmallett } s; 3535215976Sjmallett struct cvmx_pciercx_cfg042_s cn52xx; 3536215976Sjmallett struct cvmx_pciercx_cfg042_s cn52xxp1; 3537215976Sjmallett struct cvmx_pciercx_cfg042_s cn56xx; 3538215976Sjmallett struct cvmx_pciercx_cfg042_s cn56xxp1; 3539232812Sjmallett struct cvmx_pciercx_cfg042_s cn61xx; 3540215976Sjmallett struct cvmx_pciercx_cfg042_s cn63xx; 3541215976Sjmallett struct cvmx_pciercx_cfg042_s cn63xxp1; 3542232812Sjmallett struct cvmx_pciercx_cfg042_s cn66xx; 3543232812Sjmallett struct cvmx_pciercx_cfg042_s cn68xx; 3544232812Sjmallett struct cvmx_pciercx_cfg042_s cn68xxp1; 3545232812Sjmallett struct cvmx_pciercx_cfg042_s cnf71xx; 3546215976Sjmallett}; 3547215976Sjmalletttypedef union cvmx_pciercx_cfg042 cvmx_pciercx_cfg042_t; 3548215976Sjmallett 3549215976Sjmallett/** 3550215976Sjmallett * cvmx_pcierc#_cfg064 3551215976Sjmallett * 3552215976Sjmallett * PCIE_CFG064 = Sixty-fifth 32-bits of PCIE type 1 config space 3553232812Sjmallett * (PCI Express Extended Capability Header) 3554215976Sjmallett */ 3555232812Sjmallettunion cvmx_pciercx_cfg064 { 3556215976Sjmallett uint32_t u32; 3557232812Sjmallett struct cvmx_pciercx_cfg064_s { 3558232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3559215976Sjmallett uint32_t nco : 12; /**< Next Capability Offset */ 3560215976Sjmallett uint32_t cv : 4; /**< Capability Version */ 3561215976Sjmallett uint32_t pcieec : 16; /**< PCIE Express Extended Capability */ 3562215976Sjmallett#else 3563215976Sjmallett uint32_t pcieec : 16; 3564215976Sjmallett uint32_t cv : 4; 3565215976Sjmallett uint32_t nco : 12; 3566215976Sjmallett#endif 3567215976Sjmallett } s; 3568215976Sjmallett struct cvmx_pciercx_cfg064_s cn52xx; 3569215976Sjmallett struct cvmx_pciercx_cfg064_s cn52xxp1; 3570215976Sjmallett struct cvmx_pciercx_cfg064_s cn56xx; 3571215976Sjmallett struct cvmx_pciercx_cfg064_s cn56xxp1; 3572232812Sjmallett struct cvmx_pciercx_cfg064_s cn61xx; 3573215976Sjmallett struct cvmx_pciercx_cfg064_s cn63xx; 3574215976Sjmallett struct cvmx_pciercx_cfg064_s cn63xxp1; 3575232812Sjmallett struct cvmx_pciercx_cfg064_s cn66xx; 3576232812Sjmallett struct cvmx_pciercx_cfg064_s cn68xx; 3577232812Sjmallett struct cvmx_pciercx_cfg064_s cn68xxp1; 3578232812Sjmallett struct cvmx_pciercx_cfg064_s cnf71xx; 3579215976Sjmallett}; 3580215976Sjmalletttypedef union cvmx_pciercx_cfg064 cvmx_pciercx_cfg064_t; 3581215976Sjmallett 3582215976Sjmallett/** 3583215976Sjmallett * cvmx_pcierc#_cfg065 3584215976Sjmallett * 3585215976Sjmallett * PCIE_CFG065 = Sixty-sixth 32-bits of PCIE type 1 config space 3586215976Sjmallett * (Uncorrectable Error Status Register) 3587215976Sjmallett */ 3588232812Sjmallettunion cvmx_pciercx_cfg065 { 3589215976Sjmallett uint32_t u32; 3590232812Sjmallett struct cvmx_pciercx_cfg065_s { 3591232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3592232812Sjmallett uint32_t reserved_25_31 : 7; 3593232812Sjmallett uint32_t uatombs : 1; /**< Unsupported AtomicOp Egress Blocked Status */ 3594232812Sjmallett uint32_t reserved_23_23 : 1; 3595232812Sjmallett uint32_t ucies : 1; /**< Uncorrectable Internal Error Status */ 3596232812Sjmallett uint32_t reserved_21_21 : 1; 3597232812Sjmallett uint32_t ures : 1; /**< Unsupported Request Error Status */ 3598232812Sjmallett uint32_t ecrces : 1; /**< ECRC Error Status */ 3599232812Sjmallett uint32_t mtlps : 1; /**< Malformed TLP Status */ 3600232812Sjmallett uint32_t ros : 1; /**< Receiver Overflow Status */ 3601232812Sjmallett uint32_t ucs : 1; /**< Unexpected Completion Status */ 3602232812Sjmallett uint32_t cas : 1; /**< Completer Abort Status */ 3603232812Sjmallett uint32_t cts : 1; /**< Completion Timeout Status */ 3604232812Sjmallett uint32_t fcpes : 1; /**< Flow Control Protocol Error Status */ 3605232812Sjmallett uint32_t ptlps : 1; /**< Poisoned TLP Status */ 3606232812Sjmallett uint32_t reserved_6_11 : 6; 3607232812Sjmallett uint32_t sdes : 1; /**< Surprise Down Error Status (not supported) */ 3608232812Sjmallett uint32_t dlpes : 1; /**< Data Link Protocol Error Status */ 3609232812Sjmallett uint32_t reserved_0_3 : 4; 3610232812Sjmallett#else 3611232812Sjmallett uint32_t reserved_0_3 : 4; 3612232812Sjmallett uint32_t dlpes : 1; 3613232812Sjmallett uint32_t sdes : 1; 3614232812Sjmallett uint32_t reserved_6_11 : 6; 3615232812Sjmallett uint32_t ptlps : 1; 3616232812Sjmallett uint32_t fcpes : 1; 3617232812Sjmallett uint32_t cts : 1; 3618232812Sjmallett uint32_t cas : 1; 3619232812Sjmallett uint32_t ucs : 1; 3620232812Sjmallett uint32_t ros : 1; 3621232812Sjmallett uint32_t mtlps : 1; 3622232812Sjmallett uint32_t ecrces : 1; 3623232812Sjmallett uint32_t ures : 1; 3624232812Sjmallett uint32_t reserved_21_21 : 1; 3625232812Sjmallett uint32_t ucies : 1; 3626232812Sjmallett uint32_t reserved_23_23 : 1; 3627232812Sjmallett uint32_t uatombs : 1; 3628232812Sjmallett uint32_t reserved_25_31 : 7; 3629232812Sjmallett#endif 3630232812Sjmallett } s; 3631232812Sjmallett struct cvmx_pciercx_cfg065_cn52xx { 3632232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3633215976Sjmallett uint32_t reserved_21_31 : 11; 3634215976Sjmallett uint32_t ures : 1; /**< Unsupported Request Error Status */ 3635215976Sjmallett uint32_t ecrces : 1; /**< ECRC Error Status */ 3636215976Sjmallett uint32_t mtlps : 1; /**< Malformed TLP Status */ 3637215976Sjmallett uint32_t ros : 1; /**< Receiver Overflow Status */ 3638215976Sjmallett uint32_t ucs : 1; /**< Unexpected Completion Status */ 3639215976Sjmallett uint32_t cas : 1; /**< Completer Abort Status */ 3640215976Sjmallett uint32_t cts : 1; /**< Completion Timeout Status */ 3641215976Sjmallett uint32_t fcpes : 1; /**< Flow Control Protocol Error Status */ 3642215976Sjmallett uint32_t ptlps : 1; /**< Poisoned TLP Status */ 3643215976Sjmallett uint32_t reserved_6_11 : 6; 3644215976Sjmallett uint32_t sdes : 1; /**< Surprise Down Error Status (not supported) */ 3645215976Sjmallett uint32_t dlpes : 1; /**< Data Link Protocol Error Status */ 3646215976Sjmallett uint32_t reserved_0_3 : 4; 3647215976Sjmallett#else 3648215976Sjmallett uint32_t reserved_0_3 : 4; 3649215976Sjmallett uint32_t dlpes : 1; 3650215976Sjmallett uint32_t sdes : 1; 3651215976Sjmallett uint32_t reserved_6_11 : 6; 3652215976Sjmallett uint32_t ptlps : 1; 3653215976Sjmallett uint32_t fcpes : 1; 3654215976Sjmallett uint32_t cts : 1; 3655215976Sjmallett uint32_t cas : 1; 3656215976Sjmallett uint32_t ucs : 1; 3657215976Sjmallett uint32_t ros : 1; 3658215976Sjmallett uint32_t mtlps : 1; 3659215976Sjmallett uint32_t ecrces : 1; 3660215976Sjmallett uint32_t ures : 1; 3661215976Sjmallett uint32_t reserved_21_31 : 11; 3662215976Sjmallett#endif 3663232812Sjmallett } cn52xx; 3664232812Sjmallett struct cvmx_pciercx_cfg065_cn52xx cn52xxp1; 3665232812Sjmallett struct cvmx_pciercx_cfg065_cn52xx cn56xx; 3666232812Sjmallett struct cvmx_pciercx_cfg065_cn52xx cn56xxp1; 3667232812Sjmallett struct cvmx_pciercx_cfg065_cn61xx { 3668232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3669232812Sjmallett uint32_t reserved_25_31 : 7; 3670232812Sjmallett uint32_t uatombs : 1; /**< Unsupported AtomicOp Egress Blocked Status */ 3671232812Sjmallett uint32_t reserved_21_23 : 3; 3672232812Sjmallett uint32_t ures : 1; /**< Unsupported Request Error Status */ 3673232812Sjmallett uint32_t ecrces : 1; /**< ECRC Error Status */ 3674232812Sjmallett uint32_t mtlps : 1; /**< Malformed TLP Status */ 3675232812Sjmallett uint32_t ros : 1; /**< Receiver Overflow Status */ 3676232812Sjmallett uint32_t ucs : 1; /**< Unexpected Completion Status */ 3677232812Sjmallett uint32_t cas : 1; /**< Completer Abort Status */ 3678232812Sjmallett uint32_t cts : 1; /**< Completion Timeout Status */ 3679232812Sjmallett uint32_t fcpes : 1; /**< Flow Control Protocol Error Status */ 3680232812Sjmallett uint32_t ptlps : 1; /**< Poisoned TLP Status */ 3681232812Sjmallett uint32_t reserved_6_11 : 6; 3682232812Sjmallett uint32_t sdes : 1; /**< Surprise Down Error Status (not supported) */ 3683232812Sjmallett uint32_t dlpes : 1; /**< Data Link Protocol Error Status */ 3684232812Sjmallett uint32_t reserved_0_3 : 4; 3685232812Sjmallett#else 3686232812Sjmallett uint32_t reserved_0_3 : 4; 3687232812Sjmallett uint32_t dlpes : 1; 3688232812Sjmallett uint32_t sdes : 1; 3689232812Sjmallett uint32_t reserved_6_11 : 6; 3690232812Sjmallett uint32_t ptlps : 1; 3691232812Sjmallett uint32_t fcpes : 1; 3692232812Sjmallett uint32_t cts : 1; 3693232812Sjmallett uint32_t cas : 1; 3694232812Sjmallett uint32_t ucs : 1; 3695232812Sjmallett uint32_t ros : 1; 3696232812Sjmallett uint32_t mtlps : 1; 3697232812Sjmallett uint32_t ecrces : 1; 3698232812Sjmallett uint32_t ures : 1; 3699232812Sjmallett uint32_t reserved_21_23 : 3; 3700232812Sjmallett uint32_t uatombs : 1; 3701232812Sjmallett uint32_t reserved_25_31 : 7; 3702232812Sjmallett#endif 3703232812Sjmallett } cn61xx; 3704232812Sjmallett struct cvmx_pciercx_cfg065_cn52xx cn63xx; 3705232812Sjmallett struct cvmx_pciercx_cfg065_cn52xx cn63xxp1; 3706232812Sjmallett struct cvmx_pciercx_cfg065_cn61xx cn66xx; 3707232812Sjmallett struct cvmx_pciercx_cfg065_cn61xx cn68xx; 3708232812Sjmallett struct cvmx_pciercx_cfg065_cn52xx cn68xxp1; 3709232812Sjmallett struct cvmx_pciercx_cfg065_s cnf71xx; 3710215976Sjmallett}; 3711215976Sjmalletttypedef union cvmx_pciercx_cfg065 cvmx_pciercx_cfg065_t; 3712215976Sjmallett 3713215976Sjmallett/** 3714215976Sjmallett * cvmx_pcierc#_cfg066 3715215976Sjmallett * 3716215976Sjmallett * PCIE_CFG066 = Sixty-seventh 32-bits of PCIE type 1 config space 3717215976Sjmallett * (Uncorrectable Error Mask Register) 3718215976Sjmallett */ 3719232812Sjmallettunion cvmx_pciercx_cfg066 { 3720215976Sjmallett uint32_t u32; 3721232812Sjmallett struct cvmx_pciercx_cfg066_s { 3722232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3723232812Sjmallett uint32_t reserved_25_31 : 7; 3724232812Sjmallett uint32_t uatombm : 1; /**< Unsupported AtomicOp Egress Blocked Mask */ 3725232812Sjmallett uint32_t reserved_23_23 : 1; 3726232812Sjmallett uint32_t uciem : 1; /**< Uncorrectable Internal Error Mask */ 3727232812Sjmallett uint32_t reserved_21_21 : 1; 3728232812Sjmallett uint32_t urem : 1; /**< Unsupported Request Error Mask */ 3729232812Sjmallett uint32_t ecrcem : 1; /**< ECRC Error Mask */ 3730232812Sjmallett uint32_t mtlpm : 1; /**< Malformed TLP Mask */ 3731232812Sjmallett uint32_t rom : 1; /**< Receiver Overflow Mask */ 3732232812Sjmallett uint32_t ucm : 1; /**< Unexpected Completion Mask */ 3733232812Sjmallett uint32_t cam : 1; /**< Completer Abort Mask */ 3734232812Sjmallett uint32_t ctm : 1; /**< Completion Timeout Mask */ 3735232812Sjmallett uint32_t fcpem : 1; /**< Flow Control Protocol Error Mask */ 3736232812Sjmallett uint32_t ptlpm : 1; /**< Poisoned TLP Mask */ 3737232812Sjmallett uint32_t reserved_6_11 : 6; 3738232812Sjmallett uint32_t sdem : 1; /**< Surprise Down Error Mask (not supported) */ 3739232812Sjmallett uint32_t dlpem : 1; /**< Data Link Protocol Error Mask */ 3740232812Sjmallett uint32_t reserved_0_3 : 4; 3741232812Sjmallett#else 3742232812Sjmallett uint32_t reserved_0_3 : 4; 3743232812Sjmallett uint32_t dlpem : 1; 3744232812Sjmallett uint32_t sdem : 1; 3745232812Sjmallett uint32_t reserved_6_11 : 6; 3746232812Sjmallett uint32_t ptlpm : 1; 3747232812Sjmallett uint32_t fcpem : 1; 3748232812Sjmallett uint32_t ctm : 1; 3749232812Sjmallett uint32_t cam : 1; 3750232812Sjmallett uint32_t ucm : 1; 3751232812Sjmallett uint32_t rom : 1; 3752232812Sjmallett uint32_t mtlpm : 1; 3753232812Sjmallett uint32_t ecrcem : 1; 3754232812Sjmallett uint32_t urem : 1; 3755232812Sjmallett uint32_t reserved_21_21 : 1; 3756232812Sjmallett uint32_t uciem : 1; 3757232812Sjmallett uint32_t reserved_23_23 : 1; 3758232812Sjmallett uint32_t uatombm : 1; 3759232812Sjmallett uint32_t reserved_25_31 : 7; 3760232812Sjmallett#endif 3761232812Sjmallett } s; 3762232812Sjmallett struct cvmx_pciercx_cfg066_cn52xx { 3763232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3764215976Sjmallett uint32_t reserved_21_31 : 11; 3765215976Sjmallett uint32_t urem : 1; /**< Unsupported Request Error Mask */ 3766215976Sjmallett uint32_t ecrcem : 1; /**< ECRC Error Mask */ 3767215976Sjmallett uint32_t mtlpm : 1; /**< Malformed TLP Mask */ 3768215976Sjmallett uint32_t rom : 1; /**< Receiver Overflow Mask */ 3769215976Sjmallett uint32_t ucm : 1; /**< Unexpected Completion Mask */ 3770215976Sjmallett uint32_t cam : 1; /**< Completer Abort Mask */ 3771215976Sjmallett uint32_t ctm : 1; /**< Completion Timeout Mask */ 3772215976Sjmallett uint32_t fcpem : 1; /**< Flow Control Protocol Error Mask */ 3773215976Sjmallett uint32_t ptlpm : 1; /**< Poisoned TLP Mask */ 3774215976Sjmallett uint32_t reserved_6_11 : 6; 3775215976Sjmallett uint32_t sdem : 1; /**< Surprise Down Error Mask (not supported) */ 3776215976Sjmallett uint32_t dlpem : 1; /**< Data Link Protocol Error Mask */ 3777215976Sjmallett uint32_t reserved_0_3 : 4; 3778215976Sjmallett#else 3779215976Sjmallett uint32_t reserved_0_3 : 4; 3780215976Sjmallett uint32_t dlpem : 1; 3781215976Sjmallett uint32_t sdem : 1; 3782215976Sjmallett uint32_t reserved_6_11 : 6; 3783215976Sjmallett uint32_t ptlpm : 1; 3784215976Sjmallett uint32_t fcpem : 1; 3785215976Sjmallett uint32_t ctm : 1; 3786215976Sjmallett uint32_t cam : 1; 3787215976Sjmallett uint32_t ucm : 1; 3788215976Sjmallett uint32_t rom : 1; 3789215976Sjmallett uint32_t mtlpm : 1; 3790215976Sjmallett uint32_t ecrcem : 1; 3791215976Sjmallett uint32_t urem : 1; 3792215976Sjmallett uint32_t reserved_21_31 : 11; 3793215976Sjmallett#endif 3794232812Sjmallett } cn52xx; 3795232812Sjmallett struct cvmx_pciercx_cfg066_cn52xx cn52xxp1; 3796232812Sjmallett struct cvmx_pciercx_cfg066_cn52xx cn56xx; 3797232812Sjmallett struct cvmx_pciercx_cfg066_cn52xx cn56xxp1; 3798232812Sjmallett struct cvmx_pciercx_cfg066_cn61xx { 3799232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3800232812Sjmallett uint32_t reserved_25_31 : 7; 3801232812Sjmallett uint32_t uatombm : 1; /**< Unsupported AtomicOp Egress Blocked Mask */ 3802232812Sjmallett uint32_t reserved_21_23 : 3; 3803232812Sjmallett uint32_t urem : 1; /**< Unsupported Request Error Mask */ 3804232812Sjmallett uint32_t ecrcem : 1; /**< ECRC Error Mask */ 3805232812Sjmallett uint32_t mtlpm : 1; /**< Malformed TLP Mask */ 3806232812Sjmallett uint32_t rom : 1; /**< Receiver Overflow Mask */ 3807232812Sjmallett uint32_t ucm : 1; /**< Unexpected Completion Mask */ 3808232812Sjmallett uint32_t cam : 1; /**< Completer Abort Mask */ 3809232812Sjmallett uint32_t ctm : 1; /**< Completion Timeout Mask */ 3810232812Sjmallett uint32_t fcpem : 1; /**< Flow Control Protocol Error Mask */ 3811232812Sjmallett uint32_t ptlpm : 1; /**< Poisoned TLP Mask */ 3812232812Sjmallett uint32_t reserved_6_11 : 6; 3813232812Sjmallett uint32_t sdem : 1; /**< Surprise Down Error Mask (not supported) */ 3814232812Sjmallett uint32_t dlpem : 1; /**< Data Link Protocol Error Mask */ 3815232812Sjmallett uint32_t reserved_0_3 : 4; 3816232812Sjmallett#else 3817232812Sjmallett uint32_t reserved_0_3 : 4; 3818232812Sjmallett uint32_t dlpem : 1; 3819232812Sjmallett uint32_t sdem : 1; 3820232812Sjmallett uint32_t reserved_6_11 : 6; 3821232812Sjmallett uint32_t ptlpm : 1; 3822232812Sjmallett uint32_t fcpem : 1; 3823232812Sjmallett uint32_t ctm : 1; 3824232812Sjmallett uint32_t cam : 1; 3825232812Sjmallett uint32_t ucm : 1; 3826232812Sjmallett uint32_t rom : 1; 3827232812Sjmallett uint32_t mtlpm : 1; 3828232812Sjmallett uint32_t ecrcem : 1; 3829232812Sjmallett uint32_t urem : 1; 3830232812Sjmallett uint32_t reserved_21_23 : 3; 3831232812Sjmallett uint32_t uatombm : 1; 3832232812Sjmallett uint32_t reserved_25_31 : 7; 3833232812Sjmallett#endif 3834232812Sjmallett } cn61xx; 3835232812Sjmallett struct cvmx_pciercx_cfg066_cn52xx cn63xx; 3836232812Sjmallett struct cvmx_pciercx_cfg066_cn52xx cn63xxp1; 3837232812Sjmallett struct cvmx_pciercx_cfg066_cn61xx cn66xx; 3838232812Sjmallett struct cvmx_pciercx_cfg066_cn61xx cn68xx; 3839232812Sjmallett struct cvmx_pciercx_cfg066_cn52xx cn68xxp1; 3840232812Sjmallett struct cvmx_pciercx_cfg066_s cnf71xx; 3841215976Sjmallett}; 3842215976Sjmalletttypedef union cvmx_pciercx_cfg066 cvmx_pciercx_cfg066_t; 3843215976Sjmallett 3844215976Sjmallett/** 3845215976Sjmallett * cvmx_pcierc#_cfg067 3846215976Sjmallett * 3847215976Sjmallett * PCIE_CFG067 = Sixty-eighth 32-bits of PCIE type 1 config space 3848215976Sjmallett * (Uncorrectable Error Severity Register) 3849215976Sjmallett */ 3850232812Sjmallettunion cvmx_pciercx_cfg067 { 3851215976Sjmallett uint32_t u32; 3852232812Sjmallett struct cvmx_pciercx_cfg067_s { 3853232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3854232812Sjmallett uint32_t reserved_25_31 : 7; 3855232812Sjmallett uint32_t uatombs : 1; /**< Unsupported AtomicOp Egress Blocked Severity */ 3856232812Sjmallett uint32_t reserved_23_23 : 1; 3857232812Sjmallett uint32_t ucies : 1; /**< Uncorrectable Internal Error Severity */ 3858232812Sjmallett uint32_t reserved_21_21 : 1; 3859232812Sjmallett uint32_t ures : 1; /**< Unsupported Request Error Severity */ 3860232812Sjmallett uint32_t ecrces : 1; /**< ECRC Error Severity */ 3861232812Sjmallett uint32_t mtlps : 1; /**< Malformed TLP Severity */ 3862232812Sjmallett uint32_t ros : 1; /**< Receiver Overflow Severity */ 3863232812Sjmallett uint32_t ucs : 1; /**< Unexpected Completion Severity */ 3864232812Sjmallett uint32_t cas : 1; /**< Completer Abort Severity */ 3865232812Sjmallett uint32_t cts : 1; /**< Completion Timeout Severity */ 3866232812Sjmallett uint32_t fcpes : 1; /**< Flow Control Protocol Error Severity */ 3867232812Sjmallett uint32_t ptlps : 1; /**< Poisoned TLP Severity */ 3868232812Sjmallett uint32_t reserved_6_11 : 6; 3869232812Sjmallett uint32_t sdes : 1; /**< Surprise Down Error Severity (not supported) */ 3870232812Sjmallett uint32_t dlpes : 1; /**< Data Link Protocol Error Severity */ 3871232812Sjmallett uint32_t reserved_0_3 : 4; 3872232812Sjmallett#else 3873232812Sjmallett uint32_t reserved_0_3 : 4; 3874232812Sjmallett uint32_t dlpes : 1; 3875232812Sjmallett uint32_t sdes : 1; 3876232812Sjmallett uint32_t reserved_6_11 : 6; 3877232812Sjmallett uint32_t ptlps : 1; 3878232812Sjmallett uint32_t fcpes : 1; 3879232812Sjmallett uint32_t cts : 1; 3880232812Sjmallett uint32_t cas : 1; 3881232812Sjmallett uint32_t ucs : 1; 3882232812Sjmallett uint32_t ros : 1; 3883232812Sjmallett uint32_t mtlps : 1; 3884232812Sjmallett uint32_t ecrces : 1; 3885232812Sjmallett uint32_t ures : 1; 3886232812Sjmallett uint32_t reserved_21_21 : 1; 3887232812Sjmallett uint32_t ucies : 1; 3888232812Sjmallett uint32_t reserved_23_23 : 1; 3889232812Sjmallett uint32_t uatombs : 1; 3890232812Sjmallett uint32_t reserved_25_31 : 7; 3891232812Sjmallett#endif 3892232812Sjmallett } s; 3893232812Sjmallett struct cvmx_pciercx_cfg067_cn52xx { 3894232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3895215976Sjmallett uint32_t reserved_21_31 : 11; 3896215976Sjmallett uint32_t ures : 1; /**< Unsupported Request Error Severity */ 3897215976Sjmallett uint32_t ecrces : 1; /**< ECRC Error Severity */ 3898215976Sjmallett uint32_t mtlps : 1; /**< Malformed TLP Severity */ 3899215976Sjmallett uint32_t ros : 1; /**< Receiver Overflow Severity */ 3900215976Sjmallett uint32_t ucs : 1; /**< Unexpected Completion Severity */ 3901215976Sjmallett uint32_t cas : 1; /**< Completer Abort Severity */ 3902215976Sjmallett uint32_t cts : 1; /**< Completion Timeout Severity */ 3903215976Sjmallett uint32_t fcpes : 1; /**< Flow Control Protocol Error Severity */ 3904215976Sjmallett uint32_t ptlps : 1; /**< Poisoned TLP Severity */ 3905215976Sjmallett uint32_t reserved_6_11 : 6; 3906215976Sjmallett uint32_t sdes : 1; /**< Surprise Down Error Severity (not supported) */ 3907215976Sjmallett uint32_t dlpes : 1; /**< Data Link Protocol Error Severity */ 3908215976Sjmallett uint32_t reserved_0_3 : 4; 3909215976Sjmallett#else 3910215976Sjmallett uint32_t reserved_0_3 : 4; 3911215976Sjmallett uint32_t dlpes : 1; 3912215976Sjmallett uint32_t sdes : 1; 3913215976Sjmallett uint32_t reserved_6_11 : 6; 3914215976Sjmallett uint32_t ptlps : 1; 3915215976Sjmallett uint32_t fcpes : 1; 3916215976Sjmallett uint32_t cts : 1; 3917215976Sjmallett uint32_t cas : 1; 3918215976Sjmallett uint32_t ucs : 1; 3919215976Sjmallett uint32_t ros : 1; 3920215976Sjmallett uint32_t mtlps : 1; 3921215976Sjmallett uint32_t ecrces : 1; 3922215976Sjmallett uint32_t ures : 1; 3923215976Sjmallett uint32_t reserved_21_31 : 11; 3924215976Sjmallett#endif 3925232812Sjmallett } cn52xx; 3926232812Sjmallett struct cvmx_pciercx_cfg067_cn52xx cn52xxp1; 3927232812Sjmallett struct cvmx_pciercx_cfg067_cn52xx cn56xx; 3928232812Sjmallett struct cvmx_pciercx_cfg067_cn52xx cn56xxp1; 3929232812Sjmallett struct cvmx_pciercx_cfg067_cn61xx { 3930232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3931232812Sjmallett uint32_t reserved_25_31 : 7; 3932232812Sjmallett uint32_t uatombs : 1; /**< Unsupported AtomicOp Egress Blocked Severity */ 3933232812Sjmallett uint32_t reserved_21_23 : 3; 3934232812Sjmallett uint32_t ures : 1; /**< Unsupported Request Error Severity */ 3935232812Sjmallett uint32_t ecrces : 1; /**< ECRC Error Severity */ 3936232812Sjmallett uint32_t mtlps : 1; /**< Malformed TLP Severity */ 3937232812Sjmallett uint32_t ros : 1; /**< Receiver Overflow Severity */ 3938232812Sjmallett uint32_t ucs : 1; /**< Unexpected Completion Severity */ 3939232812Sjmallett uint32_t cas : 1; /**< Completer Abort Severity */ 3940232812Sjmallett uint32_t cts : 1; /**< Completion Timeout Severity */ 3941232812Sjmallett uint32_t fcpes : 1; /**< Flow Control Protocol Error Severity */ 3942232812Sjmallett uint32_t ptlps : 1; /**< Poisoned TLP Severity */ 3943232812Sjmallett uint32_t reserved_6_11 : 6; 3944232812Sjmallett uint32_t sdes : 1; /**< Surprise Down Error Severity (not supported) */ 3945232812Sjmallett uint32_t dlpes : 1; /**< Data Link Protocol Error Severity */ 3946232812Sjmallett uint32_t reserved_0_3 : 4; 3947232812Sjmallett#else 3948232812Sjmallett uint32_t reserved_0_3 : 4; 3949232812Sjmallett uint32_t dlpes : 1; 3950232812Sjmallett uint32_t sdes : 1; 3951232812Sjmallett uint32_t reserved_6_11 : 6; 3952232812Sjmallett uint32_t ptlps : 1; 3953232812Sjmallett uint32_t fcpes : 1; 3954232812Sjmallett uint32_t cts : 1; 3955232812Sjmallett uint32_t cas : 1; 3956232812Sjmallett uint32_t ucs : 1; 3957232812Sjmallett uint32_t ros : 1; 3958232812Sjmallett uint32_t mtlps : 1; 3959232812Sjmallett uint32_t ecrces : 1; 3960232812Sjmallett uint32_t ures : 1; 3961232812Sjmallett uint32_t reserved_21_23 : 3; 3962232812Sjmallett uint32_t uatombs : 1; 3963232812Sjmallett uint32_t reserved_25_31 : 7; 3964232812Sjmallett#endif 3965232812Sjmallett } cn61xx; 3966232812Sjmallett struct cvmx_pciercx_cfg067_cn52xx cn63xx; 3967232812Sjmallett struct cvmx_pciercx_cfg067_cn52xx cn63xxp1; 3968232812Sjmallett struct cvmx_pciercx_cfg067_cn61xx cn66xx; 3969232812Sjmallett struct cvmx_pciercx_cfg067_cn61xx cn68xx; 3970232812Sjmallett struct cvmx_pciercx_cfg067_cn52xx cn68xxp1; 3971232812Sjmallett struct cvmx_pciercx_cfg067_s cnf71xx; 3972215976Sjmallett}; 3973215976Sjmalletttypedef union cvmx_pciercx_cfg067 cvmx_pciercx_cfg067_t; 3974215976Sjmallett 3975215976Sjmallett/** 3976215976Sjmallett * cvmx_pcierc#_cfg068 3977215976Sjmallett * 3978215976Sjmallett * PCIE_CFG068 = Sixty-ninth 32-bits of PCIE type 1 config space 3979215976Sjmallett * (Correctable Error Status Register) 3980215976Sjmallett */ 3981232812Sjmallettunion cvmx_pciercx_cfg068 { 3982215976Sjmallett uint32_t u32; 3983232812Sjmallett struct cvmx_pciercx_cfg068_s { 3984232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3985232812Sjmallett uint32_t reserved_15_31 : 17; 3986232812Sjmallett uint32_t cies : 1; /**< Corrected Internal Error Status */ 3987232812Sjmallett uint32_t anfes : 1; /**< Advisory Non-Fatal Error Status */ 3988232812Sjmallett uint32_t rtts : 1; /**< Replay Timer Timeout Status */ 3989232812Sjmallett uint32_t reserved_9_11 : 3; 3990232812Sjmallett uint32_t rnrs : 1; /**< REPLAY_NUM Rollover Status */ 3991232812Sjmallett uint32_t bdllps : 1; /**< Bad DLLP Status */ 3992232812Sjmallett uint32_t btlps : 1; /**< Bad TLP Status */ 3993232812Sjmallett uint32_t reserved_1_5 : 5; 3994232812Sjmallett uint32_t res : 1; /**< Receiver Error Status */ 3995232812Sjmallett#else 3996232812Sjmallett uint32_t res : 1; 3997232812Sjmallett uint32_t reserved_1_5 : 5; 3998232812Sjmallett uint32_t btlps : 1; 3999232812Sjmallett uint32_t bdllps : 1; 4000232812Sjmallett uint32_t rnrs : 1; 4001232812Sjmallett uint32_t reserved_9_11 : 3; 4002232812Sjmallett uint32_t rtts : 1; 4003232812Sjmallett uint32_t anfes : 1; 4004232812Sjmallett uint32_t cies : 1; 4005232812Sjmallett uint32_t reserved_15_31 : 17; 4006232812Sjmallett#endif 4007232812Sjmallett } s; 4008232812Sjmallett struct cvmx_pciercx_cfg068_cn52xx { 4009232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4010215976Sjmallett uint32_t reserved_14_31 : 18; 4011215976Sjmallett uint32_t anfes : 1; /**< Advisory Non-Fatal Error Status */ 4012215976Sjmallett uint32_t rtts : 1; /**< Replay Timer Timeout Status */ 4013215976Sjmallett uint32_t reserved_9_11 : 3; 4014215976Sjmallett uint32_t rnrs : 1; /**< REPLAY_NUM Rollover Status */ 4015215976Sjmallett uint32_t bdllps : 1; /**< Bad DLLP Status */ 4016215976Sjmallett uint32_t btlps : 1; /**< Bad TLP Status */ 4017215976Sjmallett uint32_t reserved_1_5 : 5; 4018215976Sjmallett uint32_t res : 1; /**< Receiver Error Status */ 4019215976Sjmallett#else 4020215976Sjmallett uint32_t res : 1; 4021215976Sjmallett uint32_t reserved_1_5 : 5; 4022215976Sjmallett uint32_t btlps : 1; 4023215976Sjmallett uint32_t bdllps : 1; 4024215976Sjmallett uint32_t rnrs : 1; 4025215976Sjmallett uint32_t reserved_9_11 : 3; 4026215976Sjmallett uint32_t rtts : 1; 4027215976Sjmallett uint32_t anfes : 1; 4028215976Sjmallett uint32_t reserved_14_31 : 18; 4029215976Sjmallett#endif 4030232812Sjmallett } cn52xx; 4031232812Sjmallett struct cvmx_pciercx_cfg068_cn52xx cn52xxp1; 4032232812Sjmallett struct cvmx_pciercx_cfg068_cn52xx cn56xx; 4033232812Sjmallett struct cvmx_pciercx_cfg068_cn52xx cn56xxp1; 4034232812Sjmallett struct cvmx_pciercx_cfg068_cn52xx cn61xx; 4035232812Sjmallett struct cvmx_pciercx_cfg068_cn52xx cn63xx; 4036232812Sjmallett struct cvmx_pciercx_cfg068_cn52xx cn63xxp1; 4037232812Sjmallett struct cvmx_pciercx_cfg068_cn52xx cn66xx; 4038232812Sjmallett struct cvmx_pciercx_cfg068_cn52xx cn68xx; 4039232812Sjmallett struct cvmx_pciercx_cfg068_cn52xx cn68xxp1; 4040232812Sjmallett struct cvmx_pciercx_cfg068_s cnf71xx; 4041215976Sjmallett}; 4042215976Sjmalletttypedef union cvmx_pciercx_cfg068 cvmx_pciercx_cfg068_t; 4043215976Sjmallett 4044215976Sjmallett/** 4045215976Sjmallett * cvmx_pcierc#_cfg069 4046215976Sjmallett * 4047215976Sjmallett * PCIE_CFG069 = Seventieth 32-bits of PCIE type 1 config space 4048215976Sjmallett * (Correctable Error Mask Register) 4049215976Sjmallett */ 4050232812Sjmallettunion cvmx_pciercx_cfg069 { 4051215976Sjmallett uint32_t u32; 4052232812Sjmallett struct cvmx_pciercx_cfg069_s { 4053232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4054232812Sjmallett uint32_t reserved_15_31 : 17; 4055232812Sjmallett uint32_t ciem : 1; /**< Corrected Internal Error Mask */ 4056232812Sjmallett uint32_t anfem : 1; /**< Advisory Non-Fatal Error Mask */ 4057232812Sjmallett uint32_t rttm : 1; /**< Replay Timer Timeout Mask */ 4058232812Sjmallett uint32_t reserved_9_11 : 3; 4059232812Sjmallett uint32_t rnrm : 1; /**< REPLAY_NUM Rollover Mask */ 4060232812Sjmallett uint32_t bdllpm : 1; /**< Bad DLLP Mask */ 4061232812Sjmallett uint32_t btlpm : 1; /**< Bad TLP Mask */ 4062232812Sjmallett uint32_t reserved_1_5 : 5; 4063232812Sjmallett uint32_t rem : 1; /**< Receiver Error Mask */ 4064232812Sjmallett#else 4065232812Sjmallett uint32_t rem : 1; 4066232812Sjmallett uint32_t reserved_1_5 : 5; 4067232812Sjmallett uint32_t btlpm : 1; 4068232812Sjmallett uint32_t bdllpm : 1; 4069232812Sjmallett uint32_t rnrm : 1; 4070232812Sjmallett uint32_t reserved_9_11 : 3; 4071232812Sjmallett uint32_t rttm : 1; 4072232812Sjmallett uint32_t anfem : 1; 4073232812Sjmallett uint32_t ciem : 1; 4074232812Sjmallett uint32_t reserved_15_31 : 17; 4075232812Sjmallett#endif 4076232812Sjmallett } s; 4077232812Sjmallett struct cvmx_pciercx_cfg069_cn52xx { 4078232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4079215976Sjmallett uint32_t reserved_14_31 : 18; 4080215976Sjmallett uint32_t anfem : 1; /**< Advisory Non-Fatal Error Mask */ 4081215976Sjmallett uint32_t rttm : 1; /**< Replay Timer Timeout Mask */ 4082215976Sjmallett uint32_t reserved_9_11 : 3; 4083215976Sjmallett uint32_t rnrm : 1; /**< REPLAY_NUM Rollover Mask */ 4084215976Sjmallett uint32_t bdllpm : 1; /**< Bad DLLP Mask */ 4085215976Sjmallett uint32_t btlpm : 1; /**< Bad TLP Mask */ 4086215976Sjmallett uint32_t reserved_1_5 : 5; 4087215976Sjmallett uint32_t rem : 1; /**< Receiver Error Mask */ 4088215976Sjmallett#else 4089215976Sjmallett uint32_t rem : 1; 4090215976Sjmallett uint32_t reserved_1_5 : 5; 4091215976Sjmallett uint32_t btlpm : 1; 4092215976Sjmallett uint32_t bdllpm : 1; 4093215976Sjmallett uint32_t rnrm : 1; 4094215976Sjmallett uint32_t reserved_9_11 : 3; 4095215976Sjmallett uint32_t rttm : 1; 4096215976Sjmallett uint32_t anfem : 1; 4097215976Sjmallett uint32_t reserved_14_31 : 18; 4098215976Sjmallett#endif 4099232812Sjmallett } cn52xx; 4100232812Sjmallett struct cvmx_pciercx_cfg069_cn52xx cn52xxp1; 4101232812Sjmallett struct cvmx_pciercx_cfg069_cn52xx cn56xx; 4102232812Sjmallett struct cvmx_pciercx_cfg069_cn52xx cn56xxp1; 4103232812Sjmallett struct cvmx_pciercx_cfg069_cn52xx cn61xx; 4104232812Sjmallett struct cvmx_pciercx_cfg069_cn52xx cn63xx; 4105232812Sjmallett struct cvmx_pciercx_cfg069_cn52xx cn63xxp1; 4106232812Sjmallett struct cvmx_pciercx_cfg069_cn52xx cn66xx; 4107232812Sjmallett struct cvmx_pciercx_cfg069_cn52xx cn68xx; 4108232812Sjmallett struct cvmx_pciercx_cfg069_cn52xx cn68xxp1; 4109232812Sjmallett struct cvmx_pciercx_cfg069_s cnf71xx; 4110215976Sjmallett}; 4111215976Sjmalletttypedef union cvmx_pciercx_cfg069 cvmx_pciercx_cfg069_t; 4112215976Sjmallett 4113215976Sjmallett/** 4114215976Sjmallett * cvmx_pcierc#_cfg070 4115215976Sjmallett * 4116215976Sjmallett * PCIE_CFG070 = Seventy-first 32-bits of PCIE type 1 config space 4117215976Sjmallett * (Advanced Capabilities and Control Register) 4118215976Sjmallett */ 4119232812Sjmallettunion cvmx_pciercx_cfg070 { 4120215976Sjmallett uint32_t u32; 4121232812Sjmallett struct cvmx_pciercx_cfg070_s { 4122232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4123215976Sjmallett uint32_t reserved_9_31 : 23; 4124215976Sjmallett uint32_t ce : 1; /**< ECRC Check Enable */ 4125215976Sjmallett uint32_t cc : 1; /**< ECRC Check Capable */ 4126215976Sjmallett uint32_t ge : 1; /**< ECRC Generation Enable */ 4127215976Sjmallett uint32_t gc : 1; /**< ECRC Generation Capability */ 4128215976Sjmallett uint32_t fep : 5; /**< First Error Pointer */ 4129215976Sjmallett#else 4130215976Sjmallett uint32_t fep : 5; 4131215976Sjmallett uint32_t gc : 1; 4132215976Sjmallett uint32_t ge : 1; 4133215976Sjmallett uint32_t cc : 1; 4134215976Sjmallett uint32_t ce : 1; 4135215976Sjmallett uint32_t reserved_9_31 : 23; 4136215976Sjmallett#endif 4137215976Sjmallett } s; 4138215976Sjmallett struct cvmx_pciercx_cfg070_s cn52xx; 4139215976Sjmallett struct cvmx_pciercx_cfg070_s cn52xxp1; 4140215976Sjmallett struct cvmx_pciercx_cfg070_s cn56xx; 4141215976Sjmallett struct cvmx_pciercx_cfg070_s cn56xxp1; 4142232812Sjmallett struct cvmx_pciercx_cfg070_s cn61xx; 4143215976Sjmallett struct cvmx_pciercx_cfg070_s cn63xx; 4144215976Sjmallett struct cvmx_pciercx_cfg070_s cn63xxp1; 4145232812Sjmallett struct cvmx_pciercx_cfg070_s cn66xx; 4146232812Sjmallett struct cvmx_pciercx_cfg070_s cn68xx; 4147232812Sjmallett struct cvmx_pciercx_cfg070_s cn68xxp1; 4148232812Sjmallett struct cvmx_pciercx_cfg070_s cnf71xx; 4149215976Sjmallett}; 4150215976Sjmalletttypedef union cvmx_pciercx_cfg070 cvmx_pciercx_cfg070_t; 4151215976Sjmallett 4152215976Sjmallett/** 4153215976Sjmallett * cvmx_pcierc#_cfg071 4154215976Sjmallett * 4155215976Sjmallett * PCIE_CFG071 = Seventy-second 32-bits of PCIE type 1 config space 4156215976Sjmallett * (Header Log Register 1) 4157215976Sjmallett * 4158215976Sjmallett * The Header Log registers collect the header for the TLP corresponding to a detected error. 4159215976Sjmallett */ 4160232812Sjmallettunion cvmx_pciercx_cfg071 { 4161215976Sjmallett uint32_t u32; 4162232812Sjmallett struct cvmx_pciercx_cfg071_s { 4163232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4164215976Sjmallett uint32_t dword1 : 32; /**< Header Log Register (first DWORD) */ 4165215976Sjmallett#else 4166215976Sjmallett uint32_t dword1 : 32; 4167215976Sjmallett#endif 4168215976Sjmallett } s; 4169215976Sjmallett struct cvmx_pciercx_cfg071_s cn52xx; 4170215976Sjmallett struct cvmx_pciercx_cfg071_s cn52xxp1; 4171215976Sjmallett struct cvmx_pciercx_cfg071_s cn56xx; 4172215976Sjmallett struct cvmx_pciercx_cfg071_s cn56xxp1; 4173232812Sjmallett struct cvmx_pciercx_cfg071_s cn61xx; 4174215976Sjmallett struct cvmx_pciercx_cfg071_s cn63xx; 4175215976Sjmallett struct cvmx_pciercx_cfg071_s cn63xxp1; 4176232812Sjmallett struct cvmx_pciercx_cfg071_s cn66xx; 4177232812Sjmallett struct cvmx_pciercx_cfg071_s cn68xx; 4178232812Sjmallett struct cvmx_pciercx_cfg071_s cn68xxp1; 4179232812Sjmallett struct cvmx_pciercx_cfg071_s cnf71xx; 4180215976Sjmallett}; 4181215976Sjmalletttypedef union cvmx_pciercx_cfg071 cvmx_pciercx_cfg071_t; 4182215976Sjmallett 4183215976Sjmallett/** 4184215976Sjmallett * cvmx_pcierc#_cfg072 4185215976Sjmallett * 4186215976Sjmallett * PCIE_CFG072 = Seventy-third 32-bits of PCIE type 1 config space 4187215976Sjmallett * (Header Log Register 2) 4188215976Sjmallett * 4189215976Sjmallett * The Header Log registers collect the header for the TLP corresponding to a detected error. 4190215976Sjmallett */ 4191232812Sjmallettunion cvmx_pciercx_cfg072 { 4192215976Sjmallett uint32_t u32; 4193232812Sjmallett struct cvmx_pciercx_cfg072_s { 4194232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4195215976Sjmallett uint32_t dword2 : 32; /**< Header Log Register (second DWORD) */ 4196215976Sjmallett#else 4197215976Sjmallett uint32_t dword2 : 32; 4198215976Sjmallett#endif 4199215976Sjmallett } s; 4200215976Sjmallett struct cvmx_pciercx_cfg072_s cn52xx; 4201215976Sjmallett struct cvmx_pciercx_cfg072_s cn52xxp1; 4202215976Sjmallett struct cvmx_pciercx_cfg072_s cn56xx; 4203215976Sjmallett struct cvmx_pciercx_cfg072_s cn56xxp1; 4204232812Sjmallett struct cvmx_pciercx_cfg072_s cn61xx; 4205215976Sjmallett struct cvmx_pciercx_cfg072_s cn63xx; 4206215976Sjmallett struct cvmx_pciercx_cfg072_s cn63xxp1; 4207232812Sjmallett struct cvmx_pciercx_cfg072_s cn66xx; 4208232812Sjmallett struct cvmx_pciercx_cfg072_s cn68xx; 4209232812Sjmallett struct cvmx_pciercx_cfg072_s cn68xxp1; 4210232812Sjmallett struct cvmx_pciercx_cfg072_s cnf71xx; 4211215976Sjmallett}; 4212215976Sjmalletttypedef union cvmx_pciercx_cfg072 cvmx_pciercx_cfg072_t; 4213215976Sjmallett 4214215976Sjmallett/** 4215215976Sjmallett * cvmx_pcierc#_cfg073 4216215976Sjmallett * 4217215976Sjmallett * PCIE_CFG073 = Seventy-fourth 32-bits of PCIE type 1 config space 4218215976Sjmallett * (Header Log Register 3) 4219215976Sjmallett * 4220215976Sjmallett * The Header Log registers collect the header for the TLP corresponding to a detected error. 4221215976Sjmallett */ 4222232812Sjmallettunion cvmx_pciercx_cfg073 { 4223215976Sjmallett uint32_t u32; 4224232812Sjmallett struct cvmx_pciercx_cfg073_s { 4225232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4226215976Sjmallett uint32_t dword3 : 32; /**< Header Log Register (third DWORD) */ 4227215976Sjmallett#else 4228215976Sjmallett uint32_t dword3 : 32; 4229215976Sjmallett#endif 4230215976Sjmallett } s; 4231215976Sjmallett struct cvmx_pciercx_cfg073_s cn52xx; 4232215976Sjmallett struct cvmx_pciercx_cfg073_s cn52xxp1; 4233215976Sjmallett struct cvmx_pciercx_cfg073_s cn56xx; 4234215976Sjmallett struct cvmx_pciercx_cfg073_s cn56xxp1; 4235232812Sjmallett struct cvmx_pciercx_cfg073_s cn61xx; 4236215976Sjmallett struct cvmx_pciercx_cfg073_s cn63xx; 4237215976Sjmallett struct cvmx_pciercx_cfg073_s cn63xxp1; 4238232812Sjmallett struct cvmx_pciercx_cfg073_s cn66xx; 4239232812Sjmallett struct cvmx_pciercx_cfg073_s cn68xx; 4240232812Sjmallett struct cvmx_pciercx_cfg073_s cn68xxp1; 4241232812Sjmallett struct cvmx_pciercx_cfg073_s cnf71xx; 4242215976Sjmallett}; 4243215976Sjmalletttypedef union cvmx_pciercx_cfg073 cvmx_pciercx_cfg073_t; 4244215976Sjmallett 4245215976Sjmallett/** 4246215976Sjmallett * cvmx_pcierc#_cfg074 4247215976Sjmallett * 4248215976Sjmallett * PCIE_CFG074 = Seventy-fifth 32-bits of PCIE type 1 config space 4249215976Sjmallett * (Header Log Register 4) 4250215976Sjmallett * 4251215976Sjmallett * The Header Log registers collect the header for the TLP corresponding to a detected error. 4252215976Sjmallett */ 4253232812Sjmallettunion cvmx_pciercx_cfg074 { 4254215976Sjmallett uint32_t u32; 4255232812Sjmallett struct cvmx_pciercx_cfg074_s { 4256232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4257215976Sjmallett uint32_t dword4 : 32; /**< Header Log Register (fourth DWORD) */ 4258215976Sjmallett#else 4259215976Sjmallett uint32_t dword4 : 32; 4260215976Sjmallett#endif 4261215976Sjmallett } s; 4262215976Sjmallett struct cvmx_pciercx_cfg074_s cn52xx; 4263215976Sjmallett struct cvmx_pciercx_cfg074_s cn52xxp1; 4264215976Sjmallett struct cvmx_pciercx_cfg074_s cn56xx; 4265215976Sjmallett struct cvmx_pciercx_cfg074_s cn56xxp1; 4266232812Sjmallett struct cvmx_pciercx_cfg074_s cn61xx; 4267215976Sjmallett struct cvmx_pciercx_cfg074_s cn63xx; 4268215976Sjmallett struct cvmx_pciercx_cfg074_s cn63xxp1; 4269232812Sjmallett struct cvmx_pciercx_cfg074_s cn66xx; 4270232812Sjmallett struct cvmx_pciercx_cfg074_s cn68xx; 4271232812Sjmallett struct cvmx_pciercx_cfg074_s cn68xxp1; 4272232812Sjmallett struct cvmx_pciercx_cfg074_s cnf71xx; 4273215976Sjmallett}; 4274215976Sjmalletttypedef union cvmx_pciercx_cfg074 cvmx_pciercx_cfg074_t; 4275215976Sjmallett 4276215976Sjmallett/** 4277215976Sjmallett * cvmx_pcierc#_cfg075 4278215976Sjmallett * 4279215976Sjmallett * PCIE_CFG075 = Seventy-sixth 32-bits of PCIE type 1 config space 4280215976Sjmallett * (Root Error Command Register) 4281215976Sjmallett */ 4282232812Sjmallettunion cvmx_pciercx_cfg075 { 4283215976Sjmallett uint32_t u32; 4284232812Sjmallett struct cvmx_pciercx_cfg075_s { 4285232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4286215976Sjmallett uint32_t reserved_3_31 : 29; 4287215976Sjmallett uint32_t fere : 1; /**< Fatal Error Reporting Enable */ 4288215976Sjmallett uint32_t nfere : 1; /**< Non-Fatal Error Reporting Enable */ 4289215976Sjmallett uint32_t cere : 1; /**< Correctable Error Reporting Enable */ 4290215976Sjmallett#else 4291215976Sjmallett uint32_t cere : 1; 4292215976Sjmallett uint32_t nfere : 1; 4293215976Sjmallett uint32_t fere : 1; 4294215976Sjmallett uint32_t reserved_3_31 : 29; 4295215976Sjmallett#endif 4296215976Sjmallett } s; 4297215976Sjmallett struct cvmx_pciercx_cfg075_s cn52xx; 4298215976Sjmallett struct cvmx_pciercx_cfg075_s cn52xxp1; 4299215976Sjmallett struct cvmx_pciercx_cfg075_s cn56xx; 4300215976Sjmallett struct cvmx_pciercx_cfg075_s cn56xxp1; 4301232812Sjmallett struct cvmx_pciercx_cfg075_s cn61xx; 4302215976Sjmallett struct cvmx_pciercx_cfg075_s cn63xx; 4303215976Sjmallett struct cvmx_pciercx_cfg075_s cn63xxp1; 4304232812Sjmallett struct cvmx_pciercx_cfg075_s cn66xx; 4305232812Sjmallett struct cvmx_pciercx_cfg075_s cn68xx; 4306232812Sjmallett struct cvmx_pciercx_cfg075_s cn68xxp1; 4307232812Sjmallett struct cvmx_pciercx_cfg075_s cnf71xx; 4308215976Sjmallett}; 4309215976Sjmalletttypedef union cvmx_pciercx_cfg075 cvmx_pciercx_cfg075_t; 4310215976Sjmallett 4311215976Sjmallett/** 4312215976Sjmallett * cvmx_pcierc#_cfg076 4313215976Sjmallett * 4314215976Sjmallett * PCIE_CFG076 = Seventy-seventh 32-bits of PCIE type 1 config space 4315215976Sjmallett * (Root Error Status Register) 4316215976Sjmallett */ 4317232812Sjmallettunion cvmx_pciercx_cfg076 { 4318215976Sjmallett uint32_t u32; 4319232812Sjmallett struct cvmx_pciercx_cfg076_s { 4320232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4321215976Sjmallett uint32_t aeimn : 5; /**< Advanced Error Interrupt Message Number, 4322215976Sjmallett writable through PEM(0..1)_CFG_WR */ 4323215976Sjmallett uint32_t reserved_7_26 : 20; 4324215976Sjmallett uint32_t femr : 1; /**< Fatal Error Messages Received */ 4325215976Sjmallett uint32_t nfemr : 1; /**< Non-Fatal Error Messages Received */ 4326215976Sjmallett uint32_t fuf : 1; /**< First Uncorrectable Fatal */ 4327215976Sjmallett uint32_t multi_efnfr : 1; /**< Multiple ERR_FATAL/NONFATAL Received */ 4328215976Sjmallett uint32_t efnfr : 1; /**< ERR_FATAL/NONFATAL Received */ 4329215976Sjmallett uint32_t multi_ecr : 1; /**< Multiple ERR_COR Received */ 4330215976Sjmallett uint32_t ecr : 1; /**< ERR_COR Received */ 4331215976Sjmallett#else 4332215976Sjmallett uint32_t ecr : 1; 4333215976Sjmallett uint32_t multi_ecr : 1; 4334215976Sjmallett uint32_t efnfr : 1; 4335215976Sjmallett uint32_t multi_efnfr : 1; 4336215976Sjmallett uint32_t fuf : 1; 4337215976Sjmallett uint32_t nfemr : 1; 4338215976Sjmallett uint32_t femr : 1; 4339215976Sjmallett uint32_t reserved_7_26 : 20; 4340215976Sjmallett uint32_t aeimn : 5; 4341215976Sjmallett#endif 4342215976Sjmallett } s; 4343215976Sjmallett struct cvmx_pciercx_cfg076_s cn52xx; 4344215976Sjmallett struct cvmx_pciercx_cfg076_s cn52xxp1; 4345215976Sjmallett struct cvmx_pciercx_cfg076_s cn56xx; 4346215976Sjmallett struct cvmx_pciercx_cfg076_s cn56xxp1; 4347232812Sjmallett struct cvmx_pciercx_cfg076_s cn61xx; 4348215976Sjmallett struct cvmx_pciercx_cfg076_s cn63xx; 4349215976Sjmallett struct cvmx_pciercx_cfg076_s cn63xxp1; 4350232812Sjmallett struct cvmx_pciercx_cfg076_s cn66xx; 4351232812Sjmallett struct cvmx_pciercx_cfg076_s cn68xx; 4352232812Sjmallett struct cvmx_pciercx_cfg076_s cn68xxp1; 4353232812Sjmallett struct cvmx_pciercx_cfg076_s cnf71xx; 4354215976Sjmallett}; 4355215976Sjmalletttypedef union cvmx_pciercx_cfg076 cvmx_pciercx_cfg076_t; 4356215976Sjmallett 4357215976Sjmallett/** 4358215976Sjmallett * cvmx_pcierc#_cfg077 4359215976Sjmallett * 4360215976Sjmallett * PCIE_CFG077 = Seventy-eighth 32-bits of PCIE type 1 config space 4361215976Sjmallett * (Error Source Identification Register) 4362215976Sjmallett */ 4363232812Sjmallettunion cvmx_pciercx_cfg077 { 4364215976Sjmallett uint32_t u32; 4365232812Sjmallett struct cvmx_pciercx_cfg077_s { 4366232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4367215976Sjmallett uint32_t efnfsi : 16; /**< ERR_FATAL/NONFATAL Source Identification */ 4368215976Sjmallett uint32_t ecsi : 16; /**< ERR_COR Source Identification */ 4369215976Sjmallett#else 4370215976Sjmallett uint32_t ecsi : 16; 4371215976Sjmallett uint32_t efnfsi : 16; 4372215976Sjmallett#endif 4373215976Sjmallett } s; 4374215976Sjmallett struct cvmx_pciercx_cfg077_s cn52xx; 4375215976Sjmallett struct cvmx_pciercx_cfg077_s cn52xxp1; 4376215976Sjmallett struct cvmx_pciercx_cfg077_s cn56xx; 4377215976Sjmallett struct cvmx_pciercx_cfg077_s cn56xxp1; 4378232812Sjmallett struct cvmx_pciercx_cfg077_s cn61xx; 4379215976Sjmallett struct cvmx_pciercx_cfg077_s cn63xx; 4380215976Sjmallett struct cvmx_pciercx_cfg077_s cn63xxp1; 4381232812Sjmallett struct cvmx_pciercx_cfg077_s cn66xx; 4382232812Sjmallett struct cvmx_pciercx_cfg077_s cn68xx; 4383232812Sjmallett struct cvmx_pciercx_cfg077_s cn68xxp1; 4384232812Sjmallett struct cvmx_pciercx_cfg077_s cnf71xx; 4385215976Sjmallett}; 4386215976Sjmalletttypedef union cvmx_pciercx_cfg077 cvmx_pciercx_cfg077_t; 4387215976Sjmallett 4388215976Sjmallett/** 4389215976Sjmallett * cvmx_pcierc#_cfg448 4390215976Sjmallett * 4391215976Sjmallett * PCIE_CFG448 = Four hundred forty-ninth 32-bits of PCIE type 1 config space 4392215976Sjmallett * (Ack Latency Timer and Replay Timer Register) 4393215976Sjmallett */ 4394232812Sjmallettunion cvmx_pciercx_cfg448 { 4395215976Sjmallett uint32_t u32; 4396232812Sjmallett struct cvmx_pciercx_cfg448_s { 4397232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4398215976Sjmallett uint32_t rtl : 16; /**< Replay Time Limit 4399215976Sjmallett The replay timer expires when it reaches this limit. The PCI 4400215976Sjmallett Express bus initiates a replay upon reception of a Nak or when 4401215976Sjmallett the replay timer expires. 4402232812Sjmallett This value will be set correctly by the hardware out of reset 4403232812Sjmallett or when the negotiated Link-Width or Payload-Size changes. If 4404232812Sjmallett the user changes this value through a CSR write or by an 4405232812Sjmallett EEPROM load then they should refer to the PCIe Specification 4406232812Sjmallett for the correct value. */ 4407215976Sjmallett uint32_t rtltl : 16; /**< Round Trip Latency Time Limit 4408215976Sjmallett The Ack/Nak latency timer expires when it reaches this limit. 4409232812Sjmallett This value will be set correctly by the hardware out of reset 4410232812Sjmallett or when the negotiated Link-Width or Payload-Size changes. If 4411232812Sjmallett the user changes this value through a CSR write or by an 4412232812Sjmallett EEPROM load then they should refer to the PCIe Specification 4413232812Sjmallett for the correct value. */ 4414215976Sjmallett#else 4415215976Sjmallett uint32_t rtltl : 16; 4416215976Sjmallett uint32_t rtl : 16; 4417215976Sjmallett#endif 4418215976Sjmallett } s; 4419215976Sjmallett struct cvmx_pciercx_cfg448_s cn52xx; 4420215976Sjmallett struct cvmx_pciercx_cfg448_s cn52xxp1; 4421215976Sjmallett struct cvmx_pciercx_cfg448_s cn56xx; 4422215976Sjmallett struct cvmx_pciercx_cfg448_s cn56xxp1; 4423232812Sjmallett struct cvmx_pciercx_cfg448_s cn61xx; 4424215976Sjmallett struct cvmx_pciercx_cfg448_s cn63xx; 4425215976Sjmallett struct cvmx_pciercx_cfg448_s cn63xxp1; 4426232812Sjmallett struct cvmx_pciercx_cfg448_s cn66xx; 4427232812Sjmallett struct cvmx_pciercx_cfg448_s cn68xx; 4428232812Sjmallett struct cvmx_pciercx_cfg448_s cn68xxp1; 4429232812Sjmallett struct cvmx_pciercx_cfg448_s cnf71xx; 4430215976Sjmallett}; 4431215976Sjmalletttypedef union cvmx_pciercx_cfg448 cvmx_pciercx_cfg448_t; 4432215976Sjmallett 4433215976Sjmallett/** 4434215976Sjmallett * cvmx_pcierc#_cfg449 4435215976Sjmallett * 4436215976Sjmallett * PCIE_CFG449 = Four hundred fiftieth 32-bits of PCIE type 1 config space 4437215976Sjmallett * (Other Message Register) 4438215976Sjmallett */ 4439232812Sjmallettunion cvmx_pciercx_cfg449 { 4440215976Sjmallett uint32_t u32; 4441232812Sjmallett struct cvmx_pciercx_cfg449_s { 4442232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4443215976Sjmallett uint32_t omr : 32; /**< Other Message Register 4444215976Sjmallett This register can be used for either of the following purposes: 4445215976Sjmallett o To send a specific PCI Express Message, the application 4446215976Sjmallett writes the payload of the Message into this register, then 4447215976Sjmallett sets bit 0 of the Port Link Control Register to send the 4448215976Sjmallett Message. 4449215976Sjmallett o To store a corruption pattern for corrupting the LCRC on all 4450215976Sjmallett TLPs, the application places a 32-bit corruption pattern into 4451215976Sjmallett this register and enables this function by setting bit 25 of 4452215976Sjmallett the Port Link Control Register. When enabled, the transmit 4453215976Sjmallett LCRC result is XOR'd with this pattern before inserting 4454215976Sjmallett it into the packet. */ 4455215976Sjmallett#else 4456215976Sjmallett uint32_t omr : 32; 4457215976Sjmallett#endif 4458215976Sjmallett } s; 4459215976Sjmallett struct cvmx_pciercx_cfg449_s cn52xx; 4460215976Sjmallett struct cvmx_pciercx_cfg449_s cn52xxp1; 4461215976Sjmallett struct cvmx_pciercx_cfg449_s cn56xx; 4462215976Sjmallett struct cvmx_pciercx_cfg449_s cn56xxp1; 4463232812Sjmallett struct cvmx_pciercx_cfg449_s cn61xx; 4464215976Sjmallett struct cvmx_pciercx_cfg449_s cn63xx; 4465215976Sjmallett struct cvmx_pciercx_cfg449_s cn63xxp1; 4466232812Sjmallett struct cvmx_pciercx_cfg449_s cn66xx; 4467232812Sjmallett struct cvmx_pciercx_cfg449_s cn68xx; 4468232812Sjmallett struct cvmx_pciercx_cfg449_s cn68xxp1; 4469232812Sjmallett struct cvmx_pciercx_cfg449_s cnf71xx; 4470215976Sjmallett}; 4471215976Sjmalletttypedef union cvmx_pciercx_cfg449 cvmx_pciercx_cfg449_t; 4472215976Sjmallett 4473215976Sjmallett/** 4474215976Sjmallett * cvmx_pcierc#_cfg450 4475215976Sjmallett * 4476215976Sjmallett * PCIE_CFG450 = Four hundred fifty-first 32-bits of PCIE type 1 config space 4477215976Sjmallett * (Port Force Link Register) 4478215976Sjmallett */ 4479232812Sjmallettunion cvmx_pciercx_cfg450 { 4480215976Sjmallett uint32_t u32; 4481232812Sjmallett struct cvmx_pciercx_cfg450_s { 4482232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4483215976Sjmallett uint32_t lpec : 8; /**< Low Power Entrance Count 4484215976Sjmallett The Power Management state will wait for this many clock cycles 4485215976Sjmallett for the associated completion of a CfgWr to PCIE_CFG017 register 4486215976Sjmallett Power State (PS) field register to go low-power. This register 4487215976Sjmallett is intended for applications that do not let the PCI Express 4488215976Sjmallett bus handle a completion for configuration request to the 4489215976Sjmallett Power Management Control and Status (PCIE_CFG017) register. */ 4490215976Sjmallett uint32_t reserved_22_23 : 2; 4491215976Sjmallett uint32_t link_state : 6; /**< Link State 4492215976Sjmallett The Link state that the PCI Express Bus will be forced to 4493215976Sjmallett when bit 15 (Force Link) is set. 4494215976Sjmallett State encoding: 4495215976Sjmallett o DETECT_QUIET 00h 4496215976Sjmallett o DETECT_ACT 01h 4497215976Sjmallett o POLL_ACTIVE 02h 4498215976Sjmallett o POLL_COMPLIANCE 03h 4499215976Sjmallett o POLL_CONFIG 04h 4500215976Sjmallett o PRE_DETECT_QUIET 05h 4501215976Sjmallett o DETECT_WAIT 06h 4502215976Sjmallett o CFG_LINKWD_START 07h 4503215976Sjmallett o CFG_LINKWD_ACEPT 08h 4504215976Sjmallett o CFG_LANENUM_WAIT 09h 4505215976Sjmallett o CFG_LANENUM_ACEPT 0Ah 4506215976Sjmallett o CFG_COMPLETE 0Bh 4507215976Sjmallett o CFG_IDLE 0Ch 4508215976Sjmallett o RCVRY_LOCK 0Dh 4509215976Sjmallett o RCVRY_SPEED 0Eh 4510215976Sjmallett o RCVRY_RCVRCFG 0Fh 4511215976Sjmallett o RCVRY_IDLE 10h 4512215976Sjmallett o L0 11h 4513215976Sjmallett o L0S 12h 4514215976Sjmallett o L123_SEND_EIDLE 13h 4515215976Sjmallett o L1_IDLE 14h 4516215976Sjmallett o L2_IDLE 15h 4517215976Sjmallett o L2_WAKE 16h 4518215976Sjmallett o DISABLED_ENTRY 17h 4519215976Sjmallett o DISABLED_IDLE 18h 4520215976Sjmallett o DISABLED 19h 4521215976Sjmallett o LPBK_ENTRY 1Ah 4522215976Sjmallett o LPBK_ACTIVE 1Bh 4523215976Sjmallett o LPBK_EXIT 1Ch 4524215976Sjmallett o LPBK_EXIT_TIMEOUT 1Dh 4525215976Sjmallett o HOT_RESET_ENTRY 1Eh 4526215976Sjmallett o HOT_RESET 1Fh */ 4527215976Sjmallett uint32_t force_link : 1; /**< Force Link 4528215976Sjmallett Forces the Link to the state specified by the Link State field. 4529215976Sjmallett The Force Link pulse will trigger Link re-negotiation. 4530215976Sjmallett * As the The Force Link is a pulse, writing a 1 to it does 4531215976Sjmallett trigger the forced link state event, even thought reading it 4532215976Sjmallett always returns a 0. */ 4533215976Sjmallett uint32_t reserved_8_14 : 7; 4534215976Sjmallett uint32_t link_num : 8; /**< Link Number */ 4535215976Sjmallett#else 4536215976Sjmallett uint32_t link_num : 8; 4537215976Sjmallett uint32_t reserved_8_14 : 7; 4538215976Sjmallett uint32_t force_link : 1; 4539215976Sjmallett uint32_t link_state : 6; 4540215976Sjmallett uint32_t reserved_22_23 : 2; 4541215976Sjmallett uint32_t lpec : 8; 4542215976Sjmallett#endif 4543215976Sjmallett } s; 4544215976Sjmallett struct cvmx_pciercx_cfg450_s cn52xx; 4545215976Sjmallett struct cvmx_pciercx_cfg450_s cn52xxp1; 4546215976Sjmallett struct cvmx_pciercx_cfg450_s cn56xx; 4547215976Sjmallett struct cvmx_pciercx_cfg450_s cn56xxp1; 4548232812Sjmallett struct cvmx_pciercx_cfg450_s cn61xx; 4549215976Sjmallett struct cvmx_pciercx_cfg450_s cn63xx; 4550215976Sjmallett struct cvmx_pciercx_cfg450_s cn63xxp1; 4551232812Sjmallett struct cvmx_pciercx_cfg450_s cn66xx; 4552232812Sjmallett struct cvmx_pciercx_cfg450_s cn68xx; 4553232812Sjmallett struct cvmx_pciercx_cfg450_s cn68xxp1; 4554232812Sjmallett struct cvmx_pciercx_cfg450_s cnf71xx; 4555215976Sjmallett}; 4556215976Sjmalletttypedef union cvmx_pciercx_cfg450 cvmx_pciercx_cfg450_t; 4557215976Sjmallett 4558215976Sjmallett/** 4559215976Sjmallett * cvmx_pcierc#_cfg451 4560215976Sjmallett * 4561215976Sjmallett * PCIE_CFG451 = Four hundred fifty-second 32-bits of PCIE type 1 config space 4562215976Sjmallett * (Ack Frequency Register) 4563215976Sjmallett */ 4564232812Sjmallettunion cvmx_pciercx_cfg451 { 4565215976Sjmallett uint32_t u32; 4566232812Sjmallett struct cvmx_pciercx_cfg451_s { 4567232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4568232812Sjmallett uint32_t reserved_31_31 : 1; 4569232812Sjmallett uint32_t easpml1 : 1; /**< Enter ASPM L1 without receive in L0s 4570232812Sjmallett Allow core to enter ASPM L1 even when link partner did 4571232812Sjmallett not go to L0s (receive is not in L0s). 4572232812Sjmallett When not set, core goes to ASPM L1 only after idle period 4573232812Sjmallett during which both receive and transmit are in L0s. */ 4574232812Sjmallett uint32_t l1el : 3; /**< L1 Entrance Latency 4575232812Sjmallett Values correspond to: 4576232812Sjmallett o 000: 1 ms 4577232812Sjmallett o 001: 2 ms 4578232812Sjmallett o 010: 4 ms 4579232812Sjmallett o 011: 8 ms 4580232812Sjmallett o 100: 16 ms 4581232812Sjmallett o 101: 32 ms 4582232812Sjmallett o 110 or 111: 64 ms */ 4583232812Sjmallett uint32_t l0el : 3; /**< L0s Entrance Latency 4584232812Sjmallett Values correspond to: 4585232812Sjmallett o 000: 1 ms 4586232812Sjmallett o 001: 2 ms 4587232812Sjmallett o 010: 3 ms 4588232812Sjmallett o 011: 4 ms 4589232812Sjmallett o 100: 5 ms 4590232812Sjmallett o 101: 6 ms 4591232812Sjmallett o 110 or 111: 7 ms */ 4592232812Sjmallett uint32_t n_fts_cc : 8; /**< N_FTS when common clock is used. 4593232812Sjmallett The number of Fast Training Sequence ordered sets to be 4594232812Sjmallett transmitted when transitioning from L0s to L0. The maximum 4595232812Sjmallett number of FTS ordered-sets that a component can request is 255. 4596232812Sjmallett Note: The core does not support a value of zero; a value of 4597232812Sjmallett zero can cause the LTSSM to go into the recovery state 4598232812Sjmallett when exiting from L0s. */ 4599232812Sjmallett uint32_t n_fts : 8; /**< N_FTS 4600232812Sjmallett The number of Fast Training Sequence ordered sets to be 4601232812Sjmallett transmitted when transitioning from L0s to L0. The maximum 4602232812Sjmallett number of FTS ordered-sets that a component can request is 255. 4603232812Sjmallett Note: The core does not support a value of zero; a value of 4604232812Sjmallett zero can cause the LTSSM to go into the recovery state 4605232812Sjmallett when exiting from L0s. */ 4606232812Sjmallett uint32_t ack_freq : 8; /**< Ack Frequency 4607232812Sjmallett The number of pending Ack's specified here (up to 255) before 4608232812Sjmallett sending an Ack. */ 4609232812Sjmallett#else 4610232812Sjmallett uint32_t ack_freq : 8; 4611232812Sjmallett uint32_t n_fts : 8; 4612232812Sjmallett uint32_t n_fts_cc : 8; 4613232812Sjmallett uint32_t l0el : 3; 4614232812Sjmallett uint32_t l1el : 3; 4615232812Sjmallett uint32_t easpml1 : 1; 4616232812Sjmallett uint32_t reserved_31_31 : 1; 4617232812Sjmallett#endif 4618232812Sjmallett } s; 4619232812Sjmallett struct cvmx_pciercx_cfg451_cn52xx { 4620232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4621215976Sjmallett uint32_t reserved_30_31 : 2; 4622215976Sjmallett uint32_t l1el : 3; /**< L1 Entrance Latency 4623215976Sjmallett Values correspond to: 4624215976Sjmallett o 000: 1 ms 4625215976Sjmallett o 001: 2 ms 4626215976Sjmallett o 010: 4 ms 4627215976Sjmallett o 011: 8 ms 4628215976Sjmallett o 100: 16 ms 4629215976Sjmallett o 101: 32 ms 4630215976Sjmallett o 110 or 111: 64 ms */ 4631215976Sjmallett uint32_t l0el : 3; /**< L0s Entrance Latency 4632215976Sjmallett Values correspond to: 4633215976Sjmallett o 000: 1 ms 4634215976Sjmallett o 001: 2 ms 4635215976Sjmallett o 010: 3 ms 4636215976Sjmallett o 011: 4 ms 4637215976Sjmallett o 100: 5 ms 4638215976Sjmallett o 101: 6 ms 4639215976Sjmallett o 110 or 111: 7 ms */ 4640215976Sjmallett uint32_t n_fts_cc : 8; /**< N_FTS when common clock is used. 4641215976Sjmallett The number of Fast Training Sequence ordered sets to be 4642215976Sjmallett transmitted when transitioning from L0s to L0. The maximum 4643215976Sjmallett number of FTS ordered-sets that a component can request is 255. 4644215976Sjmallett Note: The core does not support a value of zero; a value of 4645215976Sjmallett zero can cause the LTSSM to go into the recovery state 4646215976Sjmallett when exiting from L0s. */ 4647215976Sjmallett uint32_t n_fts : 8; /**< N_FTS 4648215976Sjmallett The number of Fast Training Sequence ordered sets to be 4649215976Sjmallett transmitted when transitioning from L0s to L0. The maximum 4650215976Sjmallett number of FTS ordered-sets that a component can request is 255. 4651215976Sjmallett Note: The core does not support a value of zero; a value of 4652215976Sjmallett zero can cause the LTSSM to go into the recovery state 4653215976Sjmallett when exiting from L0s. */ 4654215976Sjmallett uint32_t ack_freq : 8; /**< Ack Frequency 4655215976Sjmallett The number of pending Ack's specified here (up to 255) before 4656215976Sjmallett sending an Ack. */ 4657215976Sjmallett#else 4658215976Sjmallett uint32_t ack_freq : 8; 4659215976Sjmallett uint32_t n_fts : 8; 4660215976Sjmallett uint32_t n_fts_cc : 8; 4661215976Sjmallett uint32_t l0el : 3; 4662215976Sjmallett uint32_t l1el : 3; 4663215976Sjmallett uint32_t reserved_30_31 : 2; 4664215976Sjmallett#endif 4665232812Sjmallett } cn52xx; 4666232812Sjmallett struct cvmx_pciercx_cfg451_cn52xx cn52xxp1; 4667232812Sjmallett struct cvmx_pciercx_cfg451_cn52xx cn56xx; 4668232812Sjmallett struct cvmx_pciercx_cfg451_cn52xx cn56xxp1; 4669232812Sjmallett struct cvmx_pciercx_cfg451_s cn61xx; 4670232812Sjmallett struct cvmx_pciercx_cfg451_cn52xx cn63xx; 4671232812Sjmallett struct cvmx_pciercx_cfg451_cn52xx cn63xxp1; 4672232812Sjmallett struct cvmx_pciercx_cfg451_s cn66xx; 4673232812Sjmallett struct cvmx_pciercx_cfg451_s cn68xx; 4674232812Sjmallett struct cvmx_pciercx_cfg451_s cn68xxp1; 4675232812Sjmallett struct cvmx_pciercx_cfg451_s cnf71xx; 4676215976Sjmallett}; 4677215976Sjmalletttypedef union cvmx_pciercx_cfg451 cvmx_pciercx_cfg451_t; 4678215976Sjmallett 4679215976Sjmallett/** 4680215976Sjmallett * cvmx_pcierc#_cfg452 4681215976Sjmallett * 4682215976Sjmallett * PCIE_CFG452 = Four hundred fifty-third 32-bits of PCIE type 1 config space 4683215976Sjmallett * (Port Link Control Register) 4684215976Sjmallett */ 4685232812Sjmallettunion cvmx_pciercx_cfg452 { 4686215976Sjmallett uint32_t u32; 4687232812Sjmallett struct cvmx_pciercx_cfg452_s { 4688232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4689215976Sjmallett uint32_t reserved_26_31 : 6; 4690215976Sjmallett uint32_t eccrc : 1; /**< Enable Corrupted CRC 4691215976Sjmallett Causes corrupt LCRC for TLPs when set, 4692215976Sjmallett using the pattern contained in the Other Message register. 4693215976Sjmallett This is a test feature, not to be used in normal operation. */ 4694215976Sjmallett uint32_t reserved_22_24 : 3; 4695215976Sjmallett uint32_t lme : 6; /**< Link Mode Enable 4696215976Sjmallett o 000001: x1 4697215976Sjmallett o 000011: x2 4698232812Sjmallett o 000111: x4 (not supported) 4699215976Sjmallett o 001111: x8 (not supported) 4700215976Sjmallett o 011111: x16 (not supported) 4701215976Sjmallett o 111111: x32 (not supported) 4702215976Sjmallett This field indicates the MAXIMUM number of lanes supported 4703232812Sjmallett by the PCIe port. The value can be set less than 0x3 4704215976Sjmallett to limit the number of lanes the PCIe will attempt to use. 4705215976Sjmallett The programming of this field needs to be done by SW BEFORE 4706215976Sjmallett enabling the link. See also MLW. 4707215976Sjmallett (Note: The value of this field does NOT indicate the number 4708215976Sjmallett of lanes in use by the PCIe. LME sets the max number of lanes 4709215976Sjmallett in the PCIe core that COULD be used. As per the PCIe specs, 4710232812Sjmallett the PCIe core can negotiate a smaller link width, so 4711232812Sjmallett x1 is also supported when LME=0x3, for example.) */ 4712215976Sjmallett uint32_t reserved_8_15 : 8; 4713215976Sjmallett uint32_t flm : 1; /**< Fast Link Mode 4714215976Sjmallett Sets all internal timers to fast mode for simulation purposes. */ 4715215976Sjmallett uint32_t reserved_6_6 : 1; 4716215976Sjmallett uint32_t dllle : 1; /**< DLL Link Enable 4717215976Sjmallett Enables Link initialization. If DLL Link Enable = 0, the PCI 4718215976Sjmallett Express bus does not transmit InitFC DLLPs and does not 4719215976Sjmallett establish a Link. */ 4720215976Sjmallett uint32_t reserved_4_4 : 1; 4721215976Sjmallett uint32_t ra : 1; /**< Reset Assert 4722215976Sjmallett Triggers a recovery and forces the LTSSM to the Hot Reset 4723215976Sjmallett state (downstream port only). */ 4724215976Sjmallett uint32_t le : 1; /**< Loopback Enable 4725215976Sjmallett Initiate loopback mode as a master. On a 0->1 transition, 4726215976Sjmallett the PCIe core sends TS ordered sets with the loopback bit set 4727215976Sjmallett to cause the link partner to enter into loopback mode as a 4728215976Sjmallett slave. Normal transmission is not possible when LE=1. To exit 4729215976Sjmallett loopback mode, take the link through a reset sequence. */ 4730215976Sjmallett uint32_t sd : 1; /**< Scramble Disable 4731215976Sjmallett Turns off data scrambling. */ 4732215976Sjmallett uint32_t omr : 1; /**< Other Message Request 4733215976Sjmallett When software writes a `1' to this bit, the PCI Express bus 4734215976Sjmallett transmits the Message contained in the Other Message register. */ 4735215976Sjmallett#else 4736215976Sjmallett uint32_t omr : 1; 4737215976Sjmallett uint32_t sd : 1; 4738215976Sjmallett uint32_t le : 1; 4739215976Sjmallett uint32_t ra : 1; 4740215976Sjmallett uint32_t reserved_4_4 : 1; 4741215976Sjmallett uint32_t dllle : 1; 4742215976Sjmallett uint32_t reserved_6_6 : 1; 4743215976Sjmallett uint32_t flm : 1; 4744215976Sjmallett uint32_t reserved_8_15 : 8; 4745215976Sjmallett uint32_t lme : 6; 4746215976Sjmallett uint32_t reserved_22_24 : 3; 4747215976Sjmallett uint32_t eccrc : 1; 4748215976Sjmallett uint32_t reserved_26_31 : 6; 4749215976Sjmallett#endif 4750215976Sjmallett } s; 4751215976Sjmallett struct cvmx_pciercx_cfg452_s cn52xx; 4752215976Sjmallett struct cvmx_pciercx_cfg452_s cn52xxp1; 4753215976Sjmallett struct cvmx_pciercx_cfg452_s cn56xx; 4754215976Sjmallett struct cvmx_pciercx_cfg452_s cn56xxp1; 4755232812Sjmallett struct cvmx_pciercx_cfg452_cn61xx { 4756232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4757232812Sjmallett uint32_t reserved_22_31 : 10; 4758232812Sjmallett uint32_t lme : 6; /**< Link Mode Enable 4759232812Sjmallett o 000001: x1 4760232812Sjmallett o 000011: x2 4761232812Sjmallett o 000111: x4 4762232812Sjmallett o 001111: x8 (not supported) 4763232812Sjmallett o 011111: x16 (not supported) 4764232812Sjmallett o 111111: x32 (not supported) 4765232812Sjmallett This field indicates the MAXIMUM number of lanes supported 4766232812Sjmallett by the PCIe port. The value can be set less than 0x7 4767232812Sjmallett to limit the number of lanes the PCIe will attempt to use. 4768232812Sjmallett The programming of this field needs to be done by SW BEFORE 4769232812Sjmallett enabling the link. See also MLW. 4770232812Sjmallett (Note: The value of this field does NOT indicate the number 4771232812Sjmallett of lanes in use by the PCIe. LME sets the max number of lanes 4772232812Sjmallett in the PCIe core that COULD be used. As per the PCIe specs, 4773232812Sjmallett the PCIe core can negotiate a smaller link width, so all 4774232812Sjmallett of x4, x2, and x1 are supported when LME=0x7, 4775232812Sjmallett for example.) */ 4776232812Sjmallett uint32_t reserved_8_15 : 8; 4777232812Sjmallett uint32_t flm : 1; /**< Fast Link Mode 4778232812Sjmallett Sets all internal timers to fast mode for simulation purposes. */ 4779232812Sjmallett uint32_t reserved_6_6 : 1; 4780232812Sjmallett uint32_t dllle : 1; /**< DLL Link Enable 4781232812Sjmallett Enables Link initialization. If DLL Link Enable = 0, the PCI 4782232812Sjmallett Express bus does not transmit InitFC DLLPs and does not 4783232812Sjmallett establish a Link. */ 4784232812Sjmallett uint32_t reserved_4_4 : 1; 4785232812Sjmallett uint32_t ra : 1; /**< Reset Assert 4786232812Sjmallett Triggers a recovery and forces the LTSSM to the Hot Reset 4787232812Sjmallett state (downstream port only). */ 4788232812Sjmallett uint32_t le : 1; /**< Loopback Enable 4789232812Sjmallett Initiate loopback mode as a master. On a 0->1 transition, 4790232812Sjmallett the PCIe core sends TS ordered sets with the loopback bit set 4791232812Sjmallett to cause the link partner to enter into loopback mode as a 4792232812Sjmallett slave. Normal transmission is not possible when LE=1. To exit 4793232812Sjmallett loopback mode, take the link through a reset sequence. */ 4794232812Sjmallett uint32_t sd : 1; /**< Scramble Disable 4795232812Sjmallett Turns off data scrambling. */ 4796232812Sjmallett uint32_t omr : 1; /**< Other Message Request 4797232812Sjmallett When software writes a `1' to this bit, the PCI Express bus 4798232812Sjmallett transmits the Message contained in the Other Message register. */ 4799232812Sjmallett#else 4800232812Sjmallett uint32_t omr : 1; 4801232812Sjmallett uint32_t sd : 1; 4802232812Sjmallett uint32_t le : 1; 4803232812Sjmallett uint32_t ra : 1; 4804232812Sjmallett uint32_t reserved_4_4 : 1; 4805232812Sjmallett uint32_t dllle : 1; 4806232812Sjmallett uint32_t reserved_6_6 : 1; 4807232812Sjmallett uint32_t flm : 1; 4808232812Sjmallett uint32_t reserved_8_15 : 8; 4809232812Sjmallett uint32_t lme : 6; 4810232812Sjmallett uint32_t reserved_22_31 : 10; 4811232812Sjmallett#endif 4812232812Sjmallett } cn61xx; 4813215976Sjmallett struct cvmx_pciercx_cfg452_s cn63xx; 4814215976Sjmallett struct cvmx_pciercx_cfg452_s cn63xxp1; 4815232812Sjmallett struct cvmx_pciercx_cfg452_cn61xx cn66xx; 4816232812Sjmallett struct cvmx_pciercx_cfg452_cn61xx cn68xx; 4817232812Sjmallett struct cvmx_pciercx_cfg452_cn61xx cn68xxp1; 4818232812Sjmallett struct cvmx_pciercx_cfg452_cn61xx cnf71xx; 4819215976Sjmallett}; 4820215976Sjmalletttypedef union cvmx_pciercx_cfg452 cvmx_pciercx_cfg452_t; 4821215976Sjmallett 4822215976Sjmallett/** 4823215976Sjmallett * cvmx_pcierc#_cfg453 4824215976Sjmallett * 4825215976Sjmallett * PCIE_CFG453 = Four hundred fifty-fourth 32-bits of PCIE type 1 config space 4826215976Sjmallett * (Lane Skew Register) 4827215976Sjmallett */ 4828232812Sjmallettunion cvmx_pciercx_cfg453 { 4829215976Sjmallett uint32_t u32; 4830232812Sjmallett struct cvmx_pciercx_cfg453_s { 4831232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4832215976Sjmallett uint32_t dlld : 1; /**< Disable Lane-to-Lane Deskew 4833215976Sjmallett Disables the internal Lane-to-Lane deskew logic. */ 4834215976Sjmallett uint32_t reserved_26_30 : 5; 4835215976Sjmallett uint32_t ack_nak : 1; /**< Ack/Nak Disable 4836215976Sjmallett Prevents the PCI Express bus from sending Ack and Nak DLLPs. */ 4837215976Sjmallett uint32_t fcd : 1; /**< Flow Control Disable 4838215976Sjmallett Prevents the PCI Express bus from sending FC DLLPs. */ 4839215976Sjmallett uint32_t ilst : 24; /**< Insert Lane Skew for Transmit (not supported for x16) 4840215976Sjmallett Causes skew between lanes for test purposes. There are three 4841215976Sjmallett bits per Lane. The value is in units of one symbol time. For 4842215976Sjmallett example, the value 010b for a Lane forces a skew of two symbol 4843215976Sjmallett times for that Lane. The maximum skew value for any Lane is 5 4844215976Sjmallett symbol times. */ 4845215976Sjmallett#else 4846215976Sjmallett uint32_t ilst : 24; 4847215976Sjmallett uint32_t fcd : 1; 4848215976Sjmallett uint32_t ack_nak : 1; 4849215976Sjmallett uint32_t reserved_26_30 : 5; 4850215976Sjmallett uint32_t dlld : 1; 4851215976Sjmallett#endif 4852215976Sjmallett } s; 4853215976Sjmallett struct cvmx_pciercx_cfg453_s cn52xx; 4854215976Sjmallett struct cvmx_pciercx_cfg453_s cn52xxp1; 4855215976Sjmallett struct cvmx_pciercx_cfg453_s cn56xx; 4856215976Sjmallett struct cvmx_pciercx_cfg453_s cn56xxp1; 4857232812Sjmallett struct cvmx_pciercx_cfg453_s cn61xx; 4858215976Sjmallett struct cvmx_pciercx_cfg453_s cn63xx; 4859215976Sjmallett struct cvmx_pciercx_cfg453_s cn63xxp1; 4860232812Sjmallett struct cvmx_pciercx_cfg453_s cn66xx; 4861232812Sjmallett struct cvmx_pciercx_cfg453_s cn68xx; 4862232812Sjmallett struct cvmx_pciercx_cfg453_s cn68xxp1; 4863232812Sjmallett struct cvmx_pciercx_cfg453_s cnf71xx; 4864215976Sjmallett}; 4865215976Sjmalletttypedef union cvmx_pciercx_cfg453 cvmx_pciercx_cfg453_t; 4866215976Sjmallett 4867215976Sjmallett/** 4868215976Sjmallett * cvmx_pcierc#_cfg454 4869215976Sjmallett * 4870215976Sjmallett * PCIE_CFG454 = Four hundred fifty-fifth 32-bits of PCIE type 1 config space 4871215976Sjmallett * (Symbol Number Register) 4872215976Sjmallett */ 4873232812Sjmallettunion cvmx_pciercx_cfg454 { 4874215976Sjmallett uint32_t u32; 4875232812Sjmallett struct cvmx_pciercx_cfg454_s { 4876232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4877232812Sjmallett uint32_t cx_nfunc : 3; /**< Number of Functions (minus 1) 4878232812Sjmallett Configuration Requests targeted at function numbers above this 4879232812Sjmallett value will be returned with unsupported request */ 4880232812Sjmallett uint32_t tmfcwt : 5; /**< Timer Modifier for Flow Control Watchdog Timer 4881232812Sjmallett Increases the timer value for the Flow Control watchdog timer, 4882232812Sjmallett in increments of 16 clock cycles. */ 4883232812Sjmallett uint32_t tmanlt : 5; /**< Timer Modifier for Ack/Nak Latency Timer 4884232812Sjmallett Increases the timer value for the Ack/Nak latency timer, in 4885232812Sjmallett increments of 64 clock cycles. */ 4886232812Sjmallett uint32_t tmrt : 5; /**< Timer Modifier for Replay Timer 4887232812Sjmallett Increases the timer value for the replay timer, in increments 4888232812Sjmallett of 64 clock cycles. */ 4889232812Sjmallett uint32_t reserved_11_13 : 3; 4890232812Sjmallett uint32_t nskps : 3; /**< Number of SKP Symbols */ 4891232812Sjmallett uint32_t reserved_0_7 : 8; 4892232812Sjmallett#else 4893232812Sjmallett uint32_t reserved_0_7 : 8; 4894232812Sjmallett uint32_t nskps : 3; 4895232812Sjmallett uint32_t reserved_11_13 : 3; 4896232812Sjmallett uint32_t tmrt : 5; 4897232812Sjmallett uint32_t tmanlt : 5; 4898232812Sjmallett uint32_t tmfcwt : 5; 4899232812Sjmallett uint32_t cx_nfunc : 3; 4900232812Sjmallett#endif 4901232812Sjmallett } s; 4902232812Sjmallett struct cvmx_pciercx_cfg454_cn52xx { 4903232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4904215976Sjmallett uint32_t reserved_29_31 : 3; 4905215976Sjmallett uint32_t tmfcwt : 5; /**< Timer Modifier for Flow Control Watchdog Timer 4906215976Sjmallett Increases the timer value for the Flow Control watchdog timer, 4907215976Sjmallett in increments of 16 clock cycles. */ 4908215976Sjmallett uint32_t tmanlt : 5; /**< Timer Modifier for Ack/Nak Latency Timer 4909215976Sjmallett Increases the timer value for the Ack/Nak latency timer, in 4910215976Sjmallett increments of 64 clock cycles. */ 4911215976Sjmallett uint32_t tmrt : 5; /**< Timer Modifier for Replay Timer 4912215976Sjmallett Increases the timer value for the replay timer, in increments 4913215976Sjmallett of 64 clock cycles. */ 4914215976Sjmallett uint32_t reserved_11_13 : 3; 4915215976Sjmallett uint32_t nskps : 3; /**< Number of SKP Symbols */ 4916215976Sjmallett uint32_t reserved_4_7 : 4; 4917215976Sjmallett uint32_t ntss : 4; /**< Number of TS Symbols 4918215976Sjmallett Sets the number of TS identifier symbols that are sent in TS1 4919215976Sjmallett and TS2 ordered sets. */ 4920215976Sjmallett#else 4921215976Sjmallett uint32_t ntss : 4; 4922215976Sjmallett uint32_t reserved_4_7 : 4; 4923215976Sjmallett uint32_t nskps : 3; 4924215976Sjmallett uint32_t reserved_11_13 : 3; 4925215976Sjmallett uint32_t tmrt : 5; 4926215976Sjmallett uint32_t tmanlt : 5; 4927215976Sjmallett uint32_t tmfcwt : 5; 4928215976Sjmallett uint32_t reserved_29_31 : 3; 4929215976Sjmallett#endif 4930232812Sjmallett } cn52xx; 4931232812Sjmallett struct cvmx_pciercx_cfg454_cn52xx cn52xxp1; 4932232812Sjmallett struct cvmx_pciercx_cfg454_cn52xx cn56xx; 4933232812Sjmallett struct cvmx_pciercx_cfg454_cn52xx cn56xxp1; 4934232812Sjmallett struct cvmx_pciercx_cfg454_cn61xx { 4935232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4936232812Sjmallett uint32_t cx_nfunc : 3; /**< Number of Functions (minus 1) 4937232812Sjmallett Configuration Requests targeted at function numbers above this 4938232812Sjmallett value will be returned with unsupported request */ 4939232812Sjmallett uint32_t tmfcwt : 5; /**< Timer Modifier for Flow Control Watchdog Timer 4940232812Sjmallett Increases the timer value for the Flow Control watchdog timer, 4941232812Sjmallett in increments of 16 clock cycles. */ 4942232812Sjmallett uint32_t tmanlt : 5; /**< Timer Modifier for Ack/Nak Latency Timer 4943232812Sjmallett Increases the timer value for the Ack/Nak latency timer, in 4944232812Sjmallett increments of 64 clock cycles. */ 4945232812Sjmallett uint32_t tmrt : 5; /**< Timer Modifier for Replay Timer 4946232812Sjmallett Increases the timer value for the replay timer, in increments 4947232812Sjmallett of 64 clock cycles. */ 4948232812Sjmallett uint32_t reserved_8_13 : 6; 4949232812Sjmallett uint32_t mfuncn : 8; /**< Max Number of Functions Supported */ 4950232812Sjmallett#else 4951232812Sjmallett uint32_t mfuncn : 8; 4952232812Sjmallett uint32_t reserved_8_13 : 6; 4953232812Sjmallett uint32_t tmrt : 5; 4954232812Sjmallett uint32_t tmanlt : 5; 4955232812Sjmallett uint32_t tmfcwt : 5; 4956232812Sjmallett uint32_t cx_nfunc : 3; 4957232812Sjmallett#endif 4958232812Sjmallett } cn61xx; 4959232812Sjmallett struct cvmx_pciercx_cfg454_cn52xx cn63xx; 4960232812Sjmallett struct cvmx_pciercx_cfg454_cn52xx cn63xxp1; 4961232812Sjmallett struct cvmx_pciercx_cfg454_cn61xx cn66xx; 4962232812Sjmallett struct cvmx_pciercx_cfg454_cn61xx cn68xx; 4963232812Sjmallett struct cvmx_pciercx_cfg454_cn52xx cn68xxp1; 4964232812Sjmallett struct cvmx_pciercx_cfg454_cn61xx cnf71xx; 4965215976Sjmallett}; 4966215976Sjmalletttypedef union cvmx_pciercx_cfg454 cvmx_pciercx_cfg454_t; 4967215976Sjmallett 4968215976Sjmallett/** 4969215976Sjmallett * cvmx_pcierc#_cfg455 4970215976Sjmallett * 4971215976Sjmallett * PCIE_CFG455 = Four hundred fifty-sixth 32-bits of PCIE type 1 config space 4972215976Sjmallett * (Symbol Timer Register/Filter Mask Register 1) 4973215976Sjmallett */ 4974232812Sjmallettunion cvmx_pciercx_cfg455 { 4975215976Sjmallett uint32_t u32; 4976232812Sjmallett struct cvmx_pciercx_cfg455_s { 4977232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4978215976Sjmallett uint32_t m_cfg0_filt : 1; /**< Mask filtering of received Configuration Requests (RC mode only) */ 4979215976Sjmallett uint32_t m_io_filt : 1; /**< Mask filtering of received I/O Requests (RC mode only) */ 4980215976Sjmallett uint32_t msg_ctrl : 1; /**< Message Control 4981215976Sjmallett The application must not change this field. */ 4982215976Sjmallett uint32_t m_cpl_ecrc_filt : 1; /**< Mask ECRC error filtering for Completions */ 4983215976Sjmallett uint32_t m_ecrc_filt : 1; /**< Mask ECRC error filtering */ 4984215976Sjmallett uint32_t m_cpl_len_err : 1; /**< Mask Length mismatch error for received Completions */ 4985215976Sjmallett uint32_t m_cpl_attr_err : 1; /**< Mask Attributes mismatch error for received Completions */ 4986215976Sjmallett uint32_t m_cpl_tc_err : 1; /**< Mask Traffic Class mismatch error for received Completions */ 4987215976Sjmallett uint32_t m_cpl_fun_err : 1; /**< Mask function mismatch error for received Completions */ 4988215976Sjmallett uint32_t m_cpl_rid_err : 1; /**< Mask Requester ID mismatch error for received Completions */ 4989215976Sjmallett uint32_t m_cpl_tag_err : 1; /**< Mask Tag error rules for received Completions */ 4990215976Sjmallett uint32_t m_lk_filt : 1; /**< Mask Locked Request filtering */ 4991215976Sjmallett uint32_t m_cfg1_filt : 1; /**< Mask Type 1 Configuration Request filtering */ 4992215976Sjmallett uint32_t m_bar_match : 1; /**< Mask BAR match filtering */ 4993215976Sjmallett uint32_t m_pois_filt : 1; /**< Mask poisoned TLP filtering */ 4994215976Sjmallett uint32_t m_fun : 1; /**< Mask function */ 4995215976Sjmallett uint32_t dfcwt : 1; /**< Disable FC Watchdog Timer */ 4996215976Sjmallett uint32_t reserved_11_14 : 4; 4997215976Sjmallett uint32_t skpiv : 11; /**< SKP Interval Value */ 4998215976Sjmallett#else 4999215976Sjmallett uint32_t skpiv : 11; 5000215976Sjmallett uint32_t reserved_11_14 : 4; 5001215976Sjmallett uint32_t dfcwt : 1; 5002215976Sjmallett uint32_t m_fun : 1; 5003215976Sjmallett uint32_t m_pois_filt : 1; 5004215976Sjmallett uint32_t m_bar_match : 1; 5005215976Sjmallett uint32_t m_cfg1_filt : 1; 5006215976Sjmallett uint32_t m_lk_filt : 1; 5007215976Sjmallett uint32_t m_cpl_tag_err : 1; 5008215976Sjmallett uint32_t m_cpl_rid_err : 1; 5009215976Sjmallett uint32_t m_cpl_fun_err : 1; 5010215976Sjmallett uint32_t m_cpl_tc_err : 1; 5011215976Sjmallett uint32_t m_cpl_attr_err : 1; 5012215976Sjmallett uint32_t m_cpl_len_err : 1; 5013215976Sjmallett uint32_t m_ecrc_filt : 1; 5014215976Sjmallett uint32_t m_cpl_ecrc_filt : 1; 5015215976Sjmallett uint32_t msg_ctrl : 1; 5016215976Sjmallett uint32_t m_io_filt : 1; 5017215976Sjmallett uint32_t m_cfg0_filt : 1; 5018215976Sjmallett#endif 5019215976Sjmallett } s; 5020215976Sjmallett struct cvmx_pciercx_cfg455_s cn52xx; 5021215976Sjmallett struct cvmx_pciercx_cfg455_s cn52xxp1; 5022215976Sjmallett struct cvmx_pciercx_cfg455_s cn56xx; 5023215976Sjmallett struct cvmx_pciercx_cfg455_s cn56xxp1; 5024232812Sjmallett struct cvmx_pciercx_cfg455_s cn61xx; 5025215976Sjmallett struct cvmx_pciercx_cfg455_s cn63xx; 5026215976Sjmallett struct cvmx_pciercx_cfg455_s cn63xxp1; 5027232812Sjmallett struct cvmx_pciercx_cfg455_s cn66xx; 5028232812Sjmallett struct cvmx_pciercx_cfg455_s cn68xx; 5029232812Sjmallett struct cvmx_pciercx_cfg455_s cn68xxp1; 5030232812Sjmallett struct cvmx_pciercx_cfg455_s cnf71xx; 5031215976Sjmallett}; 5032215976Sjmalletttypedef union cvmx_pciercx_cfg455 cvmx_pciercx_cfg455_t; 5033215976Sjmallett 5034215976Sjmallett/** 5035215976Sjmallett * cvmx_pcierc#_cfg456 5036215976Sjmallett * 5037215976Sjmallett * PCIE_CFG456 = Four hundred fifty-seventh 32-bits of PCIE type 1 config space 5038215976Sjmallett * (Filter Mask Register 2) 5039215976Sjmallett */ 5040232812Sjmallettunion cvmx_pciercx_cfg456 { 5041215976Sjmallett uint32_t u32; 5042232812Sjmallett struct cvmx_pciercx_cfg456_s { 5043232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5044232812Sjmallett uint32_t reserved_4_31 : 28; 5045232812Sjmallett uint32_t m_handle_flush : 1; /**< Mask Core Filter to handle flush request */ 5046232812Sjmallett uint32_t m_dabort_4ucpl : 1; /**< Mask DLLP abort for unexpected CPL */ 5047232812Sjmallett uint32_t m_vend1_drp : 1; /**< Mask Vendor MSG Type 1 dropped silently */ 5048232812Sjmallett uint32_t m_vend0_drp : 1; /**< Mask Vendor MSG Type 0 dropped with UR error reporting. */ 5049232812Sjmallett#else 5050232812Sjmallett uint32_t m_vend0_drp : 1; 5051232812Sjmallett uint32_t m_vend1_drp : 1; 5052232812Sjmallett uint32_t m_dabort_4ucpl : 1; 5053232812Sjmallett uint32_t m_handle_flush : 1; 5054232812Sjmallett uint32_t reserved_4_31 : 28; 5055232812Sjmallett#endif 5056232812Sjmallett } s; 5057232812Sjmallett struct cvmx_pciercx_cfg456_cn52xx { 5058232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5059215976Sjmallett uint32_t reserved_2_31 : 30; 5060215976Sjmallett uint32_t m_vend1_drp : 1; /**< Mask Vendor MSG Type 1 dropped silently */ 5061215976Sjmallett uint32_t m_vend0_drp : 1; /**< Mask Vendor MSG Type 0 dropped with UR error reporting. */ 5062215976Sjmallett#else 5063215976Sjmallett uint32_t m_vend0_drp : 1; 5064215976Sjmallett uint32_t m_vend1_drp : 1; 5065215976Sjmallett uint32_t reserved_2_31 : 30; 5066215976Sjmallett#endif 5067232812Sjmallett } cn52xx; 5068232812Sjmallett struct cvmx_pciercx_cfg456_cn52xx cn52xxp1; 5069232812Sjmallett struct cvmx_pciercx_cfg456_cn52xx cn56xx; 5070232812Sjmallett struct cvmx_pciercx_cfg456_cn52xx cn56xxp1; 5071232812Sjmallett struct cvmx_pciercx_cfg456_s cn61xx; 5072232812Sjmallett struct cvmx_pciercx_cfg456_cn52xx cn63xx; 5073232812Sjmallett struct cvmx_pciercx_cfg456_cn52xx cn63xxp1; 5074232812Sjmallett struct cvmx_pciercx_cfg456_s cn66xx; 5075232812Sjmallett struct cvmx_pciercx_cfg456_s cn68xx; 5076232812Sjmallett struct cvmx_pciercx_cfg456_cn52xx cn68xxp1; 5077232812Sjmallett struct cvmx_pciercx_cfg456_s cnf71xx; 5078215976Sjmallett}; 5079215976Sjmalletttypedef union cvmx_pciercx_cfg456 cvmx_pciercx_cfg456_t; 5080215976Sjmallett 5081215976Sjmallett/** 5082215976Sjmallett * cvmx_pcierc#_cfg458 5083215976Sjmallett * 5084215976Sjmallett * PCIE_CFG458 = Four hundred fifty-ninth 32-bits of PCIE type 1 config space 5085215976Sjmallett * (Debug Register 0) 5086215976Sjmallett */ 5087232812Sjmallettunion cvmx_pciercx_cfg458 { 5088215976Sjmallett uint32_t u32; 5089232812Sjmallett struct cvmx_pciercx_cfg458_s { 5090232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5091215976Sjmallett uint32_t dbg_info_l32 : 32; /**< The value on cxpl_debug_info[31:0]. */ 5092215976Sjmallett#else 5093215976Sjmallett uint32_t dbg_info_l32 : 32; 5094215976Sjmallett#endif 5095215976Sjmallett } s; 5096215976Sjmallett struct cvmx_pciercx_cfg458_s cn52xx; 5097215976Sjmallett struct cvmx_pciercx_cfg458_s cn52xxp1; 5098215976Sjmallett struct cvmx_pciercx_cfg458_s cn56xx; 5099215976Sjmallett struct cvmx_pciercx_cfg458_s cn56xxp1; 5100232812Sjmallett struct cvmx_pciercx_cfg458_s cn61xx; 5101215976Sjmallett struct cvmx_pciercx_cfg458_s cn63xx; 5102215976Sjmallett struct cvmx_pciercx_cfg458_s cn63xxp1; 5103232812Sjmallett struct cvmx_pciercx_cfg458_s cn66xx; 5104232812Sjmallett struct cvmx_pciercx_cfg458_s cn68xx; 5105232812Sjmallett struct cvmx_pciercx_cfg458_s cn68xxp1; 5106232812Sjmallett struct cvmx_pciercx_cfg458_s cnf71xx; 5107215976Sjmallett}; 5108215976Sjmalletttypedef union cvmx_pciercx_cfg458 cvmx_pciercx_cfg458_t; 5109215976Sjmallett 5110215976Sjmallett/** 5111215976Sjmallett * cvmx_pcierc#_cfg459 5112215976Sjmallett * 5113215976Sjmallett * PCIE_CFG459 = Four hundred sixtieth 32-bits of PCIE type 1 config space 5114215976Sjmallett * (Debug Register 1) 5115215976Sjmallett */ 5116232812Sjmallettunion cvmx_pciercx_cfg459 { 5117215976Sjmallett uint32_t u32; 5118232812Sjmallett struct cvmx_pciercx_cfg459_s { 5119232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5120215976Sjmallett uint32_t dbg_info_u32 : 32; /**< The value on cxpl_debug_info[63:32]. */ 5121215976Sjmallett#else 5122215976Sjmallett uint32_t dbg_info_u32 : 32; 5123215976Sjmallett#endif 5124215976Sjmallett } s; 5125215976Sjmallett struct cvmx_pciercx_cfg459_s cn52xx; 5126215976Sjmallett struct cvmx_pciercx_cfg459_s cn52xxp1; 5127215976Sjmallett struct cvmx_pciercx_cfg459_s cn56xx; 5128215976Sjmallett struct cvmx_pciercx_cfg459_s cn56xxp1; 5129232812Sjmallett struct cvmx_pciercx_cfg459_s cn61xx; 5130215976Sjmallett struct cvmx_pciercx_cfg459_s cn63xx; 5131215976Sjmallett struct cvmx_pciercx_cfg459_s cn63xxp1; 5132232812Sjmallett struct cvmx_pciercx_cfg459_s cn66xx; 5133232812Sjmallett struct cvmx_pciercx_cfg459_s cn68xx; 5134232812Sjmallett struct cvmx_pciercx_cfg459_s cn68xxp1; 5135232812Sjmallett struct cvmx_pciercx_cfg459_s cnf71xx; 5136215976Sjmallett}; 5137215976Sjmalletttypedef union cvmx_pciercx_cfg459 cvmx_pciercx_cfg459_t; 5138215976Sjmallett 5139215976Sjmallett/** 5140215976Sjmallett * cvmx_pcierc#_cfg460 5141215976Sjmallett * 5142215976Sjmallett * PCIE_CFG460 = Four hundred sixty-first 32-bits of PCIE type 1 config space 5143215976Sjmallett * (Transmit Posted FC Credit Status) 5144215976Sjmallett */ 5145232812Sjmallettunion cvmx_pciercx_cfg460 { 5146215976Sjmallett uint32_t u32; 5147232812Sjmallett struct cvmx_pciercx_cfg460_s { 5148232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5149215976Sjmallett uint32_t reserved_20_31 : 12; 5150215976Sjmallett uint32_t tphfcc : 8; /**< Transmit Posted Header FC Credits 5151215976Sjmallett The Posted Header credits advertised by the receiver at the 5152215976Sjmallett other end of the Link, updated with each UpdateFC DLLP. */ 5153215976Sjmallett uint32_t tpdfcc : 12; /**< Transmit Posted Data FC Credits 5154215976Sjmallett The Posted Data credits advertised by the receiver at the other 5155215976Sjmallett end of the Link, updated with each UpdateFC DLLP. */ 5156215976Sjmallett#else 5157215976Sjmallett uint32_t tpdfcc : 12; 5158215976Sjmallett uint32_t tphfcc : 8; 5159215976Sjmallett uint32_t reserved_20_31 : 12; 5160215976Sjmallett#endif 5161215976Sjmallett } s; 5162215976Sjmallett struct cvmx_pciercx_cfg460_s cn52xx; 5163215976Sjmallett struct cvmx_pciercx_cfg460_s cn52xxp1; 5164215976Sjmallett struct cvmx_pciercx_cfg460_s cn56xx; 5165215976Sjmallett struct cvmx_pciercx_cfg460_s cn56xxp1; 5166232812Sjmallett struct cvmx_pciercx_cfg460_s cn61xx; 5167215976Sjmallett struct cvmx_pciercx_cfg460_s cn63xx; 5168215976Sjmallett struct cvmx_pciercx_cfg460_s cn63xxp1; 5169232812Sjmallett struct cvmx_pciercx_cfg460_s cn66xx; 5170232812Sjmallett struct cvmx_pciercx_cfg460_s cn68xx; 5171232812Sjmallett struct cvmx_pciercx_cfg460_s cn68xxp1; 5172232812Sjmallett struct cvmx_pciercx_cfg460_s cnf71xx; 5173215976Sjmallett}; 5174215976Sjmalletttypedef union cvmx_pciercx_cfg460 cvmx_pciercx_cfg460_t; 5175215976Sjmallett 5176215976Sjmallett/** 5177215976Sjmallett * cvmx_pcierc#_cfg461 5178215976Sjmallett * 5179215976Sjmallett * PCIE_CFG461 = Four hundred sixty-second 32-bits of PCIE type 1 config space 5180215976Sjmallett * (Transmit Non-Posted FC Credit Status) 5181215976Sjmallett */ 5182232812Sjmallettunion cvmx_pciercx_cfg461 { 5183215976Sjmallett uint32_t u32; 5184232812Sjmallett struct cvmx_pciercx_cfg461_s { 5185232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5186215976Sjmallett uint32_t reserved_20_31 : 12; 5187215976Sjmallett uint32_t tchfcc : 8; /**< Transmit Non-Posted Header FC Credits 5188215976Sjmallett The Non-Posted Header credits advertised by the receiver at the 5189215976Sjmallett other end of the Link, updated with each UpdateFC DLLP. */ 5190215976Sjmallett uint32_t tcdfcc : 12; /**< Transmit Non-Posted Data FC Credits 5191215976Sjmallett The Non-Posted Data credits advertised by the receiver at the 5192215976Sjmallett other end of the Link, updated with each UpdateFC DLLP. */ 5193215976Sjmallett#else 5194215976Sjmallett uint32_t tcdfcc : 12; 5195215976Sjmallett uint32_t tchfcc : 8; 5196215976Sjmallett uint32_t reserved_20_31 : 12; 5197215976Sjmallett#endif 5198215976Sjmallett } s; 5199215976Sjmallett struct cvmx_pciercx_cfg461_s cn52xx; 5200215976Sjmallett struct cvmx_pciercx_cfg461_s cn52xxp1; 5201215976Sjmallett struct cvmx_pciercx_cfg461_s cn56xx; 5202215976Sjmallett struct cvmx_pciercx_cfg461_s cn56xxp1; 5203232812Sjmallett struct cvmx_pciercx_cfg461_s cn61xx; 5204215976Sjmallett struct cvmx_pciercx_cfg461_s cn63xx; 5205215976Sjmallett struct cvmx_pciercx_cfg461_s cn63xxp1; 5206232812Sjmallett struct cvmx_pciercx_cfg461_s cn66xx; 5207232812Sjmallett struct cvmx_pciercx_cfg461_s cn68xx; 5208232812Sjmallett struct cvmx_pciercx_cfg461_s cn68xxp1; 5209232812Sjmallett struct cvmx_pciercx_cfg461_s cnf71xx; 5210215976Sjmallett}; 5211215976Sjmalletttypedef union cvmx_pciercx_cfg461 cvmx_pciercx_cfg461_t; 5212215976Sjmallett 5213215976Sjmallett/** 5214215976Sjmallett * cvmx_pcierc#_cfg462 5215215976Sjmallett * 5216215976Sjmallett * PCIE_CFG462 = Four hundred sixty-third 32-bits of PCIE type 1 config space 5217215976Sjmallett * (Transmit Completion FC Credit Status ) 5218215976Sjmallett */ 5219232812Sjmallettunion cvmx_pciercx_cfg462 { 5220215976Sjmallett uint32_t u32; 5221232812Sjmallett struct cvmx_pciercx_cfg462_s { 5222232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5223215976Sjmallett uint32_t reserved_20_31 : 12; 5224215976Sjmallett uint32_t tchfcc : 8; /**< Transmit Completion Header FC Credits 5225215976Sjmallett The Completion Header credits advertised by the receiver at the 5226215976Sjmallett other end of the Link, updated with each UpdateFC DLLP. */ 5227215976Sjmallett uint32_t tcdfcc : 12; /**< Transmit Completion Data FC Credits 5228215976Sjmallett The Completion Data credits advertised by the receiver at the 5229215976Sjmallett other end of the Link, updated with each UpdateFC DLLP. */ 5230215976Sjmallett#else 5231215976Sjmallett uint32_t tcdfcc : 12; 5232215976Sjmallett uint32_t tchfcc : 8; 5233215976Sjmallett uint32_t reserved_20_31 : 12; 5234215976Sjmallett#endif 5235215976Sjmallett } s; 5236215976Sjmallett struct cvmx_pciercx_cfg462_s cn52xx; 5237215976Sjmallett struct cvmx_pciercx_cfg462_s cn52xxp1; 5238215976Sjmallett struct cvmx_pciercx_cfg462_s cn56xx; 5239215976Sjmallett struct cvmx_pciercx_cfg462_s cn56xxp1; 5240232812Sjmallett struct cvmx_pciercx_cfg462_s cn61xx; 5241215976Sjmallett struct cvmx_pciercx_cfg462_s cn63xx; 5242215976Sjmallett struct cvmx_pciercx_cfg462_s cn63xxp1; 5243232812Sjmallett struct cvmx_pciercx_cfg462_s cn66xx; 5244232812Sjmallett struct cvmx_pciercx_cfg462_s cn68xx; 5245232812Sjmallett struct cvmx_pciercx_cfg462_s cn68xxp1; 5246232812Sjmallett struct cvmx_pciercx_cfg462_s cnf71xx; 5247215976Sjmallett}; 5248215976Sjmalletttypedef union cvmx_pciercx_cfg462 cvmx_pciercx_cfg462_t; 5249215976Sjmallett 5250215976Sjmallett/** 5251215976Sjmallett * cvmx_pcierc#_cfg463 5252215976Sjmallett * 5253215976Sjmallett * PCIE_CFG463 = Four hundred sixty-fourth 32-bits of PCIE type 1 config space 5254215976Sjmallett * (Queue Status) 5255215976Sjmallett */ 5256232812Sjmallettunion cvmx_pciercx_cfg463 { 5257215976Sjmallett uint32_t u32; 5258232812Sjmallett struct cvmx_pciercx_cfg463_s { 5259232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5260215976Sjmallett uint32_t reserved_3_31 : 29; 5261215976Sjmallett uint32_t rqne : 1; /**< Received Queue Not Empty 5262215976Sjmallett Indicates there is data in one or more of the receive buffers. */ 5263215976Sjmallett uint32_t trbne : 1; /**< Transmit Retry Buffer Not Empty 5264215976Sjmallett Indicates that there is data in the transmit retry buffer. */ 5265215976Sjmallett uint32_t rtlpfccnr : 1; /**< Received TLP FC Credits Not Returned 5266215976Sjmallett Indicates that the PCI Express bus has sent a TLP but has not 5267215976Sjmallett yet received an UpdateFC DLLP indicating that the credits for 5268215976Sjmallett that TLP have been restored by the receiver at the other end of 5269215976Sjmallett the Link. */ 5270215976Sjmallett#else 5271215976Sjmallett uint32_t rtlpfccnr : 1; 5272215976Sjmallett uint32_t trbne : 1; 5273215976Sjmallett uint32_t rqne : 1; 5274215976Sjmallett uint32_t reserved_3_31 : 29; 5275215976Sjmallett#endif 5276215976Sjmallett } s; 5277215976Sjmallett struct cvmx_pciercx_cfg463_s cn52xx; 5278215976Sjmallett struct cvmx_pciercx_cfg463_s cn52xxp1; 5279215976Sjmallett struct cvmx_pciercx_cfg463_s cn56xx; 5280215976Sjmallett struct cvmx_pciercx_cfg463_s cn56xxp1; 5281232812Sjmallett struct cvmx_pciercx_cfg463_s cn61xx; 5282215976Sjmallett struct cvmx_pciercx_cfg463_s cn63xx; 5283215976Sjmallett struct cvmx_pciercx_cfg463_s cn63xxp1; 5284232812Sjmallett struct cvmx_pciercx_cfg463_s cn66xx; 5285232812Sjmallett struct cvmx_pciercx_cfg463_s cn68xx; 5286232812Sjmallett struct cvmx_pciercx_cfg463_s cn68xxp1; 5287232812Sjmallett struct cvmx_pciercx_cfg463_s cnf71xx; 5288215976Sjmallett}; 5289215976Sjmalletttypedef union cvmx_pciercx_cfg463 cvmx_pciercx_cfg463_t; 5290215976Sjmallett 5291215976Sjmallett/** 5292215976Sjmallett * cvmx_pcierc#_cfg464 5293215976Sjmallett * 5294215976Sjmallett * PCIE_CFG464 = Four hundred sixty-fifth 32-bits of PCIE type 1 config space 5295215976Sjmallett * (VC Transmit Arbitration Register 1) 5296215976Sjmallett */ 5297232812Sjmallettunion cvmx_pciercx_cfg464 { 5298215976Sjmallett uint32_t u32; 5299232812Sjmallett struct cvmx_pciercx_cfg464_s { 5300232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5301215976Sjmallett uint32_t wrr_vc3 : 8; /**< WRR Weight for VC3 */ 5302215976Sjmallett uint32_t wrr_vc2 : 8; /**< WRR Weight for VC2 */ 5303215976Sjmallett uint32_t wrr_vc1 : 8; /**< WRR Weight for VC1 */ 5304215976Sjmallett uint32_t wrr_vc0 : 8; /**< WRR Weight for VC0 */ 5305215976Sjmallett#else 5306215976Sjmallett uint32_t wrr_vc0 : 8; 5307215976Sjmallett uint32_t wrr_vc1 : 8; 5308215976Sjmallett uint32_t wrr_vc2 : 8; 5309215976Sjmallett uint32_t wrr_vc3 : 8; 5310215976Sjmallett#endif 5311215976Sjmallett } s; 5312215976Sjmallett struct cvmx_pciercx_cfg464_s cn52xx; 5313215976Sjmallett struct cvmx_pciercx_cfg464_s cn52xxp1; 5314215976Sjmallett struct cvmx_pciercx_cfg464_s cn56xx; 5315215976Sjmallett struct cvmx_pciercx_cfg464_s cn56xxp1; 5316232812Sjmallett struct cvmx_pciercx_cfg464_s cn61xx; 5317215976Sjmallett struct cvmx_pciercx_cfg464_s cn63xx; 5318215976Sjmallett struct cvmx_pciercx_cfg464_s cn63xxp1; 5319232812Sjmallett struct cvmx_pciercx_cfg464_s cn66xx; 5320232812Sjmallett struct cvmx_pciercx_cfg464_s cn68xx; 5321232812Sjmallett struct cvmx_pciercx_cfg464_s cn68xxp1; 5322232812Sjmallett struct cvmx_pciercx_cfg464_s cnf71xx; 5323215976Sjmallett}; 5324215976Sjmalletttypedef union cvmx_pciercx_cfg464 cvmx_pciercx_cfg464_t; 5325215976Sjmallett 5326215976Sjmallett/** 5327215976Sjmallett * cvmx_pcierc#_cfg465 5328215976Sjmallett * 5329215976Sjmallett * PCIE_CFG465 = Four hundred sixty-sixth 32-bits of config space 5330215976Sjmallett * (VC Transmit Arbitration Register 2) 5331215976Sjmallett */ 5332232812Sjmallettunion cvmx_pciercx_cfg465 { 5333215976Sjmallett uint32_t u32; 5334232812Sjmallett struct cvmx_pciercx_cfg465_s { 5335232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5336215976Sjmallett uint32_t wrr_vc7 : 8; /**< WRR Weight for VC7 */ 5337215976Sjmallett uint32_t wrr_vc6 : 8; /**< WRR Weight for VC6 */ 5338215976Sjmallett uint32_t wrr_vc5 : 8; /**< WRR Weight for VC5 */ 5339215976Sjmallett uint32_t wrr_vc4 : 8; /**< WRR Weight for VC4 */ 5340215976Sjmallett#else 5341215976Sjmallett uint32_t wrr_vc4 : 8; 5342215976Sjmallett uint32_t wrr_vc5 : 8; 5343215976Sjmallett uint32_t wrr_vc6 : 8; 5344215976Sjmallett uint32_t wrr_vc7 : 8; 5345215976Sjmallett#endif 5346215976Sjmallett } s; 5347215976Sjmallett struct cvmx_pciercx_cfg465_s cn52xx; 5348215976Sjmallett struct cvmx_pciercx_cfg465_s cn52xxp1; 5349215976Sjmallett struct cvmx_pciercx_cfg465_s cn56xx; 5350215976Sjmallett struct cvmx_pciercx_cfg465_s cn56xxp1; 5351232812Sjmallett struct cvmx_pciercx_cfg465_s cn61xx; 5352215976Sjmallett struct cvmx_pciercx_cfg465_s cn63xx; 5353215976Sjmallett struct cvmx_pciercx_cfg465_s cn63xxp1; 5354232812Sjmallett struct cvmx_pciercx_cfg465_s cn66xx; 5355232812Sjmallett struct cvmx_pciercx_cfg465_s cn68xx; 5356232812Sjmallett struct cvmx_pciercx_cfg465_s cn68xxp1; 5357232812Sjmallett struct cvmx_pciercx_cfg465_s cnf71xx; 5358215976Sjmallett}; 5359215976Sjmalletttypedef union cvmx_pciercx_cfg465 cvmx_pciercx_cfg465_t; 5360215976Sjmallett 5361215976Sjmallett/** 5362215976Sjmallett * cvmx_pcierc#_cfg466 5363215976Sjmallett * 5364215976Sjmallett * PCIE_CFG466 = Four hundred sixty-seventh 32-bits of PCIE type 1 config space 5365215976Sjmallett * (VC0 Posted Receive Queue Control) 5366215976Sjmallett */ 5367232812Sjmallettunion cvmx_pciercx_cfg466 { 5368215976Sjmallett uint32_t u32; 5369232812Sjmallett struct cvmx_pciercx_cfg466_s { 5370232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5371215976Sjmallett uint32_t rx_queue_order : 1; /**< VC Ordering for Receive Queues 5372215976Sjmallett Determines the VC ordering rule for the receive queues, used 5373215976Sjmallett only in the segmented-buffer configuration, 5374215976Sjmallett writable through PEM(0..1)_CFG_WR: 5375215976Sjmallett o 1: Strict ordering, higher numbered VCs have higher priority 5376215976Sjmallett o 0: Round robin 5377215976Sjmallett However, the application must not change this field. */ 5378215976Sjmallett uint32_t type_ordering : 1; /**< TLP Type Ordering for VC0 5379215976Sjmallett Determines the TLP type ordering rule for VC0 receive queues, 5380215976Sjmallett used only in the segmented-buffer configuration, writable 5381215976Sjmallett through PEM(0..1)_CFG_WR: 5382215976Sjmallett o 1: Ordering of received TLPs follows the rules in 5383215976Sjmallett PCI Express Base Specification 5384215976Sjmallett o 0: Strict ordering for received TLPs: Posted, then 5385215976Sjmallett Completion, then Non-Posted 5386215976Sjmallett However, the application must not change this field. */ 5387215976Sjmallett uint32_t reserved_24_29 : 6; 5388215976Sjmallett uint32_t queue_mode : 3; /**< VC0 Posted TLP Queue Mode 5389215976Sjmallett The operating mode of the Posted receive queue for VC0, used 5390215976Sjmallett only in the segmented-buffer configuration, writable through 5391215976Sjmallett PEM(0..1)_CFG_WR. 5392215976Sjmallett However, the application must not change this field. 5393215976Sjmallett Only one bit can be set at a time: 5394215976Sjmallett o Bit 23: Bypass 5395215976Sjmallett o Bit 22: Cut-through 5396215976Sjmallett o Bit 21: Store-and-forward */ 5397215976Sjmallett uint32_t reserved_20_20 : 1; 5398215976Sjmallett uint32_t header_credits : 8; /**< VC0 Posted Header Credits 5399215976Sjmallett The number of initial Posted header credits for VC0, used for 5400215976Sjmallett all receive queue buffer configurations. 5401215976Sjmallett This field is writable through PEM(0..1)_CFG_WR. 5402215976Sjmallett However, the application must not change this field. */ 5403215976Sjmallett uint32_t data_credits : 12; /**< VC0 Posted Data Credits 5404215976Sjmallett The number of initial Posted data credits for VC0, used for all 5405215976Sjmallett receive queue buffer configurations. 5406215976Sjmallett This field is writable through PEM(0..1)_CFG_WR. 5407215976Sjmallett However, the application must not change this field. */ 5408215976Sjmallett#else 5409215976Sjmallett uint32_t data_credits : 12; 5410215976Sjmallett uint32_t header_credits : 8; 5411215976Sjmallett uint32_t reserved_20_20 : 1; 5412215976Sjmallett uint32_t queue_mode : 3; 5413215976Sjmallett uint32_t reserved_24_29 : 6; 5414215976Sjmallett uint32_t type_ordering : 1; 5415215976Sjmallett uint32_t rx_queue_order : 1; 5416215976Sjmallett#endif 5417215976Sjmallett } s; 5418215976Sjmallett struct cvmx_pciercx_cfg466_s cn52xx; 5419215976Sjmallett struct cvmx_pciercx_cfg466_s cn52xxp1; 5420215976Sjmallett struct cvmx_pciercx_cfg466_s cn56xx; 5421215976Sjmallett struct cvmx_pciercx_cfg466_s cn56xxp1; 5422232812Sjmallett struct cvmx_pciercx_cfg466_s cn61xx; 5423215976Sjmallett struct cvmx_pciercx_cfg466_s cn63xx; 5424215976Sjmallett struct cvmx_pciercx_cfg466_s cn63xxp1; 5425232812Sjmallett struct cvmx_pciercx_cfg466_s cn66xx; 5426232812Sjmallett struct cvmx_pciercx_cfg466_s cn68xx; 5427232812Sjmallett struct cvmx_pciercx_cfg466_s cn68xxp1; 5428232812Sjmallett struct cvmx_pciercx_cfg466_s cnf71xx; 5429215976Sjmallett}; 5430215976Sjmalletttypedef union cvmx_pciercx_cfg466 cvmx_pciercx_cfg466_t; 5431215976Sjmallett 5432215976Sjmallett/** 5433215976Sjmallett * cvmx_pcierc#_cfg467 5434215976Sjmallett * 5435215976Sjmallett * PCIE_CFG467 = Four hundred sixty-eighth 32-bits of PCIE type 1 config space 5436215976Sjmallett * (VC0 Non-Posted Receive Queue Control) 5437215976Sjmallett */ 5438232812Sjmallettunion cvmx_pciercx_cfg467 { 5439215976Sjmallett uint32_t u32; 5440232812Sjmallett struct cvmx_pciercx_cfg467_s { 5441232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5442215976Sjmallett uint32_t reserved_24_31 : 8; 5443215976Sjmallett uint32_t queue_mode : 3; /**< VC0 Non-Posted TLP Queue Mode 5444215976Sjmallett The operating mode of the Non-Posted receive queue for VC0, 5445215976Sjmallett used only in the segmented-buffer configuration, writable 5446215976Sjmallett through PEM(0..1)_CFG_WR. 5447215976Sjmallett Only one bit can be set at a time: 5448215976Sjmallett o Bit 23: Bypass 5449215976Sjmallett o Bit 22: Cut-through 5450215976Sjmallett o Bit 21: Store-and-forward 5451215976Sjmallett However, the application must not change this field. */ 5452215976Sjmallett uint32_t reserved_20_20 : 1; 5453215976Sjmallett uint32_t header_credits : 8; /**< VC0 Non-Posted Header Credits 5454215976Sjmallett The number of initial Non-Posted header credits for VC0, used 5455215976Sjmallett for all receive queue buffer configurations. 5456215976Sjmallett This field is writable through PEM(0..1)_CFG_WR. 5457215976Sjmallett However, the application must not change this field. */ 5458215976Sjmallett uint32_t data_credits : 12; /**< VC0 Non-Posted Data Credits 5459215976Sjmallett The number of initial Non-Posted data credits for VC0, used for 5460215976Sjmallett all receive queue buffer configurations. 5461215976Sjmallett This field is writable through PEM(0..1)_CFG_WR. 5462215976Sjmallett However, the application must not change this field. */ 5463215976Sjmallett#else 5464215976Sjmallett uint32_t data_credits : 12; 5465215976Sjmallett uint32_t header_credits : 8; 5466215976Sjmallett uint32_t reserved_20_20 : 1; 5467215976Sjmallett uint32_t queue_mode : 3; 5468215976Sjmallett uint32_t reserved_24_31 : 8; 5469215976Sjmallett#endif 5470215976Sjmallett } s; 5471215976Sjmallett struct cvmx_pciercx_cfg467_s cn52xx; 5472215976Sjmallett struct cvmx_pciercx_cfg467_s cn52xxp1; 5473215976Sjmallett struct cvmx_pciercx_cfg467_s cn56xx; 5474215976Sjmallett struct cvmx_pciercx_cfg467_s cn56xxp1; 5475232812Sjmallett struct cvmx_pciercx_cfg467_s cn61xx; 5476215976Sjmallett struct cvmx_pciercx_cfg467_s cn63xx; 5477215976Sjmallett struct cvmx_pciercx_cfg467_s cn63xxp1; 5478232812Sjmallett struct cvmx_pciercx_cfg467_s cn66xx; 5479232812Sjmallett struct cvmx_pciercx_cfg467_s cn68xx; 5480232812Sjmallett struct cvmx_pciercx_cfg467_s cn68xxp1; 5481232812Sjmallett struct cvmx_pciercx_cfg467_s cnf71xx; 5482215976Sjmallett}; 5483215976Sjmalletttypedef union cvmx_pciercx_cfg467 cvmx_pciercx_cfg467_t; 5484215976Sjmallett 5485215976Sjmallett/** 5486215976Sjmallett * cvmx_pcierc#_cfg468 5487215976Sjmallett * 5488215976Sjmallett * PCIE_CFG468 = Four hundred sixty-ninth 32-bits of PCIE type 1 config space 5489215976Sjmallett * (VC0 Completion Receive Queue Control) 5490215976Sjmallett */ 5491232812Sjmallettunion cvmx_pciercx_cfg468 { 5492215976Sjmallett uint32_t u32; 5493232812Sjmallett struct cvmx_pciercx_cfg468_s { 5494232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5495215976Sjmallett uint32_t reserved_24_31 : 8; 5496215976Sjmallett uint32_t queue_mode : 3; /**< VC0 Completion TLP Queue Mode 5497215976Sjmallett The operating mode of the Completion receive queue for VC0, 5498215976Sjmallett used only in the segmented-buffer configuration, writable 5499215976Sjmallett through PEM(0..1)_CFG_WR. 5500215976Sjmallett Only one bit can be set at a time: 5501215976Sjmallett o Bit 23: Bypass 5502215976Sjmallett o Bit 22: Cut-through 5503215976Sjmallett o Bit 21: Store-and-forward 5504215976Sjmallett However, the application must not change this field. */ 5505215976Sjmallett uint32_t reserved_20_20 : 1; 5506215976Sjmallett uint32_t header_credits : 8; /**< VC0 Completion Header Credits 5507215976Sjmallett The number of initial Completion header credits for VC0, used 5508215976Sjmallett for all receive queue buffer configurations. 5509215976Sjmallett This field is writable through PEM(0..1)_CFG_WR. 5510215976Sjmallett However, the application must not change this field. */ 5511215976Sjmallett uint32_t data_credits : 12; /**< VC0 Completion Data Credits 5512215976Sjmallett The number of initial Completion data credits for VC0, used for 5513215976Sjmallett all receive queue buffer configurations. 5514215976Sjmallett This field is writable through PEM(0..1)_CFG_WR. 5515215976Sjmallett However, the application must not change this field. */ 5516215976Sjmallett#else 5517215976Sjmallett uint32_t data_credits : 12; 5518215976Sjmallett uint32_t header_credits : 8; 5519215976Sjmallett uint32_t reserved_20_20 : 1; 5520215976Sjmallett uint32_t queue_mode : 3; 5521215976Sjmallett uint32_t reserved_24_31 : 8; 5522215976Sjmallett#endif 5523215976Sjmallett } s; 5524215976Sjmallett struct cvmx_pciercx_cfg468_s cn52xx; 5525215976Sjmallett struct cvmx_pciercx_cfg468_s cn52xxp1; 5526215976Sjmallett struct cvmx_pciercx_cfg468_s cn56xx; 5527215976Sjmallett struct cvmx_pciercx_cfg468_s cn56xxp1; 5528232812Sjmallett struct cvmx_pciercx_cfg468_s cn61xx; 5529215976Sjmallett struct cvmx_pciercx_cfg468_s cn63xx; 5530215976Sjmallett struct cvmx_pciercx_cfg468_s cn63xxp1; 5531232812Sjmallett struct cvmx_pciercx_cfg468_s cn66xx; 5532232812Sjmallett struct cvmx_pciercx_cfg468_s cn68xx; 5533232812Sjmallett struct cvmx_pciercx_cfg468_s cn68xxp1; 5534232812Sjmallett struct cvmx_pciercx_cfg468_s cnf71xx; 5535215976Sjmallett}; 5536215976Sjmalletttypedef union cvmx_pciercx_cfg468 cvmx_pciercx_cfg468_t; 5537215976Sjmallett 5538215976Sjmallett/** 5539215976Sjmallett * cvmx_pcierc#_cfg490 5540215976Sjmallett * 5541215976Sjmallett * PCIE_CFG490 = Four hundred ninety-first 32-bits of PCIE type 1 config space 5542215976Sjmallett * (VC0 Posted Buffer Depth) 5543215976Sjmallett */ 5544232812Sjmallettunion cvmx_pciercx_cfg490 { 5545215976Sjmallett uint32_t u32; 5546232812Sjmallett struct cvmx_pciercx_cfg490_s { 5547232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5548215976Sjmallett uint32_t reserved_26_31 : 6; 5549215976Sjmallett uint32_t header_depth : 10; /**< VC0 Posted Header Queue Depth 5550215976Sjmallett Sets the number of entries in the Posted header queue for VC0 5551215976Sjmallett when using the segmented-buffer configuration, writable through 5552215976Sjmallett PEM(0..1)_CFG_WR. 5553215976Sjmallett However, the application must not change this field. */ 5554215976Sjmallett uint32_t reserved_14_15 : 2; 5555215976Sjmallett uint32_t data_depth : 14; /**< VC0 Posted Data Queue Depth 5556215976Sjmallett Sets the number of entries in the Posted data queue for VC0 5557215976Sjmallett when using the segmented-buffer configuration, writable 5558215976Sjmallett through PEM(0..1)_CFG_WR. 5559215976Sjmallett However, the application must not change this field. */ 5560215976Sjmallett#else 5561215976Sjmallett uint32_t data_depth : 14; 5562215976Sjmallett uint32_t reserved_14_15 : 2; 5563215976Sjmallett uint32_t header_depth : 10; 5564215976Sjmallett uint32_t reserved_26_31 : 6; 5565215976Sjmallett#endif 5566215976Sjmallett } s; 5567215976Sjmallett struct cvmx_pciercx_cfg490_s cn52xx; 5568215976Sjmallett struct cvmx_pciercx_cfg490_s cn52xxp1; 5569215976Sjmallett struct cvmx_pciercx_cfg490_s cn56xx; 5570215976Sjmallett struct cvmx_pciercx_cfg490_s cn56xxp1; 5571232812Sjmallett struct cvmx_pciercx_cfg490_s cn61xx; 5572215976Sjmallett struct cvmx_pciercx_cfg490_s cn63xx; 5573215976Sjmallett struct cvmx_pciercx_cfg490_s cn63xxp1; 5574232812Sjmallett struct cvmx_pciercx_cfg490_s cn66xx; 5575232812Sjmallett struct cvmx_pciercx_cfg490_s cn68xx; 5576232812Sjmallett struct cvmx_pciercx_cfg490_s cn68xxp1; 5577232812Sjmallett struct cvmx_pciercx_cfg490_s cnf71xx; 5578215976Sjmallett}; 5579215976Sjmalletttypedef union cvmx_pciercx_cfg490 cvmx_pciercx_cfg490_t; 5580215976Sjmallett 5581215976Sjmallett/** 5582215976Sjmallett * cvmx_pcierc#_cfg491 5583215976Sjmallett * 5584215976Sjmallett * PCIE_CFG491 = Four hundred ninety-second 32-bits of PCIE type 1 config space 5585215976Sjmallett * (VC0 Non-Posted Buffer Depth) 5586215976Sjmallett */ 5587232812Sjmallettunion cvmx_pciercx_cfg491 { 5588215976Sjmallett uint32_t u32; 5589232812Sjmallett struct cvmx_pciercx_cfg491_s { 5590232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5591215976Sjmallett uint32_t reserved_26_31 : 6; 5592215976Sjmallett uint32_t header_depth : 10; /**< VC0 Non-Posted Header Queue Depth 5593215976Sjmallett Sets the number of entries in the Non-Posted header queue for 5594215976Sjmallett VC0 when using the segmented-buffer configuration, writable 5595215976Sjmallett through PEM(0..1)_CFG_WR. 5596215976Sjmallett However, the application must not change this field. */ 5597215976Sjmallett uint32_t reserved_14_15 : 2; 5598215976Sjmallett uint32_t data_depth : 14; /**< VC0 Non-Posted Data Queue Depth 5599215976Sjmallett Sets the number of entries in the Non-Posted data queue for VC0 5600215976Sjmallett when using the segmented-buffer configuration, writable 5601215976Sjmallett through PEM(0..1)_CFG_WR. 5602215976Sjmallett However, the application must not change this field. */ 5603215976Sjmallett#else 5604215976Sjmallett uint32_t data_depth : 14; 5605215976Sjmallett uint32_t reserved_14_15 : 2; 5606215976Sjmallett uint32_t header_depth : 10; 5607215976Sjmallett uint32_t reserved_26_31 : 6; 5608215976Sjmallett#endif 5609215976Sjmallett } s; 5610215976Sjmallett struct cvmx_pciercx_cfg491_s cn52xx; 5611215976Sjmallett struct cvmx_pciercx_cfg491_s cn52xxp1; 5612215976Sjmallett struct cvmx_pciercx_cfg491_s cn56xx; 5613215976Sjmallett struct cvmx_pciercx_cfg491_s cn56xxp1; 5614232812Sjmallett struct cvmx_pciercx_cfg491_s cn61xx; 5615215976Sjmallett struct cvmx_pciercx_cfg491_s cn63xx; 5616215976Sjmallett struct cvmx_pciercx_cfg491_s cn63xxp1; 5617232812Sjmallett struct cvmx_pciercx_cfg491_s cn66xx; 5618232812Sjmallett struct cvmx_pciercx_cfg491_s cn68xx; 5619232812Sjmallett struct cvmx_pciercx_cfg491_s cn68xxp1; 5620232812Sjmallett struct cvmx_pciercx_cfg491_s cnf71xx; 5621215976Sjmallett}; 5622215976Sjmalletttypedef union cvmx_pciercx_cfg491 cvmx_pciercx_cfg491_t; 5623215976Sjmallett 5624215976Sjmallett/** 5625215976Sjmallett * cvmx_pcierc#_cfg492 5626215976Sjmallett * 5627215976Sjmallett * PCIE_CFG492 = Four hundred ninety-third 32-bits of PCIE type 1 config space 5628215976Sjmallett * (VC0 Completion Buffer Depth) 5629215976Sjmallett */ 5630232812Sjmallettunion cvmx_pciercx_cfg492 { 5631215976Sjmallett uint32_t u32; 5632232812Sjmallett struct cvmx_pciercx_cfg492_s { 5633232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5634215976Sjmallett uint32_t reserved_26_31 : 6; 5635215976Sjmallett uint32_t header_depth : 10; /**< VC0 Completion Header Queue Depth 5636215976Sjmallett Sets the number of entries in the Completion header queue for 5637215976Sjmallett VC0 when using the segmented-buffer configuration, writable 5638215976Sjmallett through PEM(0..1)_CFG_WR. 5639215976Sjmallett However, the application must not change this field. */ 5640215976Sjmallett uint32_t reserved_14_15 : 2; 5641215976Sjmallett uint32_t data_depth : 14; /**< VC0 Completion Data Queue Depth 5642215976Sjmallett Sets the number of entries in the Completion data queue for VC0 5643215976Sjmallett when using the segmented-buffer configuration, writable 5644215976Sjmallett through PEM(0..1)_CFG_WR. 5645215976Sjmallett However, the application must not change this field. */ 5646215976Sjmallett#else 5647215976Sjmallett uint32_t data_depth : 14; 5648215976Sjmallett uint32_t reserved_14_15 : 2; 5649215976Sjmallett uint32_t header_depth : 10; 5650215976Sjmallett uint32_t reserved_26_31 : 6; 5651215976Sjmallett#endif 5652215976Sjmallett } s; 5653215976Sjmallett struct cvmx_pciercx_cfg492_s cn52xx; 5654215976Sjmallett struct cvmx_pciercx_cfg492_s cn52xxp1; 5655215976Sjmallett struct cvmx_pciercx_cfg492_s cn56xx; 5656215976Sjmallett struct cvmx_pciercx_cfg492_s cn56xxp1; 5657232812Sjmallett struct cvmx_pciercx_cfg492_s cn61xx; 5658215976Sjmallett struct cvmx_pciercx_cfg492_s cn63xx; 5659215976Sjmallett struct cvmx_pciercx_cfg492_s cn63xxp1; 5660232812Sjmallett struct cvmx_pciercx_cfg492_s cn66xx; 5661232812Sjmallett struct cvmx_pciercx_cfg492_s cn68xx; 5662232812Sjmallett struct cvmx_pciercx_cfg492_s cn68xxp1; 5663232812Sjmallett struct cvmx_pciercx_cfg492_s cnf71xx; 5664215976Sjmallett}; 5665215976Sjmalletttypedef union cvmx_pciercx_cfg492 cvmx_pciercx_cfg492_t; 5666215976Sjmallett 5667215976Sjmallett/** 5668215976Sjmallett * cvmx_pcierc#_cfg515 5669215976Sjmallett * 5670215976Sjmallett * PCIE_CFG515 = Five hundred sixteenth 32-bits of PCIE type 1 config space 5671215976Sjmallett * (Port Logic Register (Gen2)) 5672215976Sjmallett */ 5673232812Sjmallettunion cvmx_pciercx_cfg515 { 5674215976Sjmallett uint32_t u32; 5675232812Sjmallett struct cvmx_pciercx_cfg515_s { 5676232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5677215976Sjmallett uint32_t reserved_21_31 : 11; 5678215976Sjmallett uint32_t s_d_e : 1; /**< SEL_DE_EMPHASIS 5679215976Sjmallett Used to set the de-emphasis level for upstream ports. */ 5680215976Sjmallett uint32_t ctcrb : 1; /**< Config Tx Compliance Receive Bit 5681215976Sjmallett When set to 1, signals LTSSM to transmit TS ordered sets 5682215976Sjmallett with the compliance receive bit assert (equal to 1). */ 5683215976Sjmallett uint32_t cpyts : 1; /**< Config PHY Tx Swing 5684215976Sjmallett Indicates the voltage level the PHY should drive. When set to 5685215976Sjmallett 1, indicates Full Swing. When set to 0, indicates Low Swing */ 5686215976Sjmallett uint32_t dsc : 1; /**< Directed Speed Change 5687232812Sjmallett o a write of '1' will initiate a speed change 5688232812Sjmallett o always reads a zero */ 5689215976Sjmallett uint32_t le : 9; /**< Lane Enable 5690215976Sjmallett Indicates the number of lanes to check for exit from electrical 5691215976Sjmallett idle in Polling.Active and Polling.Compliance. 1 = x1, 2 = x2, 5692215976Sjmallett etc. Used to limit the maximum link width to ignore broken 5693215976Sjmallett lanes that detect a receiver, but will not exit electrical 5694215976Sjmallett idle and 5695215976Sjmallett would otherwise prevent a valid link from being configured. */ 5696215976Sjmallett uint32_t n_fts : 8; /**< N_FTS 5697215976Sjmallett Sets the Number of Fast Training Sequences (N_FTS) that 5698215976Sjmallett the core advertises as its N_FTS during GEN2 Link training. 5699215976Sjmallett This value is used to inform the Link partner about the PHYs 5700215976Sjmallett ability to recover synchronization after a low power state. 5701215976Sjmallett Note: Do not set N_FTS to zero; doing so can cause the 5702215976Sjmallett LTSSM to go into the recovery state when exiting from 5703215976Sjmallett L0s. */ 5704215976Sjmallett#else 5705215976Sjmallett uint32_t n_fts : 8; 5706215976Sjmallett uint32_t le : 9; 5707215976Sjmallett uint32_t dsc : 1; 5708215976Sjmallett uint32_t cpyts : 1; 5709215976Sjmallett uint32_t ctcrb : 1; 5710215976Sjmallett uint32_t s_d_e : 1; 5711215976Sjmallett uint32_t reserved_21_31 : 11; 5712215976Sjmallett#endif 5713215976Sjmallett } s; 5714232812Sjmallett struct cvmx_pciercx_cfg515_s cn61xx; 5715215976Sjmallett struct cvmx_pciercx_cfg515_s cn63xx; 5716215976Sjmallett struct cvmx_pciercx_cfg515_s cn63xxp1; 5717232812Sjmallett struct cvmx_pciercx_cfg515_s cn66xx; 5718232812Sjmallett struct cvmx_pciercx_cfg515_s cn68xx; 5719232812Sjmallett struct cvmx_pciercx_cfg515_s cn68xxp1; 5720232812Sjmallett struct cvmx_pciercx_cfg515_s cnf71xx; 5721215976Sjmallett}; 5722215976Sjmalletttypedef union cvmx_pciercx_cfg515 cvmx_pciercx_cfg515_t; 5723215976Sjmallett 5724215976Sjmallett/** 5725215976Sjmallett * cvmx_pcierc#_cfg516 5726215976Sjmallett * 5727215976Sjmallett * PCIE_CFG516 = Five hundred seventeenth 32-bits of PCIE type 1 config space 5728215976Sjmallett * (PHY Status Register) 5729215976Sjmallett */ 5730232812Sjmallettunion cvmx_pciercx_cfg516 { 5731215976Sjmallett uint32_t u32; 5732232812Sjmallett struct cvmx_pciercx_cfg516_s { 5733232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5734215976Sjmallett uint32_t phy_stat : 32; /**< PHY Status */ 5735215976Sjmallett#else 5736215976Sjmallett uint32_t phy_stat : 32; 5737215976Sjmallett#endif 5738215976Sjmallett } s; 5739215976Sjmallett struct cvmx_pciercx_cfg516_s cn52xx; 5740215976Sjmallett struct cvmx_pciercx_cfg516_s cn52xxp1; 5741215976Sjmallett struct cvmx_pciercx_cfg516_s cn56xx; 5742215976Sjmallett struct cvmx_pciercx_cfg516_s cn56xxp1; 5743232812Sjmallett struct cvmx_pciercx_cfg516_s cn61xx; 5744215976Sjmallett struct cvmx_pciercx_cfg516_s cn63xx; 5745215976Sjmallett struct cvmx_pciercx_cfg516_s cn63xxp1; 5746232812Sjmallett struct cvmx_pciercx_cfg516_s cn66xx; 5747232812Sjmallett struct cvmx_pciercx_cfg516_s cn68xx; 5748232812Sjmallett struct cvmx_pciercx_cfg516_s cn68xxp1; 5749232812Sjmallett struct cvmx_pciercx_cfg516_s cnf71xx; 5750215976Sjmallett}; 5751215976Sjmalletttypedef union cvmx_pciercx_cfg516 cvmx_pciercx_cfg516_t; 5752215976Sjmallett 5753215976Sjmallett/** 5754215976Sjmallett * cvmx_pcierc#_cfg517 5755215976Sjmallett * 5756215976Sjmallett * PCIE_CFG517 = Five hundred eighteenth 32-bits of PCIE type 1 config space 5757215976Sjmallett * (PHY Control Register) 5758215976Sjmallett */ 5759232812Sjmallettunion cvmx_pciercx_cfg517 { 5760215976Sjmallett uint32_t u32; 5761232812Sjmallett struct cvmx_pciercx_cfg517_s { 5762232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 5763215976Sjmallett uint32_t phy_ctrl : 32; /**< PHY Control */ 5764215976Sjmallett#else 5765215976Sjmallett uint32_t phy_ctrl : 32; 5766215976Sjmallett#endif 5767215976Sjmallett } s; 5768215976Sjmallett struct cvmx_pciercx_cfg517_s cn52xx; 5769215976Sjmallett struct cvmx_pciercx_cfg517_s cn52xxp1; 5770215976Sjmallett struct cvmx_pciercx_cfg517_s cn56xx; 5771215976Sjmallett struct cvmx_pciercx_cfg517_s cn56xxp1; 5772232812Sjmallett struct cvmx_pciercx_cfg517_s cn61xx; 5773215976Sjmallett struct cvmx_pciercx_cfg517_s cn63xx; 5774215976Sjmallett struct cvmx_pciercx_cfg517_s cn63xxp1; 5775232812Sjmallett struct cvmx_pciercx_cfg517_s cn66xx; 5776232812Sjmallett struct cvmx_pciercx_cfg517_s cn68xx; 5777232812Sjmallett struct cvmx_pciercx_cfg517_s cn68xxp1; 5778232812Sjmallett struct cvmx_pciercx_cfg517_s cnf71xx; 5779215976Sjmallett}; 5780215976Sjmalletttypedef union cvmx_pciercx_cfg517 cvmx_pciercx_cfg517_t; 5781215976Sjmallett 5782215976Sjmallett#endif 5783