1215976Sjmallett/***********************license start*************** 2232812Sjmallett * Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights 3215976Sjmallett * reserved. 4215976Sjmallett * 5215976Sjmallett * 6215976Sjmallett * Redistribution and use in source and binary forms, with or without 7215976Sjmallett * modification, are permitted provided that the following conditions are 8215976Sjmallett * met: 9215976Sjmallett * 10215976Sjmallett * * Redistributions of source code must retain the above copyright 11215976Sjmallett * notice, this list of conditions and the following disclaimer. 12215976Sjmallett * 13215976Sjmallett * * Redistributions in binary form must reproduce the above 14215976Sjmallett * copyright notice, this list of conditions and the following 15215976Sjmallett * disclaimer in the documentation and/or other materials provided 16215976Sjmallett * with the distribution. 17215976Sjmallett 18232812Sjmallett * * Neither the name of Cavium Inc. nor the names of 19215976Sjmallett * its contributors may be used to endorse or promote products 20215976Sjmallett * derived from this software without specific prior written 21215976Sjmallett * permission. 22215976Sjmallett 23215976Sjmallett * This Software, including technical data, may be subject to U.S. export control 24215976Sjmallett * laws, including the U.S. Export Administration Act and its associated 25215976Sjmallett * regulations, and may be subject to export or import regulations in other 26215976Sjmallett * countries. 27215976Sjmallett 28215976Sjmallett * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS" 29232812Sjmallett * AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR 30215976Sjmallett * WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO 31215976Sjmallett * THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR 32215976Sjmallett * DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM 33215976Sjmallett * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE, 34215976Sjmallett * MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF 35215976Sjmallett * VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR 36215976Sjmallett * CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR 37215976Sjmallett * PERFORMANCE OF THE SOFTWARE LIES WITH YOU. 38215976Sjmallett ***********************license end**************************************/ 39215976Sjmallett 40215976Sjmallett 41215976Sjmallett/** 42215976Sjmallett * cvmx-npi-defs.h 43215976Sjmallett * 44215976Sjmallett * Configuration and status register (CSR) type definitions for 45215976Sjmallett * Octeon npi. 46215976Sjmallett * 47215976Sjmallett * This file is auto generated. Do not edit. 48215976Sjmallett * 49215976Sjmallett * <hr>$Revision$<hr> 50215976Sjmallett * 51215976Sjmallett */ 52232812Sjmallett#ifndef __CVMX_NPI_DEFS_H__ 53232812Sjmallett#define __CVMX_NPI_DEFS_H__ 54215976Sjmallett 55215976Sjmallett#define CVMX_NPI_BASE_ADDR_INPUT0 CVMX_NPI_BASE_ADDR_INPUTX(0) 56215976Sjmallett#define CVMX_NPI_BASE_ADDR_INPUT1 CVMX_NPI_BASE_ADDR_INPUTX(1) 57215976Sjmallett#define CVMX_NPI_BASE_ADDR_INPUT2 CVMX_NPI_BASE_ADDR_INPUTX(2) 58215976Sjmallett#define CVMX_NPI_BASE_ADDR_INPUT3 CVMX_NPI_BASE_ADDR_INPUTX(3) 59215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 60215976Sjmallettstatic inline uint64_t CVMX_NPI_BASE_ADDR_INPUTX(unsigned long offset) 61215976Sjmallett{ 62215976Sjmallett if (!( 63215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 64215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 65215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 66215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 67215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 68215976Sjmallett cvmx_warn("CVMX_NPI_BASE_ADDR_INPUTX(%lu) is invalid on this chip\n", offset); 69215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000000070ull) + ((offset) & 3) * 16; 70215976Sjmallett} 71215976Sjmallett#else 72215976Sjmallett#define CVMX_NPI_BASE_ADDR_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000070ull) + ((offset) & 3) * 16) 73215976Sjmallett#endif 74215976Sjmallett#define CVMX_NPI_BASE_ADDR_OUTPUT0 CVMX_NPI_BASE_ADDR_OUTPUTX(0) 75215976Sjmallett#define CVMX_NPI_BASE_ADDR_OUTPUT1 CVMX_NPI_BASE_ADDR_OUTPUTX(1) 76215976Sjmallett#define CVMX_NPI_BASE_ADDR_OUTPUT2 CVMX_NPI_BASE_ADDR_OUTPUTX(2) 77215976Sjmallett#define CVMX_NPI_BASE_ADDR_OUTPUT3 CVMX_NPI_BASE_ADDR_OUTPUTX(3) 78215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 79215976Sjmallettstatic inline uint64_t CVMX_NPI_BASE_ADDR_OUTPUTX(unsigned long offset) 80215976Sjmallett{ 81215976Sjmallett if (!( 82215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 83215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 84215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 85215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 86215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 87215976Sjmallett cvmx_warn("CVMX_NPI_BASE_ADDR_OUTPUTX(%lu) is invalid on this chip\n", offset); 88215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000000B8ull) + ((offset) & 3) * 8; 89215976Sjmallett} 90215976Sjmallett#else 91215976Sjmallett#define CVMX_NPI_BASE_ADDR_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000B8ull) + ((offset) & 3) * 8) 92215976Sjmallett#endif 93215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 94215976Sjmallett#define CVMX_NPI_BIST_STATUS CVMX_NPI_BIST_STATUS_FUNC() 95215976Sjmallettstatic inline uint64_t CVMX_NPI_BIST_STATUS_FUNC(void) 96215976Sjmallett{ 97215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 98215976Sjmallett cvmx_warn("CVMX_NPI_BIST_STATUS not supported on this chip\n"); 99215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000003F8ull); 100215976Sjmallett} 101215976Sjmallett#else 102215976Sjmallett#define CVMX_NPI_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011F00000003F8ull)) 103215976Sjmallett#endif 104215976Sjmallett#define CVMX_NPI_BUFF_SIZE_OUTPUT0 CVMX_NPI_BUFF_SIZE_OUTPUTX(0) 105215976Sjmallett#define CVMX_NPI_BUFF_SIZE_OUTPUT1 CVMX_NPI_BUFF_SIZE_OUTPUTX(1) 106215976Sjmallett#define CVMX_NPI_BUFF_SIZE_OUTPUT2 CVMX_NPI_BUFF_SIZE_OUTPUTX(2) 107215976Sjmallett#define CVMX_NPI_BUFF_SIZE_OUTPUT3 CVMX_NPI_BUFF_SIZE_OUTPUTX(3) 108215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 109215976Sjmallettstatic inline uint64_t CVMX_NPI_BUFF_SIZE_OUTPUTX(unsigned long offset) 110215976Sjmallett{ 111215976Sjmallett if (!( 112215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 113215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 114215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 115215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 116215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 117215976Sjmallett cvmx_warn("CVMX_NPI_BUFF_SIZE_OUTPUTX(%lu) is invalid on this chip\n", offset); 118215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000000E0ull) + ((offset) & 3) * 8; 119215976Sjmallett} 120215976Sjmallett#else 121215976Sjmallett#define CVMX_NPI_BUFF_SIZE_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F00000000E0ull) + ((offset) & 3) * 8) 122215976Sjmallett#endif 123215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 124215976Sjmallett#define CVMX_NPI_COMP_CTL CVMX_NPI_COMP_CTL_FUNC() 125215976Sjmallettstatic inline uint64_t CVMX_NPI_COMP_CTL_FUNC(void) 126215976Sjmallett{ 127215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 128215976Sjmallett cvmx_warn("CVMX_NPI_COMP_CTL not supported on this chip\n"); 129215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000000218ull); 130215976Sjmallett} 131215976Sjmallett#else 132215976Sjmallett#define CVMX_NPI_COMP_CTL (CVMX_ADD_IO_SEG(0x00011F0000000218ull)) 133215976Sjmallett#endif 134215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 135215976Sjmallett#define CVMX_NPI_CTL_STATUS CVMX_NPI_CTL_STATUS_FUNC() 136215976Sjmallettstatic inline uint64_t CVMX_NPI_CTL_STATUS_FUNC(void) 137215976Sjmallett{ 138215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 139215976Sjmallett cvmx_warn("CVMX_NPI_CTL_STATUS not supported on this chip\n"); 140215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000000010ull); 141215976Sjmallett} 142215976Sjmallett#else 143215976Sjmallett#define CVMX_NPI_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011F0000000010ull)) 144215976Sjmallett#endif 145215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 146215976Sjmallett#define CVMX_NPI_DBG_SELECT CVMX_NPI_DBG_SELECT_FUNC() 147215976Sjmallettstatic inline uint64_t CVMX_NPI_DBG_SELECT_FUNC(void) 148215976Sjmallett{ 149215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 150215976Sjmallett cvmx_warn("CVMX_NPI_DBG_SELECT not supported on this chip\n"); 151215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000000008ull); 152215976Sjmallett} 153215976Sjmallett#else 154215976Sjmallett#define CVMX_NPI_DBG_SELECT (CVMX_ADD_IO_SEG(0x00011F0000000008ull)) 155215976Sjmallett#endif 156215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 157215976Sjmallett#define CVMX_NPI_DMA_CONTROL CVMX_NPI_DMA_CONTROL_FUNC() 158215976Sjmallettstatic inline uint64_t CVMX_NPI_DMA_CONTROL_FUNC(void) 159215976Sjmallett{ 160215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 161215976Sjmallett cvmx_warn("CVMX_NPI_DMA_CONTROL not supported on this chip\n"); 162215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000000128ull); 163215976Sjmallett} 164215976Sjmallett#else 165215976Sjmallett#define CVMX_NPI_DMA_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000128ull)) 166215976Sjmallett#endif 167215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 168215976Sjmallett#define CVMX_NPI_DMA_HIGHP_COUNTS CVMX_NPI_DMA_HIGHP_COUNTS_FUNC() 169215976Sjmallettstatic inline uint64_t CVMX_NPI_DMA_HIGHP_COUNTS_FUNC(void) 170215976Sjmallett{ 171215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 172215976Sjmallett cvmx_warn("CVMX_NPI_DMA_HIGHP_COUNTS not supported on this chip\n"); 173215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000000148ull); 174215976Sjmallett} 175215976Sjmallett#else 176215976Sjmallett#define CVMX_NPI_DMA_HIGHP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000148ull)) 177215976Sjmallett#endif 178215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 179215976Sjmallett#define CVMX_NPI_DMA_HIGHP_NADDR CVMX_NPI_DMA_HIGHP_NADDR_FUNC() 180215976Sjmallettstatic inline uint64_t CVMX_NPI_DMA_HIGHP_NADDR_FUNC(void) 181215976Sjmallett{ 182215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 183215976Sjmallett cvmx_warn("CVMX_NPI_DMA_HIGHP_NADDR not supported on this chip\n"); 184215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000000158ull); 185215976Sjmallett} 186215976Sjmallett#else 187215976Sjmallett#define CVMX_NPI_DMA_HIGHP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000158ull)) 188215976Sjmallett#endif 189215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 190215976Sjmallett#define CVMX_NPI_DMA_LOWP_COUNTS CVMX_NPI_DMA_LOWP_COUNTS_FUNC() 191215976Sjmallettstatic inline uint64_t CVMX_NPI_DMA_LOWP_COUNTS_FUNC(void) 192215976Sjmallett{ 193215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 194215976Sjmallett cvmx_warn("CVMX_NPI_DMA_LOWP_COUNTS not supported on this chip\n"); 195215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000000140ull); 196215976Sjmallett} 197215976Sjmallett#else 198215976Sjmallett#define CVMX_NPI_DMA_LOWP_COUNTS (CVMX_ADD_IO_SEG(0x00011F0000000140ull)) 199215976Sjmallett#endif 200215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 201215976Sjmallett#define CVMX_NPI_DMA_LOWP_NADDR CVMX_NPI_DMA_LOWP_NADDR_FUNC() 202215976Sjmallettstatic inline uint64_t CVMX_NPI_DMA_LOWP_NADDR_FUNC(void) 203215976Sjmallett{ 204215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 205215976Sjmallett cvmx_warn("CVMX_NPI_DMA_LOWP_NADDR not supported on this chip\n"); 206215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000000150ull); 207215976Sjmallett} 208215976Sjmallett#else 209215976Sjmallett#define CVMX_NPI_DMA_LOWP_NADDR (CVMX_ADD_IO_SEG(0x00011F0000000150ull)) 210215976Sjmallett#endif 211215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 212215976Sjmallett#define CVMX_NPI_HIGHP_DBELL CVMX_NPI_HIGHP_DBELL_FUNC() 213215976Sjmallettstatic inline uint64_t CVMX_NPI_HIGHP_DBELL_FUNC(void) 214215976Sjmallett{ 215215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 216215976Sjmallett cvmx_warn("CVMX_NPI_HIGHP_DBELL not supported on this chip\n"); 217215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000000120ull); 218215976Sjmallett} 219215976Sjmallett#else 220215976Sjmallett#define CVMX_NPI_HIGHP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000120ull)) 221215976Sjmallett#endif 222215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 223215976Sjmallett#define CVMX_NPI_HIGHP_IBUFF_SADDR CVMX_NPI_HIGHP_IBUFF_SADDR_FUNC() 224215976Sjmallettstatic inline uint64_t CVMX_NPI_HIGHP_IBUFF_SADDR_FUNC(void) 225215976Sjmallett{ 226215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 227215976Sjmallett cvmx_warn("CVMX_NPI_HIGHP_IBUFF_SADDR not supported on this chip\n"); 228215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000000110ull); 229215976Sjmallett} 230215976Sjmallett#else 231215976Sjmallett#define CVMX_NPI_HIGHP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000110ull)) 232215976Sjmallett#endif 233215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 234215976Sjmallett#define CVMX_NPI_INPUT_CONTROL CVMX_NPI_INPUT_CONTROL_FUNC() 235215976Sjmallettstatic inline uint64_t CVMX_NPI_INPUT_CONTROL_FUNC(void) 236215976Sjmallett{ 237215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 238215976Sjmallett cvmx_warn("CVMX_NPI_INPUT_CONTROL not supported on this chip\n"); 239215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000000138ull); 240215976Sjmallett} 241215976Sjmallett#else 242215976Sjmallett#define CVMX_NPI_INPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000138ull)) 243215976Sjmallett#endif 244215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 245215976Sjmallett#define CVMX_NPI_INT_ENB CVMX_NPI_INT_ENB_FUNC() 246215976Sjmallettstatic inline uint64_t CVMX_NPI_INT_ENB_FUNC(void) 247215976Sjmallett{ 248215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 249215976Sjmallett cvmx_warn("CVMX_NPI_INT_ENB not supported on this chip\n"); 250215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000000020ull); 251215976Sjmallett} 252215976Sjmallett#else 253215976Sjmallett#define CVMX_NPI_INT_ENB (CVMX_ADD_IO_SEG(0x00011F0000000020ull)) 254215976Sjmallett#endif 255215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 256215976Sjmallett#define CVMX_NPI_INT_SUM CVMX_NPI_INT_SUM_FUNC() 257215976Sjmallettstatic inline uint64_t CVMX_NPI_INT_SUM_FUNC(void) 258215976Sjmallett{ 259215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 260215976Sjmallett cvmx_warn("CVMX_NPI_INT_SUM not supported on this chip\n"); 261215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000000018ull); 262215976Sjmallett} 263215976Sjmallett#else 264215976Sjmallett#define CVMX_NPI_INT_SUM (CVMX_ADD_IO_SEG(0x00011F0000000018ull)) 265215976Sjmallett#endif 266215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 267215976Sjmallett#define CVMX_NPI_LOWP_DBELL CVMX_NPI_LOWP_DBELL_FUNC() 268215976Sjmallettstatic inline uint64_t CVMX_NPI_LOWP_DBELL_FUNC(void) 269215976Sjmallett{ 270215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 271215976Sjmallett cvmx_warn("CVMX_NPI_LOWP_DBELL not supported on this chip\n"); 272215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000000118ull); 273215976Sjmallett} 274215976Sjmallett#else 275215976Sjmallett#define CVMX_NPI_LOWP_DBELL (CVMX_ADD_IO_SEG(0x00011F0000000118ull)) 276215976Sjmallett#endif 277215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 278215976Sjmallett#define CVMX_NPI_LOWP_IBUFF_SADDR CVMX_NPI_LOWP_IBUFF_SADDR_FUNC() 279215976Sjmallettstatic inline uint64_t CVMX_NPI_LOWP_IBUFF_SADDR_FUNC(void) 280215976Sjmallett{ 281215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 282215976Sjmallett cvmx_warn("CVMX_NPI_LOWP_IBUFF_SADDR not supported on this chip\n"); 283215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000000108ull); 284215976Sjmallett} 285215976Sjmallett#else 286215976Sjmallett#define CVMX_NPI_LOWP_IBUFF_SADDR (CVMX_ADD_IO_SEG(0x00011F0000000108ull)) 287215976Sjmallett#endif 288215976Sjmallett#define CVMX_NPI_MEM_ACCESS_SUBID3 CVMX_NPI_MEM_ACCESS_SUBIDX(3) 289215976Sjmallett#define CVMX_NPI_MEM_ACCESS_SUBID4 CVMX_NPI_MEM_ACCESS_SUBIDX(4) 290215976Sjmallett#define CVMX_NPI_MEM_ACCESS_SUBID5 CVMX_NPI_MEM_ACCESS_SUBIDX(5) 291215976Sjmallett#define CVMX_NPI_MEM_ACCESS_SUBID6 CVMX_NPI_MEM_ACCESS_SUBIDX(6) 292215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 293215976Sjmallettstatic inline uint64_t CVMX_NPI_MEM_ACCESS_SUBIDX(unsigned long offset) 294215976Sjmallett{ 295215976Sjmallett if (!( 296215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && (((offset >= 3) && (offset <= 6)))) || 297215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && (((offset >= 3) && (offset <= 6)))) || 298215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && (((offset >= 3) && (offset <= 6)))) || 299215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && (((offset >= 3) && (offset <= 6)))) || 300215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && (((offset >= 3) && (offset <= 6)))))) 301215976Sjmallett cvmx_warn("CVMX_NPI_MEM_ACCESS_SUBIDX(%lu) is invalid on this chip\n", offset); 302215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000000028ull) + ((offset) & 7) * 8 - 8*3; 303215976Sjmallett} 304215976Sjmallett#else 305215976Sjmallett#define CVMX_NPI_MEM_ACCESS_SUBIDX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000028ull) + ((offset) & 7) * 8 - 8*3) 306215976Sjmallett#endif 307215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 308215976Sjmallett#define CVMX_NPI_MSI_RCV CVMX_NPI_MSI_RCV_FUNC() 309215976Sjmallettstatic inline uint64_t CVMX_NPI_MSI_RCV_FUNC(void) 310215976Sjmallett{ 311215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 312215976Sjmallett cvmx_warn("CVMX_NPI_MSI_RCV not supported on this chip\n"); 313215976Sjmallett return 0x0000000000000190ull; 314215976Sjmallett} 315215976Sjmallett#else 316215976Sjmallett#define CVMX_NPI_MSI_RCV (0x0000000000000190ull) 317215976Sjmallett#endif 318215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 319215976Sjmallett#define CVMX_NPI_NPI_MSI_RCV CVMX_NPI_NPI_MSI_RCV_FUNC() 320215976Sjmallettstatic inline uint64_t CVMX_NPI_NPI_MSI_RCV_FUNC(void) 321215976Sjmallett{ 322215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 323215976Sjmallett cvmx_warn("CVMX_NPI_NPI_MSI_RCV not supported on this chip\n"); 324215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000001190ull); 325215976Sjmallett} 326215976Sjmallett#else 327215976Sjmallett#define CVMX_NPI_NPI_MSI_RCV (CVMX_ADD_IO_SEG(0x00011F0000001190ull)) 328215976Sjmallett#endif 329215976Sjmallett#define CVMX_NPI_NUM_DESC_OUTPUT0 CVMX_NPI_NUM_DESC_OUTPUTX(0) 330215976Sjmallett#define CVMX_NPI_NUM_DESC_OUTPUT1 CVMX_NPI_NUM_DESC_OUTPUTX(1) 331215976Sjmallett#define CVMX_NPI_NUM_DESC_OUTPUT2 CVMX_NPI_NUM_DESC_OUTPUTX(2) 332215976Sjmallett#define CVMX_NPI_NUM_DESC_OUTPUT3 CVMX_NPI_NUM_DESC_OUTPUTX(3) 333215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 334215976Sjmallettstatic inline uint64_t CVMX_NPI_NUM_DESC_OUTPUTX(unsigned long offset) 335215976Sjmallett{ 336215976Sjmallett if (!( 337215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 338215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 339215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 340215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 341215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 342215976Sjmallett cvmx_warn("CVMX_NPI_NUM_DESC_OUTPUTX(%lu) is invalid on this chip\n", offset); 343215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000000050ull) + ((offset) & 3) * 8; 344215976Sjmallett} 345215976Sjmallett#else 346215976Sjmallett#define CVMX_NPI_NUM_DESC_OUTPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000050ull) + ((offset) & 3) * 8) 347215976Sjmallett#endif 348215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 349215976Sjmallett#define CVMX_NPI_OUTPUT_CONTROL CVMX_NPI_OUTPUT_CONTROL_FUNC() 350215976Sjmallettstatic inline uint64_t CVMX_NPI_OUTPUT_CONTROL_FUNC(void) 351215976Sjmallett{ 352215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 353215976Sjmallett cvmx_warn("CVMX_NPI_OUTPUT_CONTROL not supported on this chip\n"); 354215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000000100ull); 355215976Sjmallett} 356215976Sjmallett#else 357215976Sjmallett#define CVMX_NPI_OUTPUT_CONTROL (CVMX_ADD_IO_SEG(0x00011F0000000100ull)) 358215976Sjmallett#endif 359215976Sjmallett#define CVMX_NPI_P0_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(0) 360215976Sjmallett#define CVMX_NPI_P0_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(0) 361215976Sjmallett#define CVMX_NPI_P0_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(0) 362215976Sjmallett#define CVMX_NPI_P0_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(0) 363215976Sjmallett#define CVMX_NPI_P1_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(1) 364215976Sjmallett#define CVMX_NPI_P1_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(1) 365215976Sjmallett#define CVMX_NPI_P1_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(1) 366215976Sjmallett#define CVMX_NPI_P1_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(1) 367215976Sjmallett#define CVMX_NPI_P2_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(2) 368215976Sjmallett#define CVMX_NPI_P2_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(2) 369215976Sjmallett#define CVMX_NPI_P2_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(2) 370215976Sjmallett#define CVMX_NPI_P2_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(2) 371215976Sjmallett#define CVMX_NPI_P3_DBPAIR_ADDR CVMX_NPI_PX_DBPAIR_ADDR(3) 372215976Sjmallett#define CVMX_NPI_P3_INSTR_ADDR CVMX_NPI_PX_INSTR_ADDR(3) 373215976Sjmallett#define CVMX_NPI_P3_INSTR_CNTS CVMX_NPI_PX_INSTR_CNTS(3) 374215976Sjmallett#define CVMX_NPI_P3_PAIR_CNTS CVMX_NPI_PX_PAIR_CNTS(3) 375215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 376215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_BAR1_INDEXX(unsigned long offset) 377215976Sjmallett{ 378215976Sjmallett if (!( 379215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 31))) || 380215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 31))) || 381215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 31))) || 382215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 31))) || 383215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 31))))) 384215976Sjmallett cvmx_warn("CVMX_NPI_PCI_BAR1_INDEXX(%lu) is invalid on this chip\n", offset); 385215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000001100ull) + ((offset) & 31) * 4; 386215976Sjmallett} 387215976Sjmallett#else 388215976Sjmallett#define CVMX_NPI_PCI_BAR1_INDEXX(offset) (CVMX_ADD_IO_SEG(0x00011F0000001100ull) + ((offset) & 31) * 4) 389215976Sjmallett#endif 390215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 391215976Sjmallett#define CVMX_NPI_PCI_BIST_REG CVMX_NPI_PCI_BIST_REG_FUNC() 392215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_BIST_REG_FUNC(void) 393215976Sjmallett{ 394215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN50XX))) 395215976Sjmallett cvmx_warn("CVMX_NPI_PCI_BIST_REG not supported on this chip\n"); 396215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000011C0ull); 397215976Sjmallett} 398215976Sjmallett#else 399215976Sjmallett#define CVMX_NPI_PCI_BIST_REG (CVMX_ADD_IO_SEG(0x00011F00000011C0ull)) 400215976Sjmallett#endif 401215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 402215976Sjmallett#define CVMX_NPI_PCI_BURST_SIZE CVMX_NPI_PCI_BURST_SIZE_FUNC() 403215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_BURST_SIZE_FUNC(void) 404215976Sjmallett{ 405215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 406215976Sjmallett cvmx_warn("CVMX_NPI_PCI_BURST_SIZE not supported on this chip\n"); 407215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000000D8ull); 408215976Sjmallett} 409215976Sjmallett#else 410215976Sjmallett#define CVMX_NPI_PCI_BURST_SIZE (CVMX_ADD_IO_SEG(0x00011F00000000D8ull)) 411215976Sjmallett#endif 412215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 413215976Sjmallett#define CVMX_NPI_PCI_CFG00 CVMX_NPI_PCI_CFG00_FUNC() 414215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_CFG00_FUNC(void) 415215976Sjmallett{ 416215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 417215976Sjmallett cvmx_warn("CVMX_NPI_PCI_CFG00 not supported on this chip\n"); 418215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000001800ull); 419215976Sjmallett} 420215976Sjmallett#else 421215976Sjmallett#define CVMX_NPI_PCI_CFG00 (CVMX_ADD_IO_SEG(0x00011F0000001800ull)) 422215976Sjmallett#endif 423215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 424215976Sjmallett#define CVMX_NPI_PCI_CFG01 CVMX_NPI_PCI_CFG01_FUNC() 425215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_CFG01_FUNC(void) 426215976Sjmallett{ 427215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 428215976Sjmallett cvmx_warn("CVMX_NPI_PCI_CFG01 not supported on this chip\n"); 429215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000001804ull); 430215976Sjmallett} 431215976Sjmallett#else 432215976Sjmallett#define CVMX_NPI_PCI_CFG01 (CVMX_ADD_IO_SEG(0x00011F0000001804ull)) 433215976Sjmallett#endif 434215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 435215976Sjmallett#define CVMX_NPI_PCI_CFG02 CVMX_NPI_PCI_CFG02_FUNC() 436215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_CFG02_FUNC(void) 437215976Sjmallett{ 438215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 439215976Sjmallett cvmx_warn("CVMX_NPI_PCI_CFG02 not supported on this chip\n"); 440215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000001808ull); 441215976Sjmallett} 442215976Sjmallett#else 443215976Sjmallett#define CVMX_NPI_PCI_CFG02 (CVMX_ADD_IO_SEG(0x00011F0000001808ull)) 444215976Sjmallett#endif 445215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 446215976Sjmallett#define CVMX_NPI_PCI_CFG03 CVMX_NPI_PCI_CFG03_FUNC() 447215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_CFG03_FUNC(void) 448215976Sjmallett{ 449215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 450215976Sjmallett cvmx_warn("CVMX_NPI_PCI_CFG03 not supported on this chip\n"); 451215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000180Cull); 452215976Sjmallett} 453215976Sjmallett#else 454215976Sjmallett#define CVMX_NPI_PCI_CFG03 (CVMX_ADD_IO_SEG(0x00011F000000180Cull)) 455215976Sjmallett#endif 456215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 457215976Sjmallett#define CVMX_NPI_PCI_CFG04 CVMX_NPI_PCI_CFG04_FUNC() 458215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_CFG04_FUNC(void) 459215976Sjmallett{ 460215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 461215976Sjmallett cvmx_warn("CVMX_NPI_PCI_CFG04 not supported on this chip\n"); 462215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000001810ull); 463215976Sjmallett} 464215976Sjmallett#else 465215976Sjmallett#define CVMX_NPI_PCI_CFG04 (CVMX_ADD_IO_SEG(0x00011F0000001810ull)) 466215976Sjmallett#endif 467215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 468215976Sjmallett#define CVMX_NPI_PCI_CFG05 CVMX_NPI_PCI_CFG05_FUNC() 469215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_CFG05_FUNC(void) 470215976Sjmallett{ 471215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 472215976Sjmallett cvmx_warn("CVMX_NPI_PCI_CFG05 not supported on this chip\n"); 473215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000001814ull); 474215976Sjmallett} 475215976Sjmallett#else 476215976Sjmallett#define CVMX_NPI_PCI_CFG05 (CVMX_ADD_IO_SEG(0x00011F0000001814ull)) 477215976Sjmallett#endif 478215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 479215976Sjmallett#define CVMX_NPI_PCI_CFG06 CVMX_NPI_PCI_CFG06_FUNC() 480215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_CFG06_FUNC(void) 481215976Sjmallett{ 482215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 483215976Sjmallett cvmx_warn("CVMX_NPI_PCI_CFG06 not supported on this chip\n"); 484215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000001818ull); 485215976Sjmallett} 486215976Sjmallett#else 487215976Sjmallett#define CVMX_NPI_PCI_CFG06 (CVMX_ADD_IO_SEG(0x00011F0000001818ull)) 488215976Sjmallett#endif 489215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 490215976Sjmallett#define CVMX_NPI_PCI_CFG07 CVMX_NPI_PCI_CFG07_FUNC() 491215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_CFG07_FUNC(void) 492215976Sjmallett{ 493215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 494215976Sjmallett cvmx_warn("CVMX_NPI_PCI_CFG07 not supported on this chip\n"); 495215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000181Cull); 496215976Sjmallett} 497215976Sjmallett#else 498215976Sjmallett#define CVMX_NPI_PCI_CFG07 (CVMX_ADD_IO_SEG(0x00011F000000181Cull)) 499215976Sjmallett#endif 500215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 501215976Sjmallett#define CVMX_NPI_PCI_CFG08 CVMX_NPI_PCI_CFG08_FUNC() 502215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_CFG08_FUNC(void) 503215976Sjmallett{ 504215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 505215976Sjmallett cvmx_warn("CVMX_NPI_PCI_CFG08 not supported on this chip\n"); 506215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000001820ull); 507215976Sjmallett} 508215976Sjmallett#else 509215976Sjmallett#define CVMX_NPI_PCI_CFG08 (CVMX_ADD_IO_SEG(0x00011F0000001820ull)) 510215976Sjmallett#endif 511215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 512215976Sjmallett#define CVMX_NPI_PCI_CFG09 CVMX_NPI_PCI_CFG09_FUNC() 513215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_CFG09_FUNC(void) 514215976Sjmallett{ 515215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 516215976Sjmallett cvmx_warn("CVMX_NPI_PCI_CFG09 not supported on this chip\n"); 517215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000001824ull); 518215976Sjmallett} 519215976Sjmallett#else 520215976Sjmallett#define CVMX_NPI_PCI_CFG09 (CVMX_ADD_IO_SEG(0x00011F0000001824ull)) 521215976Sjmallett#endif 522215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 523215976Sjmallett#define CVMX_NPI_PCI_CFG10 CVMX_NPI_PCI_CFG10_FUNC() 524215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_CFG10_FUNC(void) 525215976Sjmallett{ 526215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 527215976Sjmallett cvmx_warn("CVMX_NPI_PCI_CFG10 not supported on this chip\n"); 528215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000001828ull); 529215976Sjmallett} 530215976Sjmallett#else 531215976Sjmallett#define CVMX_NPI_PCI_CFG10 (CVMX_ADD_IO_SEG(0x00011F0000001828ull)) 532215976Sjmallett#endif 533215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 534215976Sjmallett#define CVMX_NPI_PCI_CFG11 CVMX_NPI_PCI_CFG11_FUNC() 535215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_CFG11_FUNC(void) 536215976Sjmallett{ 537215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 538215976Sjmallett cvmx_warn("CVMX_NPI_PCI_CFG11 not supported on this chip\n"); 539215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000182Cull); 540215976Sjmallett} 541215976Sjmallett#else 542215976Sjmallett#define CVMX_NPI_PCI_CFG11 (CVMX_ADD_IO_SEG(0x00011F000000182Cull)) 543215976Sjmallett#endif 544215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 545215976Sjmallett#define CVMX_NPI_PCI_CFG12 CVMX_NPI_PCI_CFG12_FUNC() 546215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_CFG12_FUNC(void) 547215976Sjmallett{ 548215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 549215976Sjmallett cvmx_warn("CVMX_NPI_PCI_CFG12 not supported on this chip\n"); 550215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000001830ull); 551215976Sjmallett} 552215976Sjmallett#else 553215976Sjmallett#define CVMX_NPI_PCI_CFG12 (CVMX_ADD_IO_SEG(0x00011F0000001830ull)) 554215976Sjmallett#endif 555215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 556215976Sjmallett#define CVMX_NPI_PCI_CFG13 CVMX_NPI_PCI_CFG13_FUNC() 557215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_CFG13_FUNC(void) 558215976Sjmallett{ 559215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 560215976Sjmallett cvmx_warn("CVMX_NPI_PCI_CFG13 not supported on this chip\n"); 561215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000001834ull); 562215976Sjmallett} 563215976Sjmallett#else 564215976Sjmallett#define CVMX_NPI_PCI_CFG13 (CVMX_ADD_IO_SEG(0x00011F0000001834ull)) 565215976Sjmallett#endif 566215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 567215976Sjmallett#define CVMX_NPI_PCI_CFG15 CVMX_NPI_PCI_CFG15_FUNC() 568215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_CFG15_FUNC(void) 569215976Sjmallett{ 570215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 571215976Sjmallett cvmx_warn("CVMX_NPI_PCI_CFG15 not supported on this chip\n"); 572215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000183Cull); 573215976Sjmallett} 574215976Sjmallett#else 575215976Sjmallett#define CVMX_NPI_PCI_CFG15 (CVMX_ADD_IO_SEG(0x00011F000000183Cull)) 576215976Sjmallett#endif 577215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 578215976Sjmallett#define CVMX_NPI_PCI_CFG16 CVMX_NPI_PCI_CFG16_FUNC() 579215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_CFG16_FUNC(void) 580215976Sjmallett{ 581215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 582215976Sjmallett cvmx_warn("CVMX_NPI_PCI_CFG16 not supported on this chip\n"); 583215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000001840ull); 584215976Sjmallett} 585215976Sjmallett#else 586215976Sjmallett#define CVMX_NPI_PCI_CFG16 (CVMX_ADD_IO_SEG(0x00011F0000001840ull)) 587215976Sjmallett#endif 588215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 589215976Sjmallett#define CVMX_NPI_PCI_CFG17 CVMX_NPI_PCI_CFG17_FUNC() 590215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_CFG17_FUNC(void) 591215976Sjmallett{ 592215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 593215976Sjmallett cvmx_warn("CVMX_NPI_PCI_CFG17 not supported on this chip\n"); 594215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000001844ull); 595215976Sjmallett} 596215976Sjmallett#else 597215976Sjmallett#define CVMX_NPI_PCI_CFG17 (CVMX_ADD_IO_SEG(0x00011F0000001844ull)) 598215976Sjmallett#endif 599215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 600215976Sjmallett#define CVMX_NPI_PCI_CFG18 CVMX_NPI_PCI_CFG18_FUNC() 601215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_CFG18_FUNC(void) 602215976Sjmallett{ 603215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 604215976Sjmallett cvmx_warn("CVMX_NPI_PCI_CFG18 not supported on this chip\n"); 605215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000001848ull); 606215976Sjmallett} 607215976Sjmallett#else 608215976Sjmallett#define CVMX_NPI_PCI_CFG18 (CVMX_ADD_IO_SEG(0x00011F0000001848ull)) 609215976Sjmallett#endif 610215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 611215976Sjmallett#define CVMX_NPI_PCI_CFG19 CVMX_NPI_PCI_CFG19_FUNC() 612215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_CFG19_FUNC(void) 613215976Sjmallett{ 614215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 615215976Sjmallett cvmx_warn("CVMX_NPI_PCI_CFG19 not supported on this chip\n"); 616215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000184Cull); 617215976Sjmallett} 618215976Sjmallett#else 619215976Sjmallett#define CVMX_NPI_PCI_CFG19 (CVMX_ADD_IO_SEG(0x00011F000000184Cull)) 620215976Sjmallett#endif 621215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 622215976Sjmallett#define CVMX_NPI_PCI_CFG20 CVMX_NPI_PCI_CFG20_FUNC() 623215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_CFG20_FUNC(void) 624215976Sjmallett{ 625215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 626215976Sjmallett cvmx_warn("CVMX_NPI_PCI_CFG20 not supported on this chip\n"); 627215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000001850ull); 628215976Sjmallett} 629215976Sjmallett#else 630215976Sjmallett#define CVMX_NPI_PCI_CFG20 (CVMX_ADD_IO_SEG(0x00011F0000001850ull)) 631215976Sjmallett#endif 632215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 633215976Sjmallett#define CVMX_NPI_PCI_CFG21 CVMX_NPI_PCI_CFG21_FUNC() 634215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_CFG21_FUNC(void) 635215976Sjmallett{ 636215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 637215976Sjmallett cvmx_warn("CVMX_NPI_PCI_CFG21 not supported on this chip\n"); 638215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000001854ull); 639215976Sjmallett} 640215976Sjmallett#else 641215976Sjmallett#define CVMX_NPI_PCI_CFG21 (CVMX_ADD_IO_SEG(0x00011F0000001854ull)) 642215976Sjmallett#endif 643215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 644215976Sjmallett#define CVMX_NPI_PCI_CFG22 CVMX_NPI_PCI_CFG22_FUNC() 645215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_CFG22_FUNC(void) 646215976Sjmallett{ 647215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 648215976Sjmallett cvmx_warn("CVMX_NPI_PCI_CFG22 not supported on this chip\n"); 649215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000001858ull); 650215976Sjmallett} 651215976Sjmallett#else 652215976Sjmallett#define CVMX_NPI_PCI_CFG22 (CVMX_ADD_IO_SEG(0x00011F0000001858ull)) 653215976Sjmallett#endif 654215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 655215976Sjmallett#define CVMX_NPI_PCI_CFG56 CVMX_NPI_PCI_CFG56_FUNC() 656215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_CFG56_FUNC(void) 657215976Sjmallett{ 658215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 659215976Sjmallett cvmx_warn("CVMX_NPI_PCI_CFG56 not supported on this chip\n"); 660215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000018E0ull); 661215976Sjmallett} 662215976Sjmallett#else 663215976Sjmallett#define CVMX_NPI_PCI_CFG56 (CVMX_ADD_IO_SEG(0x00011F00000018E0ull)) 664215976Sjmallett#endif 665215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 666215976Sjmallett#define CVMX_NPI_PCI_CFG57 CVMX_NPI_PCI_CFG57_FUNC() 667215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_CFG57_FUNC(void) 668215976Sjmallett{ 669215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 670215976Sjmallett cvmx_warn("CVMX_NPI_PCI_CFG57 not supported on this chip\n"); 671215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000018E4ull); 672215976Sjmallett} 673215976Sjmallett#else 674215976Sjmallett#define CVMX_NPI_PCI_CFG57 (CVMX_ADD_IO_SEG(0x00011F00000018E4ull)) 675215976Sjmallett#endif 676215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 677215976Sjmallett#define CVMX_NPI_PCI_CFG58 CVMX_NPI_PCI_CFG58_FUNC() 678215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_CFG58_FUNC(void) 679215976Sjmallett{ 680215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 681215976Sjmallett cvmx_warn("CVMX_NPI_PCI_CFG58 not supported on this chip\n"); 682215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000018E8ull); 683215976Sjmallett} 684215976Sjmallett#else 685215976Sjmallett#define CVMX_NPI_PCI_CFG58 (CVMX_ADD_IO_SEG(0x00011F00000018E8ull)) 686215976Sjmallett#endif 687215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 688215976Sjmallett#define CVMX_NPI_PCI_CFG59 CVMX_NPI_PCI_CFG59_FUNC() 689215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_CFG59_FUNC(void) 690215976Sjmallett{ 691215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 692215976Sjmallett cvmx_warn("CVMX_NPI_PCI_CFG59 not supported on this chip\n"); 693215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000018ECull); 694215976Sjmallett} 695215976Sjmallett#else 696215976Sjmallett#define CVMX_NPI_PCI_CFG59 (CVMX_ADD_IO_SEG(0x00011F00000018ECull)) 697215976Sjmallett#endif 698215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 699215976Sjmallett#define CVMX_NPI_PCI_CFG60 CVMX_NPI_PCI_CFG60_FUNC() 700215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_CFG60_FUNC(void) 701215976Sjmallett{ 702215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 703215976Sjmallett cvmx_warn("CVMX_NPI_PCI_CFG60 not supported on this chip\n"); 704215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000018F0ull); 705215976Sjmallett} 706215976Sjmallett#else 707215976Sjmallett#define CVMX_NPI_PCI_CFG60 (CVMX_ADD_IO_SEG(0x00011F00000018F0ull)) 708215976Sjmallett#endif 709215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 710215976Sjmallett#define CVMX_NPI_PCI_CFG61 CVMX_NPI_PCI_CFG61_FUNC() 711215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_CFG61_FUNC(void) 712215976Sjmallett{ 713215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 714215976Sjmallett cvmx_warn("CVMX_NPI_PCI_CFG61 not supported on this chip\n"); 715215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000018F4ull); 716215976Sjmallett} 717215976Sjmallett#else 718215976Sjmallett#define CVMX_NPI_PCI_CFG61 (CVMX_ADD_IO_SEG(0x00011F00000018F4ull)) 719215976Sjmallett#endif 720215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 721215976Sjmallett#define CVMX_NPI_PCI_CFG62 CVMX_NPI_PCI_CFG62_FUNC() 722215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_CFG62_FUNC(void) 723215976Sjmallett{ 724215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 725215976Sjmallett cvmx_warn("CVMX_NPI_PCI_CFG62 not supported on this chip\n"); 726215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000018F8ull); 727215976Sjmallett} 728215976Sjmallett#else 729215976Sjmallett#define CVMX_NPI_PCI_CFG62 (CVMX_ADD_IO_SEG(0x00011F00000018F8ull)) 730215976Sjmallett#endif 731215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 732215976Sjmallett#define CVMX_NPI_PCI_CFG63 CVMX_NPI_PCI_CFG63_FUNC() 733215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_CFG63_FUNC(void) 734215976Sjmallett{ 735215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 736215976Sjmallett cvmx_warn("CVMX_NPI_PCI_CFG63 not supported on this chip\n"); 737215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000018FCull); 738215976Sjmallett} 739215976Sjmallett#else 740215976Sjmallett#define CVMX_NPI_PCI_CFG63 (CVMX_ADD_IO_SEG(0x00011F00000018FCull)) 741215976Sjmallett#endif 742215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 743215976Sjmallett#define CVMX_NPI_PCI_CNT_REG CVMX_NPI_PCI_CNT_REG_FUNC() 744215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_CNT_REG_FUNC(void) 745215976Sjmallett{ 746215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 747215976Sjmallett cvmx_warn("CVMX_NPI_PCI_CNT_REG not supported on this chip\n"); 748215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000011B8ull); 749215976Sjmallett} 750215976Sjmallett#else 751215976Sjmallett#define CVMX_NPI_PCI_CNT_REG (CVMX_ADD_IO_SEG(0x00011F00000011B8ull)) 752215976Sjmallett#endif 753215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 754215976Sjmallett#define CVMX_NPI_PCI_CTL_STATUS_2 CVMX_NPI_PCI_CTL_STATUS_2_FUNC() 755215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_CTL_STATUS_2_FUNC(void) 756215976Sjmallett{ 757215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 758215976Sjmallett cvmx_warn("CVMX_NPI_PCI_CTL_STATUS_2 not supported on this chip\n"); 759215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F000000118Cull); 760215976Sjmallett} 761215976Sjmallett#else 762215976Sjmallett#define CVMX_NPI_PCI_CTL_STATUS_2 (CVMX_ADD_IO_SEG(0x00011F000000118Cull)) 763215976Sjmallett#endif 764215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 765215976Sjmallett#define CVMX_NPI_PCI_INT_ARB_CFG CVMX_NPI_PCI_INT_ARB_CFG_FUNC() 766215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_INT_ARB_CFG_FUNC(void) 767215976Sjmallett{ 768215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 769215976Sjmallett cvmx_warn("CVMX_NPI_PCI_INT_ARB_CFG not supported on this chip\n"); 770215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000000130ull); 771215976Sjmallett} 772215976Sjmallett#else 773215976Sjmallett#define CVMX_NPI_PCI_INT_ARB_CFG (CVMX_ADD_IO_SEG(0x00011F0000000130ull)) 774215976Sjmallett#endif 775215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 776215976Sjmallett#define CVMX_NPI_PCI_INT_ENB2 CVMX_NPI_PCI_INT_ENB2_FUNC() 777215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_INT_ENB2_FUNC(void) 778215976Sjmallett{ 779215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 780215976Sjmallett cvmx_warn("CVMX_NPI_PCI_INT_ENB2 not supported on this chip\n"); 781215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000011A0ull); 782215976Sjmallett} 783215976Sjmallett#else 784215976Sjmallett#define CVMX_NPI_PCI_INT_ENB2 (CVMX_ADD_IO_SEG(0x00011F00000011A0ull)) 785215976Sjmallett#endif 786215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 787215976Sjmallett#define CVMX_NPI_PCI_INT_SUM2 CVMX_NPI_PCI_INT_SUM2_FUNC() 788215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_INT_SUM2_FUNC(void) 789215976Sjmallett{ 790215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 791215976Sjmallett cvmx_warn("CVMX_NPI_PCI_INT_SUM2 not supported on this chip\n"); 792215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000001198ull); 793215976Sjmallett} 794215976Sjmallett#else 795215976Sjmallett#define CVMX_NPI_PCI_INT_SUM2 (CVMX_ADD_IO_SEG(0x00011F0000001198ull)) 796215976Sjmallett#endif 797215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 798215976Sjmallett#define CVMX_NPI_PCI_READ_CMD CVMX_NPI_PCI_READ_CMD_FUNC() 799215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_READ_CMD_FUNC(void) 800215976Sjmallett{ 801215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 802215976Sjmallett cvmx_warn("CVMX_NPI_PCI_READ_CMD not supported on this chip\n"); 803215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000000048ull); 804215976Sjmallett} 805215976Sjmallett#else 806215976Sjmallett#define CVMX_NPI_PCI_READ_CMD (CVMX_ADD_IO_SEG(0x00011F0000000048ull)) 807215976Sjmallett#endif 808215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 809215976Sjmallett#define CVMX_NPI_PCI_READ_CMD_6 CVMX_NPI_PCI_READ_CMD_6_FUNC() 810215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_READ_CMD_6_FUNC(void) 811215976Sjmallett{ 812215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 813215976Sjmallett cvmx_warn("CVMX_NPI_PCI_READ_CMD_6 not supported on this chip\n"); 814215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000001180ull); 815215976Sjmallett} 816215976Sjmallett#else 817215976Sjmallett#define CVMX_NPI_PCI_READ_CMD_6 (CVMX_ADD_IO_SEG(0x00011F0000001180ull)) 818215976Sjmallett#endif 819215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 820215976Sjmallett#define CVMX_NPI_PCI_READ_CMD_C CVMX_NPI_PCI_READ_CMD_C_FUNC() 821215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_READ_CMD_C_FUNC(void) 822215976Sjmallett{ 823215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 824215976Sjmallett cvmx_warn("CVMX_NPI_PCI_READ_CMD_C not supported on this chip\n"); 825215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000001184ull); 826215976Sjmallett} 827215976Sjmallett#else 828215976Sjmallett#define CVMX_NPI_PCI_READ_CMD_C (CVMX_ADD_IO_SEG(0x00011F0000001184ull)) 829215976Sjmallett#endif 830215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 831215976Sjmallett#define CVMX_NPI_PCI_READ_CMD_E CVMX_NPI_PCI_READ_CMD_E_FUNC() 832215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_READ_CMD_E_FUNC(void) 833215976Sjmallett{ 834215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 835215976Sjmallett cvmx_warn("CVMX_NPI_PCI_READ_CMD_E not supported on this chip\n"); 836215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000001188ull); 837215976Sjmallett} 838215976Sjmallett#else 839215976Sjmallett#define CVMX_NPI_PCI_READ_CMD_E (CVMX_ADD_IO_SEG(0x00011F0000001188ull)) 840215976Sjmallett#endif 841215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 842215976Sjmallett#define CVMX_NPI_PCI_SCM_REG CVMX_NPI_PCI_SCM_REG_FUNC() 843215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_SCM_REG_FUNC(void) 844215976Sjmallett{ 845215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 846215976Sjmallett cvmx_warn("CVMX_NPI_PCI_SCM_REG not supported on this chip\n"); 847215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000011A8ull); 848215976Sjmallett} 849215976Sjmallett#else 850215976Sjmallett#define CVMX_NPI_PCI_SCM_REG (CVMX_ADD_IO_SEG(0x00011F00000011A8ull)) 851215976Sjmallett#endif 852215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 853215976Sjmallett#define CVMX_NPI_PCI_TSR_REG CVMX_NPI_PCI_TSR_REG_FUNC() 854215976Sjmallettstatic inline uint64_t CVMX_NPI_PCI_TSR_REG_FUNC(void) 855215976Sjmallett{ 856215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 857215976Sjmallett cvmx_warn("CVMX_NPI_PCI_TSR_REG not supported on this chip\n"); 858215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000011B0ull); 859215976Sjmallett} 860215976Sjmallett#else 861215976Sjmallett#define CVMX_NPI_PCI_TSR_REG (CVMX_ADD_IO_SEG(0x00011F00000011B0ull)) 862215976Sjmallett#endif 863215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 864215976Sjmallett#define CVMX_NPI_PORT32_INSTR_HDR CVMX_NPI_PORT32_INSTR_HDR_FUNC() 865215976Sjmallettstatic inline uint64_t CVMX_NPI_PORT32_INSTR_HDR_FUNC(void) 866215976Sjmallett{ 867215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 868215976Sjmallett cvmx_warn("CVMX_NPI_PORT32_INSTR_HDR not supported on this chip\n"); 869215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000001F8ull); 870215976Sjmallett} 871215976Sjmallett#else 872215976Sjmallett#define CVMX_NPI_PORT32_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F00000001F8ull)) 873215976Sjmallett#endif 874215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 875215976Sjmallett#define CVMX_NPI_PORT33_INSTR_HDR CVMX_NPI_PORT33_INSTR_HDR_FUNC() 876215976Sjmallettstatic inline uint64_t CVMX_NPI_PORT33_INSTR_HDR_FUNC(void) 877215976Sjmallett{ 878215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 879215976Sjmallett cvmx_warn("CVMX_NPI_PORT33_INSTR_HDR not supported on this chip\n"); 880215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000000200ull); 881215976Sjmallett} 882215976Sjmallett#else 883215976Sjmallett#define CVMX_NPI_PORT33_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000200ull)) 884215976Sjmallett#endif 885215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 886215976Sjmallett#define CVMX_NPI_PORT34_INSTR_HDR CVMX_NPI_PORT34_INSTR_HDR_FUNC() 887215976Sjmallettstatic inline uint64_t CVMX_NPI_PORT34_INSTR_HDR_FUNC(void) 888215976Sjmallett{ 889215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 890215976Sjmallett cvmx_warn("CVMX_NPI_PORT34_INSTR_HDR not supported on this chip\n"); 891215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000000208ull); 892215976Sjmallett} 893215976Sjmallett#else 894215976Sjmallett#define CVMX_NPI_PORT34_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000208ull)) 895215976Sjmallett#endif 896215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 897215976Sjmallett#define CVMX_NPI_PORT35_INSTR_HDR CVMX_NPI_PORT35_INSTR_HDR_FUNC() 898215976Sjmallettstatic inline uint64_t CVMX_NPI_PORT35_INSTR_HDR_FUNC(void) 899215976Sjmallett{ 900215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 901215976Sjmallett cvmx_warn("CVMX_NPI_PORT35_INSTR_HDR not supported on this chip\n"); 902215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000000210ull); 903215976Sjmallett} 904215976Sjmallett#else 905215976Sjmallett#define CVMX_NPI_PORT35_INSTR_HDR (CVMX_ADD_IO_SEG(0x00011F0000000210ull)) 906215976Sjmallett#endif 907215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 908215976Sjmallett#define CVMX_NPI_PORT_BP_CONTROL CVMX_NPI_PORT_BP_CONTROL_FUNC() 909215976Sjmallettstatic inline uint64_t CVMX_NPI_PORT_BP_CONTROL_FUNC(void) 910215976Sjmallett{ 911215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 912215976Sjmallett cvmx_warn("CVMX_NPI_PORT_BP_CONTROL not supported on this chip\n"); 913215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000001F0ull); 914215976Sjmallett} 915215976Sjmallett#else 916215976Sjmallett#define CVMX_NPI_PORT_BP_CONTROL (CVMX_ADD_IO_SEG(0x00011F00000001F0ull)) 917215976Sjmallett#endif 918215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 919215976Sjmallettstatic inline uint64_t CVMX_NPI_PX_DBPAIR_ADDR(unsigned long offset) 920215976Sjmallett{ 921215976Sjmallett if (!( 922215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 923215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 924215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 925215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 926215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 927215976Sjmallett cvmx_warn("CVMX_NPI_PX_DBPAIR_ADDR(%lu) is invalid on this chip\n", offset); 928215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000000180ull) + ((offset) & 3) * 8; 929215976Sjmallett} 930215976Sjmallett#else 931215976Sjmallett#define CVMX_NPI_PX_DBPAIR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F0000000180ull) + ((offset) & 3) * 8) 932215976Sjmallett#endif 933215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 934215976Sjmallettstatic inline uint64_t CVMX_NPI_PX_INSTR_ADDR(unsigned long offset) 935215976Sjmallett{ 936215976Sjmallett if (!( 937215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 938215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 939215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 940215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 941215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 942215976Sjmallett cvmx_warn("CVMX_NPI_PX_INSTR_ADDR(%lu) is invalid on this chip\n", offset); 943215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000001C0ull) + ((offset) & 3) * 8; 944215976Sjmallett} 945215976Sjmallett#else 946215976Sjmallett#define CVMX_NPI_PX_INSTR_ADDR(offset) (CVMX_ADD_IO_SEG(0x00011F00000001C0ull) + ((offset) & 3) * 8) 947215976Sjmallett#endif 948215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 949215976Sjmallettstatic inline uint64_t CVMX_NPI_PX_INSTR_CNTS(unsigned long offset) 950215976Sjmallett{ 951215976Sjmallett if (!( 952215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 953215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 954215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 955215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 956215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 957215976Sjmallett cvmx_warn("CVMX_NPI_PX_INSTR_CNTS(%lu) is invalid on this chip\n", offset); 958215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000001A0ull) + ((offset) & 3) * 8; 959215976Sjmallett} 960215976Sjmallett#else 961215976Sjmallett#define CVMX_NPI_PX_INSTR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F00000001A0ull) + ((offset) & 3) * 8) 962215976Sjmallett#endif 963215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 964215976Sjmallettstatic inline uint64_t CVMX_NPI_PX_PAIR_CNTS(unsigned long offset) 965215976Sjmallett{ 966215976Sjmallett if (!( 967215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 968215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 969215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 970215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 971215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 972215976Sjmallett cvmx_warn("CVMX_NPI_PX_PAIR_CNTS(%lu) is invalid on this chip\n", offset); 973215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000000160ull) + ((offset) & 3) * 8; 974215976Sjmallett} 975215976Sjmallett#else 976215976Sjmallett#define CVMX_NPI_PX_PAIR_CNTS(offset) (CVMX_ADD_IO_SEG(0x00011F0000000160ull) + ((offset) & 3) * 8) 977215976Sjmallett#endif 978215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 979215976Sjmallett#define CVMX_NPI_RSL_INT_BLOCKS CVMX_NPI_RSL_INT_BLOCKS_FUNC() 980215976Sjmallettstatic inline uint64_t CVMX_NPI_RSL_INT_BLOCKS_FUNC(void) 981215976Sjmallett{ 982215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 983215976Sjmallett cvmx_warn("CVMX_NPI_RSL_INT_BLOCKS not supported on this chip\n"); 984215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000000000ull); 985215976Sjmallett} 986215976Sjmallett#else 987215976Sjmallett#define CVMX_NPI_RSL_INT_BLOCKS (CVMX_ADD_IO_SEG(0x00011F0000000000ull)) 988215976Sjmallett#endif 989215976Sjmallett#define CVMX_NPI_SIZE_INPUT0 CVMX_NPI_SIZE_INPUTX(0) 990215976Sjmallett#define CVMX_NPI_SIZE_INPUT1 CVMX_NPI_SIZE_INPUTX(1) 991215976Sjmallett#define CVMX_NPI_SIZE_INPUT2 CVMX_NPI_SIZE_INPUTX(2) 992215976Sjmallett#define CVMX_NPI_SIZE_INPUT3 CVMX_NPI_SIZE_INPUTX(3) 993215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 994215976Sjmallettstatic inline uint64_t CVMX_NPI_SIZE_INPUTX(unsigned long offset) 995215976Sjmallett{ 996215976Sjmallett if (!( 997215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) || 998215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) || 999215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 3))) || 1000215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) || 1001215976Sjmallett (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 3))))) 1002215976Sjmallett cvmx_warn("CVMX_NPI_SIZE_INPUTX(%lu) is invalid on this chip\n", offset); 1003215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F0000000078ull) + ((offset) & 3) * 16; 1004215976Sjmallett} 1005215976Sjmallett#else 1006215976Sjmallett#define CVMX_NPI_SIZE_INPUTX(offset) (CVMX_ADD_IO_SEG(0x00011F0000000078ull) + ((offset) & 3) * 16) 1007215976Sjmallett#endif 1008215976Sjmallett#if CVMX_ENABLE_CSR_ADDRESS_CHECKING 1009215976Sjmallett#define CVMX_NPI_WIN_READ_TO CVMX_NPI_WIN_READ_TO_FUNC() 1010215976Sjmallettstatic inline uint64_t CVMX_NPI_WIN_READ_TO_FUNC(void) 1011215976Sjmallett{ 1012215976Sjmallett if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))) 1013215976Sjmallett cvmx_warn("CVMX_NPI_WIN_READ_TO not supported on this chip\n"); 1014215976Sjmallett return CVMX_ADD_IO_SEG(0x00011F00000001E0ull); 1015215976Sjmallett} 1016215976Sjmallett#else 1017215976Sjmallett#define CVMX_NPI_WIN_READ_TO (CVMX_ADD_IO_SEG(0x00011F00000001E0ull)) 1018215976Sjmallett#endif 1019215976Sjmallett 1020215976Sjmallett/** 1021215976Sjmallett * cvmx_npi_base_addr_input# 1022215976Sjmallett * 1023215976Sjmallett * NPI_BASE_ADDR_INPUT0 = NPI's Base Address Input 0 Register 1024215976Sjmallett * 1025215976Sjmallett * The address to start reading Instructions from for Input-0. 1026215976Sjmallett */ 1027232812Sjmallettunion cvmx_npi_base_addr_inputx { 1028215976Sjmallett uint64_t u64; 1029232812Sjmallett struct cvmx_npi_base_addr_inputx_s { 1030232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1031215976Sjmallett uint64_t baddr : 61; /**< The address to read Instruction from for output 0. 1032215976Sjmallett This address is 8-byte aligned, for this reason 1033215976Sjmallett address bits [2:0] will always be zero. */ 1034215976Sjmallett uint64_t reserved_0_2 : 3; 1035215976Sjmallett#else 1036215976Sjmallett uint64_t reserved_0_2 : 3; 1037215976Sjmallett uint64_t baddr : 61; 1038215976Sjmallett#endif 1039215976Sjmallett } s; 1040215976Sjmallett struct cvmx_npi_base_addr_inputx_s cn30xx; 1041215976Sjmallett struct cvmx_npi_base_addr_inputx_s cn31xx; 1042215976Sjmallett struct cvmx_npi_base_addr_inputx_s cn38xx; 1043215976Sjmallett struct cvmx_npi_base_addr_inputx_s cn38xxp2; 1044215976Sjmallett struct cvmx_npi_base_addr_inputx_s cn50xx; 1045215976Sjmallett struct cvmx_npi_base_addr_inputx_s cn58xx; 1046215976Sjmallett struct cvmx_npi_base_addr_inputx_s cn58xxp1; 1047215976Sjmallett}; 1048215976Sjmalletttypedef union cvmx_npi_base_addr_inputx cvmx_npi_base_addr_inputx_t; 1049215976Sjmallett 1050215976Sjmallett/** 1051215976Sjmallett * cvmx_npi_base_addr_output# 1052215976Sjmallett * 1053215976Sjmallett * NPI_BASE_ADDR_OUTPUT0 = NPI's Base Address Output 0 Register 1054215976Sjmallett * 1055215976Sjmallett * The address to start reading Instructions from for Output-0. 1056215976Sjmallett */ 1057232812Sjmallettunion cvmx_npi_base_addr_outputx { 1058215976Sjmallett uint64_t u64; 1059232812Sjmallett struct cvmx_npi_base_addr_outputx_s { 1060232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1061215976Sjmallett uint64_t baddr : 61; /**< The address to read Instruction from for output 0. 1062215976Sjmallett This address is 8-byte aligned, for this reason 1063215976Sjmallett address bits [2:0] will always be zero. */ 1064215976Sjmallett uint64_t reserved_0_2 : 3; 1065215976Sjmallett#else 1066215976Sjmallett uint64_t reserved_0_2 : 3; 1067215976Sjmallett uint64_t baddr : 61; 1068215976Sjmallett#endif 1069215976Sjmallett } s; 1070215976Sjmallett struct cvmx_npi_base_addr_outputx_s cn30xx; 1071215976Sjmallett struct cvmx_npi_base_addr_outputx_s cn31xx; 1072215976Sjmallett struct cvmx_npi_base_addr_outputx_s cn38xx; 1073215976Sjmallett struct cvmx_npi_base_addr_outputx_s cn38xxp2; 1074215976Sjmallett struct cvmx_npi_base_addr_outputx_s cn50xx; 1075215976Sjmallett struct cvmx_npi_base_addr_outputx_s cn58xx; 1076215976Sjmallett struct cvmx_npi_base_addr_outputx_s cn58xxp1; 1077215976Sjmallett}; 1078215976Sjmalletttypedef union cvmx_npi_base_addr_outputx cvmx_npi_base_addr_outputx_t; 1079215976Sjmallett 1080215976Sjmallett/** 1081215976Sjmallett * cvmx_npi_bist_status 1082215976Sjmallett * 1083215976Sjmallett * NPI_BIST_STATUS = NPI's BIST Status Register 1084215976Sjmallett * 1085215976Sjmallett * Results from BIST runs of NPI's memories. 1086215976Sjmallett */ 1087232812Sjmallettunion cvmx_npi_bist_status { 1088215976Sjmallett uint64_t u64; 1089232812Sjmallett struct cvmx_npi_bist_status_s { 1090232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1091215976Sjmallett uint64_t reserved_20_63 : 44; 1092215976Sjmallett uint64_t csr_bs : 1; /**< BIST Status for the csr_fifo */ 1093215976Sjmallett uint64_t dif_bs : 1; /**< BIST Status for the dif_fifo */ 1094215976Sjmallett uint64_t rdp_bs : 1; /**< BIST Status for the rdp_fifo */ 1095215976Sjmallett uint64_t pcnc_bs : 1; /**< BIST Status for the pcn_cnt_fifo */ 1096215976Sjmallett uint64_t pcn_bs : 1; /**< BIST Status for the pcn_fifo */ 1097215976Sjmallett uint64_t rdn_bs : 1; /**< BIST Status for the rdn_fifo */ 1098215976Sjmallett uint64_t pcac_bs : 1; /**< BIST Status for the pca_cmd_fifo */ 1099215976Sjmallett uint64_t pcad_bs : 1; /**< BIST Status for the pca_data_fifo */ 1100215976Sjmallett uint64_t rdnl_bs : 1; /**< BIST Status for the rdn_length_fifo */ 1101215976Sjmallett uint64_t pgf_bs : 1; /**< BIST Status for the pgf_fifo */ 1102215976Sjmallett uint64_t pig_bs : 1; /**< BIST Status for the pig_fifo */ 1103215976Sjmallett uint64_t pof0_bs : 1; /**< BIST Status for the pof0_fifo */ 1104215976Sjmallett uint64_t pof1_bs : 1; /**< BIST Status for the pof1_fifo */ 1105215976Sjmallett uint64_t pof2_bs : 1; /**< BIST Status for the pof2_fifo */ 1106215976Sjmallett uint64_t pof3_bs : 1; /**< BIST Status for the pof3_fifo */ 1107215976Sjmallett uint64_t pos_bs : 1; /**< BIST Status for the pos_fifo */ 1108215976Sjmallett uint64_t nus_bs : 1; /**< BIST Status for the nus_fifo */ 1109215976Sjmallett uint64_t dob_bs : 1; /**< BIST Status for the dob_fifo */ 1110215976Sjmallett uint64_t pdf_bs : 1; /**< BIST Status for the pdf_fifo */ 1111215976Sjmallett uint64_t dpi_bs : 1; /**< BIST Status for the dpi_fifo */ 1112215976Sjmallett#else 1113215976Sjmallett uint64_t dpi_bs : 1; 1114215976Sjmallett uint64_t pdf_bs : 1; 1115215976Sjmallett uint64_t dob_bs : 1; 1116215976Sjmallett uint64_t nus_bs : 1; 1117215976Sjmallett uint64_t pos_bs : 1; 1118215976Sjmallett uint64_t pof3_bs : 1; 1119215976Sjmallett uint64_t pof2_bs : 1; 1120215976Sjmallett uint64_t pof1_bs : 1; 1121215976Sjmallett uint64_t pof0_bs : 1; 1122215976Sjmallett uint64_t pig_bs : 1; 1123215976Sjmallett uint64_t pgf_bs : 1; 1124215976Sjmallett uint64_t rdnl_bs : 1; 1125215976Sjmallett uint64_t pcad_bs : 1; 1126215976Sjmallett uint64_t pcac_bs : 1; 1127215976Sjmallett uint64_t rdn_bs : 1; 1128215976Sjmallett uint64_t pcn_bs : 1; 1129215976Sjmallett uint64_t pcnc_bs : 1; 1130215976Sjmallett uint64_t rdp_bs : 1; 1131215976Sjmallett uint64_t dif_bs : 1; 1132215976Sjmallett uint64_t csr_bs : 1; 1133215976Sjmallett uint64_t reserved_20_63 : 44; 1134215976Sjmallett#endif 1135215976Sjmallett } s; 1136232812Sjmallett struct cvmx_npi_bist_status_cn30xx { 1137232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1138215976Sjmallett uint64_t reserved_20_63 : 44; 1139215976Sjmallett uint64_t csr_bs : 1; /**< BIST Status for the csr_fifo */ 1140215976Sjmallett uint64_t dif_bs : 1; /**< BIST Status for the dif_fifo */ 1141215976Sjmallett uint64_t rdp_bs : 1; /**< BIST Status for the rdp_fifo */ 1142215976Sjmallett uint64_t pcnc_bs : 1; /**< BIST Status for the pcn_cnt_fifo */ 1143215976Sjmallett uint64_t pcn_bs : 1; /**< BIST Status for the pcn_fifo */ 1144215976Sjmallett uint64_t rdn_bs : 1; /**< BIST Status for the rdn_fifo */ 1145215976Sjmallett uint64_t pcac_bs : 1; /**< BIST Status for the pca_cmd_fifo */ 1146215976Sjmallett uint64_t pcad_bs : 1; /**< BIST Status for the pca_data_fifo */ 1147215976Sjmallett uint64_t rdnl_bs : 1; /**< BIST Status for the rdn_length_fifo */ 1148215976Sjmallett uint64_t pgf_bs : 1; /**< BIST Status for the pgf_fifo */ 1149215976Sjmallett uint64_t pig_bs : 1; /**< BIST Status for the pig_fifo */ 1150215976Sjmallett uint64_t pof0_bs : 1; /**< BIST Status for the pof0_fifo */ 1151215976Sjmallett uint64_t reserved_5_7 : 3; 1152215976Sjmallett uint64_t pos_bs : 1; /**< BIST Status for the pos_fifo */ 1153215976Sjmallett uint64_t nus_bs : 1; /**< BIST Status for the nus_fifo */ 1154215976Sjmallett uint64_t dob_bs : 1; /**< BIST Status for the dob_fifo */ 1155215976Sjmallett uint64_t pdf_bs : 1; /**< BIST Status for the pdf_fifo */ 1156215976Sjmallett uint64_t dpi_bs : 1; /**< BIST Status for the dpi_fifo */ 1157215976Sjmallett#else 1158215976Sjmallett uint64_t dpi_bs : 1; 1159215976Sjmallett uint64_t pdf_bs : 1; 1160215976Sjmallett uint64_t dob_bs : 1; 1161215976Sjmallett uint64_t nus_bs : 1; 1162215976Sjmallett uint64_t pos_bs : 1; 1163215976Sjmallett uint64_t reserved_5_7 : 3; 1164215976Sjmallett uint64_t pof0_bs : 1; 1165215976Sjmallett uint64_t pig_bs : 1; 1166215976Sjmallett uint64_t pgf_bs : 1; 1167215976Sjmallett uint64_t rdnl_bs : 1; 1168215976Sjmallett uint64_t pcad_bs : 1; 1169215976Sjmallett uint64_t pcac_bs : 1; 1170215976Sjmallett uint64_t rdn_bs : 1; 1171215976Sjmallett uint64_t pcn_bs : 1; 1172215976Sjmallett uint64_t pcnc_bs : 1; 1173215976Sjmallett uint64_t rdp_bs : 1; 1174215976Sjmallett uint64_t dif_bs : 1; 1175215976Sjmallett uint64_t csr_bs : 1; 1176215976Sjmallett uint64_t reserved_20_63 : 44; 1177215976Sjmallett#endif 1178215976Sjmallett } cn30xx; 1179215976Sjmallett struct cvmx_npi_bist_status_s cn31xx; 1180215976Sjmallett struct cvmx_npi_bist_status_s cn38xx; 1181215976Sjmallett struct cvmx_npi_bist_status_s cn38xxp2; 1182232812Sjmallett struct cvmx_npi_bist_status_cn50xx { 1183232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1184215976Sjmallett uint64_t reserved_20_63 : 44; 1185215976Sjmallett uint64_t csr_bs : 1; /**< BIST Status for the csr_fifo */ 1186215976Sjmallett uint64_t dif_bs : 1; /**< BIST Status for the dif_fifo */ 1187215976Sjmallett uint64_t rdp_bs : 1; /**< BIST Status for the rdp_fifo */ 1188215976Sjmallett uint64_t pcnc_bs : 1; /**< BIST Status for the pcn_cnt_fifo */ 1189215976Sjmallett uint64_t pcn_bs : 1; /**< BIST Status for the pcn_fifo */ 1190215976Sjmallett uint64_t rdn_bs : 1; /**< BIST Status for the rdn_fifo */ 1191215976Sjmallett uint64_t pcac_bs : 1; /**< BIST Status for the pca_cmd_fifo */ 1192215976Sjmallett uint64_t pcad_bs : 1; /**< BIST Status for the pca_data_fifo */ 1193215976Sjmallett uint64_t rdnl_bs : 1; /**< BIST Status for the rdn_length_fifo */ 1194215976Sjmallett uint64_t pgf_bs : 1; /**< BIST Status for the pgf_fifo */ 1195215976Sjmallett uint64_t pig_bs : 1; /**< BIST Status for the pig_fifo */ 1196215976Sjmallett uint64_t pof0_bs : 1; /**< BIST Status for the pof0_fifo */ 1197215976Sjmallett uint64_t pof1_bs : 1; /**< BIST Status for the pof1_fifo */ 1198215976Sjmallett uint64_t reserved_5_6 : 2; 1199215976Sjmallett uint64_t pos_bs : 1; /**< BIST Status for the pos_fifo */ 1200215976Sjmallett uint64_t nus_bs : 1; /**< BIST Status for the nus_fifo */ 1201215976Sjmallett uint64_t dob_bs : 1; /**< BIST Status for the dob_fifo */ 1202215976Sjmallett uint64_t pdf_bs : 1; /**< BIST Status for the pdf_fifo */ 1203215976Sjmallett uint64_t dpi_bs : 1; /**< BIST Status for the dpi_fifo */ 1204215976Sjmallett#else 1205215976Sjmallett uint64_t dpi_bs : 1; 1206215976Sjmallett uint64_t pdf_bs : 1; 1207215976Sjmallett uint64_t dob_bs : 1; 1208215976Sjmallett uint64_t nus_bs : 1; 1209215976Sjmallett uint64_t pos_bs : 1; 1210215976Sjmallett uint64_t reserved_5_6 : 2; 1211215976Sjmallett uint64_t pof1_bs : 1; 1212215976Sjmallett uint64_t pof0_bs : 1; 1213215976Sjmallett uint64_t pig_bs : 1; 1214215976Sjmallett uint64_t pgf_bs : 1; 1215215976Sjmallett uint64_t rdnl_bs : 1; 1216215976Sjmallett uint64_t pcad_bs : 1; 1217215976Sjmallett uint64_t pcac_bs : 1; 1218215976Sjmallett uint64_t rdn_bs : 1; 1219215976Sjmallett uint64_t pcn_bs : 1; 1220215976Sjmallett uint64_t pcnc_bs : 1; 1221215976Sjmallett uint64_t rdp_bs : 1; 1222215976Sjmallett uint64_t dif_bs : 1; 1223215976Sjmallett uint64_t csr_bs : 1; 1224215976Sjmallett uint64_t reserved_20_63 : 44; 1225215976Sjmallett#endif 1226215976Sjmallett } cn50xx; 1227215976Sjmallett struct cvmx_npi_bist_status_s cn58xx; 1228215976Sjmallett struct cvmx_npi_bist_status_s cn58xxp1; 1229215976Sjmallett}; 1230215976Sjmalletttypedef union cvmx_npi_bist_status cvmx_npi_bist_status_t; 1231215976Sjmallett 1232215976Sjmallett/** 1233215976Sjmallett * cvmx_npi_buff_size_output# 1234215976Sjmallett * 1235215976Sjmallett * NPI_BUFF_SIZE_OUTPUT0 = NPI's D/I Buffer Sizes For Output 0 1236215976Sjmallett * 1237215976Sjmallett * The size in bytes of the Data Bufffer and Information Buffer for output 0. 1238215976Sjmallett */ 1239232812Sjmallettunion cvmx_npi_buff_size_outputx { 1240215976Sjmallett uint64_t u64; 1241232812Sjmallett struct cvmx_npi_buff_size_outputx_s { 1242232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1243215976Sjmallett uint64_t reserved_23_63 : 41; 1244215976Sjmallett uint64_t isize : 7; /**< The number of bytes to move to the Info-Pointer 1245215976Sjmallett from the front of the packet. 1246215976Sjmallett Legal values are 0-120. */ 1247215976Sjmallett uint64_t bsize : 16; /**< The size in bytes of the area pointed to by 1248215976Sjmallett buffer pointer for output packet data. */ 1249215976Sjmallett#else 1250215976Sjmallett uint64_t bsize : 16; 1251215976Sjmallett uint64_t isize : 7; 1252215976Sjmallett uint64_t reserved_23_63 : 41; 1253215976Sjmallett#endif 1254215976Sjmallett } s; 1255215976Sjmallett struct cvmx_npi_buff_size_outputx_s cn30xx; 1256215976Sjmallett struct cvmx_npi_buff_size_outputx_s cn31xx; 1257215976Sjmallett struct cvmx_npi_buff_size_outputx_s cn38xx; 1258215976Sjmallett struct cvmx_npi_buff_size_outputx_s cn38xxp2; 1259215976Sjmallett struct cvmx_npi_buff_size_outputx_s cn50xx; 1260215976Sjmallett struct cvmx_npi_buff_size_outputx_s cn58xx; 1261215976Sjmallett struct cvmx_npi_buff_size_outputx_s cn58xxp1; 1262215976Sjmallett}; 1263215976Sjmalletttypedef union cvmx_npi_buff_size_outputx cvmx_npi_buff_size_outputx_t; 1264215976Sjmallett 1265215976Sjmallett/** 1266215976Sjmallett * cvmx_npi_comp_ctl 1267215976Sjmallett * 1268215976Sjmallett * NPI_COMP_CTL = PCI Compensation Control 1269215976Sjmallett * 1270215976Sjmallett * PCI Compensation Control 1271215976Sjmallett */ 1272232812Sjmallettunion cvmx_npi_comp_ctl { 1273215976Sjmallett uint64_t u64; 1274232812Sjmallett struct cvmx_npi_comp_ctl_s { 1275232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1276215976Sjmallett uint64_t reserved_10_63 : 54; 1277215976Sjmallett uint64_t pctl : 5; /**< Bypass value for PCTL */ 1278215976Sjmallett uint64_t nctl : 5; /**< Bypass value for NCTL */ 1279215976Sjmallett#else 1280215976Sjmallett uint64_t nctl : 5; 1281215976Sjmallett uint64_t pctl : 5; 1282215976Sjmallett uint64_t reserved_10_63 : 54; 1283215976Sjmallett#endif 1284215976Sjmallett } s; 1285215976Sjmallett struct cvmx_npi_comp_ctl_s cn50xx; 1286215976Sjmallett struct cvmx_npi_comp_ctl_s cn58xx; 1287215976Sjmallett struct cvmx_npi_comp_ctl_s cn58xxp1; 1288215976Sjmallett}; 1289215976Sjmalletttypedef union cvmx_npi_comp_ctl cvmx_npi_comp_ctl_t; 1290215976Sjmallett 1291215976Sjmallett/** 1292215976Sjmallett * cvmx_npi_ctl_status 1293215976Sjmallett * 1294215976Sjmallett * NPI_CTL_STATUS = NPI's Control Status Register 1295215976Sjmallett * 1296215976Sjmallett * Contains control ans status for NPI. 1297215976Sjmallett * Writes to this register are not ordered with writes/reads to the PCI Memory space. 1298215976Sjmallett * To ensure that a write has completed the user must read the register before 1299215976Sjmallett * making an access(i.e. PCI memory space) that requires the value of this register to be updated. 1300215976Sjmallett */ 1301232812Sjmallettunion cvmx_npi_ctl_status { 1302215976Sjmallett uint64_t u64; 1303232812Sjmallett struct cvmx_npi_ctl_status_s { 1304232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1305215976Sjmallett uint64_t reserved_63_63 : 1; 1306215976Sjmallett uint64_t chip_rev : 8; /**< The revision of the N3. */ 1307215976Sjmallett uint64_t dis_pniw : 1; /**< When asserted '1' access from the PNI Window 1308215976Sjmallett Registers are disabled. */ 1309215976Sjmallett uint64_t out3_enb : 1; /**< When asserted '1' the output3 engine is enabled. 1310215976Sjmallett After enabling the values of the associated 1311215976Sjmallett Address and Size Register should not be changed. */ 1312215976Sjmallett uint64_t out2_enb : 1; /**< When asserted '1' the output2 engine is enabled. 1313215976Sjmallett After enabling the values of the associated 1314215976Sjmallett Address and Size Register should not be changed. */ 1315215976Sjmallett uint64_t out1_enb : 1; /**< When asserted '1' the output1 engine is enabled. 1316215976Sjmallett After enabling the values of the associated 1317215976Sjmallett Address and Size Register should not be changed. */ 1318215976Sjmallett uint64_t out0_enb : 1; /**< When asserted '1' the output0 engine is enabled. 1319215976Sjmallett After enabling the values of the associated 1320215976Sjmallett Address and Size Register should not be changed. */ 1321215976Sjmallett uint64_t ins3_enb : 1; /**< When asserted '1' the gather3 engine is enabled. 1322215976Sjmallett After enabling the values of the associated 1323215976Sjmallett Address and Size Register should not be changed. */ 1324215976Sjmallett uint64_t ins2_enb : 1; /**< When asserted '1' the gather2 engine is enabled. 1325215976Sjmallett After enabling the values of the associated 1326215976Sjmallett Address and Size Register should not be changed. */ 1327215976Sjmallett uint64_t ins1_enb : 1; /**< When asserted '1' the gather1 engine is enabled. 1328215976Sjmallett After enabling the values of the associated 1329215976Sjmallett Address and Size Register should not be changed. */ 1330215976Sjmallett uint64_t ins0_enb : 1; /**< When asserted '1' the gather0 engine is enabled. 1331215976Sjmallett After enabling the values of the associated 1332215976Sjmallett Address and Size Register should not be changed. */ 1333215976Sjmallett uint64_t ins3_64b : 1; /**< When asserted '1' the instructions read by the 1334215976Sjmallett gather3 engine are 64-Byte instructions, when 1335215976Sjmallett de-asserted '0' instructions are 32-byte. */ 1336215976Sjmallett uint64_t ins2_64b : 1; /**< When asserted '1' the instructions read by the 1337215976Sjmallett gather2 engine are 64-Byte instructions, when 1338215976Sjmallett de-asserted '0' instructions are 32-byte. */ 1339215976Sjmallett uint64_t ins1_64b : 1; /**< When asserted '1' the instructions read by the 1340215976Sjmallett gather1 engine are 64-Byte instructions, when 1341215976Sjmallett de-asserted '0' instructions are 32-byte. */ 1342215976Sjmallett uint64_t ins0_64b : 1; /**< When asserted '1' the instructions read by the 1343215976Sjmallett gather0 engine are 64-Byte instructions, when 1344215976Sjmallett de-asserted '0' instructions are 32-byte. */ 1345215976Sjmallett uint64_t pci_wdis : 1; /**< When set '1' disables access to registers in 1346215976Sjmallett PNI address range 0x1000 - 0x17FF from the PCI. */ 1347215976Sjmallett uint64_t wait_com : 1; /**< When set '1' casues the NPI to wait for a commit 1348215976Sjmallett from the L2C before sending additional access to 1349215976Sjmallett the L2C from the PCI. */ 1350215976Sjmallett uint64_t reserved_37_39 : 3; 1351215976Sjmallett uint64_t max_word : 5; /**< The maximum number of words to merge into a single 1352215976Sjmallett write operation from the PPs to the PCI. Legal 1353215976Sjmallett values are 1 to 32, where a '0' is treated as 32. */ 1354215976Sjmallett uint64_t reserved_10_31 : 22; 1355215976Sjmallett uint64_t timer : 10; /**< When the NPI starts a PP to PCI write it will wait 1356215976Sjmallett no longer than the value of TIMER in eclks to 1357215976Sjmallett merge additional writes from the PPs into 1 1358215976Sjmallett large write. The values for this field is 1 to 1359215976Sjmallett 1024 where a value of '0' is treated as 1024. */ 1360215976Sjmallett#else 1361215976Sjmallett uint64_t timer : 10; 1362215976Sjmallett uint64_t reserved_10_31 : 22; 1363215976Sjmallett uint64_t max_word : 5; 1364215976Sjmallett uint64_t reserved_37_39 : 3; 1365215976Sjmallett uint64_t wait_com : 1; 1366215976Sjmallett uint64_t pci_wdis : 1; 1367215976Sjmallett uint64_t ins0_64b : 1; 1368215976Sjmallett uint64_t ins1_64b : 1; 1369215976Sjmallett uint64_t ins2_64b : 1; 1370215976Sjmallett uint64_t ins3_64b : 1; 1371215976Sjmallett uint64_t ins0_enb : 1; 1372215976Sjmallett uint64_t ins1_enb : 1; 1373215976Sjmallett uint64_t ins2_enb : 1; 1374215976Sjmallett uint64_t ins3_enb : 1; 1375215976Sjmallett uint64_t out0_enb : 1; 1376215976Sjmallett uint64_t out1_enb : 1; 1377215976Sjmallett uint64_t out2_enb : 1; 1378215976Sjmallett uint64_t out3_enb : 1; 1379215976Sjmallett uint64_t dis_pniw : 1; 1380215976Sjmallett uint64_t chip_rev : 8; 1381215976Sjmallett uint64_t reserved_63_63 : 1; 1382215976Sjmallett#endif 1383215976Sjmallett } s; 1384232812Sjmallett struct cvmx_npi_ctl_status_cn30xx { 1385232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1386215976Sjmallett uint64_t reserved_63_63 : 1; 1387215976Sjmallett uint64_t chip_rev : 8; /**< The revision of the N3. */ 1388215976Sjmallett uint64_t dis_pniw : 1; /**< When asserted '1' access from the PNI Window 1389215976Sjmallett Registers are disabled. */ 1390215976Sjmallett uint64_t reserved_51_53 : 3; 1391215976Sjmallett uint64_t out0_enb : 1; /**< When asserted '1' the output0 engine is enabled. 1392215976Sjmallett After enabling the values of the associated 1393215976Sjmallett Address and Size Register should not be changed. */ 1394215976Sjmallett uint64_t reserved_47_49 : 3; 1395215976Sjmallett uint64_t ins0_enb : 1; /**< When asserted '1' the gather0 engine is enabled. 1396215976Sjmallett After enabling the values of the associated 1397215976Sjmallett Address and Size Register should not be changed. */ 1398215976Sjmallett uint64_t reserved_43_45 : 3; 1399215976Sjmallett uint64_t ins0_64b : 1; /**< When asserted '1' the instructions read by the 1400215976Sjmallett gather0 engine are 64-Byte instructions, when 1401215976Sjmallett de-asserted '0' instructions are 32-byte. */ 1402215976Sjmallett uint64_t pci_wdis : 1; /**< When set '1' disables access to registers in 1403215976Sjmallett PNI address range 0x1000 - 0x17FF from the PCI. */ 1404215976Sjmallett uint64_t wait_com : 1; /**< When set '1' casues the NPI to wait for a commit 1405215976Sjmallett from the L2C before sending additional access to 1406215976Sjmallett the L2C from the PCI. */ 1407215976Sjmallett uint64_t reserved_37_39 : 3; 1408215976Sjmallett uint64_t max_word : 5; /**< The maximum number of words to merge into a single 1409215976Sjmallett write operation from the PPs to the PCI. Legal 1410215976Sjmallett values are 1 to 32, where a '0' is treated as 32. */ 1411215976Sjmallett uint64_t reserved_10_31 : 22; 1412215976Sjmallett uint64_t timer : 10; /**< When the NPI starts a PP to PCI write it will wait 1413215976Sjmallett no longer than the value of TIMER in eclks to 1414215976Sjmallett merge additional writes from the PPs into 1 1415215976Sjmallett large write. The values for this field is 1 to 1416215976Sjmallett 1024 where a value of '0' is treated as 1024. */ 1417215976Sjmallett#else 1418215976Sjmallett uint64_t timer : 10; 1419215976Sjmallett uint64_t reserved_10_31 : 22; 1420215976Sjmallett uint64_t max_word : 5; 1421215976Sjmallett uint64_t reserved_37_39 : 3; 1422215976Sjmallett uint64_t wait_com : 1; 1423215976Sjmallett uint64_t pci_wdis : 1; 1424215976Sjmallett uint64_t ins0_64b : 1; 1425215976Sjmallett uint64_t reserved_43_45 : 3; 1426215976Sjmallett uint64_t ins0_enb : 1; 1427215976Sjmallett uint64_t reserved_47_49 : 3; 1428215976Sjmallett uint64_t out0_enb : 1; 1429215976Sjmallett uint64_t reserved_51_53 : 3; 1430215976Sjmallett uint64_t dis_pniw : 1; 1431215976Sjmallett uint64_t chip_rev : 8; 1432215976Sjmallett uint64_t reserved_63_63 : 1; 1433215976Sjmallett#endif 1434215976Sjmallett } cn30xx; 1435232812Sjmallett struct cvmx_npi_ctl_status_cn31xx { 1436232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1437215976Sjmallett uint64_t reserved_63_63 : 1; 1438215976Sjmallett uint64_t chip_rev : 8; /**< The revision of the N3. 1439215976Sjmallett 0 => pass1.x, 1 => 2.0 */ 1440215976Sjmallett uint64_t dis_pniw : 1; /**< When asserted '1' access from the PNI Window 1441215976Sjmallett Registers are disabled. */ 1442215976Sjmallett uint64_t reserved_52_53 : 2; 1443215976Sjmallett uint64_t out1_enb : 1; /**< When asserted '1' the output1 engine is enabled. 1444215976Sjmallett After enabling the values of the associated 1445215976Sjmallett Address and Size Register should not be changed. */ 1446215976Sjmallett uint64_t out0_enb : 1; /**< When asserted '1' the output0 engine is enabled. 1447215976Sjmallett After enabling the values of the associated 1448215976Sjmallett Address and Size Register should not be changed. */ 1449215976Sjmallett uint64_t reserved_48_49 : 2; 1450215976Sjmallett uint64_t ins1_enb : 1; /**< When asserted '1' the gather1 engine is enabled. 1451215976Sjmallett After enabling the values of the associated 1452215976Sjmallett Address and Size Register should not be changed. */ 1453215976Sjmallett uint64_t ins0_enb : 1; /**< When asserted '1' the gather0 engine is enabled. 1454215976Sjmallett After enabling the values of the associated 1455215976Sjmallett Address and Size Register should not be changed. */ 1456215976Sjmallett uint64_t reserved_44_45 : 2; 1457215976Sjmallett uint64_t ins1_64b : 1; /**< When asserted '1' the instructions read by the 1458215976Sjmallett gather1 engine are 64-Byte instructions, when 1459215976Sjmallett de-asserted '0' instructions are 32-byte. */ 1460215976Sjmallett uint64_t ins0_64b : 1; /**< When asserted '1' the instructions read by the 1461215976Sjmallett gather0 engine are 64-Byte instructions, when 1462215976Sjmallett de-asserted '0' instructions are 32-byte. */ 1463215976Sjmallett uint64_t pci_wdis : 1; /**< When set '1' disables access to registers in 1464215976Sjmallett PNI address range 0x1000 - 0x17FF from the PCI. */ 1465215976Sjmallett uint64_t wait_com : 1; /**< When set '1' casues the NPI to wait for a commit 1466215976Sjmallett from the L2C before sending additional access to 1467215976Sjmallett the L2C from the PCI. */ 1468215976Sjmallett uint64_t reserved_37_39 : 3; 1469215976Sjmallett uint64_t max_word : 5; /**< The maximum number of words to merge into a single 1470215976Sjmallett write operation from the PPs to the PCI. Legal 1471215976Sjmallett values are 1 to 32, where a '0' is treated as 32. */ 1472215976Sjmallett uint64_t reserved_10_31 : 22; 1473215976Sjmallett uint64_t timer : 10; /**< When the NPI starts a PP to PCI write it will wait 1474215976Sjmallett no longer than the value of TIMER in eclks to 1475215976Sjmallett merge additional writes from the PPs into 1 1476215976Sjmallett large write. The values for this field is 1 to 1477215976Sjmallett 1024 where a value of '0' is treated as 1024. */ 1478215976Sjmallett#else 1479215976Sjmallett uint64_t timer : 10; 1480215976Sjmallett uint64_t reserved_10_31 : 22; 1481215976Sjmallett uint64_t max_word : 5; 1482215976Sjmallett uint64_t reserved_37_39 : 3; 1483215976Sjmallett uint64_t wait_com : 1; 1484215976Sjmallett uint64_t pci_wdis : 1; 1485215976Sjmallett uint64_t ins0_64b : 1; 1486215976Sjmallett uint64_t ins1_64b : 1; 1487215976Sjmallett uint64_t reserved_44_45 : 2; 1488215976Sjmallett uint64_t ins0_enb : 1; 1489215976Sjmallett uint64_t ins1_enb : 1; 1490215976Sjmallett uint64_t reserved_48_49 : 2; 1491215976Sjmallett uint64_t out0_enb : 1; 1492215976Sjmallett uint64_t out1_enb : 1; 1493215976Sjmallett uint64_t reserved_52_53 : 2; 1494215976Sjmallett uint64_t dis_pniw : 1; 1495215976Sjmallett uint64_t chip_rev : 8; 1496215976Sjmallett uint64_t reserved_63_63 : 1; 1497215976Sjmallett#endif 1498215976Sjmallett } cn31xx; 1499215976Sjmallett struct cvmx_npi_ctl_status_s cn38xx; 1500215976Sjmallett struct cvmx_npi_ctl_status_s cn38xxp2; 1501215976Sjmallett struct cvmx_npi_ctl_status_cn31xx cn50xx; 1502215976Sjmallett struct cvmx_npi_ctl_status_s cn58xx; 1503215976Sjmallett struct cvmx_npi_ctl_status_s cn58xxp1; 1504215976Sjmallett}; 1505215976Sjmalletttypedef union cvmx_npi_ctl_status cvmx_npi_ctl_status_t; 1506215976Sjmallett 1507215976Sjmallett/** 1508215976Sjmallett * cvmx_npi_dbg_select 1509215976Sjmallett * 1510215976Sjmallett * NPI_DBG_SELECT = Debug Select Register 1511215976Sjmallett * 1512215976Sjmallett * Contains the debug select value in last written to the RSLs. 1513215976Sjmallett */ 1514232812Sjmallettunion cvmx_npi_dbg_select { 1515215976Sjmallett uint64_t u64; 1516232812Sjmallett struct cvmx_npi_dbg_select_s { 1517232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1518215976Sjmallett uint64_t reserved_16_63 : 48; 1519215976Sjmallett uint64_t dbg_sel : 16; /**< When this register is written its value is sent to 1520215976Sjmallett all RSLs. */ 1521215976Sjmallett#else 1522215976Sjmallett uint64_t dbg_sel : 16; 1523215976Sjmallett uint64_t reserved_16_63 : 48; 1524215976Sjmallett#endif 1525215976Sjmallett } s; 1526215976Sjmallett struct cvmx_npi_dbg_select_s cn30xx; 1527215976Sjmallett struct cvmx_npi_dbg_select_s cn31xx; 1528215976Sjmallett struct cvmx_npi_dbg_select_s cn38xx; 1529215976Sjmallett struct cvmx_npi_dbg_select_s cn38xxp2; 1530215976Sjmallett struct cvmx_npi_dbg_select_s cn50xx; 1531215976Sjmallett struct cvmx_npi_dbg_select_s cn58xx; 1532215976Sjmallett struct cvmx_npi_dbg_select_s cn58xxp1; 1533215976Sjmallett}; 1534215976Sjmalletttypedef union cvmx_npi_dbg_select cvmx_npi_dbg_select_t; 1535215976Sjmallett 1536215976Sjmallett/** 1537215976Sjmallett * cvmx_npi_dma_control 1538215976Sjmallett * 1539215976Sjmallett * NPI_DMA_CONTROL = DMA Control Register 1540215976Sjmallett * 1541215976Sjmallett * Controls operation of the DMA IN/OUT of the NPI. 1542215976Sjmallett */ 1543232812Sjmallettunion cvmx_npi_dma_control { 1544215976Sjmallett uint64_t u64; 1545232812Sjmallett struct cvmx_npi_dma_control_s { 1546232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1547215976Sjmallett uint64_t reserved_36_63 : 28; 1548215976Sjmallett uint64_t b0_lend : 1; /**< When set '1' and the NPI is in the mode to write 1549215976Sjmallett 0 to L2C memory when a DMA is done, the address 1550215976Sjmallett to be written to will be treated as a Little 1551215976Sjmallett Endian address. This field is new to PASS-2. */ 1552215976Sjmallett uint64_t dwb_denb : 1; /**< When set '1' the NPI will send a value in the DWB 1553215976Sjmallett field for a free page operation for the memory 1554215976Sjmallett that contained the data in N3. */ 1555215976Sjmallett uint64_t dwb_ichk : 9; /**< When Instruction Chunks for DMA operations are freed 1556215976Sjmallett this value is used for the DWB field of the 1557215976Sjmallett operation. */ 1558215976Sjmallett uint64_t fpa_que : 3; /**< The FPA queue that the instruction-chunk page will 1559215976Sjmallett be returned to when used. */ 1560215976Sjmallett uint64_t o_add1 : 1; /**< When set '1' 1 will be added to the DMA counters, 1561215976Sjmallett if '0' then the number of bytes in the dma transfer 1562215976Sjmallett will be added to the count register. */ 1563215976Sjmallett uint64_t o_ro : 1; /**< Relaxed Ordering Mode for DMA. */ 1564215976Sjmallett uint64_t o_ns : 1; /**< Nosnoop For DMA. */ 1565215976Sjmallett uint64_t o_es : 2; /**< Endian Swap Mode for DMA. */ 1566215976Sjmallett uint64_t o_mode : 1; /**< Select PCI_POINTER MODE to be used. 1567215976Sjmallett '1' use pointer values for address and register 1568215976Sjmallett values for RO, ES, and NS, '0' use register 1569215976Sjmallett values for address and pointer values for 1570215976Sjmallett RO, ES, and NS. */ 1571215976Sjmallett uint64_t hp_enb : 1; /**< Enables the High Priority DMA. 1572215976Sjmallett While this bit is disabled '0' then the value 1573215976Sjmallett in the NPI_HIGHP_IBUFF_SADDR is re-loaded to the 1574215976Sjmallett starting address of the High Priority DMA engine. 1575215976Sjmallett CSIZE field will be reloaded, for the High Priority 1576215976Sjmallett DMA Engine. */ 1577215976Sjmallett uint64_t lp_enb : 1; /**< Enables the Low Priority DMA. 1578215976Sjmallett While this bit is disabled '0' then the value 1579215976Sjmallett in the NPI_LOWP_IBUFF_SADDR is re-loaded to the 1580215976Sjmallett starting address of the Low Priority DMA engine. 1581215976Sjmallett PASS-2: When this bit is '0' the value in the 1582215976Sjmallett CSIZE field will be reloaded, for the Low Priority 1583215976Sjmallett DMA Engine. */ 1584215976Sjmallett uint64_t csize : 14; /**< The size in words of the DMA Instruction Chunk. 1585215976Sjmallett This value should only be written once. After 1586215976Sjmallett writing this value a new value will not be 1587215976Sjmallett recognized until the end of the DMA I-Chunk is 1588215976Sjmallett reached. */ 1589215976Sjmallett#else 1590215976Sjmallett uint64_t csize : 14; 1591215976Sjmallett uint64_t lp_enb : 1; 1592215976Sjmallett uint64_t hp_enb : 1; 1593215976Sjmallett uint64_t o_mode : 1; 1594215976Sjmallett uint64_t o_es : 2; 1595215976Sjmallett uint64_t o_ns : 1; 1596215976Sjmallett uint64_t o_ro : 1; 1597215976Sjmallett uint64_t o_add1 : 1; 1598215976Sjmallett uint64_t fpa_que : 3; 1599215976Sjmallett uint64_t dwb_ichk : 9; 1600215976Sjmallett uint64_t dwb_denb : 1; 1601215976Sjmallett uint64_t b0_lend : 1; 1602215976Sjmallett uint64_t reserved_36_63 : 28; 1603215976Sjmallett#endif 1604215976Sjmallett } s; 1605215976Sjmallett struct cvmx_npi_dma_control_s cn30xx; 1606215976Sjmallett struct cvmx_npi_dma_control_s cn31xx; 1607215976Sjmallett struct cvmx_npi_dma_control_s cn38xx; 1608215976Sjmallett struct cvmx_npi_dma_control_s cn38xxp2; 1609215976Sjmallett struct cvmx_npi_dma_control_s cn50xx; 1610215976Sjmallett struct cvmx_npi_dma_control_s cn58xx; 1611215976Sjmallett struct cvmx_npi_dma_control_s cn58xxp1; 1612215976Sjmallett}; 1613215976Sjmalletttypedef union cvmx_npi_dma_control cvmx_npi_dma_control_t; 1614215976Sjmallett 1615215976Sjmallett/** 1616215976Sjmallett * cvmx_npi_dma_highp_counts 1617215976Sjmallett * 1618215976Sjmallett * NPI_DMA_HIGHP_COUNTS = NPI's High Priority DMA Counts 1619215976Sjmallett * 1620215976Sjmallett * Values for determing the number of instructions for High Priority DMA in the NPI. 1621215976Sjmallett */ 1622232812Sjmallettunion cvmx_npi_dma_highp_counts { 1623215976Sjmallett uint64_t u64; 1624232812Sjmallett struct cvmx_npi_dma_highp_counts_s { 1625232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1626215976Sjmallett uint64_t reserved_39_63 : 25; 1627215976Sjmallett uint64_t fcnt : 7; /**< Number of words in the Instruction FIFO. */ 1628215976Sjmallett uint64_t dbell : 32; /**< Number of available words of Instructions to read. */ 1629215976Sjmallett#else 1630215976Sjmallett uint64_t dbell : 32; 1631215976Sjmallett uint64_t fcnt : 7; 1632215976Sjmallett uint64_t reserved_39_63 : 25; 1633215976Sjmallett#endif 1634215976Sjmallett } s; 1635215976Sjmallett struct cvmx_npi_dma_highp_counts_s cn30xx; 1636215976Sjmallett struct cvmx_npi_dma_highp_counts_s cn31xx; 1637215976Sjmallett struct cvmx_npi_dma_highp_counts_s cn38xx; 1638215976Sjmallett struct cvmx_npi_dma_highp_counts_s cn38xxp2; 1639215976Sjmallett struct cvmx_npi_dma_highp_counts_s cn50xx; 1640215976Sjmallett struct cvmx_npi_dma_highp_counts_s cn58xx; 1641215976Sjmallett struct cvmx_npi_dma_highp_counts_s cn58xxp1; 1642215976Sjmallett}; 1643215976Sjmalletttypedef union cvmx_npi_dma_highp_counts cvmx_npi_dma_highp_counts_t; 1644215976Sjmallett 1645215976Sjmallett/** 1646215976Sjmallett * cvmx_npi_dma_highp_naddr 1647215976Sjmallett * 1648215976Sjmallett * NPI_DMA_HIGHP_NADDR = NPI's High Priority DMA Next Ichunk Address 1649215976Sjmallett * 1650215976Sjmallett * Place NPI will read the next Ichunk data from. This is valid when state is 0 1651215976Sjmallett */ 1652232812Sjmallettunion cvmx_npi_dma_highp_naddr { 1653215976Sjmallett uint64_t u64; 1654232812Sjmallett struct cvmx_npi_dma_highp_naddr_s { 1655232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1656215976Sjmallett uint64_t reserved_40_63 : 24; 1657215976Sjmallett uint64_t state : 4; /**< The DMA instruction engine state vector. 1658215976Sjmallett Typical value is 0 (IDLE). */ 1659215976Sjmallett uint64_t addr : 36; /**< The next L2C address to read DMA instructions 1660215976Sjmallett from for the High Priority DMA engine. */ 1661215976Sjmallett#else 1662215976Sjmallett uint64_t addr : 36; 1663215976Sjmallett uint64_t state : 4; 1664215976Sjmallett uint64_t reserved_40_63 : 24; 1665215976Sjmallett#endif 1666215976Sjmallett } s; 1667215976Sjmallett struct cvmx_npi_dma_highp_naddr_s cn30xx; 1668215976Sjmallett struct cvmx_npi_dma_highp_naddr_s cn31xx; 1669215976Sjmallett struct cvmx_npi_dma_highp_naddr_s cn38xx; 1670215976Sjmallett struct cvmx_npi_dma_highp_naddr_s cn38xxp2; 1671215976Sjmallett struct cvmx_npi_dma_highp_naddr_s cn50xx; 1672215976Sjmallett struct cvmx_npi_dma_highp_naddr_s cn58xx; 1673215976Sjmallett struct cvmx_npi_dma_highp_naddr_s cn58xxp1; 1674215976Sjmallett}; 1675215976Sjmalletttypedef union cvmx_npi_dma_highp_naddr cvmx_npi_dma_highp_naddr_t; 1676215976Sjmallett 1677215976Sjmallett/** 1678215976Sjmallett * cvmx_npi_dma_lowp_counts 1679215976Sjmallett * 1680215976Sjmallett * NPI_DMA_LOWP_COUNTS = NPI's Low Priority DMA Counts 1681215976Sjmallett * 1682215976Sjmallett * Values for determing the number of instructions for Low Priority DMA in the NPI. 1683215976Sjmallett */ 1684232812Sjmallettunion cvmx_npi_dma_lowp_counts { 1685215976Sjmallett uint64_t u64; 1686232812Sjmallett struct cvmx_npi_dma_lowp_counts_s { 1687232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1688215976Sjmallett uint64_t reserved_39_63 : 25; 1689215976Sjmallett uint64_t fcnt : 7; /**< Number of words in the Instruction FIFO. */ 1690215976Sjmallett uint64_t dbell : 32; /**< Number of available words of Instructions to read. */ 1691215976Sjmallett#else 1692215976Sjmallett uint64_t dbell : 32; 1693215976Sjmallett uint64_t fcnt : 7; 1694215976Sjmallett uint64_t reserved_39_63 : 25; 1695215976Sjmallett#endif 1696215976Sjmallett } s; 1697215976Sjmallett struct cvmx_npi_dma_lowp_counts_s cn30xx; 1698215976Sjmallett struct cvmx_npi_dma_lowp_counts_s cn31xx; 1699215976Sjmallett struct cvmx_npi_dma_lowp_counts_s cn38xx; 1700215976Sjmallett struct cvmx_npi_dma_lowp_counts_s cn38xxp2; 1701215976Sjmallett struct cvmx_npi_dma_lowp_counts_s cn50xx; 1702215976Sjmallett struct cvmx_npi_dma_lowp_counts_s cn58xx; 1703215976Sjmallett struct cvmx_npi_dma_lowp_counts_s cn58xxp1; 1704215976Sjmallett}; 1705215976Sjmalletttypedef union cvmx_npi_dma_lowp_counts cvmx_npi_dma_lowp_counts_t; 1706215976Sjmallett 1707215976Sjmallett/** 1708215976Sjmallett * cvmx_npi_dma_lowp_naddr 1709215976Sjmallett * 1710215976Sjmallett * NPI_DMA_LOWP_NADDR = NPI's Low Priority DMA Next Ichunk Address 1711215976Sjmallett * 1712215976Sjmallett * Place NPI will read the next Ichunk data from. This is valid when state is 0 1713215976Sjmallett */ 1714232812Sjmallettunion cvmx_npi_dma_lowp_naddr { 1715215976Sjmallett uint64_t u64; 1716232812Sjmallett struct cvmx_npi_dma_lowp_naddr_s { 1717232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1718215976Sjmallett uint64_t reserved_40_63 : 24; 1719215976Sjmallett uint64_t state : 4; /**< The DMA instruction engine state vector. 1720215976Sjmallett Typical value is 0 (IDLE). */ 1721215976Sjmallett uint64_t addr : 36; /**< The next L2C address to read DMA instructions 1722215976Sjmallett from for the Low Priority DMA engine. */ 1723215976Sjmallett#else 1724215976Sjmallett uint64_t addr : 36; 1725215976Sjmallett uint64_t state : 4; 1726215976Sjmallett uint64_t reserved_40_63 : 24; 1727215976Sjmallett#endif 1728215976Sjmallett } s; 1729215976Sjmallett struct cvmx_npi_dma_lowp_naddr_s cn30xx; 1730215976Sjmallett struct cvmx_npi_dma_lowp_naddr_s cn31xx; 1731215976Sjmallett struct cvmx_npi_dma_lowp_naddr_s cn38xx; 1732215976Sjmallett struct cvmx_npi_dma_lowp_naddr_s cn38xxp2; 1733215976Sjmallett struct cvmx_npi_dma_lowp_naddr_s cn50xx; 1734215976Sjmallett struct cvmx_npi_dma_lowp_naddr_s cn58xx; 1735215976Sjmallett struct cvmx_npi_dma_lowp_naddr_s cn58xxp1; 1736215976Sjmallett}; 1737215976Sjmalletttypedef union cvmx_npi_dma_lowp_naddr cvmx_npi_dma_lowp_naddr_t; 1738215976Sjmallett 1739215976Sjmallett/** 1740215976Sjmallett * cvmx_npi_highp_dbell 1741215976Sjmallett * 1742215976Sjmallett * NPI_HIGHP_DBELL = High Priority Door Bell 1743215976Sjmallett * 1744215976Sjmallett * The door bell register for the high priority DMA queue. 1745215976Sjmallett */ 1746232812Sjmallettunion cvmx_npi_highp_dbell { 1747215976Sjmallett uint64_t u64; 1748232812Sjmallett struct cvmx_npi_highp_dbell_s { 1749232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1750215976Sjmallett uint64_t reserved_16_63 : 48; 1751215976Sjmallett uint64_t dbell : 16; /**< The value written to this register is added to the 1752215976Sjmallett number of 8byte words to be read and processes for 1753215976Sjmallett the high priority dma queue. */ 1754215976Sjmallett#else 1755215976Sjmallett uint64_t dbell : 16; 1756215976Sjmallett uint64_t reserved_16_63 : 48; 1757215976Sjmallett#endif 1758215976Sjmallett } s; 1759215976Sjmallett struct cvmx_npi_highp_dbell_s cn30xx; 1760215976Sjmallett struct cvmx_npi_highp_dbell_s cn31xx; 1761215976Sjmallett struct cvmx_npi_highp_dbell_s cn38xx; 1762215976Sjmallett struct cvmx_npi_highp_dbell_s cn38xxp2; 1763215976Sjmallett struct cvmx_npi_highp_dbell_s cn50xx; 1764215976Sjmallett struct cvmx_npi_highp_dbell_s cn58xx; 1765215976Sjmallett struct cvmx_npi_highp_dbell_s cn58xxp1; 1766215976Sjmallett}; 1767215976Sjmalletttypedef union cvmx_npi_highp_dbell cvmx_npi_highp_dbell_t; 1768215976Sjmallett 1769215976Sjmallett/** 1770215976Sjmallett * cvmx_npi_highp_ibuff_saddr 1771215976Sjmallett * 1772215976Sjmallett * NPI_HIGHP_IBUFF_SADDR = DMA High Priority Instruction Buffer Starting Address 1773215976Sjmallett * 1774215976Sjmallett * The address to start reading Instructions from for HIGHP. 1775215976Sjmallett */ 1776232812Sjmallettunion cvmx_npi_highp_ibuff_saddr { 1777215976Sjmallett uint64_t u64; 1778232812Sjmallett struct cvmx_npi_highp_ibuff_saddr_s { 1779232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1780215976Sjmallett uint64_t reserved_36_63 : 28; 1781215976Sjmallett uint64_t saddr : 36; /**< The starting address to read the first instruction. */ 1782215976Sjmallett#else 1783215976Sjmallett uint64_t saddr : 36; 1784215976Sjmallett uint64_t reserved_36_63 : 28; 1785215976Sjmallett#endif 1786215976Sjmallett } s; 1787215976Sjmallett struct cvmx_npi_highp_ibuff_saddr_s cn30xx; 1788215976Sjmallett struct cvmx_npi_highp_ibuff_saddr_s cn31xx; 1789215976Sjmallett struct cvmx_npi_highp_ibuff_saddr_s cn38xx; 1790215976Sjmallett struct cvmx_npi_highp_ibuff_saddr_s cn38xxp2; 1791215976Sjmallett struct cvmx_npi_highp_ibuff_saddr_s cn50xx; 1792215976Sjmallett struct cvmx_npi_highp_ibuff_saddr_s cn58xx; 1793215976Sjmallett struct cvmx_npi_highp_ibuff_saddr_s cn58xxp1; 1794215976Sjmallett}; 1795215976Sjmalletttypedef union cvmx_npi_highp_ibuff_saddr cvmx_npi_highp_ibuff_saddr_t; 1796215976Sjmallett 1797215976Sjmallett/** 1798215976Sjmallett * cvmx_npi_input_control 1799215976Sjmallett * 1800215976Sjmallett * NPI_INPUT_CONTROL = NPI's Input Control Register 1801215976Sjmallett * 1802215976Sjmallett * Control for reads for gather list and instructions. 1803215976Sjmallett */ 1804232812Sjmallettunion cvmx_npi_input_control { 1805215976Sjmallett uint64_t u64; 1806232812Sjmallett struct cvmx_npi_input_control_s { 1807232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1808215976Sjmallett uint64_t reserved_23_63 : 41; 1809215976Sjmallett uint64_t pkt_rr : 1; /**< When set '1' the input packet selection will be 1810215976Sjmallett made with a Round Robin arbitration. When '0' 1811215976Sjmallett the input packet port is fixed in priority, 1812215976Sjmallett where the lower port number has higher priority. 1813215976Sjmallett PASS3 Field */ 1814215976Sjmallett uint64_t pbp_dhi : 13; /**< Field when in [PBP] is set to be used in 1815215976Sjmallett calculating a DPTR. */ 1816215976Sjmallett uint64_t d_nsr : 1; /**< Enables '1' NoSnoop for reading of 1817215976Sjmallett gather data. */ 1818215976Sjmallett uint64_t d_esr : 2; /**< The Endian-Swap-Mode for reading of 1819215976Sjmallett gather data. */ 1820215976Sjmallett uint64_t d_ror : 1; /**< Enables '1' Relaxed Ordering for reading of 1821215976Sjmallett gather data. */ 1822215976Sjmallett uint64_t use_csr : 1; /**< When set '1' the csr value will be used for 1823215976Sjmallett ROR, ESR, and NSR. When clear '0' the value in 1824215976Sjmallett DPTR will be used. In turn the bits not used for 1825215976Sjmallett ROR, ESR, and NSR, will be used for bits [63:60] 1826215976Sjmallett of the address used to fetch packet data. */ 1827215976Sjmallett uint64_t nsr : 1; /**< Enables '1' NoSnoop for reading of 1828215976Sjmallett gather list and gather instruction. */ 1829215976Sjmallett uint64_t esr : 2; /**< The Endian-Swap-Mode for reading of 1830215976Sjmallett gather list and gather instruction. */ 1831215976Sjmallett uint64_t ror : 1; /**< Enables '1' Relaxed Ordering for reading of 1832215976Sjmallett gather list and gather instruction. */ 1833215976Sjmallett#else 1834215976Sjmallett uint64_t ror : 1; 1835215976Sjmallett uint64_t esr : 2; 1836215976Sjmallett uint64_t nsr : 1; 1837215976Sjmallett uint64_t use_csr : 1; 1838215976Sjmallett uint64_t d_ror : 1; 1839215976Sjmallett uint64_t d_esr : 2; 1840215976Sjmallett uint64_t d_nsr : 1; 1841215976Sjmallett uint64_t pbp_dhi : 13; 1842215976Sjmallett uint64_t pkt_rr : 1; 1843215976Sjmallett uint64_t reserved_23_63 : 41; 1844215976Sjmallett#endif 1845215976Sjmallett } s; 1846232812Sjmallett struct cvmx_npi_input_control_cn30xx { 1847232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1848215976Sjmallett uint64_t reserved_22_63 : 42; 1849215976Sjmallett uint64_t pbp_dhi : 13; /**< Field when in [PBP] is set to be used in 1850215976Sjmallett calculating a DPTR. */ 1851215976Sjmallett uint64_t d_nsr : 1; /**< Enables '1' NoSnoop for reading of 1852215976Sjmallett gather data. */ 1853215976Sjmallett uint64_t d_esr : 2; /**< The Endian-Swap-Mode for reading of 1854215976Sjmallett gather data. */ 1855215976Sjmallett uint64_t d_ror : 1; /**< Enables '1' Relaxed Ordering for reading of 1856215976Sjmallett gather data. */ 1857215976Sjmallett uint64_t use_csr : 1; /**< When set '1' the csr value will be used for 1858215976Sjmallett ROR, ESR, and NSR. When clear '0' the value in 1859215976Sjmallett DPTR will be used. In turn the bits not used for 1860215976Sjmallett ROR, ESR, and NSR, will be used for bits [63:60] 1861215976Sjmallett of the address used to fetch packet data. */ 1862215976Sjmallett uint64_t nsr : 1; /**< Enables '1' NoSnoop for reading of 1863215976Sjmallett gather list and gather instruction. */ 1864215976Sjmallett uint64_t esr : 2; /**< The Endian-Swap-Mode for reading of 1865215976Sjmallett gather list and gather instruction. */ 1866215976Sjmallett uint64_t ror : 1; /**< Enables '1' Relaxed Ordering for reading of 1867215976Sjmallett gather list and gather instruction. */ 1868215976Sjmallett#else 1869215976Sjmallett uint64_t ror : 1; 1870215976Sjmallett uint64_t esr : 2; 1871215976Sjmallett uint64_t nsr : 1; 1872215976Sjmallett uint64_t use_csr : 1; 1873215976Sjmallett uint64_t d_ror : 1; 1874215976Sjmallett uint64_t d_esr : 2; 1875215976Sjmallett uint64_t d_nsr : 1; 1876215976Sjmallett uint64_t pbp_dhi : 13; 1877215976Sjmallett uint64_t reserved_22_63 : 42; 1878215976Sjmallett#endif 1879215976Sjmallett } cn30xx; 1880215976Sjmallett struct cvmx_npi_input_control_cn30xx cn31xx; 1881215976Sjmallett struct cvmx_npi_input_control_s cn38xx; 1882215976Sjmallett struct cvmx_npi_input_control_cn30xx cn38xxp2; 1883215976Sjmallett struct cvmx_npi_input_control_s cn50xx; 1884215976Sjmallett struct cvmx_npi_input_control_s cn58xx; 1885215976Sjmallett struct cvmx_npi_input_control_s cn58xxp1; 1886215976Sjmallett}; 1887215976Sjmalletttypedef union cvmx_npi_input_control cvmx_npi_input_control_t; 1888215976Sjmallett 1889215976Sjmallett/** 1890215976Sjmallett * cvmx_npi_int_enb 1891215976Sjmallett * 1892215976Sjmallett * NPI_INTERRUPT_ENB = NPI's Interrupt Enable Register 1893215976Sjmallett * 1894215976Sjmallett * Used to enable the various interrupting conditions of NPI 1895215976Sjmallett */ 1896232812Sjmallettunion cvmx_npi_int_enb { 1897215976Sjmallett uint64_t u64; 1898232812Sjmallett struct cvmx_npi_int_enb_s { 1899232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 1900215976Sjmallett uint64_t reserved_62_63 : 2; 1901215976Sjmallett uint64_t q1_a_f : 1; /**< Enables NPI_INT_SUM[Q1_A_F] to generate an 1902215976Sjmallett interrupt. */ 1903215976Sjmallett uint64_t q1_s_e : 1; /**< Enables NPI_INT_SUM[Q1_S_E] to generate an 1904215976Sjmallett interrupt. */ 1905215976Sjmallett uint64_t pdf_p_f : 1; /**< Enables NPI_INT_SUM[PDF_P_F] to generate an 1906215976Sjmallett interrupt. */ 1907215976Sjmallett uint64_t pdf_p_e : 1; /**< Enables NPI_INT_SUM[PDF_P_E] to generate an 1908215976Sjmallett interrupt. */ 1909215976Sjmallett uint64_t pcf_p_f : 1; /**< Enables NPI_INT_SUM[PCF_P_F] to generate an 1910215976Sjmallett interrupt. */ 1911215976Sjmallett uint64_t pcf_p_e : 1; /**< Enables NPI_INT_SUM[PCF_P_E] to generate an 1912215976Sjmallett interrupt. */ 1913215976Sjmallett uint64_t rdx_s_e : 1; /**< Enables NPI_INT_SUM[RDX_S_E] to generate an 1914215976Sjmallett interrupt. */ 1915215976Sjmallett uint64_t rwx_s_e : 1; /**< Enables NPI_INT_SUM[RWX_S_E] to generate an 1916215976Sjmallett interrupt. */ 1917215976Sjmallett uint64_t pnc_a_f : 1; /**< Enables NPI_INT_SUM[PNC_A_F] to generate an 1918215976Sjmallett interrupt. */ 1919215976Sjmallett uint64_t pnc_s_e : 1; /**< Enables NPI_INT_SUM[PNC_S_E] to generate an 1920215976Sjmallett interrupt. */ 1921215976Sjmallett uint64_t com_a_f : 1; /**< Enables NPI_INT_SUM[COM_A_F] to generate an 1922215976Sjmallett interrupt. */ 1923215976Sjmallett uint64_t com_s_e : 1; /**< Enables NPI_INT_SUM[COM_S_E] to generate an 1924215976Sjmallett interrupt. */ 1925215976Sjmallett uint64_t q3_a_f : 1; /**< Enables NPI_INT_SUM[Q3_A_F] to generate an 1926215976Sjmallett interrupt. */ 1927215976Sjmallett uint64_t q3_s_e : 1; /**< Enables NPI_INT_SUM[Q3_S_E] to generate an 1928215976Sjmallett interrupt. */ 1929215976Sjmallett uint64_t q2_a_f : 1; /**< Enables NPI_INT_SUM[Q2_A_F] to generate an 1930215976Sjmallett interrupt. */ 1931215976Sjmallett uint64_t q2_s_e : 1; /**< Enables NPI_INT_SUM[Q2_S_E] to generate an 1932215976Sjmallett interrupt. */ 1933215976Sjmallett uint64_t pcr_a_f : 1; /**< Enables NPI_INT_SUM[PCR_A_F] to generate an 1934215976Sjmallett interrupt. */ 1935215976Sjmallett uint64_t pcr_s_e : 1; /**< Enables NPI_INT_SUM[PCR_S_E] to generate an 1936215976Sjmallett interrupt. */ 1937215976Sjmallett uint64_t fcr_a_f : 1; /**< Enables NPI_INT_SUM[FCR_A_F] to generate an 1938215976Sjmallett interrupt. */ 1939215976Sjmallett uint64_t fcr_s_e : 1; /**< Enables NPI_INT_SUM[FCR_S_E] to generate an 1940215976Sjmallett interrupt. */ 1941215976Sjmallett uint64_t iobdma : 1; /**< Enables NPI_INT_SUM[IOBDMA] to generate an 1942215976Sjmallett interrupt. */ 1943215976Sjmallett uint64_t p_dperr : 1; /**< Enables NPI_INT_SUM[P_DPERR] to generate an 1944215976Sjmallett interrupt. */ 1945215976Sjmallett uint64_t win_rto : 1; /**< Enables NPI_INT_SUM[WIN_RTO] to generate an 1946215976Sjmallett interrupt. */ 1947215976Sjmallett uint64_t i3_pperr : 1; /**< Enables NPI_INT_SUM[I3_PPERR] to generate an 1948215976Sjmallett interrupt. */ 1949215976Sjmallett uint64_t i2_pperr : 1; /**< Enables NPI_INT_SUM[I2_PPERR] to generate an 1950215976Sjmallett interrupt. */ 1951215976Sjmallett uint64_t i1_pperr : 1; /**< Enables NPI_INT_SUM[I1_PPERR] to generate an 1952215976Sjmallett interrupt. */ 1953215976Sjmallett uint64_t i0_pperr : 1; /**< Enables NPI_INT_SUM[I0_PPERR] to generate an 1954215976Sjmallett interrupt. */ 1955215976Sjmallett uint64_t p3_ptout : 1; /**< Enables NPI_INT_SUM[P3_PTOUT] to generate an 1956215976Sjmallett interrupt. */ 1957215976Sjmallett uint64_t p2_ptout : 1; /**< Enables NPI_INT_SUM[P2_PTOUT] to generate an 1958215976Sjmallett interrupt. */ 1959215976Sjmallett uint64_t p1_ptout : 1; /**< Enables NPI_INT_SUM[P1_PTOUT] to generate an 1960215976Sjmallett interrupt. */ 1961215976Sjmallett uint64_t p0_ptout : 1; /**< Enables NPI_INT_SUM[P0_PTOUT] to generate an 1962215976Sjmallett interrupt. */ 1963215976Sjmallett uint64_t p3_pperr : 1; /**< Enables NPI_INT_SUM[P3_PPERR] to generate an 1964215976Sjmallett interrupt. */ 1965215976Sjmallett uint64_t p2_pperr : 1; /**< Enables NPI_INT_SUM[P2_PPERR] to generate an 1966215976Sjmallett interrupt. */ 1967215976Sjmallett uint64_t p1_pperr : 1; /**< Enables NPI_INT_SUM[P1_PPERR] to generate an 1968215976Sjmallett interrupt. */ 1969215976Sjmallett uint64_t p0_pperr : 1; /**< Enables NPI_INT_SUM[P0_PPERR] to generate an 1970215976Sjmallett interrupt. */ 1971215976Sjmallett uint64_t g3_rtout : 1; /**< Enables NPI_INT_SUM[G3_RTOUT] to generate an 1972215976Sjmallett interrupt. */ 1973215976Sjmallett uint64_t g2_rtout : 1; /**< Enables NPI_INT_SUM[G2_RTOUT] to generate an 1974215976Sjmallett interrupt. */ 1975215976Sjmallett uint64_t g1_rtout : 1; /**< Enables NPI_INT_SUM[G1_RTOUT] to generate an 1976215976Sjmallett interrupt. */ 1977215976Sjmallett uint64_t g0_rtout : 1; /**< Enables NPI_INT_SUM[G0_RTOUT] to generate an 1978215976Sjmallett interrupt. */ 1979215976Sjmallett uint64_t p3_perr : 1; /**< Enables NPI_INT_SUM[P3_PERR] to generate an 1980215976Sjmallett interrupt. */ 1981215976Sjmallett uint64_t p2_perr : 1; /**< Enables NPI_INT_SUM[P2_PERR] to generate an 1982215976Sjmallett interrupt. */ 1983215976Sjmallett uint64_t p1_perr : 1; /**< Enables NPI_INT_SUM[P1_PERR] to generate an 1984215976Sjmallett interrupt. */ 1985215976Sjmallett uint64_t p0_perr : 1; /**< Enables NPI_INT_SUM[P0_PERR] to generate an 1986215976Sjmallett interrupt. */ 1987215976Sjmallett uint64_t p3_rtout : 1; /**< Enables NPI_INT_SUM[P3_RTOUT] to generate an 1988215976Sjmallett interrupt. */ 1989215976Sjmallett uint64_t p2_rtout : 1; /**< Enables NPI_INT_SUM[P2_RTOUT] to generate an 1990215976Sjmallett interrupt. */ 1991215976Sjmallett uint64_t p1_rtout : 1; /**< Enables NPI_INT_SUM[P1_RTOUT] to generate an 1992215976Sjmallett interrupt. */ 1993215976Sjmallett uint64_t p0_rtout : 1; /**< Enables NPI_INT_SUM[P0_RTOUT] to generate an 1994215976Sjmallett interrupt. */ 1995215976Sjmallett uint64_t i3_overf : 1; /**< Enables NPI_INT_SUM[I3_OVERF] to generate an 1996215976Sjmallett interrupt. */ 1997215976Sjmallett uint64_t i2_overf : 1; /**< Enables NPI_INT_SUM[I2_OVERF] to generate an 1998215976Sjmallett interrupt. */ 1999215976Sjmallett uint64_t i1_overf : 1; /**< Enables NPI_INT_SUM[I1_OVERF] to generate an 2000215976Sjmallett interrupt. */ 2001215976Sjmallett uint64_t i0_overf : 1; /**< Enables NPI_INT_SUM[I0_OVERF] to generate an 2002215976Sjmallett interrupt. */ 2003215976Sjmallett uint64_t i3_rtout : 1; /**< Enables NPI_INT_SUM[I3_RTOUT] to generate an 2004215976Sjmallett interrupt. */ 2005215976Sjmallett uint64_t i2_rtout : 1; /**< Enables NPI_INT_SUM[I2_RTOUT] to generate an 2006215976Sjmallett interrupt. */ 2007215976Sjmallett uint64_t i1_rtout : 1; /**< Enables NPI_INT_SUM[I1_RTOUT] to generate an 2008215976Sjmallett interrupt. */ 2009215976Sjmallett uint64_t i0_rtout : 1; /**< Enables NPI_INT_SUM[I0_RTOUT] to generate an 2010215976Sjmallett interrupt. */ 2011215976Sjmallett uint64_t po3_2sml : 1; /**< Enables NPI_INT_SUM[PO3_2SML] to generate an 2012215976Sjmallett interrupt. */ 2013215976Sjmallett uint64_t po2_2sml : 1; /**< Enables NPI_INT_SUM[PO2_2SML] to generate an 2014215976Sjmallett interrupt. */ 2015215976Sjmallett uint64_t po1_2sml : 1; /**< Enables NPI_INT_SUM[PO1_2SML] to generate an 2016215976Sjmallett interrupt. */ 2017215976Sjmallett uint64_t po0_2sml : 1; /**< Enables NPI_INT_SUM[PO0_2SML] to generate an 2018215976Sjmallett interrupt. */ 2019215976Sjmallett uint64_t pci_rsl : 1; /**< Enables NPI_INT_SUM[PCI_RSL] to generate an 2020215976Sjmallett interrupt. */ 2021215976Sjmallett uint64_t rml_wto : 1; /**< Enables NPI_INT_SUM[RML_WTO] to generate an 2022215976Sjmallett interrupt. */ 2023215976Sjmallett uint64_t rml_rto : 1; /**< Enables NPI_INT_SUM[RML_RTO] to generate an 2024215976Sjmallett interrupt. */ 2025215976Sjmallett#else 2026215976Sjmallett uint64_t rml_rto : 1; 2027215976Sjmallett uint64_t rml_wto : 1; 2028215976Sjmallett uint64_t pci_rsl : 1; 2029215976Sjmallett uint64_t po0_2sml : 1; 2030215976Sjmallett uint64_t po1_2sml : 1; 2031215976Sjmallett uint64_t po2_2sml : 1; 2032215976Sjmallett uint64_t po3_2sml : 1; 2033215976Sjmallett uint64_t i0_rtout : 1; 2034215976Sjmallett uint64_t i1_rtout : 1; 2035215976Sjmallett uint64_t i2_rtout : 1; 2036215976Sjmallett uint64_t i3_rtout : 1; 2037215976Sjmallett uint64_t i0_overf : 1; 2038215976Sjmallett uint64_t i1_overf : 1; 2039215976Sjmallett uint64_t i2_overf : 1; 2040215976Sjmallett uint64_t i3_overf : 1; 2041215976Sjmallett uint64_t p0_rtout : 1; 2042215976Sjmallett uint64_t p1_rtout : 1; 2043215976Sjmallett uint64_t p2_rtout : 1; 2044215976Sjmallett uint64_t p3_rtout : 1; 2045215976Sjmallett uint64_t p0_perr : 1; 2046215976Sjmallett uint64_t p1_perr : 1; 2047215976Sjmallett uint64_t p2_perr : 1; 2048215976Sjmallett uint64_t p3_perr : 1; 2049215976Sjmallett uint64_t g0_rtout : 1; 2050215976Sjmallett uint64_t g1_rtout : 1; 2051215976Sjmallett uint64_t g2_rtout : 1; 2052215976Sjmallett uint64_t g3_rtout : 1; 2053215976Sjmallett uint64_t p0_pperr : 1; 2054215976Sjmallett uint64_t p1_pperr : 1; 2055215976Sjmallett uint64_t p2_pperr : 1; 2056215976Sjmallett uint64_t p3_pperr : 1; 2057215976Sjmallett uint64_t p0_ptout : 1; 2058215976Sjmallett uint64_t p1_ptout : 1; 2059215976Sjmallett uint64_t p2_ptout : 1; 2060215976Sjmallett uint64_t p3_ptout : 1; 2061215976Sjmallett uint64_t i0_pperr : 1; 2062215976Sjmallett uint64_t i1_pperr : 1; 2063215976Sjmallett uint64_t i2_pperr : 1; 2064215976Sjmallett uint64_t i3_pperr : 1; 2065215976Sjmallett uint64_t win_rto : 1; 2066215976Sjmallett uint64_t p_dperr : 1; 2067215976Sjmallett uint64_t iobdma : 1; 2068215976Sjmallett uint64_t fcr_s_e : 1; 2069215976Sjmallett uint64_t fcr_a_f : 1; 2070215976Sjmallett uint64_t pcr_s_e : 1; 2071215976Sjmallett uint64_t pcr_a_f : 1; 2072215976Sjmallett uint64_t q2_s_e : 1; 2073215976Sjmallett uint64_t q2_a_f : 1; 2074215976Sjmallett uint64_t q3_s_e : 1; 2075215976Sjmallett uint64_t q3_a_f : 1; 2076215976Sjmallett uint64_t com_s_e : 1; 2077215976Sjmallett uint64_t com_a_f : 1; 2078215976Sjmallett uint64_t pnc_s_e : 1; 2079215976Sjmallett uint64_t pnc_a_f : 1; 2080215976Sjmallett uint64_t rwx_s_e : 1; 2081215976Sjmallett uint64_t rdx_s_e : 1; 2082215976Sjmallett uint64_t pcf_p_e : 1; 2083215976Sjmallett uint64_t pcf_p_f : 1; 2084215976Sjmallett uint64_t pdf_p_e : 1; 2085215976Sjmallett uint64_t pdf_p_f : 1; 2086215976Sjmallett uint64_t q1_s_e : 1; 2087215976Sjmallett uint64_t q1_a_f : 1; 2088215976Sjmallett uint64_t reserved_62_63 : 2; 2089215976Sjmallett#endif 2090215976Sjmallett } s; 2091232812Sjmallett struct cvmx_npi_int_enb_cn30xx { 2092232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2093215976Sjmallett uint64_t reserved_62_63 : 2; 2094215976Sjmallett uint64_t q1_a_f : 1; /**< Enables NPI_INT_SUM[Q1_A_F] to generate an 2095215976Sjmallett interrupt. */ 2096215976Sjmallett uint64_t q1_s_e : 1; /**< Enables NPI_INT_SUM[Q1_S_E] to generate an 2097215976Sjmallett interrupt. */ 2098215976Sjmallett uint64_t pdf_p_f : 1; /**< Enables NPI_INT_SUM[PDF_P_F] to generate an 2099215976Sjmallett interrupt. */ 2100215976Sjmallett uint64_t pdf_p_e : 1; /**< Enables NPI_INT_SUM[PDF_P_E] to generate an 2101215976Sjmallett interrupt. */ 2102215976Sjmallett uint64_t pcf_p_f : 1; /**< Enables NPI_INT_SUM[PCF_P_F] to generate an 2103215976Sjmallett interrupt. */ 2104215976Sjmallett uint64_t pcf_p_e : 1; /**< Enables NPI_INT_SUM[PCF_P_E] to generate an 2105215976Sjmallett interrupt. */ 2106215976Sjmallett uint64_t rdx_s_e : 1; /**< Enables NPI_INT_SUM[RDX_S_E] to generate an 2107215976Sjmallett interrupt. */ 2108215976Sjmallett uint64_t rwx_s_e : 1; /**< Enables NPI_INT_SUM[RWX_S_E] to generate an 2109215976Sjmallett interrupt. */ 2110215976Sjmallett uint64_t pnc_a_f : 1; /**< Enables NPI_INT_SUM[PNC_A_F] to generate an 2111215976Sjmallett interrupt. */ 2112215976Sjmallett uint64_t pnc_s_e : 1; /**< Enables NPI_INT_SUM[PNC_S_E] to generate an 2113215976Sjmallett interrupt. */ 2114215976Sjmallett uint64_t com_a_f : 1; /**< Enables NPI_INT_SUM[COM_A_F] to generate an 2115215976Sjmallett interrupt. */ 2116215976Sjmallett uint64_t com_s_e : 1; /**< Enables NPI_INT_SUM[COM_S_E] to generate an 2117215976Sjmallett interrupt. */ 2118215976Sjmallett uint64_t q3_a_f : 1; /**< Enables NPI_INT_SUM[Q3_A_F] to generate an 2119215976Sjmallett interrupt. */ 2120215976Sjmallett uint64_t q3_s_e : 1; /**< Enables NPI_INT_SUM[Q3_S_E] to generate an 2121215976Sjmallett interrupt. */ 2122215976Sjmallett uint64_t q2_a_f : 1; /**< Enables NPI_INT_SUM[Q2_A_F] to generate an 2123215976Sjmallett interrupt. */ 2124215976Sjmallett uint64_t q2_s_e : 1; /**< Enables NPI_INT_SUM[Q2_S_E] to generate an 2125215976Sjmallett interrupt. */ 2126215976Sjmallett uint64_t pcr_a_f : 1; /**< Enables NPI_INT_SUM[PCR_A_F] to generate an 2127215976Sjmallett interrupt. */ 2128215976Sjmallett uint64_t pcr_s_e : 1; /**< Enables NPI_INT_SUM[PCR_S_E] to generate an 2129215976Sjmallett interrupt. */ 2130215976Sjmallett uint64_t fcr_a_f : 1; /**< Enables NPI_INT_SUM[FCR_A_F] to generate an 2131215976Sjmallett interrupt. */ 2132215976Sjmallett uint64_t fcr_s_e : 1; /**< Enables NPI_INT_SUM[FCR_S_E] to generate an 2133215976Sjmallett interrupt. */ 2134215976Sjmallett uint64_t iobdma : 1; /**< Enables NPI_INT_SUM[IOBDMA] to generate an 2135215976Sjmallett interrupt. */ 2136215976Sjmallett uint64_t p_dperr : 1; /**< Enables NPI_INT_SUM[P_DPERR] to generate an 2137215976Sjmallett interrupt. */ 2138215976Sjmallett uint64_t win_rto : 1; /**< Enables NPI_INT_SUM[WIN_RTO] to generate an 2139215976Sjmallett interrupt. */ 2140215976Sjmallett uint64_t reserved_36_38 : 3; 2141215976Sjmallett uint64_t i0_pperr : 1; /**< Enables NPI_INT_SUM[I0_PPERR] to generate an 2142215976Sjmallett interrupt. */ 2143215976Sjmallett uint64_t reserved_32_34 : 3; 2144215976Sjmallett uint64_t p0_ptout : 1; /**< Enables NPI_INT_SUM[P0_PTOUT] to generate an 2145215976Sjmallett interrupt. */ 2146215976Sjmallett uint64_t reserved_28_30 : 3; 2147215976Sjmallett uint64_t p0_pperr : 1; /**< Enables NPI_INT_SUM[P0_PPERR] to generate an 2148215976Sjmallett interrupt. */ 2149215976Sjmallett uint64_t reserved_24_26 : 3; 2150215976Sjmallett uint64_t g0_rtout : 1; /**< Enables NPI_INT_SUM[G0_RTOUT] to generate an 2151215976Sjmallett interrupt. */ 2152215976Sjmallett uint64_t reserved_20_22 : 3; 2153215976Sjmallett uint64_t p0_perr : 1; /**< Enables NPI_INT_SUM[P0_PERR] to generate an 2154215976Sjmallett interrupt. */ 2155215976Sjmallett uint64_t reserved_16_18 : 3; 2156215976Sjmallett uint64_t p0_rtout : 1; /**< Enables NPI_INT_SUM[P0_RTOUT] to generate an 2157215976Sjmallett interrupt. */ 2158215976Sjmallett uint64_t reserved_12_14 : 3; 2159215976Sjmallett uint64_t i0_overf : 1; /**< Enables NPI_INT_SUM[I0_OVERF] to generate an 2160215976Sjmallett interrupt. */ 2161215976Sjmallett uint64_t reserved_8_10 : 3; 2162215976Sjmallett uint64_t i0_rtout : 1; /**< Enables NPI_INT_SUM[I0_RTOUT] to generate an 2163215976Sjmallett interrupt. */ 2164215976Sjmallett uint64_t reserved_4_6 : 3; 2165215976Sjmallett uint64_t po0_2sml : 1; /**< Enables NPI_INT_SUM[PO0_2SML] to generate an 2166215976Sjmallett interrupt. */ 2167215976Sjmallett uint64_t pci_rsl : 1; /**< Enables NPI_INT_SUM[PCI_RSL] to generate an 2168215976Sjmallett interrupt. */ 2169215976Sjmallett uint64_t rml_wto : 1; /**< Enables NPI_INT_SUM[RML_WTO] to generate an 2170215976Sjmallett interrupt. */ 2171215976Sjmallett uint64_t rml_rto : 1; /**< Enables NPI_INT_SUM[RML_RTO] to generate an 2172215976Sjmallett interrupt. */ 2173215976Sjmallett#else 2174215976Sjmallett uint64_t rml_rto : 1; 2175215976Sjmallett uint64_t rml_wto : 1; 2176215976Sjmallett uint64_t pci_rsl : 1; 2177215976Sjmallett uint64_t po0_2sml : 1; 2178215976Sjmallett uint64_t reserved_4_6 : 3; 2179215976Sjmallett uint64_t i0_rtout : 1; 2180215976Sjmallett uint64_t reserved_8_10 : 3; 2181215976Sjmallett uint64_t i0_overf : 1; 2182215976Sjmallett uint64_t reserved_12_14 : 3; 2183215976Sjmallett uint64_t p0_rtout : 1; 2184215976Sjmallett uint64_t reserved_16_18 : 3; 2185215976Sjmallett uint64_t p0_perr : 1; 2186215976Sjmallett uint64_t reserved_20_22 : 3; 2187215976Sjmallett uint64_t g0_rtout : 1; 2188215976Sjmallett uint64_t reserved_24_26 : 3; 2189215976Sjmallett uint64_t p0_pperr : 1; 2190215976Sjmallett uint64_t reserved_28_30 : 3; 2191215976Sjmallett uint64_t p0_ptout : 1; 2192215976Sjmallett uint64_t reserved_32_34 : 3; 2193215976Sjmallett uint64_t i0_pperr : 1; 2194215976Sjmallett uint64_t reserved_36_38 : 3; 2195215976Sjmallett uint64_t win_rto : 1; 2196215976Sjmallett uint64_t p_dperr : 1; 2197215976Sjmallett uint64_t iobdma : 1; 2198215976Sjmallett uint64_t fcr_s_e : 1; 2199215976Sjmallett uint64_t fcr_a_f : 1; 2200215976Sjmallett uint64_t pcr_s_e : 1; 2201215976Sjmallett uint64_t pcr_a_f : 1; 2202215976Sjmallett uint64_t q2_s_e : 1; 2203215976Sjmallett uint64_t q2_a_f : 1; 2204215976Sjmallett uint64_t q3_s_e : 1; 2205215976Sjmallett uint64_t q3_a_f : 1; 2206215976Sjmallett uint64_t com_s_e : 1; 2207215976Sjmallett uint64_t com_a_f : 1; 2208215976Sjmallett uint64_t pnc_s_e : 1; 2209215976Sjmallett uint64_t pnc_a_f : 1; 2210215976Sjmallett uint64_t rwx_s_e : 1; 2211215976Sjmallett uint64_t rdx_s_e : 1; 2212215976Sjmallett uint64_t pcf_p_e : 1; 2213215976Sjmallett uint64_t pcf_p_f : 1; 2214215976Sjmallett uint64_t pdf_p_e : 1; 2215215976Sjmallett uint64_t pdf_p_f : 1; 2216215976Sjmallett uint64_t q1_s_e : 1; 2217215976Sjmallett uint64_t q1_a_f : 1; 2218215976Sjmallett uint64_t reserved_62_63 : 2; 2219215976Sjmallett#endif 2220215976Sjmallett } cn30xx; 2221232812Sjmallett struct cvmx_npi_int_enb_cn31xx { 2222232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2223215976Sjmallett uint64_t reserved_62_63 : 2; 2224215976Sjmallett uint64_t q1_a_f : 1; /**< Enables NPI_INT_SUM[Q1_A_F] to generate an 2225215976Sjmallett interrupt. */ 2226215976Sjmallett uint64_t q1_s_e : 1; /**< Enables NPI_INT_SUM[Q1_S_E] to generate an 2227215976Sjmallett interrupt. */ 2228215976Sjmallett uint64_t pdf_p_f : 1; /**< Enables NPI_INT_SUM[PDF_P_F] to generate an 2229215976Sjmallett interrupt. */ 2230215976Sjmallett uint64_t pdf_p_e : 1; /**< Enables NPI_INT_SUM[PDF_P_E] to generate an 2231215976Sjmallett interrupt. */ 2232215976Sjmallett uint64_t pcf_p_f : 1; /**< Enables NPI_INT_SUM[PCF_P_F] to generate an 2233215976Sjmallett interrupt. */ 2234215976Sjmallett uint64_t pcf_p_e : 1; /**< Enables NPI_INT_SUM[PCF_P_E] to generate an 2235215976Sjmallett interrupt. */ 2236215976Sjmallett uint64_t rdx_s_e : 1; /**< Enables NPI_INT_SUM[RDX_S_E] to generate an 2237215976Sjmallett interrupt. */ 2238215976Sjmallett uint64_t rwx_s_e : 1; /**< Enables NPI_INT_SUM[RWX_S_E] to generate an 2239215976Sjmallett interrupt. */ 2240215976Sjmallett uint64_t pnc_a_f : 1; /**< Enables NPI_INT_SUM[PNC_A_F] to generate an 2241215976Sjmallett interrupt. */ 2242215976Sjmallett uint64_t pnc_s_e : 1; /**< Enables NPI_INT_SUM[PNC_S_E] to generate an 2243215976Sjmallett interrupt. */ 2244215976Sjmallett uint64_t com_a_f : 1; /**< Enables NPI_INT_SUM[COM_A_F] to generate an 2245215976Sjmallett interrupt. */ 2246215976Sjmallett uint64_t com_s_e : 1; /**< Enables NPI_INT_SUM[COM_S_E] to generate an 2247215976Sjmallett interrupt. */ 2248215976Sjmallett uint64_t q3_a_f : 1; /**< Enables NPI_INT_SUM[Q3_A_F] to generate an 2249215976Sjmallett interrupt. */ 2250215976Sjmallett uint64_t q3_s_e : 1; /**< Enables NPI_INT_SUM[Q3_S_E] to generate an 2251215976Sjmallett interrupt. */ 2252215976Sjmallett uint64_t q2_a_f : 1; /**< Enables NPI_INT_SUM[Q2_A_F] to generate an 2253215976Sjmallett interrupt. */ 2254215976Sjmallett uint64_t q2_s_e : 1; /**< Enables NPI_INT_SUM[Q2_S_E] to generate an 2255215976Sjmallett interrupt. */ 2256215976Sjmallett uint64_t pcr_a_f : 1; /**< Enables NPI_INT_SUM[PCR_A_F] to generate an 2257215976Sjmallett interrupt. */ 2258215976Sjmallett uint64_t pcr_s_e : 1; /**< Enables NPI_INT_SUM[PCR_S_E] to generate an 2259215976Sjmallett interrupt. */ 2260215976Sjmallett uint64_t fcr_a_f : 1; /**< Enables NPI_INT_SUM[FCR_A_F] to generate an 2261215976Sjmallett interrupt. */ 2262215976Sjmallett uint64_t fcr_s_e : 1; /**< Enables NPI_INT_SUM[FCR_S_E] to generate an 2263215976Sjmallett interrupt. */ 2264215976Sjmallett uint64_t iobdma : 1; /**< Enables NPI_INT_SUM[IOBDMA] to generate an 2265215976Sjmallett interrupt. */ 2266215976Sjmallett uint64_t p_dperr : 1; /**< Enables NPI_INT_SUM[P_DPERR] to generate an 2267215976Sjmallett interrupt. */ 2268215976Sjmallett uint64_t win_rto : 1; /**< Enables NPI_INT_SUM[WIN_RTO] to generate an 2269215976Sjmallett interrupt. */ 2270215976Sjmallett uint64_t reserved_37_38 : 2; 2271215976Sjmallett uint64_t i1_pperr : 1; /**< Enables NPI_INT_SUM[I1_PPERR] to generate an 2272215976Sjmallett interrupt. */ 2273215976Sjmallett uint64_t i0_pperr : 1; /**< Enables NPI_INT_SUM[I0_PPERR] to generate an 2274215976Sjmallett interrupt. */ 2275215976Sjmallett uint64_t reserved_33_34 : 2; 2276215976Sjmallett uint64_t p1_ptout : 1; /**< Enables NPI_INT_SUM[P1_PTOUT] to generate an 2277215976Sjmallett interrupt. */ 2278215976Sjmallett uint64_t p0_ptout : 1; /**< Enables NPI_INT_SUM[P0_PTOUT] to generate an 2279215976Sjmallett interrupt. */ 2280215976Sjmallett uint64_t reserved_29_30 : 2; 2281215976Sjmallett uint64_t p1_pperr : 1; /**< Enables NPI_INT_SUM[P1_PPERR] to generate an 2282215976Sjmallett interrupt. */ 2283215976Sjmallett uint64_t p0_pperr : 1; /**< Enables NPI_INT_SUM[P0_PPERR] to generate an 2284215976Sjmallett interrupt. */ 2285215976Sjmallett uint64_t reserved_25_26 : 2; 2286215976Sjmallett uint64_t g1_rtout : 1; /**< Enables NPI_INT_SUM[G1_RTOUT] to generate an 2287215976Sjmallett interrupt. */ 2288215976Sjmallett uint64_t g0_rtout : 1; /**< Enables NPI_INT_SUM[G0_RTOUT] to generate an 2289215976Sjmallett interrupt. */ 2290215976Sjmallett uint64_t reserved_21_22 : 2; 2291215976Sjmallett uint64_t p1_perr : 1; /**< Enables NPI_INT_SUM[P1_PERR] to generate an 2292215976Sjmallett interrupt. */ 2293215976Sjmallett uint64_t p0_perr : 1; /**< Enables NPI_INT_SUM[P0_PERR] to generate an 2294215976Sjmallett interrupt. */ 2295215976Sjmallett uint64_t reserved_17_18 : 2; 2296215976Sjmallett uint64_t p1_rtout : 1; /**< Enables NPI_INT_SUM[P1_RTOUT] to generate an 2297215976Sjmallett interrupt. */ 2298215976Sjmallett uint64_t p0_rtout : 1; /**< Enables NPI_INT_SUM[P0_RTOUT] to generate an 2299215976Sjmallett interrupt. */ 2300215976Sjmallett uint64_t reserved_13_14 : 2; 2301215976Sjmallett uint64_t i1_overf : 1; /**< Enables NPI_INT_SUM[I1_OVERF] to generate an 2302215976Sjmallett interrupt. */ 2303215976Sjmallett uint64_t i0_overf : 1; /**< Enables NPI_INT_SUM[I0_OVERF] to generate an 2304215976Sjmallett interrupt. */ 2305215976Sjmallett uint64_t reserved_9_10 : 2; 2306215976Sjmallett uint64_t i1_rtout : 1; /**< Enables NPI_INT_SUM[I1_RTOUT] to generate an 2307215976Sjmallett interrupt. */ 2308215976Sjmallett uint64_t i0_rtout : 1; /**< Enables NPI_INT_SUM[I0_RTOUT] to generate an 2309215976Sjmallett interrupt. */ 2310215976Sjmallett uint64_t reserved_5_6 : 2; 2311215976Sjmallett uint64_t po1_2sml : 1; /**< Enables NPI_INT_SUM[PO1_2SML] to generate an 2312215976Sjmallett interrupt. */ 2313215976Sjmallett uint64_t po0_2sml : 1; /**< Enables NPI_INT_SUM[PO0_2SML] to generate an 2314215976Sjmallett interrupt. */ 2315215976Sjmallett uint64_t pci_rsl : 1; /**< Enables NPI_INT_SUM[PCI_RSL] to generate an 2316215976Sjmallett interrupt. */ 2317215976Sjmallett uint64_t rml_wto : 1; /**< Enables NPI_INT_SUM[RML_WTO] to generate an 2318215976Sjmallett interrupt. */ 2319215976Sjmallett uint64_t rml_rto : 1; /**< Enables NPI_INT_SUM[RML_RTO] to generate an 2320215976Sjmallett interrupt. */ 2321215976Sjmallett#else 2322215976Sjmallett uint64_t rml_rto : 1; 2323215976Sjmallett uint64_t rml_wto : 1; 2324215976Sjmallett uint64_t pci_rsl : 1; 2325215976Sjmallett uint64_t po0_2sml : 1; 2326215976Sjmallett uint64_t po1_2sml : 1; 2327215976Sjmallett uint64_t reserved_5_6 : 2; 2328215976Sjmallett uint64_t i0_rtout : 1; 2329215976Sjmallett uint64_t i1_rtout : 1; 2330215976Sjmallett uint64_t reserved_9_10 : 2; 2331215976Sjmallett uint64_t i0_overf : 1; 2332215976Sjmallett uint64_t i1_overf : 1; 2333215976Sjmallett uint64_t reserved_13_14 : 2; 2334215976Sjmallett uint64_t p0_rtout : 1; 2335215976Sjmallett uint64_t p1_rtout : 1; 2336215976Sjmallett uint64_t reserved_17_18 : 2; 2337215976Sjmallett uint64_t p0_perr : 1; 2338215976Sjmallett uint64_t p1_perr : 1; 2339215976Sjmallett uint64_t reserved_21_22 : 2; 2340215976Sjmallett uint64_t g0_rtout : 1; 2341215976Sjmallett uint64_t g1_rtout : 1; 2342215976Sjmallett uint64_t reserved_25_26 : 2; 2343215976Sjmallett uint64_t p0_pperr : 1; 2344215976Sjmallett uint64_t p1_pperr : 1; 2345215976Sjmallett uint64_t reserved_29_30 : 2; 2346215976Sjmallett uint64_t p0_ptout : 1; 2347215976Sjmallett uint64_t p1_ptout : 1; 2348215976Sjmallett uint64_t reserved_33_34 : 2; 2349215976Sjmallett uint64_t i0_pperr : 1; 2350215976Sjmallett uint64_t i1_pperr : 1; 2351215976Sjmallett uint64_t reserved_37_38 : 2; 2352215976Sjmallett uint64_t win_rto : 1; 2353215976Sjmallett uint64_t p_dperr : 1; 2354215976Sjmallett uint64_t iobdma : 1; 2355215976Sjmallett uint64_t fcr_s_e : 1; 2356215976Sjmallett uint64_t fcr_a_f : 1; 2357215976Sjmallett uint64_t pcr_s_e : 1; 2358215976Sjmallett uint64_t pcr_a_f : 1; 2359215976Sjmallett uint64_t q2_s_e : 1; 2360215976Sjmallett uint64_t q2_a_f : 1; 2361215976Sjmallett uint64_t q3_s_e : 1; 2362215976Sjmallett uint64_t q3_a_f : 1; 2363215976Sjmallett uint64_t com_s_e : 1; 2364215976Sjmallett uint64_t com_a_f : 1; 2365215976Sjmallett uint64_t pnc_s_e : 1; 2366215976Sjmallett uint64_t pnc_a_f : 1; 2367215976Sjmallett uint64_t rwx_s_e : 1; 2368215976Sjmallett uint64_t rdx_s_e : 1; 2369215976Sjmallett uint64_t pcf_p_e : 1; 2370215976Sjmallett uint64_t pcf_p_f : 1; 2371215976Sjmallett uint64_t pdf_p_e : 1; 2372215976Sjmallett uint64_t pdf_p_f : 1; 2373215976Sjmallett uint64_t q1_s_e : 1; 2374215976Sjmallett uint64_t q1_a_f : 1; 2375215976Sjmallett uint64_t reserved_62_63 : 2; 2376215976Sjmallett#endif 2377215976Sjmallett } cn31xx; 2378215976Sjmallett struct cvmx_npi_int_enb_s cn38xx; 2379232812Sjmallett struct cvmx_npi_int_enb_cn38xxp2 { 2380232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2381215976Sjmallett uint64_t reserved_42_63 : 22; 2382215976Sjmallett uint64_t iobdma : 1; /**< Enables NPI_INT_SUM[IOBDMA] to generate an 2383215976Sjmallett interrupt. */ 2384215976Sjmallett uint64_t p_dperr : 1; /**< Enables NPI_INT_SUM[P_DPERR] to generate an 2385215976Sjmallett interrupt. */ 2386215976Sjmallett uint64_t win_rto : 1; /**< Enables NPI_INT_SUM[WIN_RTO] to generate an 2387215976Sjmallett interrupt. */ 2388215976Sjmallett uint64_t i3_pperr : 1; /**< Enables NPI_INT_SUM[I3_PPERR] to generate an 2389215976Sjmallett interrupt. */ 2390215976Sjmallett uint64_t i2_pperr : 1; /**< Enables NPI_INT_SUM[I2_PPERR] to generate an 2391215976Sjmallett interrupt. */ 2392215976Sjmallett uint64_t i1_pperr : 1; /**< Enables NPI_INT_SUM[I1_PPERR] to generate an 2393215976Sjmallett interrupt. */ 2394215976Sjmallett uint64_t i0_pperr : 1; /**< Enables NPI_INT_SUM[I0_PPERR] to generate an 2395215976Sjmallett interrupt. */ 2396215976Sjmallett uint64_t p3_ptout : 1; /**< Enables NPI_INT_SUM[P3_PTOUT] to generate an 2397215976Sjmallett interrupt. */ 2398215976Sjmallett uint64_t p2_ptout : 1; /**< Enables NPI_INT_SUM[P2_PTOUT] to generate an 2399215976Sjmallett interrupt. */ 2400215976Sjmallett uint64_t p1_ptout : 1; /**< Enables NPI_INT_SUM[P1_PTOUT] to generate an 2401215976Sjmallett interrupt. */ 2402215976Sjmallett uint64_t p0_ptout : 1; /**< Enables NPI_INT_SUM[P0_PTOUT] to generate an 2403215976Sjmallett interrupt. */ 2404215976Sjmallett uint64_t p3_pperr : 1; /**< Enables NPI_INT_SUM[P3_PPERR] to generate an 2405215976Sjmallett interrupt. */ 2406215976Sjmallett uint64_t p2_pperr : 1; /**< Enables NPI_INT_SUM[P2_PPERR] to generate an 2407215976Sjmallett interrupt. */ 2408215976Sjmallett uint64_t p1_pperr : 1; /**< Enables NPI_INT_SUM[P1_PPERR] to generate an 2409215976Sjmallett interrupt. */ 2410215976Sjmallett uint64_t p0_pperr : 1; /**< Enables NPI_INT_SUM[P0_PPERR] to generate an 2411215976Sjmallett interrupt. */ 2412215976Sjmallett uint64_t g3_rtout : 1; /**< Enables NPI_INT_SUM[G3_RTOUT] to generate an 2413215976Sjmallett interrupt. */ 2414215976Sjmallett uint64_t g2_rtout : 1; /**< Enables NPI_INT_SUM[G2_RTOUT] to generate an 2415215976Sjmallett interrupt. */ 2416215976Sjmallett uint64_t g1_rtout : 1; /**< Enables NPI_INT_SUM[G1_RTOUT] to generate an 2417215976Sjmallett interrupt. */ 2418215976Sjmallett uint64_t g0_rtout : 1; /**< Enables NPI_INT_SUM[G0_RTOUT] to generate an 2419215976Sjmallett interrupt. */ 2420215976Sjmallett uint64_t p3_perr : 1; /**< Enables NPI_INT_SUM[P3_PERR] to generate an 2421215976Sjmallett interrupt. */ 2422215976Sjmallett uint64_t p2_perr : 1; /**< Enables NPI_INT_SUM[P2_PERR] to generate an 2423215976Sjmallett interrupt. */ 2424215976Sjmallett uint64_t p1_perr : 1; /**< Enables NPI_INT_SUM[P1_PERR] to generate an 2425215976Sjmallett interrupt. */ 2426215976Sjmallett uint64_t p0_perr : 1; /**< Enables NPI_INT_SUM[P0_PERR] to generate an 2427215976Sjmallett interrupt. */ 2428215976Sjmallett uint64_t p3_rtout : 1; /**< Enables NPI_INT_SUM[P3_RTOUT] to generate an 2429215976Sjmallett interrupt. */ 2430215976Sjmallett uint64_t p2_rtout : 1; /**< Enables NPI_INT_SUM[P2_RTOUT] to generate an 2431215976Sjmallett interrupt. */ 2432215976Sjmallett uint64_t p1_rtout : 1; /**< Enables NPI_INT_SUM[P1_RTOUT] to generate an 2433215976Sjmallett interrupt. */ 2434215976Sjmallett uint64_t p0_rtout : 1; /**< Enables NPI_INT_SUM[P0_RTOUT] to generate an 2435215976Sjmallett interrupt. */ 2436215976Sjmallett uint64_t i3_overf : 1; /**< Enables NPI_INT_SUM[I3_OVERF] to generate an 2437215976Sjmallett interrupt. */ 2438215976Sjmallett uint64_t i2_overf : 1; /**< Enables NPI_INT_SUM[I2_OVERF] to generate an 2439215976Sjmallett interrupt. */ 2440215976Sjmallett uint64_t i1_overf : 1; /**< Enables NPI_INT_SUM[I1_OVERF] to generate an 2441215976Sjmallett interrupt. */ 2442215976Sjmallett uint64_t i0_overf : 1; /**< Enables NPI_INT_SUM[I0_OVERF] to generate an 2443215976Sjmallett interrupt. */ 2444215976Sjmallett uint64_t i3_rtout : 1; /**< Enables NPI_INT_SUM[I3_RTOUT] to generate an 2445215976Sjmallett interrupt. */ 2446215976Sjmallett uint64_t i2_rtout : 1; /**< Enables NPI_INT_SUM[I2_RTOUT] to generate an 2447215976Sjmallett interrupt. */ 2448215976Sjmallett uint64_t i1_rtout : 1; /**< Enables NPI_INT_SUM[I1_RTOUT] to generate an 2449215976Sjmallett interrupt. */ 2450215976Sjmallett uint64_t i0_rtout : 1; /**< Enables NPI_INT_SUM[I0_RTOUT] to generate an 2451215976Sjmallett interrupt. */ 2452215976Sjmallett uint64_t po3_2sml : 1; /**< Enables NPI_INT_SUM[PO3_2SML] to generate an 2453215976Sjmallett interrupt. */ 2454215976Sjmallett uint64_t po2_2sml : 1; /**< Enables NPI_INT_SUM[PO2_2SML] to generate an 2455215976Sjmallett interrupt. */ 2456215976Sjmallett uint64_t po1_2sml : 1; /**< Enables NPI_INT_SUM[PO1_2SML] to generate an 2457215976Sjmallett interrupt. */ 2458215976Sjmallett uint64_t po0_2sml : 1; /**< Enables NPI_INT_SUM[PO0_2SML] to generate an 2459215976Sjmallett interrupt. */ 2460215976Sjmallett uint64_t pci_rsl : 1; /**< Enables NPI_INT_SUM[PCI_RSL] to generate an 2461215976Sjmallett interrupt. */ 2462215976Sjmallett uint64_t rml_wto : 1; /**< Enables NPI_INT_SUM[RML_WTO] to generate an 2463215976Sjmallett interrupt. */ 2464215976Sjmallett uint64_t rml_rto : 1; /**< Enables NPI_INT_SUM[RML_RTO] to generate an 2465215976Sjmallett interrupt. */ 2466215976Sjmallett#else 2467215976Sjmallett uint64_t rml_rto : 1; 2468215976Sjmallett uint64_t rml_wto : 1; 2469215976Sjmallett uint64_t pci_rsl : 1; 2470215976Sjmallett uint64_t po0_2sml : 1; 2471215976Sjmallett uint64_t po1_2sml : 1; 2472215976Sjmallett uint64_t po2_2sml : 1; 2473215976Sjmallett uint64_t po3_2sml : 1; 2474215976Sjmallett uint64_t i0_rtout : 1; 2475215976Sjmallett uint64_t i1_rtout : 1; 2476215976Sjmallett uint64_t i2_rtout : 1; 2477215976Sjmallett uint64_t i3_rtout : 1; 2478215976Sjmallett uint64_t i0_overf : 1; 2479215976Sjmallett uint64_t i1_overf : 1; 2480215976Sjmallett uint64_t i2_overf : 1; 2481215976Sjmallett uint64_t i3_overf : 1; 2482215976Sjmallett uint64_t p0_rtout : 1; 2483215976Sjmallett uint64_t p1_rtout : 1; 2484215976Sjmallett uint64_t p2_rtout : 1; 2485215976Sjmallett uint64_t p3_rtout : 1; 2486215976Sjmallett uint64_t p0_perr : 1; 2487215976Sjmallett uint64_t p1_perr : 1; 2488215976Sjmallett uint64_t p2_perr : 1; 2489215976Sjmallett uint64_t p3_perr : 1; 2490215976Sjmallett uint64_t g0_rtout : 1; 2491215976Sjmallett uint64_t g1_rtout : 1; 2492215976Sjmallett uint64_t g2_rtout : 1; 2493215976Sjmallett uint64_t g3_rtout : 1; 2494215976Sjmallett uint64_t p0_pperr : 1; 2495215976Sjmallett uint64_t p1_pperr : 1; 2496215976Sjmallett uint64_t p2_pperr : 1; 2497215976Sjmallett uint64_t p3_pperr : 1; 2498215976Sjmallett uint64_t p0_ptout : 1; 2499215976Sjmallett uint64_t p1_ptout : 1; 2500215976Sjmallett uint64_t p2_ptout : 1; 2501215976Sjmallett uint64_t p3_ptout : 1; 2502215976Sjmallett uint64_t i0_pperr : 1; 2503215976Sjmallett uint64_t i1_pperr : 1; 2504215976Sjmallett uint64_t i2_pperr : 1; 2505215976Sjmallett uint64_t i3_pperr : 1; 2506215976Sjmallett uint64_t win_rto : 1; 2507215976Sjmallett uint64_t p_dperr : 1; 2508215976Sjmallett uint64_t iobdma : 1; 2509215976Sjmallett uint64_t reserved_42_63 : 22; 2510215976Sjmallett#endif 2511215976Sjmallett } cn38xxp2; 2512215976Sjmallett struct cvmx_npi_int_enb_cn31xx cn50xx; 2513215976Sjmallett struct cvmx_npi_int_enb_s cn58xx; 2514215976Sjmallett struct cvmx_npi_int_enb_s cn58xxp1; 2515215976Sjmallett}; 2516215976Sjmalletttypedef union cvmx_npi_int_enb cvmx_npi_int_enb_t; 2517215976Sjmallett 2518215976Sjmallett/** 2519215976Sjmallett * cvmx_npi_int_sum 2520215976Sjmallett * 2521215976Sjmallett * NPI_INTERRUPT_SUM = NPI Interrupt Summary Register 2522215976Sjmallett * 2523215976Sjmallett * Set when an interrupt condition occurs, write '1' to clear. 2524215976Sjmallett */ 2525232812Sjmallettunion cvmx_npi_int_sum { 2526215976Sjmallett uint64_t u64; 2527232812Sjmallett struct cvmx_npi_int_sum_s { 2528232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2529215976Sjmallett uint64_t reserved_62_63 : 2; 2530215976Sjmallett uint64_t q1_a_f : 1; /**< Attempted to add when Queue-1 FIFO is full. 2531215976Sjmallett PASS3 Field. */ 2532215976Sjmallett uint64_t q1_s_e : 1; /**< Attempted to subtract when Queue-1 FIFO is empty. 2533215976Sjmallett PASS3 Field. */ 2534215976Sjmallett uint64_t pdf_p_f : 1; /**< Attempted to push a full PCN-DATA-FIFO. 2535215976Sjmallett PASS3 Field. */ 2536215976Sjmallett uint64_t pdf_p_e : 1; /**< Attempted to pop an empty PCN-DATA-FIFO. 2537215976Sjmallett PASS3 Field. */ 2538215976Sjmallett uint64_t pcf_p_f : 1; /**< Attempted to push a full PCN-CNT-FIFO. 2539215976Sjmallett PASS3 Field. */ 2540215976Sjmallett uint64_t pcf_p_e : 1; /**< Attempted to pop an empty PCN-CNT-FIFO. 2541215976Sjmallett PASS3 Field. */ 2542215976Sjmallett uint64_t rdx_s_e : 1; /**< Attempted to subtract when DPI-XFR-Wait count is 0. 2543215976Sjmallett PASS3 Field. */ 2544215976Sjmallett uint64_t rwx_s_e : 1; /**< Attempted to subtract when RDN-XFR-Wait count is 0. 2545215976Sjmallett PASS3 Field. */ 2546215976Sjmallett uint64_t pnc_a_f : 1; /**< Attempted to add when PNI-NPI Credits are max. 2547215976Sjmallett PASS3 Field. */ 2548215976Sjmallett uint64_t pnc_s_e : 1; /**< Attempted to subtract when PNI-NPI Credits are 0. 2549215976Sjmallett PASS3 Field. */ 2550215976Sjmallett uint64_t com_a_f : 1; /**< Attempted to add when PCN-Commit Counter is max. 2551215976Sjmallett PASS3 Field. */ 2552215976Sjmallett uint64_t com_s_e : 1; /**< Attempted to subtract when PCN-Commit Counter is 0. 2553215976Sjmallett PASS3 Field. */ 2554215976Sjmallett uint64_t q3_a_f : 1; /**< Attempted to add when Queue-3 FIFO is full. 2555215976Sjmallett PASS3 Field. */ 2556215976Sjmallett uint64_t q3_s_e : 1; /**< Attempted to subtract when Queue-3 FIFO is empty. 2557215976Sjmallett PASS3 Field. */ 2558215976Sjmallett uint64_t q2_a_f : 1; /**< Attempted to add when Queue-2 FIFO is full. 2559215976Sjmallett PASS3 Field. */ 2560215976Sjmallett uint64_t q2_s_e : 1; /**< Attempted to subtract when Queue-2 FIFO is empty. 2561215976Sjmallett PASS3 Field. */ 2562215976Sjmallett uint64_t pcr_a_f : 1; /**< Attempted to add when POW Credits is full. 2563215976Sjmallett PASS3 Field. */ 2564215976Sjmallett uint64_t pcr_s_e : 1; /**< Attempted to subtract when POW Credits is empty. 2565215976Sjmallett PASS3 Field. */ 2566215976Sjmallett uint64_t fcr_a_f : 1; /**< Attempted to add when FPA Credits is full. 2567215976Sjmallett PASS3 Field. */ 2568215976Sjmallett uint64_t fcr_s_e : 1; /**< Attempted to subtract when FPA Credits is empty. 2569215976Sjmallett PASS3 Field. */ 2570215976Sjmallett uint64_t iobdma : 1; /**< Requested IOBDMA read size exceeded 128 words. */ 2571215976Sjmallett uint64_t p_dperr : 1; /**< If a parity error occured on data written to L2C 2572215976Sjmallett from the PCI this bit may be set. */ 2573215976Sjmallett uint64_t win_rto : 1; /**< Windowed Load Timed Out. */ 2574215976Sjmallett uint64_t i3_pperr : 1; /**< If a parity error occured on the port's instruction 2575215976Sjmallett this bit may be set. */ 2576215976Sjmallett uint64_t i2_pperr : 1; /**< If a parity error occured on the port's instruction 2577215976Sjmallett this bit may be set. */ 2578215976Sjmallett uint64_t i1_pperr : 1; /**< If a parity error occured on the port's instruction 2579215976Sjmallett this bit may be set. */ 2580215976Sjmallett uint64_t i0_pperr : 1; /**< If a parity error occured on the port's instruction 2581215976Sjmallett this bit may be set. */ 2582215976Sjmallett uint64_t p3_ptout : 1; /**< Port-3 output had a read timeout on a DATA/INFO 2583215976Sjmallett pair. */ 2584215976Sjmallett uint64_t p2_ptout : 1; /**< Port-2 output had a read timeout on a DATA/INFO 2585215976Sjmallett pair. */ 2586215976Sjmallett uint64_t p1_ptout : 1; /**< Port-1 output had a read timeout on a DATA/INFO 2587215976Sjmallett pair. */ 2588215976Sjmallett uint64_t p0_ptout : 1; /**< Port-0 output had a read timeout on a DATA/INFO 2589215976Sjmallett pair. */ 2590215976Sjmallett uint64_t p3_pperr : 1; /**< If a parity error occured on the port DATA/INFO 2591215976Sjmallett pointer-pair, this bit may be set. */ 2592215976Sjmallett uint64_t p2_pperr : 1; /**< If a parity error occured on the port DATA/INFO 2593215976Sjmallett pointer-pair, this bit may be set. */ 2594215976Sjmallett uint64_t p1_pperr : 1; /**< If a parity error occured on the port DATA/INFO 2595215976Sjmallett pointer-pair, this bit may be set. */ 2596215976Sjmallett uint64_t p0_pperr : 1; /**< If a parity error occured on the port DATA/INFO 2597215976Sjmallett pointer-pair, this bit may be set. */ 2598215976Sjmallett uint64_t g3_rtout : 1; /**< Port-3 had a read timeout while attempting to 2599215976Sjmallett read a gather list. */ 2600215976Sjmallett uint64_t g2_rtout : 1; /**< Port-2 had a read timeout while attempting to 2601215976Sjmallett read a gather list. */ 2602215976Sjmallett uint64_t g1_rtout : 1; /**< Port-1 had a read timeout while attempting to 2603215976Sjmallett read a gather list. */ 2604215976Sjmallett uint64_t g0_rtout : 1; /**< Port-0 had a read timeout while attempting to 2605215976Sjmallett read a gather list. */ 2606215976Sjmallett uint64_t p3_perr : 1; /**< If a parity error occured on the port's packet 2607215976Sjmallett data this bit may be set. */ 2608215976Sjmallett uint64_t p2_perr : 1; /**< If a parity error occured on the port's packet 2609215976Sjmallett data this bit may be set. */ 2610215976Sjmallett uint64_t p1_perr : 1; /**< If a parity error occured on the port's packet 2611215976Sjmallett data this bit may be set. */ 2612215976Sjmallett uint64_t p0_perr : 1; /**< If a parity error occured on the port's packet 2613215976Sjmallett data this bit may be set. */ 2614215976Sjmallett uint64_t p3_rtout : 1; /**< Port-3 had a read timeout while attempting to 2615215976Sjmallett read packet data. */ 2616215976Sjmallett uint64_t p2_rtout : 1; /**< Port-2 had a read timeout while attempting to 2617215976Sjmallett read packet data. */ 2618215976Sjmallett uint64_t p1_rtout : 1; /**< Port-1 had a read timeout while attempting to 2619215976Sjmallett read packet data. */ 2620215976Sjmallett uint64_t p0_rtout : 1; /**< Port-0 had a read timeout while attempting to 2621215976Sjmallett read packet data. */ 2622215976Sjmallett uint64_t i3_overf : 1; /**< Port-3 had a doorbell overflow. Bit[31] of the 2623215976Sjmallett doorbell count was set. */ 2624215976Sjmallett uint64_t i2_overf : 1; /**< Port-2 had a doorbell overflow. Bit[31] of the 2625215976Sjmallett doorbell count was set. */ 2626215976Sjmallett uint64_t i1_overf : 1; /**< Port-1 had a doorbell overflow. Bit[31] of the 2627215976Sjmallett doorbell count was set. */ 2628215976Sjmallett uint64_t i0_overf : 1; /**< Port-0 had a doorbell overflow. Bit[31] of the 2629215976Sjmallett doorbell count was set. */ 2630215976Sjmallett uint64_t i3_rtout : 1; /**< Port-3 had a read timeout while attempting to 2631215976Sjmallett read instructions. */ 2632215976Sjmallett uint64_t i2_rtout : 1; /**< Port-2 had a read timeout while attempting to 2633215976Sjmallett read instructions. */ 2634215976Sjmallett uint64_t i1_rtout : 1; /**< Port-1 had a read timeout while attempting to 2635215976Sjmallett read instructions. */ 2636215976Sjmallett uint64_t i0_rtout : 1; /**< Port-0 had a read timeout while attempting to 2637215976Sjmallett read instructions. */ 2638215976Sjmallett uint64_t po3_2sml : 1; /**< The packet being sent out on Port3 is smaller 2639215976Sjmallett than the NPI_BUFF_SIZE_OUTPUT3[ISIZE] field. */ 2640215976Sjmallett uint64_t po2_2sml : 1; /**< The packet being sent out on Port2 is smaller 2641215976Sjmallett than the NPI_BUFF_SIZE_OUTPUT2[ISIZE] field. */ 2642215976Sjmallett uint64_t po1_2sml : 1; /**< The packet being sent out on Port1 is smaller 2643215976Sjmallett than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field. */ 2644215976Sjmallett uint64_t po0_2sml : 1; /**< The packet being sent out on Port0 is smaller 2645215976Sjmallett than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field. */ 2646215976Sjmallett uint64_t pci_rsl : 1; /**< This '1' when a bit in PCI_INT_SUM2 is SET and the 2647215976Sjmallett corresponding bit in the PCI_INT_ENB2 is SET. */ 2648215976Sjmallett uint64_t rml_wto : 1; /**< Set '1' when the RML does not receive a commit 2649215976Sjmallett back from a RSL after sending a write command to 2650215976Sjmallett a RSL. */ 2651215976Sjmallett uint64_t rml_rto : 1; /**< Set '1' when the RML does not receive read data 2652215976Sjmallett back from a RSL after sending a read command to 2653215976Sjmallett a RSL. */ 2654215976Sjmallett#else 2655215976Sjmallett uint64_t rml_rto : 1; 2656215976Sjmallett uint64_t rml_wto : 1; 2657215976Sjmallett uint64_t pci_rsl : 1; 2658215976Sjmallett uint64_t po0_2sml : 1; 2659215976Sjmallett uint64_t po1_2sml : 1; 2660215976Sjmallett uint64_t po2_2sml : 1; 2661215976Sjmallett uint64_t po3_2sml : 1; 2662215976Sjmallett uint64_t i0_rtout : 1; 2663215976Sjmallett uint64_t i1_rtout : 1; 2664215976Sjmallett uint64_t i2_rtout : 1; 2665215976Sjmallett uint64_t i3_rtout : 1; 2666215976Sjmallett uint64_t i0_overf : 1; 2667215976Sjmallett uint64_t i1_overf : 1; 2668215976Sjmallett uint64_t i2_overf : 1; 2669215976Sjmallett uint64_t i3_overf : 1; 2670215976Sjmallett uint64_t p0_rtout : 1; 2671215976Sjmallett uint64_t p1_rtout : 1; 2672215976Sjmallett uint64_t p2_rtout : 1; 2673215976Sjmallett uint64_t p3_rtout : 1; 2674215976Sjmallett uint64_t p0_perr : 1; 2675215976Sjmallett uint64_t p1_perr : 1; 2676215976Sjmallett uint64_t p2_perr : 1; 2677215976Sjmallett uint64_t p3_perr : 1; 2678215976Sjmallett uint64_t g0_rtout : 1; 2679215976Sjmallett uint64_t g1_rtout : 1; 2680215976Sjmallett uint64_t g2_rtout : 1; 2681215976Sjmallett uint64_t g3_rtout : 1; 2682215976Sjmallett uint64_t p0_pperr : 1; 2683215976Sjmallett uint64_t p1_pperr : 1; 2684215976Sjmallett uint64_t p2_pperr : 1; 2685215976Sjmallett uint64_t p3_pperr : 1; 2686215976Sjmallett uint64_t p0_ptout : 1; 2687215976Sjmallett uint64_t p1_ptout : 1; 2688215976Sjmallett uint64_t p2_ptout : 1; 2689215976Sjmallett uint64_t p3_ptout : 1; 2690215976Sjmallett uint64_t i0_pperr : 1; 2691215976Sjmallett uint64_t i1_pperr : 1; 2692215976Sjmallett uint64_t i2_pperr : 1; 2693215976Sjmallett uint64_t i3_pperr : 1; 2694215976Sjmallett uint64_t win_rto : 1; 2695215976Sjmallett uint64_t p_dperr : 1; 2696215976Sjmallett uint64_t iobdma : 1; 2697215976Sjmallett uint64_t fcr_s_e : 1; 2698215976Sjmallett uint64_t fcr_a_f : 1; 2699215976Sjmallett uint64_t pcr_s_e : 1; 2700215976Sjmallett uint64_t pcr_a_f : 1; 2701215976Sjmallett uint64_t q2_s_e : 1; 2702215976Sjmallett uint64_t q2_a_f : 1; 2703215976Sjmallett uint64_t q3_s_e : 1; 2704215976Sjmallett uint64_t q3_a_f : 1; 2705215976Sjmallett uint64_t com_s_e : 1; 2706215976Sjmallett uint64_t com_a_f : 1; 2707215976Sjmallett uint64_t pnc_s_e : 1; 2708215976Sjmallett uint64_t pnc_a_f : 1; 2709215976Sjmallett uint64_t rwx_s_e : 1; 2710215976Sjmallett uint64_t rdx_s_e : 1; 2711215976Sjmallett uint64_t pcf_p_e : 1; 2712215976Sjmallett uint64_t pcf_p_f : 1; 2713215976Sjmallett uint64_t pdf_p_e : 1; 2714215976Sjmallett uint64_t pdf_p_f : 1; 2715215976Sjmallett uint64_t q1_s_e : 1; 2716215976Sjmallett uint64_t q1_a_f : 1; 2717215976Sjmallett uint64_t reserved_62_63 : 2; 2718215976Sjmallett#endif 2719215976Sjmallett } s; 2720232812Sjmallett struct cvmx_npi_int_sum_cn30xx { 2721232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2722215976Sjmallett uint64_t reserved_62_63 : 2; 2723215976Sjmallett uint64_t q1_a_f : 1; /**< Attempted to add when Queue-1 FIFO is full. */ 2724215976Sjmallett uint64_t q1_s_e : 1; /**< Attempted to subtract when Queue-1 FIFO is empty. */ 2725215976Sjmallett uint64_t pdf_p_f : 1; /**< Attempted to push a full PCN-DATA-FIFO. */ 2726215976Sjmallett uint64_t pdf_p_e : 1; /**< Attempted to pop an empty PCN-DATA-FIFO. */ 2727215976Sjmallett uint64_t pcf_p_f : 1; /**< Attempted to push a full PCN-CNT-FIFO. */ 2728215976Sjmallett uint64_t pcf_p_e : 1; /**< Attempted to pop an empty PCN-CNT-FIFO. */ 2729215976Sjmallett uint64_t rdx_s_e : 1; /**< Attempted to subtract when DPI-XFR-Wait count is 0. */ 2730215976Sjmallett uint64_t rwx_s_e : 1; /**< Attempted to subtract when RDN-XFR-Wait count is 0. */ 2731215976Sjmallett uint64_t pnc_a_f : 1; /**< Attempted to add when PNI-NPI Credits are max. */ 2732215976Sjmallett uint64_t pnc_s_e : 1; /**< Attempted to subtract when PNI-NPI Credits are 0. */ 2733215976Sjmallett uint64_t com_a_f : 1; /**< Attempted to add when PCN-Commit Counter is max. */ 2734215976Sjmallett uint64_t com_s_e : 1; /**< Attempted to subtract when PCN-Commit Counter is 0. */ 2735215976Sjmallett uint64_t q3_a_f : 1; /**< Attempted to add when Queue-3 FIFO is full. */ 2736215976Sjmallett uint64_t q3_s_e : 1; /**< Attempted to subtract when Queue-3 FIFO is empty. */ 2737215976Sjmallett uint64_t q2_a_f : 1; /**< Attempted to add when Queue-2 FIFO is full. */ 2738215976Sjmallett uint64_t q2_s_e : 1; /**< Attempted to subtract when Queue-2 FIFO is empty. */ 2739215976Sjmallett uint64_t pcr_a_f : 1; /**< Attempted to add when POW Credits is full. */ 2740215976Sjmallett uint64_t pcr_s_e : 1; /**< Attempted to subtract when POW Credits is empty. */ 2741215976Sjmallett uint64_t fcr_a_f : 1; /**< Attempted to add when FPA Credits is full. */ 2742215976Sjmallett uint64_t fcr_s_e : 1; /**< Attempted to subtract when FPA Credits is empty. */ 2743215976Sjmallett uint64_t iobdma : 1; /**< Requested IOBDMA read size exceeded 128 words. */ 2744215976Sjmallett uint64_t p_dperr : 1; /**< If a parity error occured on data written to L2C 2745215976Sjmallett from the PCI this bit may be set. */ 2746215976Sjmallett uint64_t win_rto : 1; /**< Windowed Load Timed Out. */ 2747215976Sjmallett uint64_t reserved_36_38 : 3; 2748215976Sjmallett uint64_t i0_pperr : 1; /**< If a parity error occured on the port's instruction 2749215976Sjmallett this bit may be set. */ 2750215976Sjmallett uint64_t reserved_32_34 : 3; 2751215976Sjmallett uint64_t p0_ptout : 1; /**< Port-0 output had a read timeout on a DATA/INFO 2752215976Sjmallett pair. */ 2753215976Sjmallett uint64_t reserved_28_30 : 3; 2754215976Sjmallett uint64_t p0_pperr : 1; /**< If a parity error occured on the port DATA/INFO 2755215976Sjmallett pointer-pair, this bit may be set. */ 2756215976Sjmallett uint64_t reserved_24_26 : 3; 2757215976Sjmallett uint64_t g0_rtout : 1; /**< Port-0 had a read timeout while attempting to 2758215976Sjmallett read a gather list. */ 2759215976Sjmallett uint64_t reserved_20_22 : 3; 2760215976Sjmallett uint64_t p0_perr : 1; /**< If a parity error occured on the port's packet 2761215976Sjmallett data this bit may be set. */ 2762215976Sjmallett uint64_t reserved_16_18 : 3; 2763215976Sjmallett uint64_t p0_rtout : 1; /**< Port-0 had a read timeout while attempting to 2764215976Sjmallett read packet data. */ 2765215976Sjmallett uint64_t reserved_12_14 : 3; 2766215976Sjmallett uint64_t i0_overf : 1; /**< Port-0 had a doorbell overflow. Bit[31] of the 2767215976Sjmallett doorbell count was set. */ 2768215976Sjmallett uint64_t reserved_8_10 : 3; 2769215976Sjmallett uint64_t i0_rtout : 1; /**< Port-0 had a read timeout while attempting to 2770215976Sjmallett read instructions. */ 2771215976Sjmallett uint64_t reserved_4_6 : 3; 2772215976Sjmallett uint64_t po0_2sml : 1; /**< The packet being sent out on Port0 is smaller 2773215976Sjmallett than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field. */ 2774215976Sjmallett uint64_t pci_rsl : 1; /**< This '1' when a bit in PCI_INT_SUM2 is SET and the 2775215976Sjmallett corresponding bit in the PCI_INT_ENB2 is SET. */ 2776215976Sjmallett uint64_t rml_wto : 1; /**< Set '1' when the RML does not receive a commit 2777215976Sjmallett back from a RSL after sending a write command to 2778215976Sjmallett a RSL. */ 2779215976Sjmallett uint64_t rml_rto : 1; /**< Set '1' when the RML does not receive read data 2780215976Sjmallett back from a RSL after sending a read command to 2781215976Sjmallett a RSL. */ 2782215976Sjmallett#else 2783215976Sjmallett uint64_t rml_rto : 1; 2784215976Sjmallett uint64_t rml_wto : 1; 2785215976Sjmallett uint64_t pci_rsl : 1; 2786215976Sjmallett uint64_t po0_2sml : 1; 2787215976Sjmallett uint64_t reserved_4_6 : 3; 2788215976Sjmallett uint64_t i0_rtout : 1; 2789215976Sjmallett uint64_t reserved_8_10 : 3; 2790215976Sjmallett uint64_t i0_overf : 1; 2791215976Sjmallett uint64_t reserved_12_14 : 3; 2792215976Sjmallett uint64_t p0_rtout : 1; 2793215976Sjmallett uint64_t reserved_16_18 : 3; 2794215976Sjmallett uint64_t p0_perr : 1; 2795215976Sjmallett uint64_t reserved_20_22 : 3; 2796215976Sjmallett uint64_t g0_rtout : 1; 2797215976Sjmallett uint64_t reserved_24_26 : 3; 2798215976Sjmallett uint64_t p0_pperr : 1; 2799215976Sjmallett uint64_t reserved_28_30 : 3; 2800215976Sjmallett uint64_t p0_ptout : 1; 2801215976Sjmallett uint64_t reserved_32_34 : 3; 2802215976Sjmallett uint64_t i0_pperr : 1; 2803215976Sjmallett uint64_t reserved_36_38 : 3; 2804215976Sjmallett uint64_t win_rto : 1; 2805215976Sjmallett uint64_t p_dperr : 1; 2806215976Sjmallett uint64_t iobdma : 1; 2807215976Sjmallett uint64_t fcr_s_e : 1; 2808215976Sjmallett uint64_t fcr_a_f : 1; 2809215976Sjmallett uint64_t pcr_s_e : 1; 2810215976Sjmallett uint64_t pcr_a_f : 1; 2811215976Sjmallett uint64_t q2_s_e : 1; 2812215976Sjmallett uint64_t q2_a_f : 1; 2813215976Sjmallett uint64_t q3_s_e : 1; 2814215976Sjmallett uint64_t q3_a_f : 1; 2815215976Sjmallett uint64_t com_s_e : 1; 2816215976Sjmallett uint64_t com_a_f : 1; 2817215976Sjmallett uint64_t pnc_s_e : 1; 2818215976Sjmallett uint64_t pnc_a_f : 1; 2819215976Sjmallett uint64_t rwx_s_e : 1; 2820215976Sjmallett uint64_t rdx_s_e : 1; 2821215976Sjmallett uint64_t pcf_p_e : 1; 2822215976Sjmallett uint64_t pcf_p_f : 1; 2823215976Sjmallett uint64_t pdf_p_e : 1; 2824215976Sjmallett uint64_t pdf_p_f : 1; 2825215976Sjmallett uint64_t q1_s_e : 1; 2826215976Sjmallett uint64_t q1_a_f : 1; 2827215976Sjmallett uint64_t reserved_62_63 : 2; 2828215976Sjmallett#endif 2829215976Sjmallett } cn30xx; 2830232812Sjmallett struct cvmx_npi_int_sum_cn31xx { 2831232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2832215976Sjmallett uint64_t reserved_62_63 : 2; 2833215976Sjmallett uint64_t q1_a_f : 1; /**< Attempted to add when Queue-1 FIFO is full. */ 2834215976Sjmallett uint64_t q1_s_e : 1; /**< Attempted to subtract when Queue-1 FIFO is empty. */ 2835215976Sjmallett uint64_t pdf_p_f : 1; /**< Attempted to push a full PCN-DATA-FIFO. */ 2836215976Sjmallett uint64_t pdf_p_e : 1; /**< Attempted to pop an empty PCN-DATA-FIFO. */ 2837215976Sjmallett uint64_t pcf_p_f : 1; /**< Attempted to push a full PCN-CNT-FIFO. */ 2838215976Sjmallett uint64_t pcf_p_e : 1; /**< Attempted to pop an empty PCN-CNT-FIFO. */ 2839215976Sjmallett uint64_t rdx_s_e : 1; /**< Attempted to subtract when DPI-XFR-Wait count is 0. */ 2840215976Sjmallett uint64_t rwx_s_e : 1; /**< Attempted to subtract when RDN-XFR-Wait count is 0. */ 2841215976Sjmallett uint64_t pnc_a_f : 1; /**< Attempted to add when PNI-NPI Credits are max. */ 2842215976Sjmallett uint64_t pnc_s_e : 1; /**< Attempted to subtract when PNI-NPI Credits are 0. */ 2843215976Sjmallett uint64_t com_a_f : 1; /**< Attempted to add when PCN-Commit Counter is max. */ 2844215976Sjmallett uint64_t com_s_e : 1; /**< Attempted to subtract when PCN-Commit Counter is 0. */ 2845215976Sjmallett uint64_t q3_a_f : 1; /**< Attempted to add when Queue-3 FIFO is full. */ 2846215976Sjmallett uint64_t q3_s_e : 1; /**< Attempted to subtract when Queue-3 FIFO is empty. */ 2847215976Sjmallett uint64_t q2_a_f : 1; /**< Attempted to add when Queue-2 FIFO is full. */ 2848215976Sjmallett uint64_t q2_s_e : 1; /**< Attempted to subtract when Queue-2 FIFO is empty. */ 2849215976Sjmallett uint64_t pcr_a_f : 1; /**< Attempted to add when POW Credits is full. */ 2850215976Sjmallett uint64_t pcr_s_e : 1; /**< Attempted to subtract when POW Credits is empty. */ 2851215976Sjmallett uint64_t fcr_a_f : 1; /**< Attempted to add when FPA Credits is full. */ 2852215976Sjmallett uint64_t fcr_s_e : 1; /**< Attempted to subtract when FPA Credits is empty. */ 2853215976Sjmallett uint64_t iobdma : 1; /**< Requested IOBDMA read size exceeded 128 words. */ 2854215976Sjmallett uint64_t p_dperr : 1; /**< If a parity error occured on data written to L2C 2855215976Sjmallett from the PCI this bit may be set. */ 2856215976Sjmallett uint64_t win_rto : 1; /**< Windowed Load Timed Out. */ 2857215976Sjmallett uint64_t reserved_37_38 : 2; 2858215976Sjmallett uint64_t i1_pperr : 1; /**< If a parity error occured on the port's instruction 2859215976Sjmallett this bit may be set. */ 2860215976Sjmallett uint64_t i0_pperr : 1; /**< If a parity error occured on the port's instruction 2861215976Sjmallett this bit may be set. */ 2862215976Sjmallett uint64_t reserved_33_34 : 2; 2863215976Sjmallett uint64_t p1_ptout : 1; /**< Port-1 output had a read timeout on a DATA/INFO 2864215976Sjmallett pair. */ 2865215976Sjmallett uint64_t p0_ptout : 1; /**< Port-0 output had a read timeout on a DATA/INFO 2866215976Sjmallett pair. */ 2867215976Sjmallett uint64_t reserved_29_30 : 2; 2868215976Sjmallett uint64_t p1_pperr : 1; /**< If a parity error occured on the port DATA/INFO 2869215976Sjmallett pointer-pair, this bit may be set. */ 2870215976Sjmallett uint64_t p0_pperr : 1; /**< If a parity error occured on the port DATA/INFO 2871215976Sjmallett pointer-pair, this bit may be set. */ 2872215976Sjmallett uint64_t reserved_25_26 : 2; 2873215976Sjmallett uint64_t g1_rtout : 1; /**< Port-1 had a read timeout while attempting to 2874215976Sjmallett read a gather list. */ 2875215976Sjmallett uint64_t g0_rtout : 1; /**< Port-0 had a read timeout while attempting to 2876215976Sjmallett read a gather list. */ 2877215976Sjmallett uint64_t reserved_21_22 : 2; 2878215976Sjmallett uint64_t p1_perr : 1; /**< If a parity error occured on the port's packet 2879215976Sjmallett data this bit may be set. */ 2880215976Sjmallett uint64_t p0_perr : 1; /**< If a parity error occured on the port's packet 2881215976Sjmallett data this bit may be set. */ 2882215976Sjmallett uint64_t reserved_17_18 : 2; 2883215976Sjmallett uint64_t p1_rtout : 1; /**< Port-1 had a read timeout while attempting to 2884215976Sjmallett read packet data. */ 2885215976Sjmallett uint64_t p0_rtout : 1; /**< Port-0 had a read timeout while attempting to 2886215976Sjmallett read packet data. */ 2887215976Sjmallett uint64_t reserved_13_14 : 2; 2888215976Sjmallett uint64_t i1_overf : 1; /**< Port-1 had a doorbell overflow. Bit[31] of the 2889215976Sjmallett doorbell count was set. */ 2890215976Sjmallett uint64_t i0_overf : 1; /**< Port-0 had a doorbell overflow. Bit[31] of the 2891215976Sjmallett doorbell count was set. */ 2892215976Sjmallett uint64_t reserved_9_10 : 2; 2893215976Sjmallett uint64_t i1_rtout : 1; /**< Port-1 had a read timeout while attempting to 2894215976Sjmallett read instructions. */ 2895215976Sjmallett uint64_t i0_rtout : 1; /**< Port-0 had a read timeout while attempting to 2896215976Sjmallett read instructions. */ 2897215976Sjmallett uint64_t reserved_5_6 : 2; 2898215976Sjmallett uint64_t po1_2sml : 1; /**< The packet being sent out on Port1 is smaller 2899215976Sjmallett than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field. */ 2900215976Sjmallett uint64_t po0_2sml : 1; /**< The packet being sent out on Port0 is smaller 2901215976Sjmallett than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field. */ 2902215976Sjmallett uint64_t pci_rsl : 1; /**< This '1' when a bit in PCI_INT_SUM2 is SET and the 2903215976Sjmallett corresponding bit in the PCI_INT_ENB2 is SET. */ 2904215976Sjmallett uint64_t rml_wto : 1; /**< Set '1' when the RML does not receive a commit 2905215976Sjmallett back from a RSL after sending a write command to 2906215976Sjmallett a RSL. */ 2907215976Sjmallett uint64_t rml_rto : 1; /**< Set '1' when the RML does not receive read data 2908215976Sjmallett back from a RSL after sending a read command to 2909215976Sjmallett a RSL. */ 2910215976Sjmallett#else 2911215976Sjmallett uint64_t rml_rto : 1; 2912215976Sjmallett uint64_t rml_wto : 1; 2913215976Sjmallett uint64_t pci_rsl : 1; 2914215976Sjmallett uint64_t po0_2sml : 1; 2915215976Sjmallett uint64_t po1_2sml : 1; 2916215976Sjmallett uint64_t reserved_5_6 : 2; 2917215976Sjmallett uint64_t i0_rtout : 1; 2918215976Sjmallett uint64_t i1_rtout : 1; 2919215976Sjmallett uint64_t reserved_9_10 : 2; 2920215976Sjmallett uint64_t i0_overf : 1; 2921215976Sjmallett uint64_t i1_overf : 1; 2922215976Sjmallett uint64_t reserved_13_14 : 2; 2923215976Sjmallett uint64_t p0_rtout : 1; 2924215976Sjmallett uint64_t p1_rtout : 1; 2925215976Sjmallett uint64_t reserved_17_18 : 2; 2926215976Sjmallett uint64_t p0_perr : 1; 2927215976Sjmallett uint64_t p1_perr : 1; 2928215976Sjmallett uint64_t reserved_21_22 : 2; 2929215976Sjmallett uint64_t g0_rtout : 1; 2930215976Sjmallett uint64_t g1_rtout : 1; 2931215976Sjmallett uint64_t reserved_25_26 : 2; 2932215976Sjmallett uint64_t p0_pperr : 1; 2933215976Sjmallett uint64_t p1_pperr : 1; 2934215976Sjmallett uint64_t reserved_29_30 : 2; 2935215976Sjmallett uint64_t p0_ptout : 1; 2936215976Sjmallett uint64_t p1_ptout : 1; 2937215976Sjmallett uint64_t reserved_33_34 : 2; 2938215976Sjmallett uint64_t i0_pperr : 1; 2939215976Sjmallett uint64_t i1_pperr : 1; 2940215976Sjmallett uint64_t reserved_37_38 : 2; 2941215976Sjmallett uint64_t win_rto : 1; 2942215976Sjmallett uint64_t p_dperr : 1; 2943215976Sjmallett uint64_t iobdma : 1; 2944215976Sjmallett uint64_t fcr_s_e : 1; 2945215976Sjmallett uint64_t fcr_a_f : 1; 2946215976Sjmallett uint64_t pcr_s_e : 1; 2947215976Sjmallett uint64_t pcr_a_f : 1; 2948215976Sjmallett uint64_t q2_s_e : 1; 2949215976Sjmallett uint64_t q2_a_f : 1; 2950215976Sjmallett uint64_t q3_s_e : 1; 2951215976Sjmallett uint64_t q3_a_f : 1; 2952215976Sjmallett uint64_t com_s_e : 1; 2953215976Sjmallett uint64_t com_a_f : 1; 2954215976Sjmallett uint64_t pnc_s_e : 1; 2955215976Sjmallett uint64_t pnc_a_f : 1; 2956215976Sjmallett uint64_t rwx_s_e : 1; 2957215976Sjmallett uint64_t rdx_s_e : 1; 2958215976Sjmallett uint64_t pcf_p_e : 1; 2959215976Sjmallett uint64_t pcf_p_f : 1; 2960215976Sjmallett uint64_t pdf_p_e : 1; 2961215976Sjmallett uint64_t pdf_p_f : 1; 2962215976Sjmallett uint64_t q1_s_e : 1; 2963215976Sjmallett uint64_t q1_a_f : 1; 2964215976Sjmallett uint64_t reserved_62_63 : 2; 2965215976Sjmallett#endif 2966215976Sjmallett } cn31xx; 2967215976Sjmallett struct cvmx_npi_int_sum_s cn38xx; 2968232812Sjmallett struct cvmx_npi_int_sum_cn38xxp2 { 2969232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 2970215976Sjmallett uint64_t reserved_42_63 : 22; 2971215976Sjmallett uint64_t iobdma : 1; /**< Requested IOBDMA read size exceeded 128 words. */ 2972215976Sjmallett uint64_t p_dperr : 1; /**< If a parity error occured on data written to L2C 2973215976Sjmallett from the PCI this bit may be set. */ 2974215976Sjmallett uint64_t win_rto : 1; /**< Windowed Load Timed Out. */ 2975215976Sjmallett uint64_t i3_pperr : 1; /**< If a parity error occured on the port's instruction 2976215976Sjmallett this bit may be set. */ 2977215976Sjmallett uint64_t i2_pperr : 1; /**< If a parity error occured on the port's instruction 2978215976Sjmallett this bit may be set. */ 2979215976Sjmallett uint64_t i1_pperr : 1; /**< If a parity error occured on the port's instruction 2980215976Sjmallett this bit may be set. */ 2981215976Sjmallett uint64_t i0_pperr : 1; /**< If a parity error occured on the port's instruction 2982215976Sjmallett this bit may be set. */ 2983215976Sjmallett uint64_t p3_ptout : 1; /**< Port-3 output had a read timeout on a DATA/INFO 2984215976Sjmallett pair. */ 2985215976Sjmallett uint64_t p2_ptout : 1; /**< Port-2 output had a read timeout on a DATA/INFO 2986215976Sjmallett pair. */ 2987215976Sjmallett uint64_t p1_ptout : 1; /**< Port-1 output had a read timeout on a DATA/INFO 2988215976Sjmallett pair. */ 2989215976Sjmallett uint64_t p0_ptout : 1; /**< Port-0 output had a read timeout on a DATA/INFO 2990215976Sjmallett pair. */ 2991215976Sjmallett uint64_t p3_pperr : 1; /**< If a parity error occured on the port DATA/INFO 2992215976Sjmallett pointer-pair, this bit may be set. */ 2993215976Sjmallett uint64_t p2_pperr : 1; /**< If a parity error occured on the port DATA/INFO 2994215976Sjmallett pointer-pair, this bit may be set. */ 2995215976Sjmallett uint64_t p1_pperr : 1; /**< If a parity error occured on the port DATA/INFO 2996215976Sjmallett pointer-pair, this bit may be set. */ 2997215976Sjmallett uint64_t p0_pperr : 1; /**< If a parity error occured on the port DATA/INFO 2998215976Sjmallett pointer-pair, this bit may be set. */ 2999215976Sjmallett uint64_t g3_rtout : 1; /**< Port-3 had a read timeout while attempting to 3000215976Sjmallett read a gather list. */ 3001215976Sjmallett uint64_t g2_rtout : 1; /**< Port-2 had a read timeout while attempting to 3002215976Sjmallett read a gather list. */ 3003215976Sjmallett uint64_t g1_rtout : 1; /**< Port-1 had a read timeout while attempting to 3004215976Sjmallett read a gather list. */ 3005215976Sjmallett uint64_t g0_rtout : 1; /**< Port-0 had a read timeout while attempting to 3006215976Sjmallett read a gather list. */ 3007215976Sjmallett uint64_t p3_perr : 1; /**< If a parity error occured on the port's packet 3008215976Sjmallett data this bit may be set. */ 3009215976Sjmallett uint64_t p2_perr : 1; /**< If a parity error occured on the port's packet 3010215976Sjmallett data this bit may be set. */ 3011215976Sjmallett uint64_t p1_perr : 1; /**< If a parity error occured on the port's packet 3012215976Sjmallett data this bit may be set. */ 3013215976Sjmallett uint64_t p0_perr : 1; /**< If a parity error occured on the port's packet 3014215976Sjmallett data this bit may be set. */ 3015215976Sjmallett uint64_t p3_rtout : 1; /**< Port-3 had a read timeout while attempting to 3016215976Sjmallett read packet data. */ 3017215976Sjmallett uint64_t p2_rtout : 1; /**< Port-2 had a read timeout while attempting to 3018215976Sjmallett read packet data. */ 3019215976Sjmallett uint64_t p1_rtout : 1; /**< Port-1 had a read timeout while attempting to 3020215976Sjmallett read packet data. */ 3021215976Sjmallett uint64_t p0_rtout : 1; /**< Port-0 had a read timeout while attempting to 3022215976Sjmallett read packet data. */ 3023215976Sjmallett uint64_t i3_overf : 1; /**< Port-3 had a doorbell overflow. Bit[31] of the 3024215976Sjmallett doorbell count was set. */ 3025215976Sjmallett uint64_t i2_overf : 1; /**< Port-2 had a doorbell overflow. Bit[31] of the 3026215976Sjmallett doorbell count was set. */ 3027215976Sjmallett uint64_t i1_overf : 1; /**< Port-1 had a doorbell overflow. Bit[31] of the 3028215976Sjmallett doorbell count was set. */ 3029215976Sjmallett uint64_t i0_overf : 1; /**< Port-0 had a doorbell overflow. Bit[31] of the 3030215976Sjmallett doorbell count was set. */ 3031215976Sjmallett uint64_t i3_rtout : 1; /**< Port-3 had a read timeout while attempting to 3032215976Sjmallett read instructions. */ 3033215976Sjmallett uint64_t i2_rtout : 1; /**< Port-2 had a read timeout while attempting to 3034215976Sjmallett read instructions. */ 3035215976Sjmallett uint64_t i1_rtout : 1; /**< Port-1 had a read timeout while attempting to 3036215976Sjmallett read instructions. */ 3037215976Sjmallett uint64_t i0_rtout : 1; /**< Port-0 had a read timeout while attempting to 3038215976Sjmallett read instructions. */ 3039215976Sjmallett uint64_t po3_2sml : 1; /**< The packet being sent out on Port3 is smaller 3040215976Sjmallett than the NPI_BUFF_SIZE_OUTPUT3[ISIZE] field. */ 3041215976Sjmallett uint64_t po2_2sml : 1; /**< The packet being sent out on Port2 is smaller 3042215976Sjmallett than the NPI_BUFF_SIZE_OUTPUT2[ISIZE] field. */ 3043215976Sjmallett uint64_t po1_2sml : 1; /**< The packet being sent out on Port1 is smaller 3044215976Sjmallett than the NPI_BUFF_SIZE_OUTPUT1[ISIZE] field. */ 3045215976Sjmallett uint64_t po0_2sml : 1; /**< The packet being sent out on Port0 is smaller 3046215976Sjmallett than the NPI_BUFF_SIZE_OUTPUT0[ISIZE] field. */ 3047215976Sjmallett uint64_t pci_rsl : 1; /**< This '1' when a bit in PCI_INT_SUM2 is SET and the 3048215976Sjmallett corresponding bit in the PCI_INT_ENB2 is SET. */ 3049215976Sjmallett uint64_t rml_wto : 1; /**< Set '1' when the RML does not receive a commit 3050215976Sjmallett back from a RSL after sending a write command to 3051215976Sjmallett a RSL. */ 3052215976Sjmallett uint64_t rml_rto : 1; /**< Set '1' when the RML does not receive read data 3053215976Sjmallett back from a RSL after sending a read command to 3054215976Sjmallett a RSL. */ 3055215976Sjmallett#else 3056215976Sjmallett uint64_t rml_rto : 1; 3057215976Sjmallett uint64_t rml_wto : 1; 3058215976Sjmallett uint64_t pci_rsl : 1; 3059215976Sjmallett uint64_t po0_2sml : 1; 3060215976Sjmallett uint64_t po1_2sml : 1; 3061215976Sjmallett uint64_t po2_2sml : 1; 3062215976Sjmallett uint64_t po3_2sml : 1; 3063215976Sjmallett uint64_t i0_rtout : 1; 3064215976Sjmallett uint64_t i1_rtout : 1; 3065215976Sjmallett uint64_t i2_rtout : 1; 3066215976Sjmallett uint64_t i3_rtout : 1; 3067215976Sjmallett uint64_t i0_overf : 1; 3068215976Sjmallett uint64_t i1_overf : 1; 3069215976Sjmallett uint64_t i2_overf : 1; 3070215976Sjmallett uint64_t i3_overf : 1; 3071215976Sjmallett uint64_t p0_rtout : 1; 3072215976Sjmallett uint64_t p1_rtout : 1; 3073215976Sjmallett uint64_t p2_rtout : 1; 3074215976Sjmallett uint64_t p3_rtout : 1; 3075215976Sjmallett uint64_t p0_perr : 1; 3076215976Sjmallett uint64_t p1_perr : 1; 3077215976Sjmallett uint64_t p2_perr : 1; 3078215976Sjmallett uint64_t p3_perr : 1; 3079215976Sjmallett uint64_t g0_rtout : 1; 3080215976Sjmallett uint64_t g1_rtout : 1; 3081215976Sjmallett uint64_t g2_rtout : 1; 3082215976Sjmallett uint64_t g3_rtout : 1; 3083215976Sjmallett uint64_t p0_pperr : 1; 3084215976Sjmallett uint64_t p1_pperr : 1; 3085215976Sjmallett uint64_t p2_pperr : 1; 3086215976Sjmallett uint64_t p3_pperr : 1; 3087215976Sjmallett uint64_t p0_ptout : 1; 3088215976Sjmallett uint64_t p1_ptout : 1; 3089215976Sjmallett uint64_t p2_ptout : 1; 3090215976Sjmallett uint64_t p3_ptout : 1; 3091215976Sjmallett uint64_t i0_pperr : 1; 3092215976Sjmallett uint64_t i1_pperr : 1; 3093215976Sjmallett uint64_t i2_pperr : 1; 3094215976Sjmallett uint64_t i3_pperr : 1; 3095215976Sjmallett uint64_t win_rto : 1; 3096215976Sjmallett uint64_t p_dperr : 1; 3097215976Sjmallett uint64_t iobdma : 1; 3098215976Sjmallett uint64_t reserved_42_63 : 22; 3099215976Sjmallett#endif 3100215976Sjmallett } cn38xxp2; 3101215976Sjmallett struct cvmx_npi_int_sum_cn31xx cn50xx; 3102215976Sjmallett struct cvmx_npi_int_sum_s cn58xx; 3103215976Sjmallett struct cvmx_npi_int_sum_s cn58xxp1; 3104215976Sjmallett}; 3105215976Sjmalletttypedef union cvmx_npi_int_sum cvmx_npi_int_sum_t; 3106215976Sjmallett 3107215976Sjmallett/** 3108215976Sjmallett * cvmx_npi_lowp_dbell 3109215976Sjmallett * 3110215976Sjmallett * NPI_LOWP_DBELL = Low Priority Door Bell 3111215976Sjmallett * 3112215976Sjmallett * The door bell register for the low priority DMA queue. 3113215976Sjmallett */ 3114232812Sjmallettunion cvmx_npi_lowp_dbell { 3115215976Sjmallett uint64_t u64; 3116232812Sjmallett struct cvmx_npi_lowp_dbell_s { 3117232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3118215976Sjmallett uint64_t reserved_16_63 : 48; 3119215976Sjmallett uint64_t dbell : 16; /**< The value written to this register is added to the 3120215976Sjmallett number of 8byte words to be read and processes for 3121215976Sjmallett the low priority dma queue. */ 3122215976Sjmallett#else 3123215976Sjmallett uint64_t dbell : 16; 3124215976Sjmallett uint64_t reserved_16_63 : 48; 3125215976Sjmallett#endif 3126215976Sjmallett } s; 3127215976Sjmallett struct cvmx_npi_lowp_dbell_s cn30xx; 3128215976Sjmallett struct cvmx_npi_lowp_dbell_s cn31xx; 3129215976Sjmallett struct cvmx_npi_lowp_dbell_s cn38xx; 3130215976Sjmallett struct cvmx_npi_lowp_dbell_s cn38xxp2; 3131215976Sjmallett struct cvmx_npi_lowp_dbell_s cn50xx; 3132215976Sjmallett struct cvmx_npi_lowp_dbell_s cn58xx; 3133215976Sjmallett struct cvmx_npi_lowp_dbell_s cn58xxp1; 3134215976Sjmallett}; 3135215976Sjmalletttypedef union cvmx_npi_lowp_dbell cvmx_npi_lowp_dbell_t; 3136215976Sjmallett 3137215976Sjmallett/** 3138215976Sjmallett * cvmx_npi_lowp_ibuff_saddr 3139215976Sjmallett * 3140215976Sjmallett * NPI_LOWP_IBUFF_SADDR = DMA Low Priority's Instruction Buffer Starting Address 3141215976Sjmallett * 3142215976Sjmallett * The address to start reading Instructions from for LOWP. 3143215976Sjmallett */ 3144232812Sjmallettunion cvmx_npi_lowp_ibuff_saddr { 3145215976Sjmallett uint64_t u64; 3146232812Sjmallett struct cvmx_npi_lowp_ibuff_saddr_s { 3147232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3148215976Sjmallett uint64_t reserved_36_63 : 28; 3149215976Sjmallett uint64_t saddr : 36; /**< The starting address to read the first instruction. */ 3150215976Sjmallett#else 3151215976Sjmallett uint64_t saddr : 36; 3152215976Sjmallett uint64_t reserved_36_63 : 28; 3153215976Sjmallett#endif 3154215976Sjmallett } s; 3155215976Sjmallett struct cvmx_npi_lowp_ibuff_saddr_s cn30xx; 3156215976Sjmallett struct cvmx_npi_lowp_ibuff_saddr_s cn31xx; 3157215976Sjmallett struct cvmx_npi_lowp_ibuff_saddr_s cn38xx; 3158215976Sjmallett struct cvmx_npi_lowp_ibuff_saddr_s cn38xxp2; 3159215976Sjmallett struct cvmx_npi_lowp_ibuff_saddr_s cn50xx; 3160215976Sjmallett struct cvmx_npi_lowp_ibuff_saddr_s cn58xx; 3161215976Sjmallett struct cvmx_npi_lowp_ibuff_saddr_s cn58xxp1; 3162215976Sjmallett}; 3163215976Sjmalletttypedef union cvmx_npi_lowp_ibuff_saddr cvmx_npi_lowp_ibuff_saddr_t; 3164215976Sjmallett 3165215976Sjmallett/** 3166215976Sjmallett * cvmx_npi_mem_access_subid# 3167215976Sjmallett * 3168215976Sjmallett * NPI_MEM_ACCESS_SUBID3 = Memory Access SubId 3Register 3169215976Sjmallett * 3170215976Sjmallett * Carries Read/Write parameters for PP access to PCI memory that use NPI SubId3. 3171215976Sjmallett * Writes to this register are not ordered with writes/reads to the PCI Memory space. 3172215976Sjmallett * To ensure that a write has completed the user must read the register before 3173215976Sjmallett * making an access(i.e. PCI memory space) that requires the value of this register to be updated. 3174215976Sjmallett */ 3175232812Sjmallettunion cvmx_npi_mem_access_subidx { 3176215976Sjmallett uint64_t u64; 3177232812Sjmallett struct cvmx_npi_mem_access_subidx_s { 3178232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3179215976Sjmallett uint64_t reserved_38_63 : 26; 3180215976Sjmallett uint64_t shortl : 1; /**< Generate CMD-6 on PCI(x) when '1'. 3181215976Sjmallett Loads from the cores to the corresponding subid 3182215976Sjmallett that are 32-bits or smaller: 3183215976Sjmallett - Will generate the PCI-X "Memory Read DWORD" 3184215976Sjmallett command in PCI-X mode. (Note that "Memory 3185215976Sjmallett Read DWORD" appears much like an IO read on 3186215976Sjmallett the PCI-X bus.) 3187215976Sjmallett - Will generate the PCI "Memory Read" command 3188215976Sjmallett in PCI-X mode, irrespective of the 3189215976Sjmallett NPI_PCI_READ_CMD[CMD_SIZE] value. 3190215976Sjmallett NOT IN PASS 1 NOR PASS 2 */ 3191215976Sjmallett uint64_t nmerge : 1; /**< No Merge. (NOT IN PASS 1 NOR PASS 2) */ 3192215976Sjmallett uint64_t esr : 2; /**< Endian-Swap on read. */ 3193215976Sjmallett uint64_t esw : 2; /**< Endian-Swap on write. */ 3194215976Sjmallett uint64_t nsr : 1; /**< No-Snoop on read. */ 3195215976Sjmallett uint64_t nsw : 1; /**< No-Snoop on write. */ 3196215976Sjmallett uint64_t ror : 1; /**< Relax Read on read. */ 3197215976Sjmallett uint64_t row : 1; /**< Relax Order on write. */ 3198215976Sjmallett uint64_t ba : 28; /**< PCI Address bits [63:36]. */ 3199215976Sjmallett#else 3200215976Sjmallett uint64_t ba : 28; 3201215976Sjmallett uint64_t row : 1; 3202215976Sjmallett uint64_t ror : 1; 3203215976Sjmallett uint64_t nsw : 1; 3204215976Sjmallett uint64_t nsr : 1; 3205215976Sjmallett uint64_t esw : 2; 3206215976Sjmallett uint64_t esr : 2; 3207215976Sjmallett uint64_t nmerge : 1; 3208215976Sjmallett uint64_t shortl : 1; 3209215976Sjmallett uint64_t reserved_38_63 : 26; 3210215976Sjmallett#endif 3211215976Sjmallett } s; 3212215976Sjmallett struct cvmx_npi_mem_access_subidx_s cn30xx; 3213232812Sjmallett struct cvmx_npi_mem_access_subidx_cn31xx { 3214232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3215215976Sjmallett uint64_t reserved_36_63 : 28; 3216215976Sjmallett uint64_t esr : 2; /**< Endian-Swap on read. */ 3217215976Sjmallett uint64_t esw : 2; /**< Endian-Swap on write. */ 3218215976Sjmallett uint64_t nsr : 1; /**< No-Snoop on read. */ 3219215976Sjmallett uint64_t nsw : 1; /**< No-Snoop on write. */ 3220215976Sjmallett uint64_t ror : 1; /**< Relax Read on read. */ 3221215976Sjmallett uint64_t row : 1; /**< Relax Order on write. */ 3222215976Sjmallett uint64_t ba : 28; /**< PCI Address bits [63:36]. */ 3223215976Sjmallett#else 3224215976Sjmallett uint64_t ba : 28; 3225215976Sjmallett uint64_t row : 1; 3226215976Sjmallett uint64_t ror : 1; 3227215976Sjmallett uint64_t nsw : 1; 3228215976Sjmallett uint64_t nsr : 1; 3229215976Sjmallett uint64_t esw : 2; 3230215976Sjmallett uint64_t esr : 2; 3231215976Sjmallett uint64_t reserved_36_63 : 28; 3232215976Sjmallett#endif 3233215976Sjmallett } cn31xx; 3234215976Sjmallett struct cvmx_npi_mem_access_subidx_s cn38xx; 3235215976Sjmallett struct cvmx_npi_mem_access_subidx_cn31xx cn38xxp2; 3236215976Sjmallett struct cvmx_npi_mem_access_subidx_s cn50xx; 3237215976Sjmallett struct cvmx_npi_mem_access_subidx_s cn58xx; 3238215976Sjmallett struct cvmx_npi_mem_access_subidx_s cn58xxp1; 3239215976Sjmallett}; 3240215976Sjmalletttypedef union cvmx_npi_mem_access_subidx cvmx_npi_mem_access_subidx_t; 3241215976Sjmallett 3242215976Sjmallett/** 3243215976Sjmallett * cvmx_npi_msi_rcv 3244215976Sjmallett * 3245215976Sjmallett * NPI_MSI_RCV = NPI MSI Receive Vector Register 3246215976Sjmallett * 3247215976Sjmallett * A bit is set in this register relative to the vector received during a MSI. And cleared by a W1 to the register. 3248215976Sjmallett */ 3249232812Sjmallettunion cvmx_npi_msi_rcv { 3250215976Sjmallett uint64_t u64; 3251232812Sjmallett struct cvmx_npi_msi_rcv_s { 3252232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3253215976Sjmallett uint64_t int_vec : 64; /**< Refer to PCI_MSI_RCV */ 3254215976Sjmallett#else 3255215976Sjmallett uint64_t int_vec : 64; 3256215976Sjmallett#endif 3257215976Sjmallett } s; 3258215976Sjmallett struct cvmx_npi_msi_rcv_s cn30xx; 3259215976Sjmallett struct cvmx_npi_msi_rcv_s cn31xx; 3260215976Sjmallett struct cvmx_npi_msi_rcv_s cn38xx; 3261215976Sjmallett struct cvmx_npi_msi_rcv_s cn38xxp2; 3262215976Sjmallett struct cvmx_npi_msi_rcv_s cn50xx; 3263215976Sjmallett struct cvmx_npi_msi_rcv_s cn58xx; 3264215976Sjmallett struct cvmx_npi_msi_rcv_s cn58xxp1; 3265215976Sjmallett}; 3266215976Sjmalletttypedef union cvmx_npi_msi_rcv cvmx_npi_msi_rcv_t; 3267215976Sjmallett 3268215976Sjmallett/** 3269215976Sjmallett * cvmx_npi_num_desc_output# 3270215976Sjmallett * 3271215976Sjmallett * NUM_DESC_OUTPUT0 = Number Of Descriptors Available For Output 0 3272215976Sjmallett * 3273215976Sjmallett * The size of the Buffer/Info Pointer Pair ring for Output-0. 3274215976Sjmallett */ 3275232812Sjmallettunion cvmx_npi_num_desc_outputx { 3276215976Sjmallett uint64_t u64; 3277232812Sjmallett struct cvmx_npi_num_desc_outputx_s { 3278232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3279215976Sjmallett uint64_t reserved_32_63 : 32; 3280215976Sjmallett uint64_t size : 32; /**< The size of the Buffer/Info Pointer Pair ring. */ 3281215976Sjmallett#else 3282215976Sjmallett uint64_t size : 32; 3283215976Sjmallett uint64_t reserved_32_63 : 32; 3284215976Sjmallett#endif 3285215976Sjmallett } s; 3286215976Sjmallett struct cvmx_npi_num_desc_outputx_s cn30xx; 3287215976Sjmallett struct cvmx_npi_num_desc_outputx_s cn31xx; 3288215976Sjmallett struct cvmx_npi_num_desc_outputx_s cn38xx; 3289215976Sjmallett struct cvmx_npi_num_desc_outputx_s cn38xxp2; 3290215976Sjmallett struct cvmx_npi_num_desc_outputx_s cn50xx; 3291215976Sjmallett struct cvmx_npi_num_desc_outputx_s cn58xx; 3292215976Sjmallett struct cvmx_npi_num_desc_outputx_s cn58xxp1; 3293215976Sjmallett}; 3294215976Sjmalletttypedef union cvmx_npi_num_desc_outputx cvmx_npi_num_desc_outputx_t; 3295215976Sjmallett 3296215976Sjmallett/** 3297215976Sjmallett * cvmx_npi_output_control 3298215976Sjmallett * 3299215976Sjmallett * NPI_OUTPUT_CONTROL = NPI's Output Control Register 3300215976Sjmallett * 3301215976Sjmallett * The address to start reading Instructions from for Output-3. 3302215976Sjmallett */ 3303232812Sjmallettunion cvmx_npi_output_control { 3304215976Sjmallett uint64_t u64; 3305232812Sjmallett struct cvmx_npi_output_control_s { 3306232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3307215976Sjmallett uint64_t reserved_49_63 : 15; 3308215976Sjmallett uint64_t pkt_rr : 1; /**< When set '1' the output packet selection will be 3309215976Sjmallett made with a Round Robin arbitration. When '0' 3310215976Sjmallett the output packet port is fixed in priority, 3311215976Sjmallett where the lower port number has higher priority. 3312215976Sjmallett PASS3 Field */ 3313215976Sjmallett uint64_t p3_bmode : 1; /**< When set '1' PCI_PKTS_SENT3 register will be 3314215976Sjmallett updated with the number of bytes in the packet 3315215976Sjmallett sent, when '0' the register will have a value 3316215976Sjmallett of '1' added. */ 3317215976Sjmallett uint64_t p2_bmode : 1; /**< When set '1' PCI_PKTS_SENT2 register will be 3318215976Sjmallett updated with the number of bytes in the packet 3319215976Sjmallett sent, when '0' the register will have a value 3320215976Sjmallett of '1' added. */ 3321215976Sjmallett uint64_t p1_bmode : 1; /**< When set '1' PCI_PKTS_SENT1 register will be 3322215976Sjmallett updated with the number of bytes in the packet 3323215976Sjmallett sent, when '0' the register will have a value 3324215976Sjmallett of '1' added. */ 3325215976Sjmallett uint64_t p0_bmode : 1; /**< When set '1' PCI_PKTS_SENT0 register will be 3326215976Sjmallett updated with the number of bytes in the packet 3327215976Sjmallett sent, when '0' the register will have a value 3328215976Sjmallett of '1' added. */ 3329215976Sjmallett uint64_t o3_es : 2; /**< Endian Swap for Output3 Data. */ 3330215976Sjmallett uint64_t o3_ns : 1; /**< NoSnoop Enable for Output3 Data. */ 3331215976Sjmallett uint64_t o3_ro : 1; /**< Relaxed Ordering Enable for Output3 Data. */ 3332215976Sjmallett uint64_t o2_es : 2; /**< Endian Swap for Output2 Data. */ 3333215976Sjmallett uint64_t o2_ns : 1; /**< NoSnoop Enable for Output2 Data. */ 3334215976Sjmallett uint64_t o2_ro : 1; /**< Relaxed Ordering Enable for Output2 Data. */ 3335215976Sjmallett uint64_t o1_es : 2; /**< Endian Swap for Output1 Data. */ 3336215976Sjmallett uint64_t o1_ns : 1; /**< NoSnoop Enable for Output1 Data. */ 3337215976Sjmallett uint64_t o1_ro : 1; /**< Relaxed Ordering Enable for Output1 Data. */ 3338215976Sjmallett uint64_t o0_es : 2; /**< Endian Swap for Output0 Data. */ 3339215976Sjmallett uint64_t o0_ns : 1; /**< NoSnoop Enable for Output0 Data. */ 3340215976Sjmallett uint64_t o0_ro : 1; /**< Relaxed Ordering Enable for Output0 Data. */ 3341215976Sjmallett uint64_t o3_csrm : 1; /**< When '1' the address[63:60] to write packet data, 3342215976Sjmallett comes from the DPTR[63:60] in the scatter-list pair, 3343215976Sjmallett and the RO, NS, ES values come from the O3_ES, 3344215976Sjmallett O3_NS, O3_RO. When '0' the RO == DPTR[60], 3345215976Sjmallett NS == DPTR[61], ES == DPTR[63:62], the address the 3346215976Sjmallett packet will be written to is ADDR[63:60] == 3347215976Sjmallett O3_ES[1:0], O3_NS, O3_RO. For Output Port-3. */ 3348215976Sjmallett uint64_t o2_csrm : 1; /**< When '1' the address[63:60] to write packet data, 3349215976Sjmallett comes from the DPTR[63:60] in the scatter-list pair, 3350215976Sjmallett and the RO, NS, ES values come from the O2_ES, 3351215976Sjmallett O2_NS, O2_RO. When '0' the RO == DPTR[60], 3352215976Sjmallett NS == DPTR[61], ES == DPTR[63:62], the address the 3353215976Sjmallett packet will be written to is ADDR[63:60] == 3354215976Sjmallett O2_ES[1:0], O2_NS, O2_RO. For Output Port-2. */ 3355215976Sjmallett uint64_t o1_csrm : 1; /**< When '1' the address[63:60] to write packet data, 3356215976Sjmallett comes from the DPTR[63:60] in the scatter-list pair, 3357215976Sjmallett and the RO, NS, ES values come from the O1_ES, 3358215976Sjmallett O1_NS, O1_RO. When '0' the RO == DPTR[60], 3359215976Sjmallett NS == DPTR[61], ES == DPTR[63:62], the address the 3360215976Sjmallett packet will be written to is ADDR[63:60] == 3361215976Sjmallett O1_ES[1:0], O1_NS, O1_RO. For Output Port-1. */ 3362215976Sjmallett uint64_t o0_csrm : 1; /**< When '1' the address[63:60] to write packet data, 3363215976Sjmallett comes from the DPTR[63:60] in the scatter-list pair, 3364215976Sjmallett and the RO, NS, ES values come from the O0_ES, 3365215976Sjmallett O0_NS, O0_RO. When '0' the RO == DPTR[60], 3366215976Sjmallett NS == DPTR[61], ES == DPTR[63:62], the address the 3367215976Sjmallett packet will be written to is ADDR[63:60] == 3368215976Sjmallett O0_ES[1:0], O0_NS, O0_RO. For Output Port-0. */ 3369215976Sjmallett uint64_t reserved_20_23 : 4; 3370215976Sjmallett uint64_t iptr_o3 : 1; /**< Uses the Info-Pointer to store length and data 3371215976Sjmallett for output-3. */ 3372215976Sjmallett uint64_t iptr_o2 : 1; /**< Uses the Info-Pointer to store length and data 3373215976Sjmallett for output-2. */ 3374215976Sjmallett uint64_t iptr_o1 : 1; /**< Uses the Info-Pointer to store length and data 3375215976Sjmallett for output-1. */ 3376215976Sjmallett uint64_t iptr_o0 : 1; /**< Uses the Info-Pointer to store length and data 3377215976Sjmallett for output-0. */ 3378215976Sjmallett uint64_t esr_sl3 : 2; /**< The Endian-Swap-Mode for Slist3 reads. */ 3379215976Sjmallett uint64_t nsr_sl3 : 1; /**< Enables '1' NoSnoop for Slist3 reads. */ 3380215976Sjmallett uint64_t ror_sl3 : 1; /**< Enables '1' Relaxed Ordering for Slist3 reads. */ 3381215976Sjmallett uint64_t esr_sl2 : 2; /**< The Endian-Swap-Mode for Slist2 reads. */ 3382215976Sjmallett uint64_t nsr_sl2 : 1; /**< Enables '1' NoSnoop for Slist2 reads. */ 3383215976Sjmallett uint64_t ror_sl2 : 1; /**< Enables '1' Relaxed Ordering for Slist2 reads. */ 3384215976Sjmallett uint64_t esr_sl1 : 2; /**< The Endian-Swap-Mode for Slist1 reads. */ 3385215976Sjmallett uint64_t nsr_sl1 : 1; /**< Enables '1' NoSnoop for Slist1 reads. */ 3386215976Sjmallett uint64_t ror_sl1 : 1; /**< Enables '1' Relaxed Ordering for Slist1 reads. */ 3387215976Sjmallett uint64_t esr_sl0 : 2; /**< The Endian-Swap-Mode for Slist0 reads. */ 3388215976Sjmallett uint64_t nsr_sl0 : 1; /**< Enables '1' NoSnoop for Slist0 reads. */ 3389215976Sjmallett uint64_t ror_sl0 : 1; /**< Enables '1' Relaxed Ordering for Slist0 reads. */ 3390215976Sjmallett#else 3391215976Sjmallett uint64_t ror_sl0 : 1; 3392215976Sjmallett uint64_t nsr_sl0 : 1; 3393215976Sjmallett uint64_t esr_sl0 : 2; 3394215976Sjmallett uint64_t ror_sl1 : 1; 3395215976Sjmallett uint64_t nsr_sl1 : 1; 3396215976Sjmallett uint64_t esr_sl1 : 2; 3397215976Sjmallett uint64_t ror_sl2 : 1; 3398215976Sjmallett uint64_t nsr_sl2 : 1; 3399215976Sjmallett uint64_t esr_sl2 : 2; 3400215976Sjmallett uint64_t ror_sl3 : 1; 3401215976Sjmallett uint64_t nsr_sl3 : 1; 3402215976Sjmallett uint64_t esr_sl3 : 2; 3403215976Sjmallett uint64_t iptr_o0 : 1; 3404215976Sjmallett uint64_t iptr_o1 : 1; 3405215976Sjmallett uint64_t iptr_o2 : 1; 3406215976Sjmallett uint64_t iptr_o3 : 1; 3407215976Sjmallett uint64_t reserved_20_23 : 4; 3408215976Sjmallett uint64_t o0_csrm : 1; 3409215976Sjmallett uint64_t o1_csrm : 1; 3410215976Sjmallett uint64_t o2_csrm : 1; 3411215976Sjmallett uint64_t o3_csrm : 1; 3412215976Sjmallett uint64_t o0_ro : 1; 3413215976Sjmallett uint64_t o0_ns : 1; 3414215976Sjmallett uint64_t o0_es : 2; 3415215976Sjmallett uint64_t o1_ro : 1; 3416215976Sjmallett uint64_t o1_ns : 1; 3417215976Sjmallett uint64_t o1_es : 2; 3418215976Sjmallett uint64_t o2_ro : 1; 3419215976Sjmallett uint64_t o2_ns : 1; 3420215976Sjmallett uint64_t o2_es : 2; 3421215976Sjmallett uint64_t o3_ro : 1; 3422215976Sjmallett uint64_t o3_ns : 1; 3423215976Sjmallett uint64_t o3_es : 2; 3424215976Sjmallett uint64_t p0_bmode : 1; 3425215976Sjmallett uint64_t p1_bmode : 1; 3426215976Sjmallett uint64_t p2_bmode : 1; 3427215976Sjmallett uint64_t p3_bmode : 1; 3428215976Sjmallett uint64_t pkt_rr : 1; 3429215976Sjmallett uint64_t reserved_49_63 : 15; 3430215976Sjmallett#endif 3431215976Sjmallett } s; 3432232812Sjmallett struct cvmx_npi_output_control_cn30xx { 3433232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3434215976Sjmallett uint64_t reserved_45_63 : 19; 3435215976Sjmallett uint64_t p0_bmode : 1; /**< When set '1' PCI_PKTS_SENT0 register will be 3436215976Sjmallett updated with the number of bytes in the packet 3437215976Sjmallett sent, when '0' the register will have a value 3438215976Sjmallett of '1' added. */ 3439215976Sjmallett uint64_t reserved_32_43 : 12; 3440215976Sjmallett uint64_t o0_es : 2; /**< Endian Swap for Output0 Data. */ 3441215976Sjmallett uint64_t o0_ns : 1; /**< NoSnoop Enable for Output0 Data. */ 3442215976Sjmallett uint64_t o0_ro : 1; /**< Relaxed Ordering Enable for Output0 Data. */ 3443215976Sjmallett uint64_t reserved_25_27 : 3; 3444215976Sjmallett uint64_t o0_csrm : 1; /**< When '1' the address[63:60] to write packet data, 3445215976Sjmallett comes from the DPTR[63:60] in the scatter-list pair, 3446215976Sjmallett and the RO, NS, ES values come from the O0_ES, 3447215976Sjmallett O0_NS, O0_RO. When '0' the RO == DPTR[60], 3448215976Sjmallett NS == DPTR[61], ES == DPTR[63:62], the address the 3449215976Sjmallett packet will be written to is ADDR[63:60] == 3450215976Sjmallett O0_ES[1:0], O0_NS, O0_RO. For Output Port-0. */ 3451215976Sjmallett uint64_t reserved_17_23 : 7; 3452215976Sjmallett uint64_t iptr_o0 : 1; /**< Uses the Info-Pointer to store length and data 3453215976Sjmallett for output-0. */ 3454215976Sjmallett uint64_t reserved_4_15 : 12; 3455215976Sjmallett uint64_t esr_sl0 : 2; /**< The Endian-Swap-Mode for Slist0 reads. */ 3456215976Sjmallett uint64_t nsr_sl0 : 1; /**< Enables '1' NoSnoop for Slist0 reads. */ 3457215976Sjmallett uint64_t ror_sl0 : 1; /**< Enables '1' Relaxed Ordering for Slist0 reads. */ 3458215976Sjmallett#else 3459215976Sjmallett uint64_t ror_sl0 : 1; 3460215976Sjmallett uint64_t nsr_sl0 : 1; 3461215976Sjmallett uint64_t esr_sl0 : 2; 3462215976Sjmallett uint64_t reserved_4_15 : 12; 3463215976Sjmallett uint64_t iptr_o0 : 1; 3464215976Sjmallett uint64_t reserved_17_23 : 7; 3465215976Sjmallett uint64_t o0_csrm : 1; 3466215976Sjmallett uint64_t reserved_25_27 : 3; 3467215976Sjmallett uint64_t o0_ro : 1; 3468215976Sjmallett uint64_t o0_ns : 1; 3469215976Sjmallett uint64_t o0_es : 2; 3470215976Sjmallett uint64_t reserved_32_43 : 12; 3471215976Sjmallett uint64_t p0_bmode : 1; 3472215976Sjmallett uint64_t reserved_45_63 : 19; 3473215976Sjmallett#endif 3474215976Sjmallett } cn30xx; 3475232812Sjmallett struct cvmx_npi_output_control_cn31xx { 3476232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3477215976Sjmallett uint64_t reserved_46_63 : 18; 3478215976Sjmallett uint64_t p1_bmode : 1; /**< When set '1' PCI_PKTS_SENT1 register will be 3479215976Sjmallett updated with the number of bytes in the packet 3480215976Sjmallett sent, when '0' the register will have a value 3481215976Sjmallett of '1' added. */ 3482215976Sjmallett uint64_t p0_bmode : 1; /**< When set '1' PCI_PKTS_SENT0 register will be 3483215976Sjmallett updated with the number of bytes in the packet 3484215976Sjmallett sent, when '0' the register will have a value 3485215976Sjmallett of '1' added. */ 3486215976Sjmallett uint64_t reserved_36_43 : 8; 3487215976Sjmallett uint64_t o1_es : 2; /**< Endian Swap for Output1 Data. */ 3488215976Sjmallett uint64_t o1_ns : 1; /**< NoSnoop Enable for Output1 Data. */ 3489215976Sjmallett uint64_t o1_ro : 1; /**< Relaxed Ordering Enable for Output1 Data. */ 3490215976Sjmallett uint64_t o0_es : 2; /**< Endian Swap for Output0 Data. */ 3491215976Sjmallett uint64_t o0_ns : 1; /**< NoSnoop Enable for Output0 Data. */ 3492215976Sjmallett uint64_t o0_ro : 1; /**< Relaxed Ordering Enable for Output0 Data. */ 3493215976Sjmallett uint64_t reserved_26_27 : 2; 3494215976Sjmallett uint64_t o1_csrm : 1; /**< When '1' the address[63:60] to write packet data, 3495215976Sjmallett comes from the DPTR[63:60] in the scatter-list pair, 3496215976Sjmallett and the RO, NS, ES values come from the O1_ES, 3497215976Sjmallett O1_NS, O1_RO. When '0' the RO == DPTR[60], 3498215976Sjmallett NS == DPTR[61], ES == DPTR[63:62], the address the 3499215976Sjmallett packet will be written to is ADDR[63:60] == 3500215976Sjmallett O1_ES[1:0], O1_NS, O1_RO. For Output Port-1. */ 3501215976Sjmallett uint64_t o0_csrm : 1; /**< When '1' the address[63:60] to write packet data, 3502215976Sjmallett comes from the DPTR[63:60] in the scatter-list pair, 3503215976Sjmallett and the RO, NS, ES values come from the O0_ES, 3504215976Sjmallett O0_NS, O0_RO. When '0' the RO == DPTR[60], 3505215976Sjmallett NS == DPTR[61], ES == DPTR[63:62], the address the 3506215976Sjmallett packet will be written to is ADDR[63:60] == 3507215976Sjmallett O0_ES[1:0], O0_NS, O0_RO. For Output Port-0. */ 3508215976Sjmallett uint64_t reserved_18_23 : 6; 3509215976Sjmallett uint64_t iptr_o1 : 1; /**< Uses the Info-Pointer to store length and data 3510215976Sjmallett for output-1. */ 3511215976Sjmallett uint64_t iptr_o0 : 1; /**< Uses the Info-Pointer to store length and data 3512215976Sjmallett for output-0. */ 3513215976Sjmallett uint64_t reserved_8_15 : 8; 3514215976Sjmallett uint64_t esr_sl1 : 2; /**< The Endian-Swap-Mode for Slist1 reads. */ 3515215976Sjmallett uint64_t nsr_sl1 : 1; /**< Enables '1' NoSnoop for Slist1 reads. */ 3516215976Sjmallett uint64_t ror_sl1 : 1; /**< Enables '1' Relaxed Ordering for Slist1 reads. */ 3517215976Sjmallett uint64_t esr_sl0 : 2; /**< The Endian-Swap-Mode for Slist0 reads. */ 3518215976Sjmallett uint64_t nsr_sl0 : 1; /**< Enables '1' NoSnoop for Slist0 reads. */ 3519215976Sjmallett uint64_t ror_sl0 : 1; /**< Enables '1' Relaxed Ordering for Slist0 reads. */ 3520215976Sjmallett#else 3521215976Sjmallett uint64_t ror_sl0 : 1; 3522215976Sjmallett uint64_t nsr_sl0 : 1; 3523215976Sjmallett uint64_t esr_sl0 : 2; 3524215976Sjmallett uint64_t ror_sl1 : 1; 3525215976Sjmallett uint64_t nsr_sl1 : 1; 3526215976Sjmallett uint64_t esr_sl1 : 2; 3527215976Sjmallett uint64_t reserved_8_15 : 8; 3528215976Sjmallett uint64_t iptr_o0 : 1; 3529215976Sjmallett uint64_t iptr_o1 : 1; 3530215976Sjmallett uint64_t reserved_18_23 : 6; 3531215976Sjmallett uint64_t o0_csrm : 1; 3532215976Sjmallett uint64_t o1_csrm : 1; 3533215976Sjmallett uint64_t reserved_26_27 : 2; 3534215976Sjmallett uint64_t o0_ro : 1; 3535215976Sjmallett uint64_t o0_ns : 1; 3536215976Sjmallett uint64_t o0_es : 2; 3537215976Sjmallett uint64_t o1_ro : 1; 3538215976Sjmallett uint64_t o1_ns : 1; 3539215976Sjmallett uint64_t o1_es : 2; 3540215976Sjmallett uint64_t reserved_36_43 : 8; 3541215976Sjmallett uint64_t p0_bmode : 1; 3542215976Sjmallett uint64_t p1_bmode : 1; 3543215976Sjmallett uint64_t reserved_46_63 : 18; 3544215976Sjmallett#endif 3545215976Sjmallett } cn31xx; 3546215976Sjmallett struct cvmx_npi_output_control_s cn38xx; 3547232812Sjmallett struct cvmx_npi_output_control_cn38xxp2 { 3548232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3549215976Sjmallett uint64_t reserved_48_63 : 16; 3550215976Sjmallett uint64_t p3_bmode : 1; /**< When set '1' PCI_PKTS_SENT3 register will be 3551215976Sjmallett updated with the number of bytes in the packet 3552215976Sjmallett sent, when '0' the register will have a value 3553215976Sjmallett of '1' added. */ 3554215976Sjmallett uint64_t p2_bmode : 1; /**< When set '1' PCI_PKTS_SENT2 register will be 3555215976Sjmallett updated with the number of bytes in the packet 3556215976Sjmallett sent, when '0' the register will have a value 3557215976Sjmallett of '1' added. */ 3558215976Sjmallett uint64_t p1_bmode : 1; /**< When set '1' PCI_PKTS_SENT1 register will be 3559215976Sjmallett updated with the number of bytes in the packet 3560215976Sjmallett sent, when '0' the register will have a value 3561215976Sjmallett of '1' added. */ 3562215976Sjmallett uint64_t p0_bmode : 1; /**< When set '1' PCI_PKTS_SENT0 register will be 3563215976Sjmallett updated with the number of bytes in the packet 3564215976Sjmallett sent, when '0' the register will have a value 3565215976Sjmallett of '1' added. */ 3566215976Sjmallett uint64_t o3_es : 2; /**< Endian Swap for Output3 Data. */ 3567215976Sjmallett uint64_t o3_ns : 1; /**< NoSnoop Enable for Output3 Data. */ 3568215976Sjmallett uint64_t o3_ro : 1; /**< Relaxed Ordering Enable for Output3 Data. */ 3569215976Sjmallett uint64_t o2_es : 2; /**< Endian Swap for Output2 Data. */ 3570215976Sjmallett uint64_t o2_ns : 1; /**< NoSnoop Enable for Output2 Data. */ 3571215976Sjmallett uint64_t o2_ro : 1; /**< Relaxed Ordering Enable for Output2 Data. */ 3572215976Sjmallett uint64_t o1_es : 2; /**< Endian Swap for Output1 Data. */ 3573215976Sjmallett uint64_t o1_ns : 1; /**< NoSnoop Enable for Output1 Data. */ 3574215976Sjmallett uint64_t o1_ro : 1; /**< Relaxed Ordering Enable for Output1 Data. */ 3575215976Sjmallett uint64_t o0_es : 2; /**< Endian Swap for Output0 Data. */ 3576215976Sjmallett uint64_t o0_ns : 1; /**< NoSnoop Enable for Output0 Data. */ 3577215976Sjmallett uint64_t o0_ro : 1; /**< Relaxed Ordering Enable for Output0 Data. */ 3578215976Sjmallett uint64_t o3_csrm : 1; /**< When '1' the address[63:60] to write packet data, 3579215976Sjmallett comes from the DPTR[63:60] in the scatter-list pair, 3580215976Sjmallett and the RO, NS, ES values come from the O3_ES, 3581215976Sjmallett O3_NS, O3_RO. When '0' the RO == DPTR[60], 3582215976Sjmallett NS == DPTR[61], ES == DPTR[63:62], the address the 3583215976Sjmallett packet will be written to is ADDR[63:60] == 3584215976Sjmallett O3_ES[1:0], O3_NS, O3_RO. For Output Port-3. */ 3585215976Sjmallett uint64_t o2_csrm : 1; /**< When '1' the address[63:60] to write packet data, 3586215976Sjmallett comes from the DPTR[63:60] in the scatter-list pair, 3587215976Sjmallett and the RO, NS, ES values come from the O2_ES, 3588215976Sjmallett O2_NS, O2_RO. When '0' the RO == DPTR[60], 3589215976Sjmallett NS == DPTR[61], ES == DPTR[63:62], the address the 3590215976Sjmallett packet will be written to is ADDR[63:60] == 3591215976Sjmallett O2_ES[1:0], O2_NS, O2_RO. For Output Port-2. */ 3592215976Sjmallett uint64_t o1_csrm : 1; /**< When '1' the address[63:60] to write packet data, 3593215976Sjmallett comes from the DPTR[63:60] in the scatter-list pair, 3594215976Sjmallett and the RO, NS, ES values come from the O1_ES, 3595215976Sjmallett O1_NS, O1_RO. When '0' the RO == DPTR[60], 3596215976Sjmallett NS == DPTR[61], ES == DPTR[63:62], the address the 3597215976Sjmallett packet will be written to is ADDR[63:60] == 3598215976Sjmallett O1_ES[1:0], O1_NS, O1_RO. For Output Port-1. */ 3599215976Sjmallett uint64_t o0_csrm : 1; /**< When '1' the address[63:60] to write packet data, 3600215976Sjmallett comes from the DPTR[63:60] in the scatter-list pair, 3601215976Sjmallett and the RO, NS, ES values come from the O0_ES, 3602215976Sjmallett O0_NS, O0_RO. When '0' the RO == DPTR[60], 3603215976Sjmallett NS == DPTR[61], ES == DPTR[63:62], the address the 3604215976Sjmallett packet will be written to is ADDR[63:60] == 3605215976Sjmallett O0_ES[1:0], O0_NS, O0_RO. For Output Port-0. */ 3606215976Sjmallett uint64_t reserved_20_23 : 4; 3607215976Sjmallett uint64_t iptr_o3 : 1; /**< Uses the Info-Pointer to store length and data 3608215976Sjmallett for output-3. */ 3609215976Sjmallett uint64_t iptr_o2 : 1; /**< Uses the Info-Pointer to store length and data 3610215976Sjmallett for output-2. */ 3611215976Sjmallett uint64_t iptr_o1 : 1; /**< Uses the Info-Pointer to store length and data 3612215976Sjmallett for output-1. */ 3613215976Sjmallett uint64_t iptr_o0 : 1; /**< Uses the Info-Pointer to store length and data 3614215976Sjmallett for output-0. */ 3615215976Sjmallett uint64_t esr_sl3 : 2; /**< The Endian-Swap-Mode for Slist3 reads. */ 3616215976Sjmallett uint64_t nsr_sl3 : 1; /**< Enables '1' NoSnoop for Slist3 reads. */ 3617215976Sjmallett uint64_t ror_sl3 : 1; /**< Enables '1' Relaxed Ordering for Slist3 reads. */ 3618215976Sjmallett uint64_t esr_sl2 : 2; /**< The Endian-Swap-Mode for Slist2 reads. */ 3619215976Sjmallett uint64_t nsr_sl2 : 1; /**< Enables '1' NoSnoop for Slist2 reads. */ 3620215976Sjmallett uint64_t ror_sl2 : 1; /**< Enables '1' Relaxed Ordering for Slist2 reads. */ 3621215976Sjmallett uint64_t esr_sl1 : 2; /**< The Endian-Swap-Mode for Slist1 reads. */ 3622215976Sjmallett uint64_t nsr_sl1 : 1; /**< Enables '1' NoSnoop for Slist1 reads. */ 3623215976Sjmallett uint64_t ror_sl1 : 1; /**< Enables '1' Relaxed Ordering for Slist1 reads. */ 3624215976Sjmallett uint64_t esr_sl0 : 2; /**< The Endian-Swap-Mode for Slist0 reads. */ 3625215976Sjmallett uint64_t nsr_sl0 : 1; /**< Enables '1' NoSnoop for Slist0 reads. */ 3626215976Sjmallett uint64_t ror_sl0 : 1; /**< Enables '1' Relaxed Ordering for Slist0 reads. */ 3627215976Sjmallett#else 3628215976Sjmallett uint64_t ror_sl0 : 1; 3629215976Sjmallett uint64_t nsr_sl0 : 1; 3630215976Sjmallett uint64_t esr_sl0 : 2; 3631215976Sjmallett uint64_t ror_sl1 : 1; 3632215976Sjmallett uint64_t nsr_sl1 : 1; 3633215976Sjmallett uint64_t esr_sl1 : 2; 3634215976Sjmallett uint64_t ror_sl2 : 1; 3635215976Sjmallett uint64_t nsr_sl2 : 1; 3636215976Sjmallett uint64_t esr_sl2 : 2; 3637215976Sjmallett uint64_t ror_sl3 : 1; 3638215976Sjmallett uint64_t nsr_sl3 : 1; 3639215976Sjmallett uint64_t esr_sl3 : 2; 3640215976Sjmallett uint64_t iptr_o0 : 1; 3641215976Sjmallett uint64_t iptr_o1 : 1; 3642215976Sjmallett uint64_t iptr_o2 : 1; 3643215976Sjmallett uint64_t iptr_o3 : 1; 3644215976Sjmallett uint64_t reserved_20_23 : 4; 3645215976Sjmallett uint64_t o0_csrm : 1; 3646215976Sjmallett uint64_t o1_csrm : 1; 3647215976Sjmallett uint64_t o2_csrm : 1; 3648215976Sjmallett uint64_t o3_csrm : 1; 3649215976Sjmallett uint64_t o0_ro : 1; 3650215976Sjmallett uint64_t o0_ns : 1; 3651215976Sjmallett uint64_t o0_es : 2; 3652215976Sjmallett uint64_t o1_ro : 1; 3653215976Sjmallett uint64_t o1_ns : 1; 3654215976Sjmallett uint64_t o1_es : 2; 3655215976Sjmallett uint64_t o2_ro : 1; 3656215976Sjmallett uint64_t o2_ns : 1; 3657215976Sjmallett uint64_t o2_es : 2; 3658215976Sjmallett uint64_t o3_ro : 1; 3659215976Sjmallett uint64_t o3_ns : 1; 3660215976Sjmallett uint64_t o3_es : 2; 3661215976Sjmallett uint64_t p0_bmode : 1; 3662215976Sjmallett uint64_t p1_bmode : 1; 3663215976Sjmallett uint64_t p2_bmode : 1; 3664215976Sjmallett uint64_t p3_bmode : 1; 3665215976Sjmallett uint64_t reserved_48_63 : 16; 3666215976Sjmallett#endif 3667215976Sjmallett } cn38xxp2; 3668232812Sjmallett struct cvmx_npi_output_control_cn50xx { 3669232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3670215976Sjmallett uint64_t reserved_49_63 : 15; 3671215976Sjmallett uint64_t pkt_rr : 1; /**< When set '1' the output packet selection will be 3672215976Sjmallett made with a Round Robin arbitration. When '0' 3673215976Sjmallett the output packet port is fixed in priority, 3674215976Sjmallett where the lower port number has higher priority. 3675215976Sjmallett PASS2 Field */ 3676215976Sjmallett uint64_t reserved_46_47 : 2; 3677215976Sjmallett uint64_t p1_bmode : 1; /**< When set '1' PCI_PKTS_SENT1 register will be 3678215976Sjmallett updated with the number of bytes in the packet 3679215976Sjmallett sent, when '0' the register will have a value 3680215976Sjmallett of '1' added. */ 3681215976Sjmallett uint64_t p0_bmode : 1; /**< When set '1' PCI_PKTS_SENT0 register will be 3682215976Sjmallett updated with the number of bytes in the packet 3683215976Sjmallett sent, when '0' the register will have a value 3684215976Sjmallett of '1' added. */ 3685215976Sjmallett uint64_t reserved_36_43 : 8; 3686215976Sjmallett uint64_t o1_es : 2; /**< Endian Swap for Output1 Data. */ 3687215976Sjmallett uint64_t o1_ns : 1; /**< NoSnoop Enable for Output1 Data. */ 3688215976Sjmallett uint64_t o1_ro : 1; /**< Relaxed Ordering Enable for Output1 Data. */ 3689215976Sjmallett uint64_t o0_es : 2; /**< Endian Swap for Output0 Data. */ 3690215976Sjmallett uint64_t o0_ns : 1; /**< NoSnoop Enable for Output0 Data. */ 3691215976Sjmallett uint64_t o0_ro : 1; /**< Relaxed Ordering Enable for Output0 Data. */ 3692215976Sjmallett uint64_t reserved_26_27 : 2; 3693215976Sjmallett uint64_t o1_csrm : 1; /**< When '1' the address[63:60] to write packet data, 3694215976Sjmallett comes from the DPTR[63:60] in the scatter-list pair, 3695215976Sjmallett and the RO, NS, ES values come from the O1_ES, 3696215976Sjmallett O1_NS, O1_RO. When '0' the RO == DPTR[60], 3697215976Sjmallett NS == DPTR[61], ES == DPTR[63:62], the address the 3698215976Sjmallett packet will be written to is ADDR[63:60] == 3699215976Sjmallett O1_ES[1:0], O1_NS, O1_RO. For Output Port-1. */ 3700215976Sjmallett uint64_t o0_csrm : 1; /**< When '1' the address[63:60] to write packet data, 3701215976Sjmallett comes from the DPTR[63:60] in the scatter-list pair, 3702215976Sjmallett and the RO, NS, ES values come from the O0_ES, 3703215976Sjmallett O0_NS, O0_RO. When '0' the RO == DPTR[60], 3704215976Sjmallett NS == DPTR[61], ES == DPTR[63:62], the address the 3705215976Sjmallett packet will be written to is ADDR[63:60] == 3706215976Sjmallett O0_ES[1:0], O0_NS, O0_RO. For Output Port-0. */ 3707215976Sjmallett uint64_t reserved_18_23 : 6; 3708215976Sjmallett uint64_t iptr_o1 : 1; /**< Uses the Info-Pointer to store length and data 3709215976Sjmallett for output-1. */ 3710215976Sjmallett uint64_t iptr_o0 : 1; /**< Uses the Info-Pointer to store length and data 3711215976Sjmallett for output-0. */ 3712215976Sjmallett uint64_t reserved_8_15 : 8; 3713215976Sjmallett uint64_t esr_sl1 : 2; /**< The Endian-Swap-Mode for Slist1 reads. */ 3714215976Sjmallett uint64_t nsr_sl1 : 1; /**< Enables '1' NoSnoop for Slist1 reads. */ 3715215976Sjmallett uint64_t ror_sl1 : 1; /**< Enables '1' Relaxed Ordering for Slist1 reads. */ 3716215976Sjmallett uint64_t esr_sl0 : 2; /**< The Endian-Swap-Mode for Slist0 reads. */ 3717215976Sjmallett uint64_t nsr_sl0 : 1; /**< Enables '1' NoSnoop for Slist0 reads. */ 3718215976Sjmallett uint64_t ror_sl0 : 1; /**< Enables '1' Relaxed Ordering for Slist0 reads. */ 3719215976Sjmallett#else 3720215976Sjmallett uint64_t ror_sl0 : 1; 3721215976Sjmallett uint64_t nsr_sl0 : 1; 3722215976Sjmallett uint64_t esr_sl0 : 2; 3723215976Sjmallett uint64_t ror_sl1 : 1; 3724215976Sjmallett uint64_t nsr_sl1 : 1; 3725215976Sjmallett uint64_t esr_sl1 : 2; 3726215976Sjmallett uint64_t reserved_8_15 : 8; 3727215976Sjmallett uint64_t iptr_o0 : 1; 3728215976Sjmallett uint64_t iptr_o1 : 1; 3729215976Sjmallett uint64_t reserved_18_23 : 6; 3730215976Sjmallett uint64_t o0_csrm : 1; 3731215976Sjmallett uint64_t o1_csrm : 1; 3732215976Sjmallett uint64_t reserved_26_27 : 2; 3733215976Sjmallett uint64_t o0_ro : 1; 3734215976Sjmallett uint64_t o0_ns : 1; 3735215976Sjmallett uint64_t o0_es : 2; 3736215976Sjmallett uint64_t o1_ro : 1; 3737215976Sjmallett uint64_t o1_ns : 1; 3738215976Sjmallett uint64_t o1_es : 2; 3739215976Sjmallett uint64_t reserved_36_43 : 8; 3740215976Sjmallett uint64_t p0_bmode : 1; 3741215976Sjmallett uint64_t p1_bmode : 1; 3742215976Sjmallett uint64_t reserved_46_47 : 2; 3743215976Sjmallett uint64_t pkt_rr : 1; 3744215976Sjmallett uint64_t reserved_49_63 : 15; 3745215976Sjmallett#endif 3746215976Sjmallett } cn50xx; 3747215976Sjmallett struct cvmx_npi_output_control_s cn58xx; 3748215976Sjmallett struct cvmx_npi_output_control_s cn58xxp1; 3749215976Sjmallett}; 3750215976Sjmalletttypedef union cvmx_npi_output_control cvmx_npi_output_control_t; 3751215976Sjmallett 3752215976Sjmallett/** 3753215976Sjmallett * cvmx_npi_p#_dbpair_addr 3754215976Sjmallett * 3755215976Sjmallett * NPI_P0_DBPAIR_ADDR = NPI's Port-0 DATA-BUFFER Pair Next Read Address. 3756215976Sjmallett * 3757215976Sjmallett * Contains the next address to read for Port's-0 Data/Buffer Pair. 3758215976Sjmallett */ 3759232812Sjmallettunion cvmx_npi_px_dbpair_addr { 3760215976Sjmallett uint64_t u64; 3761232812Sjmallett struct cvmx_npi_px_dbpair_addr_s { 3762232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3763215976Sjmallett uint64_t reserved_63_63 : 1; 3764215976Sjmallett uint64_t state : 2; /**< POS state machine vector. Used to tell when NADDR 3765215976Sjmallett is valid (when STATE == 0). */ 3766215976Sjmallett uint64_t naddr : 61; /**< Bits [63:3] of the next Data-Info Pair to read. 3767215976Sjmallett Value is only valid when STATE == 0. */ 3768215976Sjmallett#else 3769215976Sjmallett uint64_t naddr : 61; 3770215976Sjmallett uint64_t state : 2; 3771215976Sjmallett uint64_t reserved_63_63 : 1; 3772215976Sjmallett#endif 3773215976Sjmallett } s; 3774215976Sjmallett struct cvmx_npi_px_dbpair_addr_s cn30xx; 3775215976Sjmallett struct cvmx_npi_px_dbpair_addr_s cn31xx; 3776215976Sjmallett struct cvmx_npi_px_dbpair_addr_s cn38xx; 3777215976Sjmallett struct cvmx_npi_px_dbpair_addr_s cn38xxp2; 3778215976Sjmallett struct cvmx_npi_px_dbpair_addr_s cn50xx; 3779215976Sjmallett struct cvmx_npi_px_dbpair_addr_s cn58xx; 3780215976Sjmallett struct cvmx_npi_px_dbpair_addr_s cn58xxp1; 3781215976Sjmallett}; 3782215976Sjmalletttypedef union cvmx_npi_px_dbpair_addr cvmx_npi_px_dbpair_addr_t; 3783215976Sjmallett 3784215976Sjmallett/** 3785215976Sjmallett * cvmx_npi_p#_instr_addr 3786215976Sjmallett * 3787215976Sjmallett * NPI_P0_INSTR_ADDR = NPI's Port-0 Instruction Next Read Address. 3788215976Sjmallett * 3789215976Sjmallett * Contains the next address to read for Port's-0 Instructions. 3790215976Sjmallett */ 3791232812Sjmallettunion cvmx_npi_px_instr_addr { 3792215976Sjmallett uint64_t u64; 3793232812Sjmallett struct cvmx_npi_px_instr_addr_s { 3794232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3795215976Sjmallett uint64_t state : 3; /**< Gather engine state vector. Used to tell when 3796215976Sjmallett NADDR is valid (when STATE == 0). */ 3797215976Sjmallett uint64_t naddr : 61; /**< Bits [63:3] of the next Instruction to read. 3798215976Sjmallett Value is only valid when STATE == 0. */ 3799215976Sjmallett#else 3800215976Sjmallett uint64_t naddr : 61; 3801215976Sjmallett uint64_t state : 3; 3802215976Sjmallett#endif 3803215976Sjmallett } s; 3804215976Sjmallett struct cvmx_npi_px_instr_addr_s cn30xx; 3805215976Sjmallett struct cvmx_npi_px_instr_addr_s cn31xx; 3806215976Sjmallett struct cvmx_npi_px_instr_addr_s cn38xx; 3807215976Sjmallett struct cvmx_npi_px_instr_addr_s cn38xxp2; 3808215976Sjmallett struct cvmx_npi_px_instr_addr_s cn50xx; 3809215976Sjmallett struct cvmx_npi_px_instr_addr_s cn58xx; 3810215976Sjmallett struct cvmx_npi_px_instr_addr_s cn58xxp1; 3811215976Sjmallett}; 3812215976Sjmalletttypedef union cvmx_npi_px_instr_addr cvmx_npi_px_instr_addr_t; 3813215976Sjmallett 3814215976Sjmallett/** 3815215976Sjmallett * cvmx_npi_p#_instr_cnts 3816215976Sjmallett * 3817215976Sjmallett * NPI_P0_INSTR_CNTS = NPI's Port-0 Instruction Counts For Packets In. 3818215976Sjmallett * 3819215976Sjmallett * Used to determine the number of instruction in the NPI and to be fetched for Input-Packets. 3820215976Sjmallett */ 3821232812Sjmallettunion cvmx_npi_px_instr_cnts { 3822215976Sjmallett uint64_t u64; 3823232812Sjmallett struct cvmx_npi_px_instr_cnts_s { 3824232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3825215976Sjmallett uint64_t reserved_38_63 : 26; 3826215976Sjmallett uint64_t fcnt : 6; /**< Number entries in the Instruction FIFO. */ 3827215976Sjmallett uint64_t avail : 32; /**< Doorbell count to be read. */ 3828215976Sjmallett#else 3829215976Sjmallett uint64_t avail : 32; 3830215976Sjmallett uint64_t fcnt : 6; 3831215976Sjmallett uint64_t reserved_38_63 : 26; 3832215976Sjmallett#endif 3833215976Sjmallett } s; 3834215976Sjmallett struct cvmx_npi_px_instr_cnts_s cn30xx; 3835215976Sjmallett struct cvmx_npi_px_instr_cnts_s cn31xx; 3836215976Sjmallett struct cvmx_npi_px_instr_cnts_s cn38xx; 3837215976Sjmallett struct cvmx_npi_px_instr_cnts_s cn38xxp2; 3838215976Sjmallett struct cvmx_npi_px_instr_cnts_s cn50xx; 3839215976Sjmallett struct cvmx_npi_px_instr_cnts_s cn58xx; 3840215976Sjmallett struct cvmx_npi_px_instr_cnts_s cn58xxp1; 3841215976Sjmallett}; 3842215976Sjmalletttypedef union cvmx_npi_px_instr_cnts cvmx_npi_px_instr_cnts_t; 3843215976Sjmallett 3844215976Sjmallett/** 3845215976Sjmallett * cvmx_npi_p#_pair_cnts 3846215976Sjmallett * 3847215976Sjmallett * NPI_P0_PAIR_CNTS = NPI's Port-0 Instruction Counts For Packets Out. 3848215976Sjmallett * 3849215976Sjmallett * Used to determine the number of instruction in the NPI and to be fetched for Output-Packets. 3850215976Sjmallett */ 3851232812Sjmallettunion cvmx_npi_px_pair_cnts { 3852215976Sjmallett uint64_t u64; 3853232812Sjmallett struct cvmx_npi_px_pair_cnts_s { 3854232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3855215976Sjmallett uint64_t reserved_37_63 : 27; 3856215976Sjmallett uint64_t fcnt : 5; /**< 16 - number entries in the D/I Pair FIFO. */ 3857215976Sjmallett uint64_t avail : 32; /**< Doorbell count to be read. */ 3858215976Sjmallett#else 3859215976Sjmallett uint64_t avail : 32; 3860215976Sjmallett uint64_t fcnt : 5; 3861215976Sjmallett uint64_t reserved_37_63 : 27; 3862215976Sjmallett#endif 3863215976Sjmallett } s; 3864215976Sjmallett struct cvmx_npi_px_pair_cnts_s cn30xx; 3865215976Sjmallett struct cvmx_npi_px_pair_cnts_s cn31xx; 3866215976Sjmallett struct cvmx_npi_px_pair_cnts_s cn38xx; 3867215976Sjmallett struct cvmx_npi_px_pair_cnts_s cn38xxp2; 3868215976Sjmallett struct cvmx_npi_px_pair_cnts_s cn50xx; 3869215976Sjmallett struct cvmx_npi_px_pair_cnts_s cn58xx; 3870215976Sjmallett struct cvmx_npi_px_pair_cnts_s cn58xxp1; 3871215976Sjmallett}; 3872215976Sjmalletttypedef union cvmx_npi_px_pair_cnts cvmx_npi_px_pair_cnts_t; 3873215976Sjmallett 3874215976Sjmallett/** 3875215976Sjmallett * cvmx_npi_pci_burst_size 3876215976Sjmallett * 3877215976Sjmallett * NPI_PCI_BURST_SIZE = NPI PCI Burst Size Register 3878215976Sjmallett * 3879215976Sjmallett * Control the number of words the NPI will attempt to read / write to/from the PCI. 3880215976Sjmallett */ 3881232812Sjmallettunion cvmx_npi_pci_burst_size { 3882215976Sjmallett uint64_t u64; 3883232812Sjmallett struct cvmx_npi_pci_burst_size_s { 3884232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3885215976Sjmallett uint64_t reserved_14_63 : 50; 3886215976Sjmallett uint64_t wr_brst : 7; /**< The number of 8B words to write to PCI in any one 3887215976Sjmallett write operation. A zero is equal to 128. This 3888215976Sjmallett value is used the packet reads and is clamped at 3889215976Sjmallett a max of 112 for dma writes. */ 3890215976Sjmallett uint64_t rd_brst : 7; /**< Number of 8B words to read from PCI in any one 3891215976Sjmallett read operation. Legal values are 1 to 127, where 3892215976Sjmallett a 0 will be treated as a 1. 3893215976Sjmallett "For reading of packet data value is limited to 64 3894215976Sjmallett in PASS-2." 3895215976Sjmallett This value does not control the size of a read 3896215976Sjmallett caused by an IOBDMA from a PP. */ 3897215976Sjmallett#else 3898215976Sjmallett uint64_t rd_brst : 7; 3899215976Sjmallett uint64_t wr_brst : 7; 3900215976Sjmallett uint64_t reserved_14_63 : 50; 3901215976Sjmallett#endif 3902215976Sjmallett } s; 3903215976Sjmallett struct cvmx_npi_pci_burst_size_s cn30xx; 3904215976Sjmallett struct cvmx_npi_pci_burst_size_s cn31xx; 3905215976Sjmallett struct cvmx_npi_pci_burst_size_s cn38xx; 3906215976Sjmallett struct cvmx_npi_pci_burst_size_s cn38xxp2; 3907215976Sjmallett struct cvmx_npi_pci_burst_size_s cn50xx; 3908215976Sjmallett struct cvmx_npi_pci_burst_size_s cn58xx; 3909215976Sjmallett struct cvmx_npi_pci_burst_size_s cn58xxp1; 3910215976Sjmallett}; 3911215976Sjmalletttypedef union cvmx_npi_pci_burst_size cvmx_npi_pci_burst_size_t; 3912215976Sjmallett 3913215976Sjmallett/** 3914215976Sjmallett * cvmx_npi_pci_int_arb_cfg 3915215976Sjmallett * 3916215976Sjmallett * NPI_PCI_INT_ARB_CFG = Configuration For PCI Arbiter 3917215976Sjmallett * 3918215976Sjmallett * Controls operation of the Internal PCI Arbiter. This register should 3919215976Sjmallett * only be written when PRST# is asserted. NPI_PCI_INT_ARB_CFG[EN] should 3920215976Sjmallett * only be set when Octane is a host. 3921215976Sjmallett */ 3922232812Sjmallettunion cvmx_npi_pci_int_arb_cfg { 3923215976Sjmallett uint64_t u64; 3924232812Sjmallett struct cvmx_npi_pci_int_arb_cfg_s { 3925232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3926215976Sjmallett uint64_t reserved_13_63 : 51; 3927215976Sjmallett uint64_t hostmode : 1; /**< PCI Host Mode Pin (sampled for use by software). 3928215976Sjmallett This bit reflects the sampled PCI_HOSTMODE pin. 3929215976Sjmallett In HOST Mode, OCTEON drives the PCI_CLK_OUT and 3930215976Sjmallett PCI initialization pattern during PCI_RST_N deassertion). */ 3931215976Sjmallett uint64_t pci_ovr : 4; /**< PCI Host Mode Bus Speed/Type Override 3932215976Sjmallett When in Host Mode(PCI_HOSTMODE pin =1), OCTEON acting 3933215976Sjmallett as the PCI Central Agent, samples the PCI_PCI100, 3934215976Sjmallett PCI_M66EN and PCI_PCIXCAP pins to determine the 3935215976Sjmallett 'sampled' PCI Bus speed and Bus Type (PCI or PCIX). 3936215976Sjmallett (see: PCI_CNT_REG[HM_SPEED,HM_PCIX]) 3937215976Sjmallett However, in some cases, SW may want to override the 3938215976Sjmallett the 'sampled' PCI Bus Type/Speed, and use some 3939215976Sjmallett SLOWER Bus frequency. 3940215976Sjmallett The PCI_OVR field encoding represents the 'override' 3941215976Sjmallett PCI Bus Type/Speed which will be used to generate the 3942215976Sjmallett PCI_CLK_OUT and determines the PCI initialization pattern 3943215976Sjmallett driven during PCI_RST_N deassertion. 3944215976Sjmallett PCI_OVR[3]: OVERRIDE (0:DISABLE/1:ENABLE) 3945215976Sjmallett PCI_OVR[2]: BUS TYPE(0:PCI/1:PCIX) 3946215976Sjmallett PCI_OVR[1:0]: BUS SPEED(0:33/1:66/2:100/3:133) 3947215976Sjmallett OVERRIDE TYPE SPEED | Override Configuration 3948215976Sjmallett [3] [2] [1:0] | TYPE SPEED 3949215976Sjmallett ------------------+------------------------------- 3950215976Sjmallett 0 x xx | No override(uses 'sampled' 3951215976Sjmallett | Bus Speed(HM_SPEED) and Bus Type(HM_PCIX) 3952215976Sjmallett 1 0 00 | PCI Mode 33MHz 3953215976Sjmallett 1 0 01 | PCI Mode 66MHz 3954215976Sjmallett 1 0 10 | RESERVED (DO NOT USE) 3955215976Sjmallett 1 0 11 | RESERVED (DO NOT USE) 3956215976Sjmallett 1 1 00 | RESERVED (DO NOT USE) 3957215976Sjmallett 1 1 01 | PCIX Mode 66MHz 3958215976Sjmallett 1 1 10 | PCIX Mode 100MHz 3959215976Sjmallett 1 1 11 | PCIX Mode 133MHz 3960215976Sjmallett NOTES: 3961215976Sjmallett - NPI_PCI_INT_ARB_CFG[PCI_OVR] has NO EFFECT on 3962215976Sjmallett PCI_CNT_REG[HM_SPEED,HM_PCIX] (ie: the sampled PCI Bus 3963215976Sjmallett Type/Speed), but WILL EFFECT PCI_CTL_STATUS_2[AP_PCIX] 3964215976Sjmallett which reflects the actual PCI Bus Type(0:PCI/1:PCIX). 3965215976Sjmallett - Software should never 'up' configure the recommended values. 3966215976Sjmallett In other words, if the 'sampled' Bus Type=PCI(HM_PCIX=0), 3967215976Sjmallett then SW should NOT attempt to set TYPE[2]=1 for PCIX Mode. 3968215976Sjmallett Likewise, if the sampled Bus Speed=66MHz(HM_SPEED=01), 3969215976Sjmallett then SW should NOT attempt to 'speed up' the bus [ie: 3970215976Sjmallett SPEED[1:0]=10(100MHz)]. 3971215976Sjmallett - If PCI_OVR<3> is set prior to PCI reset de-assertion 3972215976Sjmallett in host mode, NPI_PCI_INT_ARB_CFG[PCI_OVR] 3973215976Sjmallett indicates the Bus Type/Speed that OCTEON drove on the 3974215976Sjmallett DEVSEL/STOP/TRDY pins during reset de-assertion. (user 3975215976Sjmallett should then ignore the 'sampled' Bus Type/Speed 3976215976Sjmallett contained in the PCI_CNT_REG[HM_PCIX, HM_SPEED]) fields. 3977215976Sjmallett - If PCI_OVR<3> is clear prior to PCI reset de-assertion 3978215976Sjmallett in host mode, PCI_CNT_REG[HM_PCIX,HM_SPEED]) 3979215976Sjmallett indicates the Bus Type/Speed that OCTEON drove on the 3980215976Sjmallett DEVSEL/STOP/TRDY pins during reset de-assertion. */ 3981215976Sjmallett uint64_t reserved_5_7 : 3; 3982215976Sjmallett uint64_t en : 1; /**< Internal arbiter enable. */ 3983215976Sjmallett uint64_t park_mod : 1; /**< Bus park mode. 0=park on last, 1=park on device. */ 3984215976Sjmallett uint64_t park_dev : 3; /**< Bus park device. 0-3 External device, 4 = Octane. */ 3985215976Sjmallett#else 3986215976Sjmallett uint64_t park_dev : 3; 3987215976Sjmallett uint64_t park_mod : 1; 3988215976Sjmallett uint64_t en : 1; 3989215976Sjmallett uint64_t reserved_5_7 : 3; 3990215976Sjmallett uint64_t pci_ovr : 4; 3991215976Sjmallett uint64_t hostmode : 1; 3992215976Sjmallett uint64_t reserved_13_63 : 51; 3993215976Sjmallett#endif 3994215976Sjmallett } s; 3995232812Sjmallett struct cvmx_npi_pci_int_arb_cfg_cn30xx { 3996232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 3997215976Sjmallett uint64_t reserved_5_63 : 59; 3998215976Sjmallett uint64_t en : 1; /**< Internal arbiter enable. */ 3999215976Sjmallett uint64_t park_mod : 1; /**< Bus park mode. 0=park on last, 1=park on device. */ 4000215976Sjmallett uint64_t park_dev : 3; /**< Bus park device. 0-3 External device, 4 = Octane. */ 4001215976Sjmallett#else 4002215976Sjmallett uint64_t park_dev : 3; 4003215976Sjmallett uint64_t park_mod : 1; 4004215976Sjmallett uint64_t en : 1; 4005215976Sjmallett uint64_t reserved_5_63 : 59; 4006215976Sjmallett#endif 4007215976Sjmallett } cn30xx; 4008215976Sjmallett struct cvmx_npi_pci_int_arb_cfg_cn30xx cn31xx; 4009215976Sjmallett struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xx; 4010215976Sjmallett struct cvmx_npi_pci_int_arb_cfg_cn30xx cn38xxp2; 4011215976Sjmallett struct cvmx_npi_pci_int_arb_cfg_s cn50xx; 4012215976Sjmallett struct cvmx_npi_pci_int_arb_cfg_s cn58xx; 4013215976Sjmallett struct cvmx_npi_pci_int_arb_cfg_s cn58xxp1; 4014215976Sjmallett}; 4015215976Sjmalletttypedef union cvmx_npi_pci_int_arb_cfg cvmx_npi_pci_int_arb_cfg_t; 4016215976Sjmallett 4017215976Sjmallett/** 4018215976Sjmallett * cvmx_npi_pci_read_cmd 4019215976Sjmallett * 4020215976Sjmallett * NPI_PCI_READ_CMD = NPI PCI Read Command Register 4021215976Sjmallett * 4022215976Sjmallett * Controls the type of read command sent. 4023215976Sjmallett * Writes to this register are not ordered with writes/reads to the PCI Memory space. 4024215976Sjmallett * To ensure that a write has completed the user must read the register before 4025215976Sjmallett * making an access(i.e. PCI memory space) that requires the value of this register to be updated. 4026215976Sjmallett * Also any previously issued reads/writes to PCI memory space, still stored in the outbound 4027215976Sjmallett * FIFO will use the value of this register after it has been updated. 4028215976Sjmallett */ 4029232812Sjmallettunion cvmx_npi_pci_read_cmd { 4030215976Sjmallett uint64_t u64; 4031232812Sjmallett struct cvmx_npi_pci_read_cmd_s { 4032232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4033215976Sjmallett uint64_t reserved_11_63 : 53; 4034215976Sjmallett uint64_t cmd_size : 11; /**< Number bytes to be read is equal to or exceeds this 4035215976Sjmallett size will cause the PCI in PCI mode to use a 4036215976Sjmallett Memory-Read-Multiple. This register has a value 4037215976Sjmallett from 8 to 2048. A value of 0-7 will be treated as 4038215976Sjmallett a value of 2048. */ 4039215976Sjmallett#else 4040215976Sjmallett uint64_t cmd_size : 11; 4041215976Sjmallett uint64_t reserved_11_63 : 53; 4042215976Sjmallett#endif 4043215976Sjmallett } s; 4044215976Sjmallett struct cvmx_npi_pci_read_cmd_s cn30xx; 4045215976Sjmallett struct cvmx_npi_pci_read_cmd_s cn31xx; 4046215976Sjmallett struct cvmx_npi_pci_read_cmd_s cn38xx; 4047215976Sjmallett struct cvmx_npi_pci_read_cmd_s cn38xxp2; 4048215976Sjmallett struct cvmx_npi_pci_read_cmd_s cn50xx; 4049215976Sjmallett struct cvmx_npi_pci_read_cmd_s cn58xx; 4050215976Sjmallett struct cvmx_npi_pci_read_cmd_s cn58xxp1; 4051215976Sjmallett}; 4052215976Sjmalletttypedef union cvmx_npi_pci_read_cmd cvmx_npi_pci_read_cmd_t; 4053215976Sjmallett 4054215976Sjmallett/** 4055215976Sjmallett * cvmx_npi_port32_instr_hdr 4056215976Sjmallett * 4057215976Sjmallett * NPI_PORT32_INSTR_HDR = NPI Port 32 Instruction Header 4058215976Sjmallett * 4059215976Sjmallett * Contains bits [62:42] of the Instruction Header for port 32. 4060215976Sjmallett */ 4061232812Sjmallettunion cvmx_npi_port32_instr_hdr { 4062215976Sjmallett uint64_t u64; 4063232812Sjmallett struct cvmx_npi_port32_instr_hdr_s { 4064232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4065215976Sjmallett uint64_t reserved_44_63 : 20; 4066215976Sjmallett uint64_t pbp : 1; /**< Enable Packet-by-packet mode. */ 4067215976Sjmallett uint64_t rsv_f : 5; /**< Reserved */ 4068215976Sjmallett uint64_t rparmode : 2; /**< Parse Mode. Used when packet is raw and PBP==0. */ 4069215976Sjmallett uint64_t rsv_e : 1; /**< Reserved */ 4070215976Sjmallett uint64_t rskp_len : 7; /**< Skip Length. Used when packet is raw and PBP==0. */ 4071215976Sjmallett uint64_t rsv_d : 6; /**< Reserved */ 4072215976Sjmallett uint64_t use_ihdr : 1; /**< When set '1' the instruction header will be sent 4073215976Sjmallett as part of the packet data, regardless of the 4074215976Sjmallett value of bit [63] of the instruction header. 4075215976Sjmallett USE_IHDR must be set whenever PBP is set. */ 4076215976Sjmallett uint64_t rsv_c : 5; /**< Reserved */ 4077215976Sjmallett uint64_t par_mode : 2; /**< Parse Mode. Used when USE_IHDR is set and packet 4078215976Sjmallett is not raw and PBP is not set. */ 4079215976Sjmallett uint64_t rsv_b : 1; /**< Reserved 4080215976Sjmallett instruction header sent to IPD. */ 4081215976Sjmallett uint64_t skp_len : 7; /**< Skip Length. Used when USE_IHDR is set and packet 4082215976Sjmallett is not raw and PBP is not set. */ 4083215976Sjmallett uint64_t rsv_a : 6; /**< Reserved */ 4084215976Sjmallett#else 4085215976Sjmallett uint64_t rsv_a : 6; 4086215976Sjmallett uint64_t skp_len : 7; 4087215976Sjmallett uint64_t rsv_b : 1; 4088215976Sjmallett uint64_t par_mode : 2; 4089215976Sjmallett uint64_t rsv_c : 5; 4090215976Sjmallett uint64_t use_ihdr : 1; 4091215976Sjmallett uint64_t rsv_d : 6; 4092215976Sjmallett uint64_t rskp_len : 7; 4093215976Sjmallett uint64_t rsv_e : 1; 4094215976Sjmallett uint64_t rparmode : 2; 4095215976Sjmallett uint64_t rsv_f : 5; 4096215976Sjmallett uint64_t pbp : 1; 4097215976Sjmallett uint64_t reserved_44_63 : 20; 4098215976Sjmallett#endif 4099215976Sjmallett } s; 4100215976Sjmallett struct cvmx_npi_port32_instr_hdr_s cn30xx; 4101215976Sjmallett struct cvmx_npi_port32_instr_hdr_s cn31xx; 4102215976Sjmallett struct cvmx_npi_port32_instr_hdr_s cn38xx; 4103215976Sjmallett struct cvmx_npi_port32_instr_hdr_s cn38xxp2; 4104215976Sjmallett struct cvmx_npi_port32_instr_hdr_s cn50xx; 4105215976Sjmallett struct cvmx_npi_port32_instr_hdr_s cn58xx; 4106215976Sjmallett struct cvmx_npi_port32_instr_hdr_s cn58xxp1; 4107215976Sjmallett}; 4108215976Sjmalletttypedef union cvmx_npi_port32_instr_hdr cvmx_npi_port32_instr_hdr_t; 4109215976Sjmallett 4110215976Sjmallett/** 4111215976Sjmallett * cvmx_npi_port33_instr_hdr 4112215976Sjmallett * 4113215976Sjmallett * NPI_PORT33_INSTR_HDR = NPI Port 33 Instruction Header 4114215976Sjmallett * 4115215976Sjmallett * Contains bits [62:42] of the Instruction Header for port 33. 4116215976Sjmallett */ 4117232812Sjmallettunion cvmx_npi_port33_instr_hdr { 4118215976Sjmallett uint64_t u64; 4119232812Sjmallett struct cvmx_npi_port33_instr_hdr_s { 4120232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4121215976Sjmallett uint64_t reserved_44_63 : 20; 4122215976Sjmallett uint64_t pbp : 1; /**< Enable Packet-by-packet mode. */ 4123215976Sjmallett uint64_t rsv_f : 5; /**< Reserved */ 4124215976Sjmallett uint64_t rparmode : 2; /**< Parse Mode. Used when packet is raw and PBP==0. */ 4125215976Sjmallett uint64_t rsv_e : 1; /**< Reserved */ 4126215976Sjmallett uint64_t rskp_len : 7; /**< Skip Length. Used when packet is raw and PBP==0. */ 4127215976Sjmallett uint64_t rsv_d : 6; /**< Reserved */ 4128215976Sjmallett uint64_t use_ihdr : 1; /**< When set '1' the instruction header will be sent 4129215976Sjmallett as part of the packet data, regardless of the 4130215976Sjmallett value of bit [63] of the instruction header. 4131215976Sjmallett USE_IHDR must be set whenever PBP is set. */ 4132215976Sjmallett uint64_t rsv_c : 5; /**< Reserved */ 4133215976Sjmallett uint64_t par_mode : 2; /**< Parse Mode. Used when USE_IHDR is set and packet 4134215976Sjmallett is not raw and PBP is not set. */ 4135215976Sjmallett uint64_t rsv_b : 1; /**< Reserved 4136215976Sjmallett instruction header sent to IPD. */ 4137215976Sjmallett uint64_t skp_len : 7; /**< Skip Length. Used when USE_IHDR is set and packet 4138215976Sjmallett is not raw and PBP is not set. */ 4139215976Sjmallett uint64_t rsv_a : 6; /**< Reserved */ 4140215976Sjmallett#else 4141215976Sjmallett uint64_t rsv_a : 6; 4142215976Sjmallett uint64_t skp_len : 7; 4143215976Sjmallett uint64_t rsv_b : 1; 4144215976Sjmallett uint64_t par_mode : 2; 4145215976Sjmallett uint64_t rsv_c : 5; 4146215976Sjmallett uint64_t use_ihdr : 1; 4147215976Sjmallett uint64_t rsv_d : 6; 4148215976Sjmallett uint64_t rskp_len : 7; 4149215976Sjmallett uint64_t rsv_e : 1; 4150215976Sjmallett uint64_t rparmode : 2; 4151215976Sjmallett uint64_t rsv_f : 5; 4152215976Sjmallett uint64_t pbp : 1; 4153215976Sjmallett uint64_t reserved_44_63 : 20; 4154215976Sjmallett#endif 4155215976Sjmallett } s; 4156215976Sjmallett struct cvmx_npi_port33_instr_hdr_s cn31xx; 4157215976Sjmallett struct cvmx_npi_port33_instr_hdr_s cn38xx; 4158215976Sjmallett struct cvmx_npi_port33_instr_hdr_s cn38xxp2; 4159215976Sjmallett struct cvmx_npi_port33_instr_hdr_s cn50xx; 4160215976Sjmallett struct cvmx_npi_port33_instr_hdr_s cn58xx; 4161215976Sjmallett struct cvmx_npi_port33_instr_hdr_s cn58xxp1; 4162215976Sjmallett}; 4163215976Sjmalletttypedef union cvmx_npi_port33_instr_hdr cvmx_npi_port33_instr_hdr_t; 4164215976Sjmallett 4165215976Sjmallett/** 4166215976Sjmallett * cvmx_npi_port34_instr_hdr 4167215976Sjmallett * 4168215976Sjmallett * NPI_PORT34_INSTR_HDR = NPI Port 34 Instruction Header 4169215976Sjmallett * 4170215976Sjmallett * Contains bits [62:42] of the Instruction Header for port 34. Added for PASS-2. 4171215976Sjmallett */ 4172232812Sjmallettunion cvmx_npi_port34_instr_hdr { 4173215976Sjmallett uint64_t u64; 4174232812Sjmallett struct cvmx_npi_port34_instr_hdr_s { 4175232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4176215976Sjmallett uint64_t reserved_44_63 : 20; 4177215976Sjmallett uint64_t pbp : 1; /**< Enable Packet-by-packet mode. */ 4178215976Sjmallett uint64_t rsv_f : 5; /**< Reserved */ 4179215976Sjmallett uint64_t rparmode : 2; /**< Parse Mode. Used when packet is raw and PBP==0. */ 4180215976Sjmallett uint64_t rsv_e : 1; /**< Reserved */ 4181215976Sjmallett uint64_t rskp_len : 7; /**< Skip Length. Used when packet is raw and PBP==0. */ 4182215976Sjmallett uint64_t rsv_d : 6; /**< Reserved */ 4183215976Sjmallett uint64_t use_ihdr : 1; /**< When set '1' the instruction header will be sent 4184215976Sjmallett as part of the packet data, regardless of the 4185215976Sjmallett value of bit [63] of the instruction header. 4186215976Sjmallett USE_IHDR must be set whenever PBP is set. */ 4187215976Sjmallett uint64_t rsv_c : 5; /**< Reserved */ 4188215976Sjmallett uint64_t par_mode : 2; /**< Parse Mode. Used when USE_IHDR is set and packet 4189215976Sjmallett is not raw and PBP is not set. */ 4190215976Sjmallett uint64_t rsv_b : 1; /**< Reserved 4191215976Sjmallett instruction header sent to IPD. */ 4192215976Sjmallett uint64_t skp_len : 7; /**< Skip Length. Used when USE_IHDR is set and packet 4193215976Sjmallett is not raw and PBP is not set. */ 4194215976Sjmallett uint64_t rsv_a : 6; /**< Reserved */ 4195215976Sjmallett#else 4196215976Sjmallett uint64_t rsv_a : 6; 4197215976Sjmallett uint64_t skp_len : 7; 4198215976Sjmallett uint64_t rsv_b : 1; 4199215976Sjmallett uint64_t par_mode : 2; 4200215976Sjmallett uint64_t rsv_c : 5; 4201215976Sjmallett uint64_t use_ihdr : 1; 4202215976Sjmallett uint64_t rsv_d : 6; 4203215976Sjmallett uint64_t rskp_len : 7; 4204215976Sjmallett uint64_t rsv_e : 1; 4205215976Sjmallett uint64_t rparmode : 2; 4206215976Sjmallett uint64_t rsv_f : 5; 4207215976Sjmallett uint64_t pbp : 1; 4208215976Sjmallett uint64_t reserved_44_63 : 20; 4209215976Sjmallett#endif 4210215976Sjmallett } s; 4211215976Sjmallett struct cvmx_npi_port34_instr_hdr_s cn38xx; 4212215976Sjmallett struct cvmx_npi_port34_instr_hdr_s cn38xxp2; 4213215976Sjmallett struct cvmx_npi_port34_instr_hdr_s cn58xx; 4214215976Sjmallett struct cvmx_npi_port34_instr_hdr_s cn58xxp1; 4215215976Sjmallett}; 4216215976Sjmalletttypedef union cvmx_npi_port34_instr_hdr cvmx_npi_port34_instr_hdr_t; 4217215976Sjmallett 4218215976Sjmallett/** 4219215976Sjmallett * cvmx_npi_port35_instr_hdr 4220215976Sjmallett * 4221215976Sjmallett * NPI_PORT35_INSTR_HDR = NPI Port 35 Instruction Header 4222215976Sjmallett * 4223215976Sjmallett * Contains bits [62:42] of the Instruction Header for port 35. Added for PASS-2. 4224215976Sjmallett */ 4225232812Sjmallettunion cvmx_npi_port35_instr_hdr { 4226215976Sjmallett uint64_t u64; 4227232812Sjmallett struct cvmx_npi_port35_instr_hdr_s { 4228232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4229215976Sjmallett uint64_t reserved_44_63 : 20; 4230215976Sjmallett uint64_t pbp : 1; /**< Enable Packet-by-packet mode. */ 4231215976Sjmallett uint64_t rsv_f : 5; /**< Reserved */ 4232215976Sjmallett uint64_t rparmode : 2; /**< Parse Mode. Used when packet is raw and PBP==0. */ 4233215976Sjmallett uint64_t rsv_e : 1; /**< Reserved */ 4234215976Sjmallett uint64_t rskp_len : 7; /**< Skip Length. Used when packet is raw and PBP==0. */ 4235215976Sjmallett uint64_t rsv_d : 6; /**< Reserved */ 4236215976Sjmallett uint64_t use_ihdr : 1; /**< When set '1' the instruction header will be sent 4237215976Sjmallett as part of the packet data, regardless of the 4238215976Sjmallett value of bit [63] of the instruction header. 4239215976Sjmallett USE_IHDR must be set whenever PBP is set. */ 4240215976Sjmallett uint64_t rsv_c : 5; /**< Reserved */ 4241215976Sjmallett uint64_t par_mode : 2; /**< Parse Mode. Used when USE_IHDR is set and packet 4242215976Sjmallett is not raw and PBP is not set. */ 4243215976Sjmallett uint64_t rsv_b : 1; /**< Reserved 4244215976Sjmallett instruction header sent to IPD. */ 4245215976Sjmallett uint64_t skp_len : 7; /**< Skip Length. Used when USE_IHDR is set and packet 4246215976Sjmallett is not raw and PBP is not set. */ 4247215976Sjmallett uint64_t rsv_a : 6; /**< Reserved */ 4248215976Sjmallett#else 4249215976Sjmallett uint64_t rsv_a : 6; 4250215976Sjmallett uint64_t skp_len : 7; 4251215976Sjmallett uint64_t rsv_b : 1; 4252215976Sjmallett uint64_t par_mode : 2; 4253215976Sjmallett uint64_t rsv_c : 5; 4254215976Sjmallett uint64_t use_ihdr : 1; 4255215976Sjmallett uint64_t rsv_d : 6; 4256215976Sjmallett uint64_t rskp_len : 7; 4257215976Sjmallett uint64_t rsv_e : 1; 4258215976Sjmallett uint64_t rparmode : 2; 4259215976Sjmallett uint64_t rsv_f : 5; 4260215976Sjmallett uint64_t pbp : 1; 4261215976Sjmallett uint64_t reserved_44_63 : 20; 4262215976Sjmallett#endif 4263215976Sjmallett } s; 4264215976Sjmallett struct cvmx_npi_port35_instr_hdr_s cn38xx; 4265215976Sjmallett struct cvmx_npi_port35_instr_hdr_s cn38xxp2; 4266215976Sjmallett struct cvmx_npi_port35_instr_hdr_s cn58xx; 4267215976Sjmallett struct cvmx_npi_port35_instr_hdr_s cn58xxp1; 4268215976Sjmallett}; 4269215976Sjmalletttypedef union cvmx_npi_port35_instr_hdr cvmx_npi_port35_instr_hdr_t; 4270215976Sjmallett 4271215976Sjmallett/** 4272215976Sjmallett * cvmx_npi_port_bp_control 4273215976Sjmallett * 4274215976Sjmallett * NPI_PORT_BP_CONTROL = Port Backpressure Control 4275215976Sjmallett * 4276215976Sjmallett * Enables Port Level Backpressure 4277215976Sjmallett */ 4278232812Sjmallettunion cvmx_npi_port_bp_control { 4279215976Sjmallett uint64_t u64; 4280232812Sjmallett struct cvmx_npi_port_bp_control_s { 4281232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4282215976Sjmallett uint64_t reserved_8_63 : 56; 4283215976Sjmallett uint64_t bp_on : 4; /**< Port 35-32 port level backpressure applied. */ 4284215976Sjmallett uint64_t enb : 4; /**< Enables port level backpressure from the IPD. */ 4285215976Sjmallett#else 4286215976Sjmallett uint64_t enb : 4; 4287215976Sjmallett uint64_t bp_on : 4; 4288215976Sjmallett uint64_t reserved_8_63 : 56; 4289215976Sjmallett#endif 4290215976Sjmallett } s; 4291215976Sjmallett struct cvmx_npi_port_bp_control_s cn30xx; 4292215976Sjmallett struct cvmx_npi_port_bp_control_s cn31xx; 4293215976Sjmallett struct cvmx_npi_port_bp_control_s cn38xx; 4294215976Sjmallett struct cvmx_npi_port_bp_control_s cn38xxp2; 4295215976Sjmallett struct cvmx_npi_port_bp_control_s cn50xx; 4296215976Sjmallett struct cvmx_npi_port_bp_control_s cn58xx; 4297215976Sjmallett struct cvmx_npi_port_bp_control_s cn58xxp1; 4298215976Sjmallett}; 4299215976Sjmalletttypedef union cvmx_npi_port_bp_control cvmx_npi_port_bp_control_t; 4300215976Sjmallett 4301215976Sjmallett/** 4302215976Sjmallett * cvmx_npi_rsl_int_blocks 4303215976Sjmallett * 4304215976Sjmallett * RSL_INT_BLOCKS = RSL Interrupt Blocks Register 4305215976Sjmallett * 4306215976Sjmallett * Reading this register will return a vector with a bit set '1' for a corresponding RSL block 4307215976Sjmallett * that presently has an interrupt pending. The Field Description below supplies the name of the 4308215976Sjmallett * register that software should read to find out why that intterupt bit is set. 4309215976Sjmallett */ 4310232812Sjmallettunion cvmx_npi_rsl_int_blocks { 4311215976Sjmallett uint64_t u64; 4312232812Sjmallett struct cvmx_npi_rsl_int_blocks_s { 4313232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4314215976Sjmallett uint64_t reserved_32_63 : 32; 4315215976Sjmallett uint64_t rint_31 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4316215976Sjmallett uint64_t iob : 1; /**< IOB_INT_SUM */ 4317215976Sjmallett uint64_t reserved_28_29 : 2; 4318215976Sjmallett uint64_t rint_27 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4319215976Sjmallett uint64_t rint_26 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4320215976Sjmallett uint64_t rint_25 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4321215976Sjmallett uint64_t rint_24 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4322215976Sjmallett uint64_t asx1 : 1; /**< ASX1_INT_REG */ 4323215976Sjmallett uint64_t asx0 : 1; /**< ASX0_INT_REG */ 4324215976Sjmallett uint64_t rint_21 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4325215976Sjmallett uint64_t pip : 1; /**< PIP_INT_REG. */ 4326215976Sjmallett uint64_t spx1 : 1; /**< SPX1_INT_REG & STX1_INT_REG */ 4327215976Sjmallett uint64_t spx0 : 1; /**< SPX0_INT_REG & STX0_INT_REG */ 4328215976Sjmallett uint64_t lmc : 1; /**< LMC_MEM_CFG0 */ 4329215976Sjmallett uint64_t l2c : 1; /**< L2T_ERR & L2D_ERR */ 4330215976Sjmallett uint64_t rint_15 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4331215976Sjmallett uint64_t reserved_13_14 : 2; 4332215976Sjmallett uint64_t pow : 1; /**< POW_ECC_ERR */ 4333215976Sjmallett uint64_t tim : 1; /**< TIM_REG_ERROR */ 4334215976Sjmallett uint64_t pko : 1; /**< PKO_REG_ERROR */ 4335215976Sjmallett uint64_t ipd : 1; /**< IPD_INT_SUM */ 4336215976Sjmallett uint64_t rint_8 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4337215976Sjmallett uint64_t zip : 1; /**< ZIP_ERROR */ 4338215976Sjmallett uint64_t dfa : 1; /**< DFA_ERR */ 4339215976Sjmallett uint64_t fpa : 1; /**< FPA_INT_SUM */ 4340215976Sjmallett uint64_t key : 1; /**< KEY_INT_SUM */ 4341215976Sjmallett uint64_t npi : 1; /**< NPI_INT_SUM */ 4342215976Sjmallett uint64_t gmx1 : 1; /**< GMX1_RX*_INT_REG & GMX1_TX_INT_REG */ 4343215976Sjmallett uint64_t gmx0 : 1; /**< GMX0_RX*_INT_REG & GMX0_TX_INT_REG */ 4344215976Sjmallett uint64_t mio : 1; /**< MIO_BOOT_ERR */ 4345215976Sjmallett#else 4346215976Sjmallett uint64_t mio : 1; 4347215976Sjmallett uint64_t gmx0 : 1; 4348215976Sjmallett uint64_t gmx1 : 1; 4349215976Sjmallett uint64_t npi : 1; 4350215976Sjmallett uint64_t key : 1; 4351215976Sjmallett uint64_t fpa : 1; 4352215976Sjmallett uint64_t dfa : 1; 4353215976Sjmallett uint64_t zip : 1; 4354215976Sjmallett uint64_t rint_8 : 1; 4355215976Sjmallett uint64_t ipd : 1; 4356215976Sjmallett uint64_t pko : 1; 4357215976Sjmallett uint64_t tim : 1; 4358215976Sjmallett uint64_t pow : 1; 4359215976Sjmallett uint64_t reserved_13_14 : 2; 4360215976Sjmallett uint64_t rint_15 : 1; 4361215976Sjmallett uint64_t l2c : 1; 4362215976Sjmallett uint64_t lmc : 1; 4363215976Sjmallett uint64_t spx0 : 1; 4364215976Sjmallett uint64_t spx1 : 1; 4365215976Sjmallett uint64_t pip : 1; 4366215976Sjmallett uint64_t rint_21 : 1; 4367215976Sjmallett uint64_t asx0 : 1; 4368215976Sjmallett uint64_t asx1 : 1; 4369215976Sjmallett uint64_t rint_24 : 1; 4370215976Sjmallett uint64_t rint_25 : 1; 4371215976Sjmallett uint64_t rint_26 : 1; 4372215976Sjmallett uint64_t rint_27 : 1; 4373215976Sjmallett uint64_t reserved_28_29 : 2; 4374215976Sjmallett uint64_t iob : 1; 4375215976Sjmallett uint64_t rint_31 : 1; 4376215976Sjmallett uint64_t reserved_32_63 : 32; 4377215976Sjmallett#endif 4378215976Sjmallett } s; 4379232812Sjmallett struct cvmx_npi_rsl_int_blocks_cn30xx { 4380232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4381215976Sjmallett uint64_t reserved_32_63 : 32; 4382215976Sjmallett uint64_t rint_31 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4383215976Sjmallett uint64_t iob : 1; /**< IOB_INT_SUM */ 4384215976Sjmallett uint64_t rint_29 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4385215976Sjmallett uint64_t rint_28 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4386215976Sjmallett uint64_t rint_27 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4387215976Sjmallett uint64_t rint_26 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4388215976Sjmallett uint64_t rint_25 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4389215976Sjmallett uint64_t rint_24 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4390215976Sjmallett uint64_t asx1 : 1; /**< ASX1_INT_REG */ 4391215976Sjmallett uint64_t asx0 : 1; /**< ASX0_INT_REG */ 4392215976Sjmallett uint64_t rint_21 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4393215976Sjmallett uint64_t pip : 1; /**< PIP_INT_REG. */ 4394215976Sjmallett uint64_t spx1 : 1; /**< SPX1_INT_REG & STX1_INT_REG */ 4395215976Sjmallett uint64_t spx0 : 1; /**< SPX0_INT_REG & STX0_INT_REG */ 4396215976Sjmallett uint64_t lmc : 1; /**< LMC_MEM_CFG0 */ 4397215976Sjmallett uint64_t l2c : 1; /**< L2T_ERR & L2D_ERR */ 4398215976Sjmallett uint64_t rint_15 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4399215976Sjmallett uint64_t rint_14 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4400215976Sjmallett uint64_t usb : 1; /**< USBN_INT_SUM */ 4401215976Sjmallett uint64_t pow : 1; /**< POW_ECC_ERR */ 4402215976Sjmallett uint64_t tim : 1; /**< TIM_REG_ERROR */ 4403215976Sjmallett uint64_t pko : 1; /**< PKO_REG_ERROR */ 4404215976Sjmallett uint64_t ipd : 1; /**< IPD_INT_SUM */ 4405215976Sjmallett uint64_t rint_8 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4406215976Sjmallett uint64_t zip : 1; /**< ZIP_ERROR */ 4407215976Sjmallett uint64_t dfa : 1; /**< DFA_ERR */ 4408215976Sjmallett uint64_t fpa : 1; /**< FPA_INT_SUM */ 4409215976Sjmallett uint64_t key : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4410215976Sjmallett uint64_t npi : 1; /**< NPI_INT_SUM */ 4411215976Sjmallett uint64_t gmx1 : 1; /**< GMX1_RX*_INT_REG & GMX1_TX_INT_REG */ 4412215976Sjmallett uint64_t gmx0 : 1; /**< GMX0_RX*_INT_REG & GMX0_TX_INT_REG */ 4413215976Sjmallett uint64_t mio : 1; /**< MIO_BOOT_ERR */ 4414215976Sjmallett#else 4415215976Sjmallett uint64_t mio : 1; 4416215976Sjmallett uint64_t gmx0 : 1; 4417215976Sjmallett uint64_t gmx1 : 1; 4418215976Sjmallett uint64_t npi : 1; 4419215976Sjmallett uint64_t key : 1; 4420215976Sjmallett uint64_t fpa : 1; 4421215976Sjmallett uint64_t dfa : 1; 4422215976Sjmallett uint64_t zip : 1; 4423215976Sjmallett uint64_t rint_8 : 1; 4424215976Sjmallett uint64_t ipd : 1; 4425215976Sjmallett uint64_t pko : 1; 4426215976Sjmallett uint64_t tim : 1; 4427215976Sjmallett uint64_t pow : 1; 4428215976Sjmallett uint64_t usb : 1; 4429215976Sjmallett uint64_t rint_14 : 1; 4430215976Sjmallett uint64_t rint_15 : 1; 4431215976Sjmallett uint64_t l2c : 1; 4432215976Sjmallett uint64_t lmc : 1; 4433215976Sjmallett uint64_t spx0 : 1; 4434215976Sjmallett uint64_t spx1 : 1; 4435215976Sjmallett uint64_t pip : 1; 4436215976Sjmallett uint64_t rint_21 : 1; 4437215976Sjmallett uint64_t asx0 : 1; 4438215976Sjmallett uint64_t asx1 : 1; 4439215976Sjmallett uint64_t rint_24 : 1; 4440215976Sjmallett uint64_t rint_25 : 1; 4441215976Sjmallett uint64_t rint_26 : 1; 4442215976Sjmallett uint64_t rint_27 : 1; 4443215976Sjmallett uint64_t rint_28 : 1; 4444215976Sjmallett uint64_t rint_29 : 1; 4445215976Sjmallett uint64_t iob : 1; 4446215976Sjmallett uint64_t rint_31 : 1; 4447215976Sjmallett uint64_t reserved_32_63 : 32; 4448215976Sjmallett#endif 4449215976Sjmallett } cn30xx; 4450215976Sjmallett struct cvmx_npi_rsl_int_blocks_cn30xx cn31xx; 4451232812Sjmallett struct cvmx_npi_rsl_int_blocks_cn38xx { 4452232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4453215976Sjmallett uint64_t reserved_32_63 : 32; 4454215976Sjmallett uint64_t rint_31 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4455215976Sjmallett uint64_t iob : 1; /**< IOB_INT_SUM */ 4456215976Sjmallett uint64_t rint_29 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4457215976Sjmallett uint64_t rint_28 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4458215976Sjmallett uint64_t rint_27 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4459215976Sjmallett uint64_t rint_26 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4460215976Sjmallett uint64_t rint_25 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4461215976Sjmallett uint64_t rint_24 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4462215976Sjmallett uint64_t asx1 : 1; /**< ASX1_INT_REG */ 4463215976Sjmallett uint64_t asx0 : 1; /**< ASX0_INT_REG */ 4464215976Sjmallett uint64_t rint_21 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4465215976Sjmallett uint64_t pip : 1; /**< PIP_INT_REG. */ 4466215976Sjmallett uint64_t spx1 : 1; /**< SPX1_INT_REG & STX1_INT_REG */ 4467215976Sjmallett uint64_t spx0 : 1; /**< SPX0_INT_REG & STX0_INT_REG */ 4468215976Sjmallett uint64_t lmc : 1; /**< LMC_MEM_CFG0 */ 4469215976Sjmallett uint64_t l2c : 1; /**< L2T_ERR & L2D_ERR */ 4470215976Sjmallett uint64_t rint_15 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4471215976Sjmallett uint64_t rint_14 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4472215976Sjmallett uint64_t rint_13 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4473215976Sjmallett uint64_t pow : 1; /**< POW_ECC_ERR */ 4474215976Sjmallett uint64_t tim : 1; /**< TIM_REG_ERROR */ 4475215976Sjmallett uint64_t pko : 1; /**< PKO_REG_ERROR */ 4476215976Sjmallett uint64_t ipd : 1; /**< IPD_INT_SUM */ 4477215976Sjmallett uint64_t rint_8 : 1; /**< Set '1' when RSL bLock has an interrupt. */ 4478215976Sjmallett uint64_t zip : 1; /**< ZIP_ERROR */ 4479215976Sjmallett uint64_t dfa : 1; /**< DFA_ERR */ 4480215976Sjmallett uint64_t fpa : 1; /**< FPA_INT_SUM */ 4481215976Sjmallett uint64_t key : 1; /**< KEY_INT_SUM */ 4482215976Sjmallett uint64_t npi : 1; /**< NPI_INT_SUM */ 4483215976Sjmallett uint64_t gmx1 : 1; /**< GMX1_RX*_INT_REG & GMX1_TX_INT_REG */ 4484215976Sjmallett uint64_t gmx0 : 1; /**< GMX0_RX*_INT_REG & GMX0_TX_INT_REG */ 4485215976Sjmallett uint64_t mio : 1; /**< MIO_BOOT_ERR */ 4486215976Sjmallett#else 4487215976Sjmallett uint64_t mio : 1; 4488215976Sjmallett uint64_t gmx0 : 1; 4489215976Sjmallett uint64_t gmx1 : 1; 4490215976Sjmallett uint64_t npi : 1; 4491215976Sjmallett uint64_t key : 1; 4492215976Sjmallett uint64_t fpa : 1; 4493215976Sjmallett uint64_t dfa : 1; 4494215976Sjmallett uint64_t zip : 1; 4495215976Sjmallett uint64_t rint_8 : 1; 4496215976Sjmallett uint64_t ipd : 1; 4497215976Sjmallett uint64_t pko : 1; 4498215976Sjmallett uint64_t tim : 1; 4499215976Sjmallett uint64_t pow : 1; 4500215976Sjmallett uint64_t rint_13 : 1; 4501215976Sjmallett uint64_t rint_14 : 1; 4502215976Sjmallett uint64_t rint_15 : 1; 4503215976Sjmallett uint64_t l2c : 1; 4504215976Sjmallett uint64_t lmc : 1; 4505215976Sjmallett uint64_t spx0 : 1; 4506215976Sjmallett uint64_t spx1 : 1; 4507215976Sjmallett uint64_t pip : 1; 4508215976Sjmallett uint64_t rint_21 : 1; 4509215976Sjmallett uint64_t asx0 : 1; 4510215976Sjmallett uint64_t asx1 : 1; 4511215976Sjmallett uint64_t rint_24 : 1; 4512215976Sjmallett uint64_t rint_25 : 1; 4513215976Sjmallett uint64_t rint_26 : 1; 4514215976Sjmallett uint64_t rint_27 : 1; 4515215976Sjmallett uint64_t rint_28 : 1; 4516215976Sjmallett uint64_t rint_29 : 1; 4517215976Sjmallett uint64_t iob : 1; 4518215976Sjmallett uint64_t rint_31 : 1; 4519215976Sjmallett uint64_t reserved_32_63 : 32; 4520215976Sjmallett#endif 4521215976Sjmallett } cn38xx; 4522215976Sjmallett struct cvmx_npi_rsl_int_blocks_cn38xx cn38xxp2; 4523232812Sjmallett struct cvmx_npi_rsl_int_blocks_cn50xx { 4524232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4525215976Sjmallett uint64_t reserved_31_63 : 33; 4526215976Sjmallett uint64_t iob : 1; /**< IOB_INT_SUM */ 4527215976Sjmallett uint64_t lmc1 : 1; /**< Always reads as zero */ 4528215976Sjmallett uint64_t agl : 1; /**< Always reads as zero */ 4529215976Sjmallett uint64_t reserved_24_27 : 4; 4530215976Sjmallett uint64_t asx1 : 1; /**< Always reads as zero */ 4531215976Sjmallett uint64_t asx0 : 1; /**< ASX0_INT_REG */ 4532215976Sjmallett uint64_t reserved_21_21 : 1; 4533215976Sjmallett uint64_t pip : 1; /**< PIP_INT_REG. */ 4534215976Sjmallett uint64_t spx1 : 1; /**< Always reads as zero */ 4535215976Sjmallett uint64_t spx0 : 1; /**< Always reads as zero */ 4536215976Sjmallett uint64_t lmc : 1; /**< LMC_MEM_CFG0 */ 4537215976Sjmallett uint64_t l2c : 1; /**< L2T_ERR & L2D_ERR */ 4538215976Sjmallett uint64_t reserved_15_15 : 1; 4539215976Sjmallett uint64_t rad : 1; /**< Always reads as zero */ 4540215976Sjmallett uint64_t usb : 1; /**< USBN_INT_SUM */ 4541215976Sjmallett uint64_t pow : 1; /**< POW_ECC_ERR */ 4542215976Sjmallett uint64_t tim : 1; /**< TIM_REG_ERROR */ 4543215976Sjmallett uint64_t pko : 1; /**< PKO_REG_ERROR */ 4544215976Sjmallett uint64_t ipd : 1; /**< IPD_INT_SUM */ 4545215976Sjmallett uint64_t reserved_8_8 : 1; 4546215976Sjmallett uint64_t zip : 1; /**< Always reads as zero */ 4547215976Sjmallett uint64_t dfa : 1; /**< Always reads as zero */ 4548215976Sjmallett uint64_t fpa : 1; /**< FPA_INT_SUM */ 4549215976Sjmallett uint64_t key : 1; /**< Always reads as zero */ 4550215976Sjmallett uint64_t npi : 1; /**< NPI_INT_SUM */ 4551215976Sjmallett uint64_t gmx1 : 1; /**< Always reads as zero */ 4552215976Sjmallett uint64_t gmx0 : 1; /**< GMX0_RX*_INT_REG & GMX0_TX_INT_REG */ 4553215976Sjmallett uint64_t mio : 1; /**< MIO_BOOT_ERR */ 4554215976Sjmallett#else 4555215976Sjmallett uint64_t mio : 1; 4556215976Sjmallett uint64_t gmx0 : 1; 4557215976Sjmallett uint64_t gmx1 : 1; 4558215976Sjmallett uint64_t npi : 1; 4559215976Sjmallett uint64_t key : 1; 4560215976Sjmallett uint64_t fpa : 1; 4561215976Sjmallett uint64_t dfa : 1; 4562215976Sjmallett uint64_t zip : 1; 4563215976Sjmallett uint64_t reserved_8_8 : 1; 4564215976Sjmallett uint64_t ipd : 1; 4565215976Sjmallett uint64_t pko : 1; 4566215976Sjmallett uint64_t tim : 1; 4567215976Sjmallett uint64_t pow : 1; 4568215976Sjmallett uint64_t usb : 1; 4569215976Sjmallett uint64_t rad : 1; 4570215976Sjmallett uint64_t reserved_15_15 : 1; 4571215976Sjmallett uint64_t l2c : 1; 4572215976Sjmallett uint64_t lmc : 1; 4573215976Sjmallett uint64_t spx0 : 1; 4574215976Sjmallett uint64_t spx1 : 1; 4575215976Sjmallett uint64_t pip : 1; 4576215976Sjmallett uint64_t reserved_21_21 : 1; 4577215976Sjmallett uint64_t asx0 : 1; 4578215976Sjmallett uint64_t asx1 : 1; 4579215976Sjmallett uint64_t reserved_24_27 : 4; 4580215976Sjmallett uint64_t agl : 1; 4581215976Sjmallett uint64_t lmc1 : 1; 4582215976Sjmallett uint64_t iob : 1; 4583215976Sjmallett uint64_t reserved_31_63 : 33; 4584215976Sjmallett#endif 4585215976Sjmallett } cn50xx; 4586215976Sjmallett struct cvmx_npi_rsl_int_blocks_cn38xx cn58xx; 4587215976Sjmallett struct cvmx_npi_rsl_int_blocks_cn38xx cn58xxp1; 4588215976Sjmallett}; 4589215976Sjmalletttypedef union cvmx_npi_rsl_int_blocks cvmx_npi_rsl_int_blocks_t; 4590215976Sjmallett 4591215976Sjmallett/** 4592215976Sjmallett * cvmx_npi_size_input# 4593215976Sjmallett * 4594215976Sjmallett * NPI_SIZE_INPUT0 = NPI's Size for Input 0 Register 4595215976Sjmallett * 4596215976Sjmallett * The size (in instructions) of Instruction Queue-0. 4597215976Sjmallett */ 4598232812Sjmallettunion cvmx_npi_size_inputx { 4599215976Sjmallett uint64_t u64; 4600232812Sjmallett struct cvmx_npi_size_inputx_s { 4601232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4602215976Sjmallett uint64_t reserved_32_63 : 32; 4603215976Sjmallett uint64_t size : 32; /**< The size of the Instruction Queue used by Octane. 4604215976Sjmallett The value [SIZE] is in Instructions. 4605215976Sjmallett A value of 0 in this field is illegal. */ 4606215976Sjmallett#else 4607215976Sjmallett uint64_t size : 32; 4608215976Sjmallett uint64_t reserved_32_63 : 32; 4609215976Sjmallett#endif 4610215976Sjmallett } s; 4611215976Sjmallett struct cvmx_npi_size_inputx_s cn30xx; 4612215976Sjmallett struct cvmx_npi_size_inputx_s cn31xx; 4613215976Sjmallett struct cvmx_npi_size_inputx_s cn38xx; 4614215976Sjmallett struct cvmx_npi_size_inputx_s cn38xxp2; 4615215976Sjmallett struct cvmx_npi_size_inputx_s cn50xx; 4616215976Sjmallett struct cvmx_npi_size_inputx_s cn58xx; 4617215976Sjmallett struct cvmx_npi_size_inputx_s cn58xxp1; 4618215976Sjmallett}; 4619215976Sjmalletttypedef union cvmx_npi_size_inputx cvmx_npi_size_inputx_t; 4620215976Sjmallett 4621215976Sjmallett/** 4622215976Sjmallett * cvmx_npi_win_read_to 4623215976Sjmallett * 4624215976Sjmallett * NPI_WIN_READ_TO = NPI WINDOW READ Timeout Register 4625215976Sjmallett * 4626215976Sjmallett * Number of core clocks to wait before timing out on a WINDOW-READ to the NCB. 4627215976Sjmallett */ 4628232812Sjmallettunion cvmx_npi_win_read_to { 4629215976Sjmallett uint64_t u64; 4630232812Sjmallett struct cvmx_npi_win_read_to_s { 4631232812Sjmallett#ifdef __BIG_ENDIAN_BITFIELD 4632215976Sjmallett uint64_t reserved_32_63 : 32; 4633215976Sjmallett uint64_t time : 32; /**< Time to wait in core clocks. A value of 0 will 4634215976Sjmallett cause no timeouts. */ 4635215976Sjmallett#else 4636215976Sjmallett uint64_t time : 32; 4637215976Sjmallett uint64_t reserved_32_63 : 32; 4638215976Sjmallett#endif 4639215976Sjmallett } s; 4640215976Sjmallett struct cvmx_npi_win_read_to_s cn30xx; 4641215976Sjmallett struct cvmx_npi_win_read_to_s cn31xx; 4642215976Sjmallett struct cvmx_npi_win_read_to_s cn38xx; 4643215976Sjmallett struct cvmx_npi_win_read_to_s cn38xxp2; 4644215976Sjmallett struct cvmx_npi_win_read_to_s cn50xx; 4645215976Sjmallett struct cvmx_npi_win_read_to_s cn58xx; 4646215976Sjmallett struct cvmx_npi_win_read_to_s cn58xxp1; 4647215976Sjmallett}; 4648215976Sjmalletttypedef union cvmx_npi_win_read_to cvmx_npi_win_read_to_t; 4649215976Sjmallett 4650215976Sjmallett#endif 4651