1/*-
2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
3 * Copyright (c) 2014 Steven Lawrance <stl@koffein.net>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
29__FBSDID("$FreeBSD$");
30
31/*
32 * Analog PLL and power regulator driver for Freescale i.MX6 family of SoCs.
33 * Also, temperature montoring and cpu frequency control.  It was Freescale who
34 * kitchen-sinked this device, not us. :)
35 *
36 * We don't really do anything with analog PLLs, but the registers for
37 * controlling them belong to the same block as the power regulator registers.
38 * Since the newbus hierarchy makes it hard for anyone other than us to get at
39 * them, we just export a couple public functions to allow the imx6 CCM clock
40 * driver to read and write those registers.
41 *
42 * We also don't do anything about power regulation yet, but when the need
43 * arises, this would be the place for that code to live.
44 *
45 * I have no idea where the "anatop" name comes from.  It's in the standard DTS
46 * source describing i.MX6 SoCs, and in the linux and u-boot code which comes
47 * from Freescale, but it's not in the SoC manual.
48 *
49 * Note that temperature values throughout this code are handled in two types of
50 * units.  Items with '_cnt' in the name use the hardware temperature count
51 * units (higher counts are lower temperatures).  Items with '_val' in the name
52 * are deci-Celcius, which are converted to/from deci-Kelvins in the sysctl
53 * handlers (dK is the standard unit for temperature in sysctl).
54 */
55
56#include <sys/param.h>
57#include <sys/systm.h>
58#include <sys/callout.h>
59#include <sys/kernel.h>
60#include <sys/limits.h>
61#include <sys/sysctl.h>
62#include <sys/module.h>
63#include <sys/bus.h>
64#include <sys/rman.h>
65
66#include <dev/ofw/ofw_bus.h>
67#include <dev/ofw/ofw_bus_subr.h>
68
69#include <machine/bus.h>
70#include <machine/fdt.h>
71
72#include <arm/arm/mpcore_timervar.h>
73#include <arm/freescale/fsl_ocotpreg.h>
74#include <arm/freescale/fsl_ocotpvar.h>
75#include <arm/freescale/imx/imx6_anatopreg.h>
76#include <arm/freescale/imx/imx6_anatopvar.h>
77
78static SYSCTL_NODE(_hw, OID_AUTO, imx6, CTLFLAG_RW, NULL, "i.MX6 container");
79
80static struct resource_spec imx6_anatop_spec[] = {
81	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
82	{ SYS_RES_IRQ,		0,	RF_ACTIVE },
83	{ -1, 0 }
84};
85#define	MEMRES	0
86#define	IRQRES	1
87
88struct imx6_anatop_softc {
89	device_t	dev;
90	struct resource	*res[2];
91	uint32_t	cpu_curmhz;
92	uint32_t	cpu_curmv;
93	uint32_t	cpu_minmhz;
94	uint32_t	cpu_minmv;
95	uint32_t	cpu_maxmhz;
96	uint32_t	cpu_maxmv;
97	uint32_t	cpu_maxmhz_hw;
98	boolean_t	cpu_overclock_enable;
99	uint32_t	refosc_mhz;
100	void		*temp_intrhand;
101	uint32_t	temp_high_val;
102	uint32_t	temp_high_cnt;
103	uint32_t	temp_last_cnt;
104	uint32_t	temp_room_cnt;
105	struct callout	temp_throttle_callout;
106	sbintime_t	temp_throttle_delay;
107	uint32_t	temp_throttle_reset_cnt;
108	uint32_t	temp_throttle_trigger_cnt;
109	uint32_t	temp_throttle_val;
110};
111
112static struct imx6_anatop_softc *imx6_anatop_sc;
113
114/*
115 * Table of "operating points".
116 * These are combinations of frequency and voltage blessed by Freescale.
117 */
118static struct oppt {
119	uint32_t	mhz;
120	uint32_t	mv;
121} imx6_oppt_table[] = {
122/*      { 396,	 925},  XXX: need functional ccm code for this speed */
123	{ 792,	1150},
124	{ 852,	1225},
125	{ 996,	1225},
126	{1200,	1275},
127};
128
129/*
130 * Table of CPU max frequencies.  This is used to translate the max frequency
131 * value (0-3) from the ocotp CFG3 register into a mhz value that can be looked
132 * up in the operating points table.
133 */
134static uint32_t imx6_ocotp_mhz_tab[] = {792, 852, 996, 1200};
135
136#define	TZ_ZEROC	2732	/* deci-Kelvin <-> deci-Celcius offset. */
137
138uint32_t
139imx6_anatop_read_4(bus_size_t offset)
140{
141
142	KASSERT(imx6_anatop_sc != NULL, ("imx6_anatop_read_4 sc NULL"));
143
144	return (bus_read_4(imx6_anatop_sc->res[MEMRES], offset));
145}
146
147void
148imx6_anatop_write_4(bus_size_t offset, uint32_t value)
149{
150
151	KASSERT(imx6_anatop_sc != NULL, ("imx6_anatop_write_4 sc NULL"));
152
153	bus_write_4(imx6_anatop_sc->res[MEMRES], offset, value);
154}
155
156static void
157vdd_set(struct imx6_anatop_softc *sc, int mv)
158{
159	int newtarg, oldtarg;
160	uint32_t delay, pmureg;
161	static boolean_t init_done = false;
162
163	/*
164	 * The datasheet says VDD_PU and VDD_SOC must be equal, and VDD_ARM
165	 * can't be more than 50mV above or 200mV below them.  For now to keep
166	 * things simple we set all three to the same value.
167	 */
168
169	pmureg = imx6_anatop_read_4(IMX6_ANALOG_PMU_REG_CORE);
170	oldtarg = pmureg & IMX6_ANALOG_PMU_REG0_TARG_MASK;
171
172	/* Convert mV to target value.  Clamp target to valid range. */
173	if (mv < 725)
174		newtarg = 0x00;
175	else if (mv > 1450)
176		newtarg = 0x1F;
177	else
178		newtarg = (mv - 700) / 25;
179
180	/*
181	 * The first time through the 3 voltages might not be equal so use a
182	 * long conservative delay.  After that we need to delay 3uS for every
183	 * 25mV step upward.  No need to delay at all when lowering.
184	 */
185	if (init_done) {
186		if (newtarg == oldtarg)
187			return;
188		else if (newtarg > oldtarg)
189			delay = (newtarg - oldtarg) * 3;
190		else
191			delay = 0;
192	} else {
193		delay = 700 / 25 * 3;
194		init_done = true;
195	}
196
197	/*
198	 * Make the change and wait for it to take effect.
199	 */
200	pmureg &= ~(IMX6_ANALOG_PMU_REG0_TARG_MASK |
201	    IMX6_ANALOG_PMU_REG1_TARG_MASK |
202	    IMX6_ANALOG_PMU_REG2_TARG_MASK);
203
204	pmureg |= newtarg << IMX6_ANALOG_PMU_REG0_TARG_SHIFT;
205	pmureg |= newtarg << IMX6_ANALOG_PMU_REG1_TARG_SHIFT;
206	pmureg |= newtarg << IMX6_ANALOG_PMU_REG2_TARG_SHIFT;
207
208	imx6_anatop_write_4(IMX6_ANALOG_PMU_REG_CORE, pmureg);
209	DELAY(delay);
210	sc->cpu_curmv = newtarg * 25 + 700;
211}
212
213static inline uint32_t
214cpufreq_mhz_from_div(struct imx6_anatop_softc *sc, uint32_t div)
215{
216
217	return (sc->refosc_mhz * (div / 2));
218}
219
220static inline uint32_t
221cpufreq_mhz_to_div(struct imx6_anatop_softc *sc, uint32_t cpu_mhz)
222{
223
224	return (cpu_mhz / (sc->refosc_mhz / 2));
225}
226
227static inline uint32_t
228cpufreq_actual_mhz(struct imx6_anatop_softc *sc, uint32_t cpu_mhz)
229{
230
231	return (cpufreq_mhz_from_div(sc, cpufreq_mhz_to_div(sc, cpu_mhz)));
232}
233
234static struct oppt *
235cpufreq_nearest_oppt(struct imx6_anatop_softc *sc, uint32_t cpu_newmhz)
236{
237	int d, diff, i, nearest;
238
239	if (cpu_newmhz > sc->cpu_maxmhz_hw && !sc->cpu_overclock_enable)
240		cpu_newmhz = sc->cpu_maxmhz_hw;
241
242	diff = INT_MAX;
243	nearest = 0;
244	for (i = 0; i < nitems(imx6_oppt_table); ++i) {
245		d = abs((int)cpu_newmhz - (int)imx6_oppt_table[i].mhz);
246		if (diff > d) {
247			diff = d;
248			nearest = i;
249		}
250	}
251	return (&imx6_oppt_table[nearest]);
252}
253
254static void
255cpufreq_set_clock(struct imx6_anatop_softc * sc, struct oppt *op)
256{
257	uint32_t timeout, wrk32;
258
259	/* If increasing the frequency, we must first increase the voltage. */
260	if (op->mhz > sc->cpu_curmhz) {
261		vdd_set(sc, op->mv);
262	}
263
264	/*
265	 * I can't find a documented procedure for changing the ARM PLL divisor,
266	 * but some trial and error came up with this:
267	 *  - Set the bypass clock source to REF_CLK_24M (source #0).
268	 *  - Set the PLL into bypass mode; cpu should now be running at 24mhz.
269	 *  - Change the divisor.
270	 *  - Wait for the LOCK bit to come on; it takes ~50 loop iterations.
271	 *  - Turn off bypass mode; cpu should now be running at the new speed.
272	 */
273	imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_CLR,
274	    IMX6_ANALOG_CCM_PLL_ARM_CLK_SRC_MASK);
275	imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_SET,
276	    IMX6_ANALOG_CCM_PLL_ARM_BYPASS);
277
278	wrk32 = imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM);
279	wrk32 &= ~IMX6_ANALOG_CCM_PLL_ARM_DIV_MASK;
280	wrk32 |= cpufreq_mhz_to_div(sc, op->mhz);
281	imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM, wrk32);
282
283	timeout = 10000;
284	while ((imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM) &
285	    IMX6_ANALOG_CCM_PLL_ARM_LOCK) == 0)
286		if (--timeout == 0)
287			panic("imx6_set_cpu_clock(): PLL never locked");
288
289	imx6_anatop_write_4(IMX6_ANALOG_CCM_PLL_ARM_CLR,
290	    IMX6_ANALOG_CCM_PLL_ARM_BYPASS);
291
292	/* If lowering the frequency, it is now safe to lower the voltage. */
293	if (op->mhz < sc->cpu_curmhz)
294		vdd_set(sc, op->mv);
295	sc->cpu_curmhz = op->mhz;
296
297	/* Tell the mpcore timer that its frequency has changed. */
298        arm_tmr_change_frequency(
299	    cpufreq_actual_mhz(sc, sc->cpu_curmhz) * 1000000 / 2);
300}
301
302static int
303cpufreq_sysctl_minmhz(SYSCTL_HANDLER_ARGS)
304{
305	struct imx6_anatop_softc *sc;
306	struct oppt * op;
307	uint32_t temp;
308	int err;
309
310	sc = arg1;
311
312	temp = sc->cpu_minmhz;
313	err = sysctl_handle_int(oidp, &temp, 0, req);
314	if (err != 0 || req->newptr == NULL)
315		return (err);
316
317	op = cpufreq_nearest_oppt(sc, temp);
318	if (op->mhz > sc->cpu_maxmhz)
319		return (ERANGE);
320	else if (op->mhz == sc->cpu_minmhz)
321		return (0);
322
323	/*
324	 * Value changed, update softc.  If the new min is higher than the
325	 * current speed, raise the current speed to match.
326	 */
327	sc->cpu_minmhz = op->mhz;
328	if (sc->cpu_minmhz > sc->cpu_curmhz) {
329		cpufreq_set_clock(sc, op);
330	}
331	return (err);
332}
333
334static int
335cpufreq_sysctl_maxmhz(SYSCTL_HANDLER_ARGS)
336{
337	struct imx6_anatop_softc *sc;
338	struct oppt * op;
339	uint32_t temp;
340	int err;
341
342	sc = arg1;
343
344	temp = sc->cpu_maxmhz;
345	err = sysctl_handle_int(oidp, &temp, 0, req);
346	if (err != 0 || req->newptr == NULL)
347		return (err);
348
349	op = cpufreq_nearest_oppt(sc, temp);
350	if (op->mhz < sc->cpu_minmhz)
351		return (ERANGE);
352	else if (op->mhz == sc->cpu_maxmhz)
353		return (0);
354
355	/*
356	 *  Value changed, update softc and hardware.  The hardware update is
357	 *  unconditional.  We always try to run at max speed, so any change of
358	 *  the max means we need to change the current speed too, regardless of
359	 *  whether it is higher or lower than the old max.
360	 */
361	sc->cpu_maxmhz = op->mhz;
362	cpufreq_set_clock(sc, op);
363
364	return (err);
365}
366
367static void
368cpufreq_initialize(struct imx6_anatop_softc *sc)
369{
370	uint32_t cfg3speed;
371	struct oppt * op;
372
373	SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6),
374	    OID_AUTO, "cpu_mhz", CTLFLAG_RD, &sc->cpu_curmhz, 0,
375	    "CPU frequency");
376
377	SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6),
378	    OID_AUTO, "cpu_minmhz", CTLTYPE_INT | CTLFLAG_RWTUN, sc, 0,
379	    cpufreq_sysctl_minmhz, "IU", "Minimum CPU frequency");
380
381	SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6),
382	    OID_AUTO, "cpu_maxmhz", CTLTYPE_INT | CTLFLAG_RWTUN, sc, 0,
383	    cpufreq_sysctl_maxmhz, "IU", "Maximum CPU frequency");
384
385	SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6),
386	    OID_AUTO, "cpu_maxmhz_hw", CTLFLAG_RD, &sc->cpu_maxmhz_hw, 0,
387	    "Maximum CPU frequency allowed by hardware");
388
389	SYSCTL_ADD_INT(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6),
390	    OID_AUTO, "cpu_overclock_enable", CTLFLAG_RWTUN,
391	    &sc->cpu_overclock_enable, 0,
392	    "Allow setting CPU frequency higher than cpu_maxmhz_hw");
393
394	/*
395	 * XXX 24mhz shouldn't be hard-coded, should get this from imx6_ccm
396	 * (even though in the real world it will always be 24mhz).  Oh wait a
397	 * sec, I never wrote imx6_ccm.
398	 */
399	sc->refosc_mhz = 24;
400
401	/*
402	 * Get the maximum speed this cpu can be set to.  The values in the
403	 * OCOTP CFG3 register are not documented in the reference manual.
404	 * The following info was in an archived email found via web search:
405	 *   - 2b'11: 1200000000Hz;
406	 *   - 2b'10: 996000000Hz;
407	 *   - 2b'01: 852000000Hz; -- i.MX6Q Only, exclusive with 996MHz.
408	 *   - 2b'00: 792000000Hz;
409	 * The default hardware max speed can be overridden by a tunable.
410	 */
411	cfg3speed = (fsl_ocotp_read_4(FSL_OCOTP_CFG3) &
412	    FSL_OCOTP_CFG3_SPEED_MASK) >> FSL_OCOTP_CFG3_SPEED_SHIFT;
413	sc->cpu_maxmhz_hw = imx6_ocotp_mhz_tab[cfg3speed];
414	sc->cpu_maxmhz = sc->cpu_maxmhz_hw;
415
416	TUNABLE_INT_FETCH("hw.imx6.cpu_overclock_enable",
417	    &sc->cpu_overclock_enable);
418
419	TUNABLE_INT_FETCH("hw.imx6.cpu_minmhz", &sc->cpu_minmhz);
420	op = cpufreq_nearest_oppt(sc, sc->cpu_minmhz);
421	sc->cpu_minmhz = op->mhz;
422	sc->cpu_minmv = op->mv;
423
424	TUNABLE_INT_FETCH("hw.imx6.cpu_maxmhz", &sc->cpu_maxmhz);
425	op = cpufreq_nearest_oppt(sc, sc->cpu_maxmhz);
426	sc->cpu_maxmhz = op->mhz;
427	sc->cpu_maxmv = op->mv;
428
429	/*
430	 * Set the CPU to maximum speed.
431	 *
432	 * We won't have thermal throttling until interrupts are enabled, but we
433	 * want to run at full speed through all the device init stuff.  This
434	 * basically assumes that a single core can't overheat before interrupts
435	 * are enabled; empirical testing shows that to be a safe assumption.
436	 */
437	cpufreq_set_clock(sc, op);
438}
439
440static inline uint32_t
441temp_from_count(struct imx6_anatop_softc *sc, uint32_t count)
442{
443
444	return (((sc->temp_high_val - (count - sc->temp_high_cnt) *
445	    (sc->temp_high_val - 250) /
446	    (sc->temp_room_cnt - sc->temp_high_cnt))));
447}
448
449static inline uint32_t
450temp_to_count(struct imx6_anatop_softc *sc, uint32_t temp)
451{
452
453	return ((sc->temp_room_cnt - sc->temp_high_cnt) *
454	    (sc->temp_high_val - temp) / (sc->temp_high_val - 250) +
455	    sc->temp_high_cnt);
456}
457
458static void
459temp_update_count(struct imx6_anatop_softc *sc)
460{
461	uint32_t val;
462
463	val = imx6_anatop_read_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0);
464	if (!(val & IMX6_ANALOG_TEMPMON_TEMPSENSE0_VALID))
465		return;
466	sc->temp_last_cnt =
467	    (val & IMX6_ANALOG_TEMPMON_TEMPSENSE0_TEMP_CNT_MASK) >>
468	    IMX6_ANALOG_TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT;
469}
470
471static int
472temp_sysctl_handler(SYSCTL_HANDLER_ARGS)
473{
474	struct imx6_anatop_softc *sc = arg1;
475	uint32_t t;
476
477	temp_update_count(sc);
478
479	t = temp_from_count(sc, sc->temp_last_cnt) + TZ_ZEROC;
480
481	return (sysctl_handle_int(oidp, &t, 0, req));
482}
483
484static int
485temp_throttle_sysctl_handler(SYSCTL_HANDLER_ARGS)
486{
487	struct imx6_anatop_softc *sc = arg1;
488	int err;
489	uint32_t temp;
490
491	temp = sc->temp_throttle_val + TZ_ZEROC;
492	err = sysctl_handle_int(oidp, &temp, 0, req);
493	if (temp < TZ_ZEROC)
494		return (ERANGE);
495	temp -= TZ_ZEROC;
496	if (err != 0 || req->newptr == NULL || temp == sc->temp_throttle_val)
497		return (err);
498
499	/* Value changed, update counts in softc and hardware. */
500	sc->temp_throttle_val = temp;
501	sc->temp_throttle_trigger_cnt = temp_to_count(sc, sc->temp_throttle_val);
502	sc->temp_throttle_reset_cnt = temp_to_count(sc, sc->temp_throttle_val - 100);
503	imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0_CLR,
504	    IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_MASK);
505	imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0_SET,
506	    (sc->temp_throttle_trigger_cnt <<
507	     IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_SHIFT));
508	return (err);
509}
510
511static void
512tempmon_gofast(struct imx6_anatop_softc *sc)
513{
514
515	if (sc->cpu_curmhz < sc->cpu_maxmhz) {
516		cpufreq_set_clock(sc, cpufreq_nearest_oppt(sc, sc->cpu_maxmhz));
517	}
518}
519
520static void
521tempmon_goslow(struct imx6_anatop_softc *sc)
522{
523
524	if (sc->cpu_curmhz > sc->cpu_minmhz) {
525		cpufreq_set_clock(sc, cpufreq_nearest_oppt(sc, sc->cpu_minmhz));
526	}
527}
528
529static int
530tempmon_intr(void *arg)
531{
532	struct imx6_anatop_softc *sc = arg;
533
534	/*
535	 * XXX Note that this code doesn't currently run (for some mysterious
536	 * reason we just never get an interrupt), so the real monitoring is
537	 * done by tempmon_throttle_check().
538	 */
539	tempmon_goslow(sc);
540	/* XXX Schedule callout to speed back up eventually. */
541	return (FILTER_HANDLED);
542}
543
544static void
545tempmon_throttle_check(void *arg)
546{
547	struct imx6_anatop_softc *sc = arg;
548
549	/* Lower counts are higher temperatures. */
550	if (sc->temp_last_cnt < sc->temp_throttle_trigger_cnt)
551		tempmon_goslow(sc);
552	else if (sc->temp_last_cnt > (sc->temp_throttle_reset_cnt))
553		tempmon_gofast(sc);
554
555	callout_reset_sbt(&sc->temp_throttle_callout, sc->temp_throttle_delay,
556		0, tempmon_throttle_check, sc, 0);
557
558}
559
560static void
561initialize_tempmon(struct imx6_anatop_softc *sc)
562{
563	uint32_t cal;
564
565	/*
566	 * Fetch calibration data: a sensor count at room temperature (25C),
567	 * a sensor count at a high temperature, and that temperature
568	 */
569	cal = fsl_ocotp_read_4(FSL_OCOTP_ANA1);
570	sc->temp_room_cnt = (cal & 0xFFF00000) >> 20;
571	sc->temp_high_cnt = (cal & 0x000FFF00) >> 8;
572	sc->temp_high_val = (cal & 0x000000FF) * 10;
573
574	/*
575	 * Throttle to a lower cpu freq at 10C below the "hot" temperature, and
576	 * reset back to max cpu freq at 5C below the trigger.
577	 */
578	sc->temp_throttle_val = sc->temp_high_val - 100;
579	sc->temp_throttle_trigger_cnt =
580	    temp_to_count(sc, sc->temp_throttle_val);
581	sc->temp_throttle_reset_cnt =
582	    temp_to_count(sc, sc->temp_throttle_val - 50);
583
584	/*
585	 * Set the sensor to sample automatically at 16Hz (32.768KHz/0x800), set
586	 * the throttle count, and begin making measurements.
587	 */
588	imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE1, 0x0800);
589	imx6_anatop_write_4(IMX6_ANALOG_TEMPMON_TEMPSENSE0,
590	    (sc->temp_throttle_trigger_cnt <<
591	    IMX6_ANALOG_TEMPMON_TEMPSENSE0_ALARM_SHIFT) |
592	    IMX6_ANALOG_TEMPMON_TEMPSENSE0_MEASURE);
593
594	/*
595	 * XXX Note that the alarm-interrupt feature isn't working yet, so
596	 * we'll use a callout handler to check at 10Hz.  Make sure we have an
597	 * initial temperature reading before starting up the callouts so we
598	 * don't get a bogus reading of zero.
599	 */
600	while (sc->temp_last_cnt == 0)
601		temp_update_count(sc);
602	sc->temp_throttle_delay = 100 * SBT_1MS;
603	callout_init(&sc->temp_throttle_callout, 0);
604	callout_reset_sbt(&sc->temp_throttle_callout, sc->temp_throttle_delay,
605	    0, tempmon_throttle_check, sc, 0);
606
607	SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6),
608	    OID_AUTO, "temperature", CTLTYPE_INT | CTLFLAG_RD, sc, 0,
609	    temp_sysctl_handler, "IK", "Current die temperature");
610	SYSCTL_ADD_PROC(NULL, SYSCTL_STATIC_CHILDREN(_hw_imx6),
611	    OID_AUTO, "throttle_temperature", CTLTYPE_INT | CTLFLAG_RW, sc,
612	    0, temp_throttle_sysctl_handler, "IK",
613	    "Throttle CPU when exceeding this temperature");
614}
615
616static int
617imx6_anatop_detach(device_t dev)
618{
619
620	return (EBUSY);
621}
622
623static int
624imx6_anatop_attach(device_t dev)
625{
626	struct imx6_anatop_softc *sc;
627	int err;
628
629	sc = device_get_softc(dev);
630	sc->dev = dev;
631
632	/* Allocate bus_space resources. */
633	if (bus_alloc_resources(dev, imx6_anatop_spec, sc->res)) {
634		device_printf(dev, "Cannot allocate resources\n");
635		err = ENXIO;
636		goto out;
637	}
638
639	err = bus_setup_intr(dev, sc->res[IRQRES], INTR_TYPE_MISC | INTR_MPSAFE,
640	    tempmon_intr, NULL, sc, &sc->temp_intrhand);
641	if (err != 0)
642		goto out;
643
644	SYSCTL_ADD_UINT(device_get_sysctl_ctx(sc->dev),
645	    SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)),
646	    OID_AUTO, "cpu_voltage", CTLFLAG_RD,
647	    &sc->cpu_curmv, 0, "Current CPU voltage in millivolts");
648
649	imx6_anatop_sc = sc;
650
651	/*
652	 * Other code seen on the net sets this SELFBIASOFF flag around the same
653	 * time the temperature sensor is set up, although it's unclear how the
654	 * two are related (if at all).
655	 */
656	imx6_anatop_write_4(IMX6_ANALOG_PMU_MISC0_SET,
657	    IMX6_ANALOG_PMU_MISC0_SELFBIASOFF);
658
659	cpufreq_initialize(sc);
660	initialize_tempmon(sc);
661
662	if (bootverbose) {
663		device_printf(sc->dev, "CPU %uMHz @ %umV\n", sc->cpu_curmhz,
664		    sc->cpu_curmv);
665	}
666	err = 0;
667
668out:
669
670	if (err != 0) {
671		bus_release_resources(dev, imx6_anatop_spec, sc->res);
672	}
673
674	return (err);
675}
676
677static int
678imx6_anatop_probe(device_t dev)
679{
680
681	if (!ofw_bus_status_okay(dev))
682		return (ENXIO);
683
684	if (ofw_bus_is_compatible(dev, "fsl,imx6q-anatop") == 0)
685		return (ENXIO);
686
687	device_set_desc(dev, "Freescale i.MX6 Analog PLLs and Power");
688
689	return (BUS_PROBE_DEFAULT);
690}
691
692uint32_t
693imx6_get_cpu_clock()
694{
695	uint32_t div;
696
697	div = imx6_anatop_read_4(IMX6_ANALOG_CCM_PLL_ARM) &
698	    IMX6_ANALOG_CCM_PLL_ARM_DIV_MASK;
699	return (cpufreq_mhz_from_div(imx6_anatop_sc, div));
700}
701
702static device_method_t imx6_anatop_methods[] = {
703	/* Device interface */
704	DEVMETHOD(device_probe,  imx6_anatop_probe),
705	DEVMETHOD(device_attach, imx6_anatop_attach),
706	DEVMETHOD(device_detach, imx6_anatop_detach),
707
708	DEVMETHOD_END
709};
710
711static driver_t imx6_anatop_driver = {
712	"imx6_anatop",
713	imx6_anatop_methods,
714	sizeof(struct imx6_anatop_softc)
715};
716
717static devclass_t imx6_anatop_devclass;
718
719DRIVER_MODULE(imx6_anatop, simplebus, imx6_anatop_driver, imx6_anatop_devclass, 0, 0);
720
721